mirror of https://github.com/xemu-project/xemu.git
ahci: Add test_hba_enable to ahci-test.
This test engages the HBA functionality and initializes values to sane defaults to allow for minimal HBA functionality. Buffers are allocated and pointers are updated to allow minimal I/O commands to complete as expected. Error registers and responses are sanity checked for specification adherence. Signed-off-by: John Snow <jsnow@redhat.com> Message-id: 1408643079-30675-8-git-send-email-jsnow@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
John Snow
Stefan Hajnoczi
parent
c2f3029fbc
commit
dbc180e572
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@ -277,11 +277,17 @@ static uint32_t ahci_fingerprint;
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#define AHCI_WRITE(OFST, VAL) qpci_io_writel(ahci, hba_base + (OFST), (VAL))
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#define AHCI_WRITE(OFST, VAL) qpci_io_writel(ahci, hba_base + (OFST), (VAL))
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#define AHCI_RREG(regno) AHCI_READ(4 * (regno))
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#define AHCI_RREG(regno) AHCI_READ(4 * (regno))
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#define AHCI_WREG(regno, val) AHCI_WRITE(4 * (regno), (val))
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#define AHCI_WREG(regno, val) AHCI_WRITE(4 * (regno), (val))
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#define AHCI_SET(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) | (mask))
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#define AHCI_CLR(regno, mask) AHCI_WREG((regno), AHCI_RREG(regno) & ~(mask))
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/*** IO macros for port-specific offsets inside of AHCI memory. ***/
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/*** IO macros for port-specific offsets inside of AHCI memory. ***/
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#define PX_OFST(port, regno) (HBA_PORT_NUM_REG * (port) + AHCI_PORTS + (regno))
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#define PX_OFST(port, regno) (HBA_PORT_NUM_REG * (port) + AHCI_PORTS + (regno))
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#define PX_RREG(port, regno) AHCI_RREG(PX_OFST((port), (regno)))
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#define PX_RREG(port, regno) AHCI_RREG(PX_OFST((port), (regno)))
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#define PX_WREG(port, regno, val) AHCI_WREG(PX_OFST((port), (regno)), (val))
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#define PX_WREG(port, regno, val) AHCI_WREG(PX_OFST((port), (regno)), (val))
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#define PX_SET(port, reg, mask) PX_WREG((port), (reg), \
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PX_RREG((port), (reg)) | (mask));
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#define PX_CLR(port, reg, mask) PX_WREG((port), (reg), \
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PX_RREG((port), (reg)) & ~(mask));
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/*** Function Declarations ***/
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/*** Function Declarations ***/
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static QPCIDevice *get_ahci_device(void);
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static QPCIDevice *get_ahci_device(void);
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@ -432,6 +438,140 @@ static QPCIDevice *start_ahci_device(QPCIDevice *ahci, void **hba_base)
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return ahci;
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return ahci;
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}
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}
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/**
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* Test and initialize the AHCI's HBA memory areas.
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* Initialize and start any ports with devices attached.
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* Bring the HBA into the idle state.
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*/
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static void ahci_hba_enable(QPCIDevice *ahci, void *hba_base)
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{
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/* Bits of interest in this section:
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* GHC.AE Global Host Control / AHCI Enable
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* PxCMD.ST Port Command: Start
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* PxCMD.SUD "Spin Up Device"
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* PxCMD.POD "Power On Device"
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* PxCMD.FRE "FIS Receive Enable"
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* PxCMD.FR "FIS Receive Running"
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* PxCMD.CR "Command List Running"
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*/
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g_assert(ahci != NULL);
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g_assert(hba_base != NULL);
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uint32_t reg, ports_impl, clb, fb;
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uint16_t i;
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uint8_t num_cmd_slots;
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g_assert(hba_base != 0);
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/* Set GHC.AE to 1 */
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AHCI_SET(AHCI_GHC, AHCI_GHC_AE);
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reg = AHCI_RREG(AHCI_GHC);
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ASSERT_BIT_SET(reg, AHCI_GHC_AE);
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/* Read CAP.NCS, how many command slots do we have? */
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reg = AHCI_RREG(AHCI_CAP);
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num_cmd_slots = ((reg & AHCI_CAP_NCS) >> ctzl(AHCI_CAP_NCS)) + 1;
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g_test_message("Number of Command Slots: %u", num_cmd_slots);
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/* Determine which ports are implemented. */
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ports_impl = AHCI_RREG(AHCI_PI);
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for (i = 0; ports_impl; ports_impl >>= 1, ++i) {
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if (!(ports_impl & 0x01)) {
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continue;
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}
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g_test_message("Initializing port %u", i);
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reg = PX_RREG(i, AHCI_PX_CMD);
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if (BITCLR(reg, AHCI_PX_CMD_ST | AHCI_PX_CMD_CR |
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AHCI_PX_CMD_FRE | AHCI_PX_CMD_FR)) {
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g_test_message("port is idle");
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} else {
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g_test_message("port needs to be idled");
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PX_CLR(i, AHCI_PX_CMD, (AHCI_PX_CMD_ST | AHCI_PX_CMD_FRE));
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/* The port has 500ms to disengage. */
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usleep(500000);
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reg = PX_RREG(i, AHCI_PX_CMD);
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ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR);
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ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_FR);
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g_test_message("port is now idle");
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/* The spec does allow for possibly needing a PORT RESET
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* or HBA reset if we fail to idle the port. */
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}
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/* Allocate Memory for the Command List Buffer & FIS Buffer */
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/* PxCLB space ... 0x20 per command, as in 4.2.2 p 36 */
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clb = guest_alloc(guest_malloc, num_cmd_slots * 0x20);
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g_test_message("CLB: 0x%08x", clb);
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PX_WREG(i, AHCI_PX_CLB, clb);
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g_assert_cmphex(clb, ==, PX_RREG(i, AHCI_PX_CLB));
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/* PxFB space ... 0x100, as in 4.2.1 p 35 */
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fb = guest_alloc(guest_malloc, 0x100);
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g_test_message("FB: 0x%08x", fb);
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PX_WREG(i, AHCI_PX_FB, fb);
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g_assert_cmphex(fb, ==, PX_RREG(i, AHCI_PX_FB));
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/* Clear PxSERR, PxIS, then IS.IPS[x] by writing '1's. */
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PX_WREG(i, AHCI_PX_SERR, 0xFFFFFFFF);
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PX_WREG(i, AHCI_PX_IS, 0xFFFFFFFF);
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AHCI_WREG(AHCI_IS, (1 << i));
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/* Verify Interrupts Cleared */
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reg = PX_RREG(i, AHCI_PX_SERR);
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g_assert_cmphex(reg, ==, 0);
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reg = PX_RREG(i, AHCI_PX_IS);
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g_assert_cmphex(reg, ==, 0);
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reg = AHCI_RREG(AHCI_IS);
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ASSERT_BIT_CLEAR(reg, (1 << i));
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/* Enable All Interrupts: */
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PX_WREG(i, AHCI_PX_IE, 0xFFFFFFFF);
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reg = PX_RREG(i, AHCI_PX_IE);
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g_assert_cmphex(reg, ==, ~((uint32_t)AHCI_PX_IE_RESERVED));
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/* Enable the FIS Receive Engine. */
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PX_SET(i, AHCI_PX_CMD, AHCI_PX_CMD_FRE);
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reg = PX_RREG(i, AHCI_PX_CMD);
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ASSERT_BIT_SET(reg, AHCI_PX_CMD_FR);
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/* AHCI 1.3 spec: if !STS.BSY, !STS.DRQ and PxSSTS.DET indicates
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* physical presence, a device is present and may be started. However,
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* PxSERR.DIAG.X /may/ need to be cleared a priori. */
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reg = PX_RREG(i, AHCI_PX_SERR);
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if (BITSET(reg, AHCI_PX_SERR_DIAG_X)) {
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PX_SET(i, AHCI_PX_SERR, AHCI_PX_SERR_DIAG_X);
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}
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reg = PX_RREG(i, AHCI_PX_TFD);
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if (BITCLR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ)) {
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reg = PX_RREG(i, AHCI_PX_SSTS);
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if ((reg & AHCI_PX_SSTS_DET) == SSTS_DET_ESTABLISHED) {
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/* Device Found: set PxCMD.ST := 1 */
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PX_SET(i, AHCI_PX_CMD, AHCI_PX_CMD_ST);
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ASSERT_BIT_SET(PX_RREG(i, AHCI_PX_CMD), AHCI_PX_CMD_CR);
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g_test_message("Started Device %u", i);
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} else if ((reg & AHCI_PX_SSTS_DET)) {
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/* Device present, but in some unknown state. */
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g_assert_not_reached();
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}
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}
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}
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/* Enable GHC.IE */
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AHCI_SET(AHCI_GHC, AHCI_GHC_IE);
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reg = AHCI_RREG(AHCI_GHC);
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ASSERT_BIT_SET(reg, AHCI_GHC_IE);
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/* TODO: The device should now be idling and waiting for commands.
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* In the future, a small test-case to inspect the Register D2H FIS
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* and clear the initial interrupts might be good. */
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}
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/*** Specification Adherence Tests ***/
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/*** Specification Adherence Tests ***/
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/**
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/**
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@ -1038,6 +1178,21 @@ static void test_hba_spec(void)
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ahci_shutdown(ahci);
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ahci_shutdown(ahci);
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}
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}
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/**
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* Engage the HBA functionality of the AHCI PCI device,
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* and bring it into a functional idle state.
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*/
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static void test_hba_enable(void)
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{
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QPCIDevice *ahci;
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void *hba_base;
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ahci = ahci_boot();
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ahci_pci_enable(ahci, &hba_base);
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ahci_hba_enable(ahci, hba_base);
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ahci_shutdown(ahci);
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}
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/******************************************************************************/
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/******************************************************************************/
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int main(int argc, char **argv)
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int main(int argc, char **argv)
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@ -1091,6 +1246,7 @@ int main(int argc, char **argv)
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qtest_add_func("/ahci/pci_spec", test_pci_spec);
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qtest_add_func("/ahci/pci_spec", test_pci_spec);
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qtest_add_func("/ahci/pci_enable", test_pci_enable);
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qtest_add_func("/ahci/pci_enable", test_pci_enable);
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qtest_add_func("/ahci/hba_spec", test_hba_spec);
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qtest_add_func("/ahci/hba_spec", test_hba_spec);
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qtest_add_func("/ahci/hba_enable", test_hba_enable);
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ret = g_test_run();
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ret = g_test_run();
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