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target/riscv: Use background registers also for MSTATUS_MPV
The current condition for the use of background registers only considers the hypervisor load and store instructions, but not accesses from M mode via MSTATUS_MPRV+MPV. Signed-off-by: Georg Kotheimer <georg.kotheimer@kernkonzept.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20210311103036.1401073-1-georg.kotheimer@kernkonzept.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -364,7 +364,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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* was called. Background registers will be used if the guest has
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* forced a two stage translation to be on (in HS or M mode).
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*/
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if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
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if (!riscv_cpu_virt_enabled(env) && two_stage) {
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use_background = true;
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}
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