mirror of https://github.com/xemu-project/xemu.git
Revert "target-ppc: stop translation after a trap instruction"
This reverts commit 6454e7be1b
.
This commit is contained in:
parent
d9812b033a
commit
db9a231d1f
|
@ -3618,9 +3618,8 @@ static void gen_sc(DisasContext *ctx)
|
||||||
static void gen_tw(DisasContext *ctx)
|
static void gen_tw(DisasContext *ctx)
|
||||||
{
|
{
|
||||||
TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
|
TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
|
||||||
/* Stop the translation since this might generate a trap exception
|
/* Update the nip since this might generate a trap exception */
|
||||||
and/or following instructions might be invalid */
|
gen_update_nip(ctx, ctx->nip);
|
||||||
gen_stop_exception(ctx);
|
|
||||||
gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
|
gen_helper_tw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
|
||||||
tcg_temp_free_i32(t0);
|
tcg_temp_free_i32(t0);
|
||||||
}
|
}
|
||||||
|
@ -3630,9 +3629,8 @@ static void gen_twi(DisasContext *ctx)
|
||||||
{
|
{
|
||||||
TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
|
TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
|
||||||
TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
|
TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
|
||||||
/* Stop the translation since this might generate a trap exception
|
/* Update the nip since this might generate a trap exception */
|
||||||
and/or following instructions might be invalid */
|
gen_update_nip(ctx, ctx->nip);
|
||||||
gen_stop_exception(ctx);
|
|
||||||
gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
|
gen_helper_tw(cpu_gpr[rA(ctx->opcode)], t0, t1);
|
||||||
tcg_temp_free(t0);
|
tcg_temp_free(t0);
|
||||||
tcg_temp_free_i32(t1);
|
tcg_temp_free_i32(t1);
|
||||||
|
@ -3643,9 +3641,8 @@ static void gen_twi(DisasContext *ctx)
|
||||||
static void gen_td(DisasContext *ctx)
|
static void gen_td(DisasContext *ctx)
|
||||||
{
|
{
|
||||||
TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
|
TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
|
||||||
/* Stop the translation since this might generate a trap exception
|
/* Update the nip since this might generate a trap exception */
|
||||||
and/or following instructions might be invalid */
|
gen_update_nip(ctx, ctx->nip);
|
||||||
gen_stop_exception(ctx);
|
|
||||||
gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
|
gen_helper_td(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
|
||||||
tcg_temp_free_i32(t0);
|
tcg_temp_free_i32(t0);
|
||||||
}
|
}
|
||||||
|
@ -3655,9 +3652,8 @@ static void gen_tdi(DisasContext *ctx)
|
||||||
{
|
{
|
||||||
TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
|
TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
|
||||||
TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
|
TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
|
||||||
/* Stop the translation since this might generate a trap exception
|
/* Update the nip since this might generate a trap exception */
|
||||||
and/or following instructions might be invalid */
|
gen_update_nip(ctx, ctx->nip);
|
||||||
gen_stop_exception(ctx);
|
|
||||||
gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
|
gen_helper_td(cpu_gpr[rA(ctx->opcode)], t0, t1);
|
||||||
tcg_temp_free(t0);
|
tcg_temp_free(t0);
|
||||||
tcg_temp_free_i32(t1);
|
tcg_temp_free_i32(t1);
|
||||||
|
|
Loading…
Reference in New Issue