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target/riscv: csr: Rename HCOUNTEREN_CY and friends 

The macro name HCOUNTEREN_CY suggests it is for CSR HCOUNTEREN, but
in fact it applies to M-mode and S-mode CSR too. Rename these macros
to have the COUNTEREN_ prefix.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20210915084601.24304-1-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Bin Meng 2021-09-15 16:46:01 +08:00 committed by Alistair Francis
parent c601354756
commit db70794ea8
2 changed files with 16 additions and 16 deletions
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8
target/riscv/cpu_bits.h
View File

@ -397,10 +397,10 @@
#define HSTATUS32_WPRI 0xFF8FF87E #define HSTATUS32_WPRI 0xFF8FF87E
#define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
#define HCOUNTEREN_CY (1 << 0) #define COUNTEREN_CY (1 << 0)
#define HCOUNTEREN_TM (1 << 1) #define COUNTEREN_TM (1 << 1)
#define HCOUNTEREN_IR (1 << 2) #define COUNTEREN_IR (1 << 2)
#define HCOUNTEREN_HPM3 (1 << 3) #define COUNTEREN_HPM3 (1 << 3)
/* Privilege modes */ /* Privilege modes */
#define PRV_U 0 #define PRV_U 0

24
target/riscv/csr.c
View File

@ -71,20 +71,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
if (riscv_cpu_virt_enabled(env)) { if (riscv_cpu_virt_enabled(env)) {
switch (csrno) { switch (csrno) {
case CSR_CYCLE: case CSR_CYCLE:
if (!get_field(env->hcounteren, HCOUNTEREN_CY) && if (!get_field(env->hcounteren, COUNTEREN_CY) &&
get_field(env->mcounteren, HCOUNTEREN_CY)) { get_field(env->mcounteren, COUNTEREN_CY)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
} }
break; break;
case CSR_TIME: case CSR_TIME:
if (!get_field(env->hcounteren, HCOUNTEREN_TM) && if (!get_field(env->hcounteren, COUNTEREN_TM) &&
get_field(env->mcounteren, HCOUNTEREN_TM)) { get_field(env->mcounteren, COUNTEREN_TM)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
} }
break; break;
case CSR_INSTRET: case CSR_INSTRET:
if (!get_field(env->hcounteren, HCOUNTEREN_IR) && if (!get_field(env->hcounteren, COUNTEREN_IR) &&
get_field(env->mcounteren, HCOUNTEREN_IR)) { get_field(env->mcounteren, COUNTEREN_IR)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
} }
break; break;
@ -98,20 +98,20 @@ static RISCVException ctr(CPURISCVState *env, int csrno)
if (riscv_cpu_is_32bit(env)) { if (riscv_cpu_is_32bit(env)) {
switch (csrno) { switch (csrno) {
case CSR_CYCLEH: case CSR_CYCLEH:
if (!get_field(env->hcounteren, HCOUNTEREN_CY) && if (!get_field(env->hcounteren, COUNTEREN_CY) &&
get_field(env->mcounteren, HCOUNTEREN_CY)) { get_field(env->mcounteren, COUNTEREN_CY)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
} }
break; break;
case CSR_TIMEH: case CSR_TIMEH:
if (!get_field(env->hcounteren, HCOUNTEREN_TM) && if (!get_field(env->hcounteren, COUNTEREN_TM) &&
get_field(env->mcounteren, HCOUNTEREN_TM)) { get_field(env->mcounteren, COUNTEREN_TM)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
} }
break; break;
case CSR_INSTRETH: case CSR_INSTRETH:
if (!get_field(env->hcounteren, HCOUNTEREN_IR) && if (!get_field(env->hcounteren, COUNTEREN_IR) &&
get_field(env->mcounteren, HCOUNTEREN_IR)) { get_field(env->mcounteren, COUNTEREN_IR)) {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
} }
break; break;