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target-alpha: Convert opcode 0x11 to source/sink 

Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson 2014-03-18 22:56:35 -07:00
parent 194cfb43d5
commit db4a16458c
1 changed files with 37 additions and 89 deletions
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126
target-alpha/translate.c
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@ -2100,32 +2100,43 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
goto invalid_opc; goto invalid_opc;
} }
break; break;
case 0x11: case 0x11:
if (fn7 == 0x20) {
if (rc == 31) {
/* Special case BIS as NOP. */
break;
}
if (ra == 31) {
/* Special case BIS as MOV. */
vc = dest_gpr(ctx, rc);
if (islit) {
tcg_gen_movi_i64(vc, lit);
} else {
tcg_gen_mov_i64(vc, load_gpr(ctx, rb));
}
break;
}
}
vc = dest_gpr(ctx, rc);
vb = load_gpr_lit(ctx, rb, lit, islit);
if (fn7 == 0x28 && ra == 31) {
/* Special case ORNOT as NOT. */
tcg_gen_not_i64(vc, vb);
break;
}
va = load_gpr(ctx, ra);
switch (fn7) { switch (fn7) {
case 0x00: case 0x00:
/* AND */ /* AND */
if (likely(rc != 31)) { tcg_gen_and_i64(vc, va, vb);
if (ra == 31) {
tcg_gen_movi_i64(cpu_ir[rc], 0);
} else if (islit) {
tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], lit);
} else {
tcg_gen_and_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
}
}
break; break;
case 0x08: case 0x08:
/* BIC */ /* BIC */
if (likely(rc != 31)) { tcg_gen_andc_i64(vc, va, vb);
if (ra != 31) {
if (islit) {
tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
} else {
tcg_gen_andc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
}
} else
tcg_gen_movi_i64(cpu_ir[rc], 0);
}
break; break;
case 0x14: case 0x14:
/* CMOVLBS */ /* CMOVLBS */
@ -2137,21 +2148,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x20: case 0x20:
/* BIS */ /* BIS */
if (likely(rc != 31)) { tcg_gen_or_i64(vc, va, vb);
if (ra != 31) {
if (islit) {
tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], lit);
} else {
tcg_gen_or_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
}
} else {
if (islit) {
tcg_gen_movi_i64(cpu_ir[rc], lit);
} else {
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
}
}
}
break; break;
case 0x24: case 0x24:
/* CMOVEQ */ /* CMOVEQ */
@ -2163,39 +2160,11 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x28: case 0x28:
/* ORNOT */ /* ORNOT */
if (likely(rc != 31)) { tcg_gen_orc_i64(vc, va, vb);
if (ra != 31) {
if (islit) {
tcg_gen_ori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
} else {
tcg_gen_orc_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
}
} else {
if (islit) {
tcg_gen_movi_i64(cpu_ir[rc], ~lit);
} else {
tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
}
}
}
break; break;
case 0x40: case 0x40:
/* XOR */ /* XOR */
if (likely(rc != 31)) { tcg_gen_xor_i64(vc, va, vb);
if (ra != 31) {
if (islit) {
tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], lit);
} else {
tcg_gen_xor_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
}
} else {
if (islit) {
tcg_gen_movi_i64(cpu_ir[rc], lit);
} else {
tcg_gen_mov_i64(cpu_ir[rc], cpu_ir[rb]);
}
}
}
break; break;
case 0x44: case 0x44:
/* CMOVLT */ /* CMOVLT */
@ -2207,33 +2176,14 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
break; break;
case 0x48: case 0x48:
/* EQV */ /* EQV */
if (likely(rc != 31)) { tcg_gen_eqv_i64(vc, va, vb);
if (ra != 31) {
if (islit) {
tcg_gen_xori_i64(cpu_ir[rc], cpu_ir[ra], ~lit);
} else {
tcg_gen_eqv_i64(cpu_ir[rc], cpu_ir[ra], cpu_ir[rb]);
}
} else {
if (islit) {
tcg_gen_movi_i64(cpu_ir[rc], ~lit);
} else {
tcg_gen_not_i64(cpu_ir[rc], cpu_ir[rb]);
}
}
}
break; break;
case 0x61: case 0x61:
/* AMASK */ /* AMASK */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
if (likely(rc != 31)) { {
uint64_t amask = ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT; uint64_t amask = ctx->tb->flags >> TB_FLAGS_AMASK_SHIFT;
tcg_gen_andi_i64(vc, vb, ~amask);
if (islit) {
tcg_gen_movi_i64(cpu_ir[rc], lit & ~amask);
} else {
tcg_gen_andi_i64(cpu_ir[rc], cpu_ir[rb], ~amask);
}
} }
break; break;
case 0x64: case 0x64:
@ -2247,9 +2197,7 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
case 0x6C: case 0x6C:
/* IMPLVER */ /* IMPLVER */
REQUIRE_REG_31(ra); REQUIRE_REG_31(ra);
if (rc != 31) { tcg_gen_movi_i64(vc, ctx->implver);
tcg_gen_movi_i64(cpu_ir[rc], ctx->implver);
}
break; break;
default: default:
goto invalid_opc; goto invalid_opc;