ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/rx: Avoid tcg_const_i32 

All remaining uses are strictly read-only.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-02-26 10:13:07 -10:00
parent 09374ee274
commit daefc08567
1 changed files with 16 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
target/rx/translate.c
View File

@ -456,7 +456,7 @@ static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a)
static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a)
{ {
TCGv imm, mem; TCGv imm, mem;
imm = tcg_const_i32(a->imm); imm = tcg_constant_i32(a->imm);
mem = tcg_temp_new(); mem = tcg_temp_new();
tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz);
rx_gen_st(a->sz, imm, mem); rx_gen_st(a->sz, imm, mem);
@ -729,8 +729,8 @@ static inline void stcond(TCGCond cond, int rd, int imm)
{ {
TCGv z; TCGv z;
TCGv _imm; TCGv _imm;
z = tcg_const_i32(0); z = tcg_constant_i32(0);
_imm = tcg_const_i32(imm); _imm = tcg_constant_i32(imm);
tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z,
_imm, cpu_regs[rd]); _imm, cpu_regs[rd]);
} }
@ -815,7 +815,7 @@ static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2)
static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2) static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src2)
{ {
TCGv imm = tcg_const_i32(src2); TCGv imm = tcg_constant_i32(src2);
opr(cpu_regs[dst], cpu_regs[src], imm); opr(cpu_regs[dst], cpu_regs[src], imm);
} }
@ -1188,7 +1188,7 @@ static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a)
/* emul #imm, rd */ /* emul #imm, rd */
static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a)
{ {
TCGv imm = tcg_const_i32(a->imm); TCGv imm = tcg_constant_i32(a->imm);
if (a->rd > 14) { if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
} }
@ -1215,7 +1215,7 @@ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a)
/* emulu #imm, rd */ /* emulu #imm, rd */
static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a)
{ {
TCGv imm = tcg_const_i32(a->imm); TCGv imm = tcg_constant_i32(a->imm);
if (a->rd > 14) { if (a->rd > 14) {
qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd);
} }
@ -1585,7 +1585,7 @@ static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a)
static inline void rx_save_pc(DisasContext *ctx) static inline void rx_save_pc(DisasContext *ctx)
{ {
TCGv pc = tcg_const_i32(ctx->base.pc_next); TCGv pc = tcg_constant_i32(ctx->base.pc_next);
push(pc); push(pc);
} }
@ -1668,7 +1668,7 @@ static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a)
#define STRING(op) \ #define STRING(op) \
do { \ do { \
TCGv size = tcg_const_i32(a->sz); \ TCGv size = tcg_constant_i32(a->sz); \
gen_helper_##op(cpu_env, size); \ gen_helper_##op(cpu_env, size); \
} while (0) } while (0)
@ -1799,7 +1799,7 @@ static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a)
/* racw #imm */ /* racw #imm */
static bool trans_RACW(DisasContext *ctx, arg_RACW *a) static bool trans_RACW(DisasContext *ctx, arg_RACW *a)
{ {
TCGv imm = tcg_const_i32(a->imm + 1); TCGv imm = tcg_constant_i32(a->imm + 1);
gen_helper_racw(cpu_env, imm); gen_helper_racw(cpu_env, imm);
return true; return true;
} }
@ -1809,7 +1809,7 @@ static bool trans_SAT(DisasContext *ctx, arg_SAT *a)
{ {
TCGv tmp, z; TCGv tmp, z;
tmp = tcg_temp_new(); tmp = tcg_temp_new();
z = tcg_const_i32(0); z = tcg_constant_i32(0);
/* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */ /* S == 1 -> 0xffffffff / S == 0 -> 0x00000000 */
tcg_gen_sari_i32(tmp, cpu_psw_s, 31); tcg_gen_sari_i32(tmp, cpu_psw_s, 31);
/* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */ /* S == 1 -> 0x7fffffff / S == 0 -> 0x80000000 */
@ -1831,7 +1831,7 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ static bool cat3(trans_, name, _ir)(DisasContext *ctx, \
cat3(arg_, name, _ir) * a) \ cat3(arg_, name, _ir) * a) \
{ \ { \
TCGv imm = tcg_const_i32(li(ctx, 0)); \ TCGv imm = tcg_constant_i32(li(ctx, 0)); \
gen_helper_##op(cpu_regs[a->rd], cpu_env, \ gen_helper_##op(cpu_regs[a->rd], cpu_env, \
cpu_regs[a->rd], imm); \ cpu_regs[a->rd], imm); \
return true; \ return true; \
@ -1865,7 +1865,7 @@ FOP(FDIV, fdiv)
/* fcmp #imm, rd */ /* fcmp #imm, rd */
static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
{ {
TCGv imm = tcg_const_i32(li(ctx, 0)); TCGv imm = tcg_constant_i32(li(ctx, 0));
gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm); gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm);
return true; return true;
} }
@ -1962,7 +1962,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
{ \ { \
TCGv mask, mem, addr; \ TCGv mask, mem, addr; \
mem = tcg_temp_new(); \ mem = tcg_temp_new(); \
mask = tcg_const_i32(1 << a->imm); \ mask = tcg_constant_i32(1 << a->imm); \
addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ addr = rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \
cat3(rx_, op, m)(addr, mask); \ cat3(rx_, op, m)(addr, mask); \
return true; \ return true; \
@ -1971,7 +1971,7 @@ static inline void rx_bnotr(TCGv reg, TCGv mask)
cat3(arg_, name, _ir) * a) \ cat3(arg_, name, _ir) * a) \
{ \ { \
TCGv mask; \ TCGv mask; \
mask = tcg_const_i32(1 << a->imm); \ mask = tcg_constant_i32(1 << a->imm); \
cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ cat3(rx_, op, r)(cpu_regs[a->rd], mask); \
return true; \ return true; \
} \ } \
@ -2116,7 +2116,7 @@ static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a)
{ {
TCGv imm; TCGv imm;
imm = tcg_const_i32(a->imm); imm = tcg_constant_i32(a->imm);
move_to_cr(ctx, imm, a->cr); move_to_cr(ctx, imm, a->cr);
return true; return true;
} }
@ -2178,7 +2178,7 @@ static bool trans_INT(DisasContext *ctx, arg_INT *a)
TCGv vec; TCGv vec;
tcg_debug_assert(a->imm < 0x100); tcg_debug_assert(a->imm < 0x100);
vec = tcg_const_i32(a->imm); vec = tcg_constant_i32(a->imm);
tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next);
gen_helper_rxint(cpu_env, vec); gen_helper_rxint(cpu_env, vec);
ctx->base.is_jmp = DISAS_NORETURN; ctx->base.is_jmp = DISAS_NORETURN;