mirror of https://github.com/xemu-project/xemu.git
Hexagon (target/hexagon) Add overrides for dealloc-return instructions
These instructions perform a deallocframe+return (jumpr r31)
Add overrides for
L4_return
SL2_return
L4_return_t
L4_return_f
L4_return_tnew_pt
L4_return_fnew_pt
L4_return_tnew_pnt
L4_return_fnew_pnt
SL2_return_t
SL2_return_f
SL2_return_tnew
SL2_return_fnew
This patch eliminates the last helper that uses write_new_pc, so we
remove it from op_helper.c
Signed-off-by: Taylor Simpson <tsimpson@quicinc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230307025828.1612809-5-tsimpson@quicinc.com>
This commit is contained in:
Taylor Simpson
parent
b8552a78a2
commit
dae386b80f
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@ -491,6 +491,59 @@
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#define fGEN_TCG_S2_storerinew_pcr(SHORTCODE) \
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fGEN_TCG_STORE_pcr(2, fSTORE(1, 4, EA, NtN))
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/*
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* dealloc_return
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* Assembler mapped to
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* r31:30 = dealloc_return(r30):raw
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*/
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#define fGEN_TCG_L4_return(SHORTCODE) \
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gen_return(ctx, RddV, RsV)
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/*
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* sub-instruction version (no RddV, so handle it manually)
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*/
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#define fGEN_TCG_SL2_return(SHORTCODE) \
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do { \
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TCGv_i64 RddV = tcg_temp_new_i64(); \
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gen_return(ctx, RddV, hex_gpr[HEX_REG_FP]); \
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gen_log_reg_write_pair(HEX_REG_FP, RddV); \
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} while (0)
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/*
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* Conditional returns follow this naming convention
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* _t predicate true
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* _f predicate false
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* _tnew_pt predicate.new true predict taken
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* _fnew_pt predicate.new false predict taken
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* _tnew_pnt predicate.new true predict not taken
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* _fnew_pnt predicate.new false predict not taken
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* Predictions are not modelled in QEMU
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*
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* Example:
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* if (p1) r31:30 = dealloc_return(r30):raw
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*/
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#define fGEN_TCG_L4_return_t(SHORTCODE) \
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gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_EQ);
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#define fGEN_TCG_L4_return_f(SHORTCODE) \
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gen_cond_return(ctx, RddV, RsV, PvV, TCG_COND_NE)
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#define fGEN_TCG_L4_return_tnew_pt(SHORTCODE) \
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gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ)
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#define fGEN_TCG_L4_return_fnew_pt(SHORTCODE) \
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gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE)
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#define fGEN_TCG_L4_return_tnew_pnt(SHORTCODE) \
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gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_EQ)
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#define fGEN_TCG_L4_return_fnew_pnt(SHORTCODE) \
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gen_cond_return(ctx, RddV, RsV, PvN, TCG_COND_NE)
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#define fGEN_TCG_SL2_return_t(SHORTCODE) \
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gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_pred[0])
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#define fGEN_TCG_SL2_return_f(SHORTCODE) \
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gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_pred[0])
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#define fGEN_TCG_SL2_return_tnew(SHORTCODE) \
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gen_cond_return_subinsn(ctx, TCG_COND_EQ, hex_new_pred_value[0])
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#define fGEN_TCG_SL2_return_fnew(SHORTCODE) \
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gen_cond_return_subinsn(ctx, TCG_COND_NE, hex_new_pred_value[0])
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/*
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* Mathematical operations with more than one definition require
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* special handling
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@ -715,6 +715,83 @@ static void gen_cond_callr(DisasContext *ctx,
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gen_set_label(skip);
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}
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/* frame ^= (int64_t)FRAMEKEY << 32 */
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static void gen_frame_unscramble(TCGv_i64 frame)
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{
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TCGv_i64 framekey = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(framekey, hex_gpr[HEX_REG_FRAMEKEY]);
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tcg_gen_shli_i64(framekey, framekey, 32);
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tcg_gen_xor_i64(frame, frame, framekey);
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}
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static void gen_load_frame(DisasContext *ctx, TCGv_i64 frame, TCGv EA)
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{
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Insn *insn = ctx->insn; /* Needed for CHECK_NOSHUF */
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CHECK_NOSHUF(EA, 8);
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tcg_gen_qemu_ld64(frame, EA, ctx->mem_idx);
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}
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static void gen_return_base(DisasContext *ctx, TCGv_i64 dst, TCGv src,
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TCGv r29)
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{
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/*
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* frame = *src
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* dst = frame_unscramble(frame)
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* SP = src + 8
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* PC = dst.w[1]
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*/
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TCGv_i64 frame = tcg_temp_new_i64();
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TCGv r31 = tcg_temp_new();
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gen_load_frame(ctx, frame, src);
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gen_frame_unscramble(frame);
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tcg_gen_mov_i64(dst, frame);
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tcg_gen_addi_tl(r29, src, 8);
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tcg_gen_extrh_i64_i32(r31, dst);
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gen_jumpr(ctx, r31);
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}
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static void gen_return(DisasContext *ctx, TCGv_i64 dst, TCGv src)
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{
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TCGv r29 = tcg_temp_new();
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gen_return_base(ctx, dst, src, r29);
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gen_log_reg_write(HEX_REG_SP, r29);
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}
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/* if (pred) dst = dealloc_return(src):raw */
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static void gen_cond_return(DisasContext *ctx, TCGv_i64 dst, TCGv src,
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TCGv pred, TCGCond cond)
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{
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TCGv LSB = tcg_temp_new();
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TCGv mask = tcg_temp_new();
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TCGv r29 = tcg_temp_new();
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TCGLabel *skip = gen_new_label();
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tcg_gen_andi_tl(LSB, pred, 1);
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/* Initialize the results in case the predicate is false */
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tcg_gen_movi_i64(dst, 0);
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tcg_gen_movi_tl(r29, 0);
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/* Set the bit in hex_slot_cancelled if the predicate is flase */
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tcg_gen_movi_tl(mask, 1 << ctx->insn->slot);
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tcg_gen_or_tl(mask, hex_slot_cancelled, mask);
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tcg_gen_movcond_tl(cond, hex_slot_cancelled, LSB, tcg_constant_tl(0),
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mask, hex_slot_cancelled);
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tcg_gen_brcondi_tl(cond, LSB, 0, skip);
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gen_return_base(ctx, dst, src, r29);
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gen_set_label(skip);
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gen_log_predicated_reg_write(HEX_REG_SP, r29, ctx->insn->slot);
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}
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/* sub-instruction version (no RddV, so handle it manually) */
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static void gen_cond_return_subinsn(DisasContext *ctx, TCGCond cond, TCGv pred)
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{
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TCGv_i64 RddV = tcg_temp_new_i64();
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gen_cond_return(ctx, RddV, hex_gpr[HEX_REG_FP], pred, cond);
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gen_log_predicated_reg_write_pair(HEX_REG_FP, RddV, ctx->insn->slot);
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}
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static void gen_endloop0(DisasContext *ctx)
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{
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TCGv lpcfg = tcg_temp_new();
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@ -1,5 +1,5 @@
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/*
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* Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Reserved.
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* Copyright(c) 2019-2023 Qualcomm Innovation Center, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -105,30 +105,6 @@ void log_store64(CPUHexagonState *env, target_ulong addr,
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env->mem_log_stores[slot].data64 = val;
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}
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void write_new_pc(CPUHexagonState *env, bool pkt_has_multi_cof,
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target_ulong addr)
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{
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HEX_DEBUG_LOG("write_new_pc(0x" TARGET_FMT_lx ")\n", addr);
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if (pkt_has_multi_cof) {
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/*
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* If more than one branch is taken in a packet, only the first one
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* is actually done.
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*/
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if (env->branch_taken) {
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HEX_DEBUG_LOG("INFO: multiple branches taken in same packet, "
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"ignoring the second one\n");
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} else {
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fCHECK_PCALIGN(addr);
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env->gpr[HEX_REG_PC] = addr;
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env->branch_taken = 1;
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}
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} else {
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fCHECK_PCALIGN(addr);
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env->gpr[HEX_REG_PC] = addr;
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}
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}
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/* Handy place to set a breakpoint */
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void HELPER(debug_start_packet)(CPUHexagonState *env)
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{
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