mirror of https://github.com/xemu-project/xemu.git
ppc4xx_pci: convert to memory API
Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
parent
d09510b276
commit
da726e5e06
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@ -54,6 +54,8 @@ struct PPC4xxPCIState {
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PCIHostState pci_state;
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PCIHostState pci_state;
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PCIDevice *pci_dev;
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PCIDevice *pci_dev;
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MemoryRegion iomem_addr;
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MemoryRegion iomem_regs;
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};
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};
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typedef struct PPC4xxPCIState PPC4xxPCIState;
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typedef struct PPC4xxPCIState PPC4xxPCIState;
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@ -84,35 +86,30 @@ typedef struct PPC4xxPCIState PPC4xxPCIState;
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#define PCI_REG_SIZE 0x40
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#define PCI_REG_SIZE 0x40
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static uint32_t pci4xx_cfgaddr_readl(void *opaque, target_phys_addr_t addr)
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static uint64_t pci4xx_cfgaddr_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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{
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PPC4xxPCIState *ppc4xx_pci = opaque;
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PPC4xxPCIState *ppc4xx_pci = opaque;
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return ppc4xx_pci->pci_state.config_reg;
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return ppc4xx_pci->pci_state.config_reg;
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}
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}
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static CPUReadMemoryFunc * const pci4xx_cfgaddr_read[] = {
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static void pci4xx_cfgaddr_write(void *opaque, target_phys_addr_t addr,
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&pci4xx_cfgaddr_readl,
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uint64_t value, unsigned size)
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&pci4xx_cfgaddr_readl,
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&pci4xx_cfgaddr_readl,
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};
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static void pci4xx_cfgaddr_writel(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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{
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PPC4xxPCIState *ppc4xx_pci = opaque;
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PPC4xxPCIState *ppc4xx_pci = opaque;
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ppc4xx_pci->pci_state.config_reg = value & ~0x3;
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ppc4xx_pci->pci_state.config_reg = value & ~0x3;
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}
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}
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static CPUWriteMemoryFunc * const pci4xx_cfgaddr_write[] = {
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static const MemoryRegionOps pci4xx_cfgaddr_ops = {
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&pci4xx_cfgaddr_writel,
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.read = pci4xx_cfgaddr_read,
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&pci4xx_cfgaddr_writel,
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.write = pci4xx_cfgaddr_write,
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&pci4xx_cfgaddr_writel,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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};
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static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
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static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
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uint32_t value)
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uint64_t value, unsigned size)
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{
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{
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struct PPC4xxPCIState *pci = opaque;
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struct PPC4xxPCIState *pci = opaque;
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@ -179,7 +176,8 @@ static void ppc4xx_pci_reg_write4(void *opaque, target_phys_addr_t offset,
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}
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}
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}
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}
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static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
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static uint64_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset,
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unsigned size)
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{
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{
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struct PPC4xxPCIState *pci = opaque;
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struct PPC4xxPCIState *pci = opaque;
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uint32_t value;
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uint32_t value;
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@ -246,16 +244,10 @@ static uint32_t ppc4xx_pci_reg_read4(void *opaque, target_phys_addr_t offset)
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return value;
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return value;
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}
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}
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static CPUReadMemoryFunc * const pci_reg_read[] = {
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static const MemoryRegionOps pci_reg_ops = {
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&ppc4xx_pci_reg_read4,
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.read = ppc4xx_pci_reg_read4,
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&ppc4xx_pci_reg_read4,
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.write = ppc4xx_pci_reg_write4,
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&ppc4xx_pci_reg_read4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static CPUWriteMemoryFunc * const pci_reg_write[] = {
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&ppc4xx_pci_reg_write4,
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&ppc4xx_pci_reg_write4,
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&ppc4xx_pci_reg_write4,
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};
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};
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static void ppc4xx_pci_reset(void *opaque)
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static void ppc4xx_pci_reset(void *opaque)
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@ -337,7 +329,6 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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target_phys_addr_t registers)
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target_phys_addr_t registers)
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{
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{
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PPC4xxPCIState *controller;
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PPC4xxPCIState *controller;
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int index;
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static int ppc4xx_pci_id;
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static int ppc4xx_pci_id;
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uint8_t *pci_conf;
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uint8_t *pci_conf;
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@ -360,12 +351,11 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
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pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
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/* CFGADDR */
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/* CFGADDR */
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index = cpu_register_io_memory(pci4xx_cfgaddr_read,
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memory_region_init_io(&controller->iomem_addr, &pci4xx_cfgaddr_ops,
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pci4xx_cfgaddr_write, controller,
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controller, "pci.cfgaddr", 4);
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DEVICE_LITTLE_ENDIAN);
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memory_region_add_subregion(get_system_memory(),
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if (index < 0)
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config_space + PCIC0_CFGADDR,
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goto free;
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&controller->iomem_addr);
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cpu_register_physical_memory(config_space + PCIC0_CFGADDR, 4, index);
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/* CFGDATA */
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/* CFGDATA */
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memory_region_init_io(&controller->pci_state.data_mem,
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memory_region_init_io(&controller->pci_state.data_mem,
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@ -376,11 +366,10 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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&controller->pci_state.data_mem);
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&controller->pci_state.data_mem);
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/* Internal registers */
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/* Internal registers */
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index = cpu_register_io_memory(pci_reg_read, pci_reg_write, controller,
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memory_region_init_io(&controller->iomem_regs, &pci_reg_ops, controller,
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DEVICE_LITTLE_ENDIAN);
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"pci.regs", PCI_REG_SIZE);
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if (index < 0)
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memory_region_add_subregion(get_system_memory(), registers,
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goto free;
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&controller->iomem_regs);
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cpu_register_physical_memory(registers, PCI_REG_SIZE, index);
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qemu_register_reset(ppc4xx_pci_reset, controller);
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qemu_register_reset(ppc4xx_pci_reset, controller);
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@ -389,9 +378,4 @@ PCIBus *ppc4xx_pci_init(CPUState *env, qemu_irq pci_irqs[4],
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&vmstate_ppc4xx_pci, controller);
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&vmstate_ppc4xx_pci, controller);
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return controller->pci_state.bus;
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return controller->pci_state.bus;
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free:
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printf("%s error\n", __func__);
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g_free(controller);
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return NULL;
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}
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}
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