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accel/tcg: Create io_recompile_replay_branch hook 

Create a hook in which to split out the mips and
sh4 ifdefs from cpu_io_recompile.

[AJB: s/stoped/stopped/]

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210208233906.479571-3-richard.henderson@linaro.org>
Message-Id: <20210213130325.14781-12-alex.bennee@linaro.org>
This commit is contained in:
Richard Henderson 2021-02-13 13:03:13 +00:00 committed by Alex Bennée
parent 8349d2aeb3
commit d9bcb58a12
2 changed files with 23 additions and 4 deletions
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17
accel/tcg/translate-all.c
View File

@ -60,6 +60,7 @@
#include "sysemu/cpu-timers.h" #include "sysemu/cpu-timers.h"
#include "sysemu/tcg.h" #include "sysemu/tcg.h"
#include "qapi/error.h" #include "qapi/error.h"
#include "hw/core/tcg-cpu-ops.h"
#include "internal.h" #include "internal.h"
/* #define DEBUG_TB_INVALIDATE */ /* #define DEBUG_TB_INVALIDATE */
@ -2421,6 +2422,7 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
CPUArchState *env = cpu->env_ptr; CPUArchState *env = cpu->env_ptr;
#endif #endif
TranslationBlock *tb; TranslationBlock *tb;
CPUClass *cc;
uint32_t n; uint32_t n;
tb = tcg_tb_lookup(retaddr); tb = tcg_tb_lookup(retaddr);
@ -2430,11 +2432,18 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr)
} }
cpu_restore_state_from_tb(cpu, tb, retaddr, true); cpu_restore_state_from_tb(cpu, tb, retaddr, true);
/* On MIPS and SH, delay slot instructions can only be restarted if /*
they were already the first instruction in the TB. If this is not * Some guests must re-execute the branch when re-executing a delay
the first instruction in a TB then re-execute the preceding * slot instruction. When this is the case, adjust icount and N
branch. */ * to account for the re-execution of the branch.
*/
n = 1; n = 1;
cc = CPU_GET_CLASS(cpu);
if (cc->tcg_ops->io_recompile_replay_branch &&
cc->tcg_ops->io_recompile_replay_branch(cpu, tb)) {
cpu_neg(cpu)->icount_decr.u16.low++;
n = 2;
}
#if defined(TARGET_MIPS) #if defined(TARGET_MIPS)
if ((env->hflags & MIPS_HFLAG_BMASK) != 0 if ((env->hflags & MIPS_HFLAG_BMASK) != 0
&& env->active_tc.PC != tb->pc) { && env->active_tc.PC != tb->pc) {

10
include/hw/core/tcg-cpu-ops.h
View File

@ -88,6 +88,16 @@ struct TCGCPUOps {
*/ */
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
/**
* @io_recompile_replay_branch: Callback for cpu_io_recompile.
*
* The cpu has been stopped, and cpu_restore_state_from_tb has been
* called. If the faulting instruction is in a delay slot, and the
* target architecture requires re-execution of the branch, then
* adjust the cpu state as required and return true.
*/
bool (*io_recompile_replay_branch)(CPUState *cpu,
const TranslationBlock *tb);
#endif /* CONFIG_SOFTMMU */ #endif /* CONFIG_SOFTMMU */
#endif /* NEED_CPU_H */ #endif /* NEED_CPU_H */