From 8f06bf693dec29642255adcc2828bc6b7daa83d9 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sat, 22 Sep 2012 23:08:38 +0200 Subject: [PATCH 01/12] tcg/mips: fix MIPS32(R2) detection Fix the MIPS32(R2) cpu detection so that it also works with -march=octeon. Thanks to Andrew Pinski for the hint. Cc: Andrew Pinski Signed-off-by: Aurelien Jarno --- tcg/mips/tcg-target.c | 10 +++++----- tcg/mips/tcg-target.h | 8 ++++---- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c index f70910a90f..34e3e7f823 100644 --- a/tcg/mips/tcg-target.c +++ b/tcg/mips/tcg-target.c @@ -419,7 +419,7 @@ static inline void tcg_out_movi(TCGContext *s, TCGType type, static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) { -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); #else /* ret and arg can't be register at */ @@ -436,7 +436,7 @@ static inline void tcg_out_bswap16(TCGContext *s, TCGReg ret, TCGReg arg) static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) { -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); tcg_out_opc_reg(s, OPC_SEH, ret, 0, ret); #else @@ -454,7 +454,7 @@ static inline void tcg_out_bswap16s(TCGContext *s, TCGReg ret, TCGReg arg) static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) { -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) tcg_out_opc_reg(s, OPC_WSBH, ret, 0, arg); tcg_out_opc_sa(s, OPC_ROTR, ret, ret, 16); #else @@ -480,7 +480,7 @@ static inline void tcg_out_bswap32(TCGContext *s, TCGReg ret, TCGReg arg) static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) { -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) tcg_out_opc_reg(s, OPC_SEB, ret, 0, arg); #else tcg_out_opc_sa(s, OPC_SLL, ret, arg, 24); @@ -490,7 +490,7 @@ static inline void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) static inline void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) { -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) tcg_out_opc_reg(s, OPC_SEH, ret, 0, arg); #else tcg_out_opc_sa(s, OPC_SLL, ret, arg, 16); diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index d147e70eb1..7020d65845 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -88,16 +88,16 @@ typedef enum { #define TCG_TARGET_HAS_nand_i32 0 /* optional instructions only implemented on MIPS4, MIPS32 and Loongson 2 */ -#if defined(_MIPS_ARCH_MIPS4) || defined(_MIPS_ARCH_MIPS32) || \ - defined(_MIPS_ARCH_MIPS32R2) || defined(_MIPS_ARCH_LOONGSON2E) || \ - defined(_MIPS_ARCH_LOONGSON2F) +#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \ + defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \ + defined(_MIPS_ARCH_MIPS4) #define TCG_TARGET_HAS_movcond_i32 1 #else #define TCG_TARGET_HAS_movcond_i32 0 #endif /* optional instructions only implemented on MIPS32R2 */ -#ifdef _MIPS_ARCH_MIPS32R2 +#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2) #define TCG_TARGET_HAS_bswap16_i32 1 #define TCG_TARGET_HAS_bswap32_i32 1 #define TCG_TARGET_HAS_rot_i32 1 From 5a696f6ac0641f200cdd2dfe7a6fd397d48ea7bd Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 21 Sep 2012 17:18:09 -0700 Subject: [PATCH 02/12] tcg: Adjust descriptions of *cond opcodes The README file documented the operand ordering of the tcg_gen_* functions. Since we're documenting opcodes here, use the true operand ordering. Signed-off-by: Richard Henderson Cc: malc Signed-off-by: Aurelien Jarno --- tcg/README | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/tcg/README b/tcg/README index 33783ee17b..27846f1ea4 100644 --- a/tcg/README +++ b/tcg/README @@ -141,7 +141,7 @@ Define label 'label' at the current program point. Jump to label. -* brcond_i32/i64 cond, t0, t1, label +* brcond_i32/i64 t0, t1, cond, label Conditional jump if t0 cond t1 is true. cond can be: TCG_COND_EQ @@ -301,13 +301,13 @@ This operation would be equivalent to ********* Conditional moves -* setcond_i32/i64 cond, dest, t1, t2 +* setcond_i32/i64 dest, t1, t2, cond dest = (t1 cond t2) Set DEST to 1 if (T1 cond T2) is true, otherwise set to 0. -* movcond_i32/i64 cond, dest, c1, c2, v1, v2 +* movcond_i32/i64 dest, c1, c2, v1, v2, cond dest = (c1 cond c2 ? v1 : v2) @@ -360,7 +360,7 @@ The following opcodes are internal to TCG. Thus they are to be implemented by 32-bit host code generators, but are not to be emitted by guest translators. They are emitted as needed by inline functions within "tcg-op.h". -* brcond2_i32 cond, t0_low, t0_high, t1_low, t1_high, label +* brcond2_i32 t0_low, t0_high, t1_low, t1_high, cond, label Similar to brcond, except that the 64-bit values T0 and T1 are formed from two 32-bit arguments. @@ -377,7 +377,7 @@ is returned in two 32-bit outputs. Similar to mul, except two 32-bit (unsigned) inputs T1 and T2 yielding the full 64-bit product T0. The later is returned in two 32-bit outputs. -* setcond2_i32 cond, dest, t1_low, t1_high, t2_low, t2_high +* setcond2_i32 dest, t1_low, t1_high, t2_low, t2_high, cond Similar to setcond, except that the 64-bit values T1 and T2 are formed from two 32-bit arguments. The result is a 32-bit value. From 42ce3e2015b26df591e1d4c5aa1814fb8c45c36c Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 21 Sep 2012 17:18:10 -0700 Subject: [PATCH 03/12] tcg: Emit ANDI as EXTU for appropriate constants Note that andi_i64 failed to perform even the minimal optimizations promised by the README. Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/tcg-op.h | 65 ++++++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 10 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 6d28f82ad8..c8633ffd78 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -518,18 +518,34 @@ static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) } } -static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) +static inline void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2) { - /* some cases can be optimized here */ - if (arg2 == 0) { + TCGv_i32 t0; + /* Some cases can be optimized here. */ + switch (arg2) { + case 0: tcg_gen_movi_i32(ret, 0); - } else if (arg2 == 0xffffffff) { + return; + case 0xffffffffu: tcg_gen_mov_i32(ret, arg1); - } else { - TCGv_i32 t0 = tcg_const_i32(arg2); - tcg_gen_and_i32(ret, arg1, t0); - tcg_temp_free_i32(t0); + return; + case 0xffu: + /* Don't recurse with tcg_gen_ext8u_i32. */ + if (TCG_TARGET_HAS_ext8u_i32) { + tcg_gen_op2_i32(INDEX_op_ext8u_i32, ret, arg1); + return; + } + break; + case 0xffffu: + if (TCG_TARGET_HAS_ext16u_i32) { + tcg_gen_op2_i32(INDEX_op_ext16u_i32, ret, arg1); + return; + } + break; } + t0 = tcg_const_i32(arg2); + tcg_gen_and_i32(ret, arg1, t0); + tcg_temp_free_i32(t0); } static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) @@ -1120,9 +1136,38 @@ static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) } } -static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) +static inline void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2) { - TCGv_i64 t0 = tcg_const_i64(arg2); + TCGv_i64 t0; + /* Some cases can be optimized here. */ + switch (arg2) { + case 0: + tcg_gen_movi_i64(ret, 0); + return; + case 0xffffffffffffffffull: + tcg_gen_mov_i64(ret, arg1); + return; + case 0xffull: + /* Don't recurse with tcg_gen_ext8u_i32. */ + if (TCG_TARGET_HAS_ext8u_i64) { + tcg_gen_op2_i64(INDEX_op_ext8u_i64, ret, arg1); + return; + } + break; + case 0xffffu: + if (TCG_TARGET_HAS_ext16u_i64) { + tcg_gen_op2_i64(INDEX_op_ext16u_i64, ret, arg1); + return; + } + break; + case 0xffffffffull: + if (TCG_TARGET_HAS_ext32u_i64) { + tcg_gen_op2_i64(INDEX_op_ext32u_i64, ret, arg1); + return; + } + break; + } + t0 = tcg_const_i64(arg2); tcg_gen_and_i64(ret, arg1, t0); tcg_temp_free_i64(t0); } From d81ada7fa43e588a24856da4bfcdcac020d8e25b Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 21 Sep 2012 17:18:11 -0700 Subject: [PATCH 04/12] tcg: Optimize initial inputs for ori_i64 Copy the same optimizations from ori_i32. Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/tcg-op.h | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index c8633ffd78..fd1649996c 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -559,9 +559,9 @@ static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) static inline void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { - /* some cases can be optimized here */ - if (arg2 == 0xffffffff) { - tcg_gen_movi_i32(ret, 0xffffffff); + /* Some cases can be optimized here. */ + if (arg2 == -1) { + tcg_gen_movi_i32(ret, -1); } else if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); } else { @@ -1183,9 +1183,16 @@ static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) static inline void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_or_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + /* Some cases can be optimized here. */ + if (arg2 == -1) { + tcg_gen_movi_i64(ret, -1); + } else if (arg2 == 0) { + tcg_gen_mov_i64(ret, arg1); + } else { + TCGv_i64 t0 = tcg_const_i64(arg2); + tcg_gen_or_i64(ret, arg1, t0); + tcg_temp_free_i64(t0); + } } static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) From 6f3bb33eaa79570b7009f3704ca55c4f8296219f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 21 Sep 2012 17:18:12 -0700 Subject: [PATCH 05/12] tcg: Emit XORI as NOT for appropriate constants Note that xori_i64 failed to perform even the minimal optimizations promised by the README. Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/tcg-op.h | 19 +++++++++++++++---- 1 file changed, 15 insertions(+), 4 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index fd1649996c..bcfb60b507 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -582,9 +582,12 @@ static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) static inline void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2) { - /* some cases can be optimized here */ + /* Some cases can be optimized here. */ if (arg2 == 0) { tcg_gen_mov_i32(ret, arg1); + } else if (arg2 == -1 && TCG_TARGET_HAS_not_i32) { + /* Don't recurse with tcg_gen_not_i32. */ + tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg1); } else { TCGv_i32 t0 = tcg_const_i32(arg2); tcg_gen_xor_i32(ret, arg1, t0); @@ -1206,9 +1209,17 @@ static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) static inline void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2) { - TCGv_i64 t0 = tcg_const_i64(arg2); - tcg_gen_xor_i64(ret, arg1, t0); - tcg_temp_free_i64(t0); + /* Some cases can be optimized here. */ + if (arg2 == 0) { + tcg_gen_mov_i64(ret, arg1); + } else if (arg2 == -1 && TCG_TARGET_HAS_not_i64) { + /* Don't recurse with tcg_gen_not_i64. */ + tcg_gen_op2_i64(INDEX_op_not_i64, ret, arg1); + } else { + TCGv_i64 t0 = tcg_const_i64(arg2); + tcg_gen_xor_i64(ret, arg1, t0); + tcg_temp_free_i64(t0); + } } static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) From 77276f6581b660a14bec069ec8d20f1280bddeb6 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 21 Sep 2012 17:18:13 -0700 Subject: [PATCH 06/12] tcg: Implement concat*_i64 with deposit_i64 For tcg_gen_concat_i32_i64 we only use deposit if the host supports it. For tcg_gen_concat32_i64 even if the host does not, as we get identical code before and after. Note that this relies on the ANDI -> EXTU patch for the identity claim. Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/tcg-op.h | 60 ++++++++++++++++++++++++++-------------------------- 1 file changed, 30 insertions(+), 30 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index bcfb60b507..d2fb283764 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -1809,36 +1809,6 @@ static inline void tcg_gen_discard_i64(TCGv_i64 arg) #endif } -static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high) -{ -#if TCG_TARGET_REG_BITS == 32 - tcg_gen_mov_i32(TCGV_LOW(dest), low); - tcg_gen_mov_i32(TCGV_HIGH(dest), high); -#else - TCGv_i64 tmp = tcg_temp_new_i64(); - /* This extension is only needed for type correctness. - We may be able to do better given target specific information. */ - tcg_gen_extu_i32_i64(tmp, high); - tcg_gen_shli_i64(tmp, tmp, 32); - tcg_gen_extu_i32_i64(dest, low); - tcg_gen_or_i64(dest, dest, tmp); - tcg_temp_free_i64(tmp); -#endif -} - -static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, TCGv_i64 high) -{ -#if TCG_TARGET_REG_BITS == 32 - tcg_gen_concat_i32_i64(dest, TCGV_LOW(low), TCGV_LOW(high)); -#else - TCGv_i64 tmp = tcg_temp_new_i64(); - tcg_gen_ext32u_i64(dest, low); - tcg_gen_shli_i64(tmp, high, 32); - tcg_gen_or_i64(dest, dest, tmp); - tcg_temp_free_i64(tmp); -#endif -} - static inline void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) { if (TCG_TARGET_HAS_andc_i32) { @@ -2181,6 +2151,36 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, tcg_temp_free_i64(t1); } +static inline void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, + TCGv_i32 high) +{ +#if TCG_TARGET_REG_BITS == 32 + tcg_gen_mov_i32(TCGV_LOW(dest), low); + tcg_gen_mov_i32(TCGV_HIGH(dest), high); +#else + TCGv_i64 tmp = tcg_temp_new_i64(); + /* These extensions are only needed for type correctness. + We may be able to do better given target specific information. */ + tcg_gen_extu_i32_i64(tmp, high); + tcg_gen_extu_i32_i64(dest, low); + /* If deposit is available, use it. Otherwise use the extra + knowledge that we have of the zero-extensions above. */ + if (TCG_TARGET_HAS_deposit_i64 && TCG_TARGET_deposit_i64_valid(32, 32)) { + tcg_gen_deposit_i64(dest, dest, tmp, 32, 32); + } else { + tcg_gen_shli_i64(tmp, tmp, 32); + tcg_gen_or_i64(dest, dest, tmp); + } + tcg_temp_free_i64(tmp); +#endif +} + +static inline void tcg_gen_concat32_i64(TCGv_i64 dest, TCGv_i64 low, + TCGv_i64 high) +{ + tcg_gen_deposit_i64(dest, low, high, 32, 32); +} + static inline void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2) From c552d6c038f7cf4058d1fd5987118ffd41e0e050 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 21 Sep 2012 17:18:14 -0700 Subject: [PATCH 07/12] tcg: Add tcg_debug_assert Like the C assert macro, except only enabled for CONFIG_DEBUG_TCG, and without having to set _NDEBUG and disable all other asserts at the same time. The use of __builtin_unreachable (when available) gives the compiler the same information, which may (or may not) help it optimize better. Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/tcg.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/tcg/tcg.h b/tcg/tcg.h index 48a56f0b15..4501c1520f 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -530,6 +530,15 @@ do {\ abort();\ } while (0) +#ifdef CONFIG_DEBUG_TCG +# define tcg_debug_assert(X) do { assert(X); } while (0) +#elif QEMU_GNUC_PREREQ(4, 5) +# define tcg_debug_assert(X) \ + do { if (!(X)) { __builtin_unreachable(); } } while (0) +#else +# define tcg_debug_assert(X) do { (void)(X); } while (0) +#endif + void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs); #if TCG_TARGET_REG_BITS == 32 From 717e70368bdc339d241f84aba00ed72d051e0236 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 21 Sep 2012 17:18:15 -0700 Subject: [PATCH 08/12] tcg: Sanity check deposit inputs Given these are constants, checking once here means everything after can assume they're correct. Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/tcg-op.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index d2fb283764..ecb1ac3e2e 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2081,6 +2081,10 @@ static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t mask; TCGv_i32 t1; + tcg_debug_assert(ofs < 32); + tcg_debug_assert(len <= 32); + tcg_debug_assert(ofs + len <= 32); + if (ofs == 0 && len == 32) { tcg_gen_mov_i32(ret, arg2); return; @@ -2112,6 +2116,10 @@ static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t mask; TCGv_i64 t1; + tcg_debug_assert(ofs < 64); + tcg_debug_assert(len <= 64); + tcg_debug_assert(ofs + len <= 64); + if (ofs == 0 && len == 64) { tcg_gen_mov_i64(ret, arg2); return; From 0a209d4bb119b92eb14b9afab55cef5bc0555554 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 21 Sep 2012 17:18:16 -0700 Subject: [PATCH 09/12] tcg: Sanity check goto_tb input Checking that we don't try for idx != [01] is trivial. Checking that we don't issue more than one of any index requires a tad more data and some ifdefs protecting that new variable. Signed-off-by: Richard Henderson Cc: Max Filippov Signed-off-by: Aurelien Jarno --- tcg/tcg-op.h | 9 ++++++++- tcg/tcg.c | 4 ++++ tcg/tcg.h | 1 + 3 files changed, 13 insertions(+), 1 deletion(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index ecb1ac3e2e..9bfed48830 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2275,8 +2275,15 @@ static inline void tcg_gen_exit_tb(tcg_target_long val) tcg_gen_op1i(INDEX_op_exit_tb, val); } -static inline void tcg_gen_goto_tb(int idx) +static inline void tcg_gen_goto_tb(unsigned idx) { + /* We only support two chained exits. */ + tcg_debug_assert(idx <= 1); +#ifdef CONFIG_DEBUG_TCG + /* Verify that we havn't seen this numbered exit before. */ + tcg_debug_assert((tcg_ctx.goto_tb_issue_mask & (1 << idx)) == 0); + tcg_ctx.goto_tb_issue_mask |= 1 << idx; +#endif tcg_gen_op1i(INDEX_op_goto_tb, idx); } diff --git a/tcg/tcg.c b/tcg/tcg.c index b3c265013d..c069e44a0e 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -298,6 +298,10 @@ void tcg_func_start(TCGContext *s) s->nb_labels = 0; s->current_frame_offset = s->frame_start; +#ifdef CONFIG_DEBUG_TCG + s->goto_tb_issue_mask = 0; +#endif + gen_opc_ptr = gen_opc_buf; gen_opparam_ptr = gen_opparam_buf; } diff --git a/tcg/tcg.h b/tcg/tcg.h index 4501c1520f..af7464a650 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -390,6 +390,7 @@ struct TCGContext { #ifdef CONFIG_DEBUG_TCG int temps_in_use; + int goto_tb_issue_mask; #endif }; From a463133ee26b9172728476962eb9d411985b480f Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 24 Sep 2012 13:44:59 -0700 Subject: [PATCH 10/12] tcg: Streamline movcond_i64 using 32-bit arithmetic Avoiding 64-bit arithmetic (outside of the compare) reduces the generated op count from 15 to 12, and the generated code size on i686 from 105 to 88 bytes. Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/tcg-op.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 9bfed48830..027270cd63 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2212,6 +2212,25 @@ static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2) { +#if TCG_TARGET_REG_BITS == 32 + TCGv_i32 t0 = tcg_temp_new_i32(); + TCGv_i32 t1 = tcg_temp_new_i32(); + tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, + TCGV_LOW(c1), TCGV_HIGH(c1), + TCGV_LOW(c2), TCGV_HIGH(c2), cond); + tcg_gen_neg_i32(t0, t0); + + tcg_gen_and_i32(t1, TCGV_LOW(v1), t0); + tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0); + tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1); + + tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0); + tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0); + tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1); + + tcg_temp_free_i32(t0); + tcg_temp_free_i32(t1); +#else if (TCG_TARGET_HAS_movcond_i64) { tcg_gen_op6i_i64(INDEX_op_movcond_i64, ret, c1, c2, v1, v2, cond); } else { @@ -2225,6 +2244,7 @@ static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); } +#endif } /***************************************/ From a80a6b63e362cc8eda7aae5b4c3f9e4e49013d62 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Mon, 24 Sep 2012 13:45:00 -0700 Subject: [PATCH 11/12] tcg: Streamline movcond_i64 using movcond_i32 When movcond_i32 is available we can further reduce the generated op count from 12 to 6, and the generated code size on i686 from 88 to 74 bytes. Signed-off-by: Richard Henderson Signed-off-by: Aurelien Jarno --- tcg/tcg-op.h | 22 +++++++++++++++------- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index 027270cd63..bd93fe4f03 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -2218,16 +2218,24 @@ static inline void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, tcg_gen_op6i_i32(INDEX_op_setcond2_i32, t0, TCGV_LOW(c1), TCGV_HIGH(c1), TCGV_LOW(c2), TCGV_HIGH(c2), cond); - tcg_gen_neg_i32(t0, t0); - tcg_gen_and_i32(t1, TCGV_LOW(v1), t0); - tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0); - tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1); + if (TCG_TARGET_HAS_movcond_i32) { + tcg_gen_movi_i32(t1, 0); + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_LOW(ret), t0, t1, + TCGV_LOW(v1), TCGV_LOW(v2)); + tcg_gen_movcond_i32(TCG_COND_NE, TCGV_HIGH(ret), t0, t1, + TCGV_HIGH(v1), TCGV_HIGH(v2)); + } else { + tcg_gen_neg_i32(t0, t0); - tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0); - tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0); - tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1); + tcg_gen_and_i32(t1, TCGV_LOW(v1), t0); + tcg_gen_andc_i32(TCGV_LOW(ret), TCGV_LOW(v2), t0); + tcg_gen_or_i32(TCGV_LOW(ret), TCGV_LOW(ret), t1); + tcg_gen_and_i32(t1, TCGV_HIGH(v1), t0); + tcg_gen_andc_i32(TCGV_HIGH(ret), TCGV_HIGH(v2), t0); + tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(ret), t1); + } tcg_temp_free_i32(t0); tcg_temp_free_i32(t1); #else From f813cb838f19ee8637d3c365659e6a6bb0c9c974 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 26 Sep 2012 00:30:12 +0200 Subject: [PATCH 12/12] tcg/i386: fix build with -march < i686 The movcond_i32 op has to be protected with TCG_TARGET_HAS_movcond_i32 to fix the build with -march < i686. Thanks to Richard Henderson for the hint. Reported-by: Alex Barcelo Signed-off-by: Aurelien Jarno --- tcg/i386/tcg-target.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index 122d63630c..0e218c8614 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -1893,7 +1893,9 @@ static const TCGTargetOpDef x86_op_defs[] = { { INDEX_op_setcond_i32, { "q", "r", "ri" } }, { INDEX_op_deposit_i32, { "Q", "0", "Q" } }, +#if TCG_TARGET_HAS_movcond_i32 { INDEX_op_movcond_i32, { "r", "r", "ri", "r", "0" } }, +#endif #if TCG_TARGET_REG_BITS == 32 { INDEX_op_mulu2_i32, { "a", "d", "a", "r" } },