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hw/intc/arm_gic: Fix writes to GICD_ITARGETSRn 

According to the GICv2 specification section 4.3.12, "Interrupt Processor
Targets Registers, GICD_ITARGETSRn":

"Any change to a CPU targets field value:
[...]
* Has an effect on any pending interrupts. This means:
  - adding a CPU interface to the target list of a pending interrupt makes that
    interrupt pending on that CPU interface
  - removing a CPU interface from the target list of a pending interrupt
    removes the pending state of that interrupt on that CPU interface."

Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Message-id: 20240524113256.8102-3-sebastian.huber@embedded-brains.de
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Sebastian Huber 2024-05-24 13:32:56 +02:00 committed by Peter Maydell
parent f5e328fef0
commit d9aff83ad5
1 changed files with 7 additions and 0 deletions
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7
hw/intc/arm_gic.c
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@ -1410,6 +1410,13 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
value = ALL_CPU_MASK;
}
s->irq_target[irq] = value & ALL_CPU_MASK;
if (irq >= GIC_INTERNAL && s->irq_state[irq].pending) {
/*
* Changing the target of an interrupt that is currently
* pending updates the set of CPUs it is pending on.
*/
s->irq_state[irq].pending = value & ALL_CPU_MASK;
}
}
} else if (offset < 0xf00) {
/* Interrupt Configuration. */