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target/arm: Name CPState type 

Give this enum a name and use in ARMCPRegInfo,
add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.

Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2022-04-30 22:49:50 -07:00 committed by Peter Maydell
parent 3910733718
commit d95101d602
2 changed files with 7 additions and 5 deletions
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6
target/arm/cpregs.h
View File

@ -114,11 +114,11 @@ enum {
* Note that we rely on the values of these enums as we iterate through * Note that we rely on the values of these enums as we iterate through
* the various states in some places. * the various states in some places.
*/ */
enum { typedef enum {
ARM_CP_STATE_AA32 = 0, ARM_CP_STATE_AA32 = 0,
ARM_CP_STATE_AA64 = 1, ARM_CP_STATE_AA64 = 1,
ARM_CP_STATE_BOTH = 2, ARM_CP_STATE_BOTH = 2,
}; } CPState;
/* /*
* ARM CP register secure state flags. These flags identify security state * ARM CP register secure state flags. These flags identify security state
@ -260,7 +260,7 @@ struct ARMCPRegInfo {
uint8_t opc1; uint8_t opc1;
uint8_t opc2; uint8_t opc2;
/* Execution state in which this register is visible: ARM_CP_STATE_* */ /* Execution state in which this register is visible: ARM_CP_STATE_* */
int state; CPState state;
/* Register type: ARM_CP_* bits/values */ /* Register type: ARM_CP_* bits/values */
int type; int type;
/* Access rights: PL*_[RW] */ /* Access rights: PL*_[RW] */

6
target/arm/helper.c
View File

@ -8502,7 +8502,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
} }
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
void *opaque, int state, int secstate, void *opaque, CPState state, int secstate,
int crm, int opc1, int opc2, int crm, int opc1, int opc2,
const char *name) const char *name)
{ {
@ -8662,13 +8662,15 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
* bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
* the register, if any. * the register, if any.
*/ */
int crm, opc1, opc2, state; int crm, opc1, opc2;
int crmmin = (r->crm == CP_ANY) ? 0 : r->crm; int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
int crmmax = (r->crm == CP_ANY) ? 15 : r->crm; int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1; int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1; int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2; int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2; int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
CPState state;
/* 64 bit registers have only CRm and Opc1 fields */ /* 64 bit registers have only CRm and Opc1 fields */
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
/* op0 only exists in the AArch64 encodings */ /* op0 only exists in the AArch64 encodings */