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target/arm: Name CPState type
Give this enum a name and use in ARMCPRegInfo, add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20220501055028.646596-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -114,11 +114,11 @@ enum {
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* Note that we rely on the values of these enums as we iterate through
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* the various states in some places.
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*/
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enum {
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typedef enum {
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ARM_CP_STATE_AA32 = 0,
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ARM_CP_STATE_AA64 = 1,
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ARM_CP_STATE_BOTH = 2,
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};
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} CPState;
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/*
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* ARM CP register secure state flags. These flags identify security state
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@ -260,7 +260,7 @@ struct ARMCPRegInfo {
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uint8_t opc1;
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uint8_t opc2;
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/* Execution state in which this register is visible: ARM_CP_STATE_* */
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int state;
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CPState state;
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/* Register type: ARM_CP_* bits/values */
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int type;
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/* Access rights: PL*_[RW] */
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@ -8502,7 +8502,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
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}
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static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
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void *opaque, int state, int secstate,
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void *opaque, CPState state, int secstate,
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int crm, int opc1, int opc2,
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const char *name)
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{
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@ -8662,13 +8662,15 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
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* bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
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* the register, if any.
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*/
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int crm, opc1, opc2, state;
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int crm, opc1, opc2;
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int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
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int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
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int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
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int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
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int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
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int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
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CPState state;
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/* 64 bit registers have only CRm and Opc1 fields */
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assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
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/* op0 only exists in the AArch64 encodings */
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