mirror of https://github.com/xemu-project/xemu.git
pc_piix: Move kvm irq routing functions out of pc_piix.c
Rename: kvm_piix3_gsi_handlei() -> kvm_pc_gsi_handler() kvm_piix3_setup_irq_routing() -> kvm_pc_setup_irq_routing() This is in preparation for other users, namely q35 at this time. Signed-off-by: Jason Baron <jbaron@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
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a39e356458
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@ -15,6 +15,46 @@
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#include "hw/apic_internal.h"
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#include "hw/apic_internal.h"
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#include "kvm.h"
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#include "kvm.h"
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/* PC Utility function */
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void kvm_pc_setup_irq_routing(bool pci_enabled)
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{
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KVMState *s = kvm_state;
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int i;
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if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
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for (i = 0; i < 8; ++i) {
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if (i == 2) {
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continue;
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}
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
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}
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for (i = 8; i < 16; ++i) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
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}
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if (pci_enabled) {
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for (i = 0; i < 24; ++i) {
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if (i == 0) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
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} else if (i != 2) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i);
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}
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}
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}
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}
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}
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void kvm_pc_gsi_handler(void *opaque, int n, int level)
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{
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GSIState *s = opaque;
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if (n < ISA_NUM_IRQS) {
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/* Kernel will forward to both PIC and IOAPIC */
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qemu_set_irq(s->i8259_irq[n], level);
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} else {
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qemu_set_irq(s->ioapic_irq[n], level);
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}
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}
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typedef struct KVMIOAPICState KVMIOAPICState;
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typedef struct KVMIOAPICState KVMIOAPICState;
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struct KVMIOAPICState {
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struct KVMIOAPICState {
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45
hw/pc_piix.c
45
hw/pc_piix.c
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@ -54,47 +54,6 @@ static const int ide_iobase[MAX_IDE_BUS] = { 0x1f0, 0x170 };
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static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
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static const int ide_iobase2[MAX_IDE_BUS] = { 0x3f6, 0x376 };
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static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
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static const int ide_irq[MAX_IDE_BUS] = { 14, 15 };
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static void kvm_piix3_setup_irq_routing(bool pci_enabled)
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{
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#ifdef CONFIG_KVM
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KVMState *s = kvm_state;
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int i;
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if (kvm_check_extension(s, KVM_CAP_IRQ_ROUTING)) {
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for (i = 0; i < 8; ++i) {
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if (i == 2) {
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continue;
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}
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_MASTER, i);
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}
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for (i = 8; i < 16; ++i) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_PIC_SLAVE, i - 8);
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}
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if (pci_enabled) {
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for (i = 0; i < 24; ++i) {
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if (i == 0) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, 2);
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} else if (i != 2) {
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kvm_irqchip_add_irq_route(s, i, KVM_IRQCHIP_IOAPIC, i);
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}
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}
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}
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}
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#endif /* CONFIG_KVM */
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}
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static void kvm_piix3_gsi_handler(void *opaque, int n, int level)
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{
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GSIState *s = opaque;
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if (n < ISA_NUM_IRQS) {
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/* Kernel will forward to both PIC and IOAPIC */
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qemu_set_irq(s->i8259_irq[n], level);
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} else {
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qemu_set_irq(s->ioapic_irq[n], level);
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}
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}
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/* PC hardware initialisation */
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/* PC hardware initialisation */
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static void pc_init1(MemoryRegion *system_memory,
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static void pc_init1(MemoryRegion *system_memory,
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MemoryRegion *system_io,
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MemoryRegion *system_io,
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@ -160,8 +119,8 @@ static void pc_init1(MemoryRegion *system_memory,
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gsi_state = g_malloc0(sizeof(*gsi_state));
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gsi_state = g_malloc0(sizeof(*gsi_state));
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if (kvm_irqchip_in_kernel()) {
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if (kvm_irqchip_in_kernel()) {
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kvm_piix3_setup_irq_routing(pci_enabled);
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kvm_pc_setup_irq_routing(pci_enabled);
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gsi = qemu_allocate_irqs(kvm_piix3_gsi_handler, gsi_state,
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gsi = qemu_allocate_irqs(kvm_pc_gsi_handler, gsi_state,
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GSI_NUM_PINS);
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GSI_NUM_PINS);
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} else {
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} else {
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gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
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gsi = qemu_allocate_irqs(gsi_handler, gsi_state, GSI_NUM_PINS);
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2
kvm.h
2
kvm.h
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@ -275,4 +275,6 @@ void kvm_irqchip_release_virq(KVMState *s, int virq);
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int kvm_irqchip_add_irqfd_notifier(KVMState *s, EventNotifier *n, int virq);
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int kvm_irqchip_add_irqfd_notifier(KVMState *s, EventNotifier *n, int virq);
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int kvm_irqchip_remove_irqfd_notifier(KVMState *s, EventNotifier *n, int virq);
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int kvm_irqchip_remove_irqfd_notifier(KVMState *s, EventNotifier *n, int virq);
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void kvm_pc_gsi_handler(void *opaque, int n, int level);
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void kvm_pc_setup_irq_routing(bool pci_enabled);
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#endif
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#endif
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