mirror of https://github.com/xemu-project/xemu.git
hw/intc/arm_gicv3: Implement NMI interrupt priority
If GICD_CTLR_DS bit is zero and the NMI is non-secure, the NMI priority is higher than 0x80, otherwise it is higher than 0x0. And save the interrupt non-maskable property in hppi.nmi to deliver NMI exception. Since both GICR and GICD can deliver NMI, it is both necessary to check whether the pending irq is NMI in gicv3_redist_update_noirqset and gicv3_update_noirqset. Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20240407081733.3231820-21-ruanjinjie@huawei.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -21,7 +21,7 @@
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#include "hw/intc/arm_gicv3.h"
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#include "gicv3_internal.h"
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static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
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static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio, bool nmi)
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{
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/* Return true if this IRQ at this priority should take
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* precedence over the current recorded highest priority
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@ -30,14 +30,23 @@ static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
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* is the same as this one (a property which the calling code
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* relies on).
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*/
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if (prio < cs->hppi.prio) {
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return true;
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if (prio != cs->hppi.prio) {
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return prio < cs->hppi.prio;
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}
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/*
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* The same priority IRQ with non-maskable property should signal to
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* the CPU as it have the priority higher than the labelled 0x80 or 0x00.
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*/
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if (nmi != cs->hppi.nmi) {
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return nmi;
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}
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/* If multiple pending interrupts have the same priority then it is an
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* IMPDEF choice which of them to signal to the CPU. We choose to
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* signal the one with the lowest interrupt number.
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*/
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if (prio == cs->hppi.prio && irq <= cs->hppi.irq) {
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if (irq <= cs->hppi.irq) {
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return true;
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}
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return false;
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@ -129,6 +138,40 @@ static uint32_t gicr_int_pending(GICv3CPUState *cs)
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return pend;
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}
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static bool gicv3_get_priority(GICv3CPUState *cs, bool is_redist, int irq,
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uint8_t *prio)
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{
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uint32_t nmi = 0x0;
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if (is_redist) {
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nmi = extract32(cs->gicr_inmir0, irq, 1);
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} else {
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nmi = *gic_bmp_ptr32(cs->gic->nmi, irq);
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nmi = nmi & (1 << (irq & 0x1f));
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}
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if (nmi) {
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/* DS = 0 & Non-secure NMI */
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if (!(cs->gic->gicd_ctlr & GICD_CTLR_DS) &&
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((is_redist && extract32(cs->gicr_igroupr0, irq, 1)) ||
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(!is_redist && gicv3_gicd_group_test(cs->gic, irq)))) {
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*prio = 0x80;
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} else {
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*prio = 0x0;
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}
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return true;
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}
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if (is_redist) {
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*prio = cs->gicr_ipriorityr[irq];
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} else {
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*prio = cs->gic->gicd_ipriority[irq];
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}
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return false;
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}
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/* Update the interrupt status after state in a redistributor
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* or CPU interface has changed, but don't tell the CPU i/f.
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*/
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@ -141,6 +184,7 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
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uint8_t prio;
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int i;
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uint32_t pend;
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bool nmi = false;
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/* Find out which redistributor interrupts are eligible to be
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* signaled to the CPU interface.
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@ -152,10 +196,11 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
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if (!(pend & (1 << i))) {
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continue;
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}
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prio = cs->gicr_ipriorityr[i];
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if (irqbetter(cs, i, prio)) {
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nmi = gicv3_get_priority(cs, true, i, &prio);
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if (irqbetter(cs, i, prio, nmi)) {
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cs->hppi.irq = i;
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cs->hppi.prio = prio;
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cs->hppi.nmi = nmi;
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seenbetter = true;
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}
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}
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@ -168,9 +213,10 @@ static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
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if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
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(cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) &&
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(cs->hpplpi.prio != 0xff)) {
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if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
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if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio, cs->hpplpi.nmi)) {
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cs->hppi.irq = cs->hpplpi.irq;
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cs->hppi.prio = cs->hpplpi.prio;
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cs->hppi.nmi = cs->hpplpi.nmi;
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cs->hppi.grp = cs->hpplpi.grp;
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seenbetter = true;
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}
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@ -213,6 +259,7 @@ static void gicv3_update_noirqset(GICv3State *s, int start, int len)
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int i;
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uint8_t prio;
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uint32_t pend = 0;
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bool nmi = false;
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assert(start >= GIC_INTERNAL);
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assert(len > 0);
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@ -240,10 +287,11 @@ static void gicv3_update_noirqset(GICv3State *s, int start, int len)
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*/
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continue;
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}
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prio = s->gicd_ipriority[i];
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if (irqbetter(cs, i, prio)) {
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nmi = gicv3_get_priority(cs, false, i, &prio);
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if (irqbetter(cs, i, prio, nmi)) {
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cs->hppi.irq = i;
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cs->hppi.prio = prio;
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cs->hppi.nmi = nmi;
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cs->seenbetter = true;
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}
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}
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@ -293,6 +341,7 @@ void gicv3_full_update_noirqset(GICv3State *s)
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for (i = 0; i < s->num_cpu; i++) {
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s->cpu[i].hppi.prio = 0xff;
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s->cpu[i].hppi.nmi = false;
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}
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/* Note that we can guarantee that these functions will not
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@ -536,8 +536,11 @@ static void arm_gicv3_common_reset_hold(Object *obj)
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memset(cs->gicr_ipriorityr, 0, sizeof(cs->gicr_ipriorityr));
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cs->hppi.prio = 0xff;
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cs->hppi.nmi = false;
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cs->hpplpi.prio = 0xff;
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cs->hpplpi.nmi = false;
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cs->hppvlpi.prio = 0xff;
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cs->hppvlpi.nmi = false;
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/* State in the CPU interface must *not* be reset here, because it
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* is part of the CPU's reset domain, not the GIC device's.
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@ -120,6 +120,7 @@ static void update_for_one_lpi(GICv3CPUState *cs, int irq,
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((prio == hpp->prio) && (irq <= hpp->irq))) {
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hpp->irq = irq;
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hpp->prio = prio;
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hpp->nmi = false;
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/* LPIs and vLPIs are always non-secure Grp1 interrupts */
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hpp->grp = GICV3_G1NS;
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}
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@ -156,6 +157,7 @@ static void update_for_all_lpis(GICv3CPUState *cs, uint64_t ptbase,
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int i, bit;
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hpp->prio = 0xff;
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hpp->nmi = false;
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for (i = GICV3_LPI_INTID_START / 8; i < pendt_size / 8; i++) {
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address_space_read(as, ptbase + i, MEMTXATTRS_UNSPECIFIED, &pend, 1);
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@ -241,6 +243,7 @@ static void gicv3_redist_update_vlpi_only(GICv3CPUState *cs)
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if (!FIELD_EX64(cs->gicr_vpendbaser, GICR_VPENDBASER, VALID)) {
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cs->hppvlpi.prio = 0xff;
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cs->hppvlpi.nmi = false;
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return;
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}
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