From d781cb7798e41141f377784257e27f615041603d Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Tue, 19 Sep 2023 16:07:14 +0200
Subject: [PATCH] target/hppa: Fix extrw and depw with sar for hppa64
These are 32-bit operations regardless of processor.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/translate.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index ffa367b91f..ed88f724ce 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3230,7 +3230,9 @@ static bool trans_extrw_sar(DisasContext *ctx, arg_extrw_sar *a)
tmp = tcg_temp_new();
/* Recall that SAR is using big-endian bit numbering. */
- tcg_gen_xori_reg(tmp, cpu_sar, TARGET_REGISTER_BITS - 1);
+ tcg_gen_andi_reg(tmp, cpu_sar, 31);
+ tcg_gen_xori_reg(tmp, tmp, 31);
+
if (a->se) {
tcg_gen_sar_reg(dest, src, tmp);
tcg_gen_sextract_reg(dest, dest, 0, len);
@@ -3355,7 +3357,8 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c,
tmp = tcg_temp_new();
/* Convert big-endian bit numbering in SAR to left-shift. */
- tcg_gen_xori_reg(shift, cpu_sar, TARGET_REGISTER_BITS - 1);
+ tcg_gen_andi_reg(shift, cpu_sar, 31);
+ tcg_gen_xori_reg(shift, shift, 31);
mask = tcg_temp_new();
tcg_gen_movi_reg(mask, msb + (msb - 1));