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target/riscv: Fix 32-bit HS mode access permissions 

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: cb1ef2061547dc9028ce3cf4f6622588f9c09149.1617290165.git.alistair.francis@wdc.com
This commit is contained in:
Alistair Francis 2021-04-01 11:17:48 -04:00
parent 0e62f92eac
commit d6f20dacea
1 changed files with 5 additions and 1 deletions
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6
target/riscv/csr.c
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@ -181,7 +181,11 @@ static RISCVException hmode(CPURISCVState *env, int csrno)
static RISCVException hmode32(CPURISCVState *env, int csrno) static RISCVException hmode32(CPURISCVState *env, int csrno)
{ {
if (!riscv_cpu_is_32bit(env)) { if (!riscv_cpu_is_32bit(env)) {
return RISCV_EXCP_NONE; if (riscv_cpu_virt_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
} else {
return RISCV_EXCP_VIRT_INSTRUCTION_FAULT;
}
} }
return hmode(env, csrno); return hmode(env, csrno);