mirror of https://github.com/xemu-project/xemu.git
target/arm: Convert Advanced SIMD copy to decodetree
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20240524232121.284515-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
d90a473363
commit
d6edf915c7
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@ -658,3 +658,16 @@ SM3TT2B 11001110 010 ..... 10 .. 11 ..... ..... @crypto3i
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### Cryptographic XAR
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XAR 1100 1110 100 rm:5 imm:6 rn:5 rd:5
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### Advanced SIMD scalar copy
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DUP_element_s 0101 1110 000 imm:5 0 0000 1 rn:5 rd:5
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### Advanced SIMD copy
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DUP_element_v 0 q:1 00 1110 000 imm:5 0 0000 1 rn:5 rd:5
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DUP_general 0 q:1 00 1110 000 imm:5 0 0001 1 rn:5 rd:5
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INS_general 0 1 00 1110 000 imm:5 0 0011 1 rn:5 rd:5
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SMOV 0 q:1 00 1110 000 imm:5 0 0101 1 rn:5 rd:5
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UMOV 0 q:1 00 1110 000 imm:5 0 0111 1 rn:5 rd:5
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INS_element 0 1 10 1110 000 di:5 0 si:4 1 rn:5 rd:5
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@ -4702,6 +4702,145 @@ static bool trans_XAR(DisasContext *s, arg_XAR *a)
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return true;
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}
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/*
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* Advanced SIMD copy
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*/
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static bool decode_esz_idx(int imm, MemOp *pesz, unsigned *pidx)
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{
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unsigned esz = ctz32(imm);
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if (esz <= MO_64) {
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*pesz = esz;
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*pidx = imm >> (esz + 1);
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return true;
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}
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return false;
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}
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static bool trans_DUP_element_s(DisasContext *s, arg_DUP_element_s *a)
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{
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MemOp esz;
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unsigned idx;
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if (!decode_esz_idx(a->imm, &esz, &idx)) {
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return false;
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}
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if (fp_access_check(s)) {
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/*
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* This instruction just extracts the specified element and
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* zero-extends it into the bottom of the destination register.
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*/
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TCGv_i64 tmp = tcg_temp_new_i64();
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read_vec_element(s, tmp, a->rn, idx, esz);
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write_fp_dreg(s, a->rd, tmp);
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}
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return true;
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}
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static bool trans_DUP_element_v(DisasContext *s, arg_DUP_element_v *a)
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{
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MemOp esz;
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unsigned idx;
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if (!decode_esz_idx(a->imm, &esz, &idx)) {
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return false;
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}
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if (esz == MO_64 && !a->q) {
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return false;
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}
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if (fp_access_check(s)) {
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tcg_gen_gvec_dup_mem(esz, vec_full_reg_offset(s, a->rd),
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vec_reg_offset(s, a->rn, idx, esz),
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a->q ? 16 : 8, vec_full_reg_size(s));
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}
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return true;
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}
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static bool trans_DUP_general(DisasContext *s, arg_DUP_general *a)
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{
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MemOp esz;
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unsigned idx;
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if (!decode_esz_idx(a->imm, &esz, &idx)) {
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return false;
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}
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if (esz == MO_64 && !a->q) {
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return false;
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}
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if (fp_access_check(s)) {
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tcg_gen_gvec_dup_i64(esz, vec_full_reg_offset(s, a->rd),
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a->q ? 16 : 8, vec_full_reg_size(s),
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cpu_reg(s, a->rn));
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}
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return true;
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}
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static bool do_smov_umov(DisasContext *s, arg_SMOV *a, MemOp is_signed)
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{
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MemOp esz;
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unsigned idx;
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if (!decode_esz_idx(a->imm, &esz, &idx)) {
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return false;
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}
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if (is_signed) {
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if (esz == MO_64 || (esz == MO_32 && !a->q)) {
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return false;
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}
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} else {
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if (esz == MO_64 ? !a->q : a->q) {
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return false;
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}
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}
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if (fp_access_check(s)) {
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TCGv_i64 tcg_rd = cpu_reg(s, a->rd);
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read_vec_element(s, tcg_rd, a->rn, idx, esz | is_signed);
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if (is_signed && !a->q) {
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tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
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}
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}
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return true;
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}
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TRANS(SMOV, do_smov_umov, a, MO_SIGN)
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TRANS(UMOV, do_smov_umov, a, 0)
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static bool trans_INS_general(DisasContext *s, arg_INS_general *a)
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{
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MemOp esz;
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unsigned idx;
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if (!decode_esz_idx(a->imm, &esz, &idx)) {
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return false;
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}
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if (fp_access_check(s)) {
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write_vec_element(s, cpu_reg(s, a->rn), a->rd, idx, esz);
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clear_vec_high(s, true, a->rd);
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}
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return true;
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}
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static bool trans_INS_element(DisasContext *s, arg_INS_element *a)
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{
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MemOp esz;
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unsigned didx, sidx;
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if (!decode_esz_idx(a->di, &esz, &didx)) {
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return false;
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}
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sidx = a->si >> esz;
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if (fp_access_check(s)) {
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TCGv_i64 tmp = tcg_temp_new_i64();
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read_vec_element(s, tmp, a->rn, sidx, esz);
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write_vec_element(s, tmp, a->rd, didx, esz);
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/* INS is considered a 128-bit write for SVE. */
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clear_vec_high(s, true, a->rd);
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}
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return true;
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}
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/* Shift a TCGv src by TCGv shift_amount, put result in dst.
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* Note that it is the caller's responsibility to ensure that the
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* shift amount is in range (ie 0..31 or 0..63) and provide the ARM
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@ -7760,268 +7899,6 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn)
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write_fp_dreg(s, rd, tcg_res);
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}
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/* DUP (Element, Vector)
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*
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* 31 30 29 21 20 16 15 10 9 5 4 0
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* +---+---+-------------------+--------+-------------+------+------+
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* | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
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* +---+---+-------------------+--------+-------------+------+------+
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*
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* size: encoded in imm5 (see ARM ARM LowestSetBit())
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*/
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static void handle_simd_dupe(DisasContext *s, int is_q, int rd, int rn,
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int imm5)
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{
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int size = ctz32(imm5);
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int index;
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if (size > 3 || (size == 3 && !is_q)) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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index = imm5 >> (size + 1);
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tcg_gen_gvec_dup_mem(size, vec_full_reg_offset(s, rd),
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vec_reg_offset(s, rn, index, size),
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is_q ? 16 : 8, vec_full_reg_size(s));
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}
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/* DUP (element, scalar)
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* 31 21 20 16 15 10 9 5 4 0
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* +-----------------------+--------+-------------+------+------+
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* | 0 1 0 1 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 0 1 | Rn | Rd |
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* +-----------------------+--------+-------------+------+------+
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*/
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static void handle_simd_dupes(DisasContext *s, int rd, int rn,
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int imm5)
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{
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int size = ctz32(imm5);
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int index;
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TCGv_i64 tmp;
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if (size > 3) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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index = imm5 >> (size + 1);
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/* This instruction just extracts the specified element and
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* zero-extends it into the bottom of the destination register.
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*/
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tmp = tcg_temp_new_i64();
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read_vec_element(s, tmp, rn, index, size);
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write_fp_dreg(s, rd, tmp);
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}
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/* DUP (General)
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*
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* 31 30 29 21 20 16 15 10 9 5 4 0
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* +---+---+-------------------+--------+-------------+------+------+
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* | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 0 1 1 | Rn | Rd |
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* +---+---+-------------------+--------+-------------+------+------+
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*
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* size: encoded in imm5 (see ARM ARM LowestSetBit())
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*/
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static void handle_simd_dupg(DisasContext *s, int is_q, int rd, int rn,
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int imm5)
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{
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int size = ctz32(imm5);
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uint32_t dofs, oprsz, maxsz;
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if (size > 3 || ((size == 3) && !is_q)) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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dofs = vec_full_reg_offset(s, rd);
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oprsz = is_q ? 16 : 8;
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maxsz = vec_full_reg_size(s);
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tcg_gen_gvec_dup_i64(size, dofs, oprsz, maxsz, cpu_reg(s, rn));
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}
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/* INS (Element)
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*
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* 31 21 20 16 15 14 11 10 9 5 4 0
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* +-----------------------+--------+------------+---+------+------+
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* | 0 1 1 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
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* +-----------------------+--------+------------+---+------+------+
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*
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* size: encoded in imm5 (see ARM ARM LowestSetBit())
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* index: encoded in imm5<4:size+1>
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*/
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static void handle_simd_inse(DisasContext *s, int rd, int rn,
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int imm4, int imm5)
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{
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int size = ctz32(imm5);
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int src_index, dst_index;
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TCGv_i64 tmp;
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if (size > 3) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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dst_index = extract32(imm5, 1+size, 5);
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src_index = extract32(imm4, size, 4);
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tmp = tcg_temp_new_i64();
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read_vec_element(s, tmp, rn, src_index, size);
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write_vec_element(s, tmp, rd, dst_index, size);
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/* INS is considered a 128-bit write for SVE. */
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clear_vec_high(s, true, rd);
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}
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/* INS (General)
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*
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* 31 21 20 16 15 10 9 5 4 0
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* +-----------------------+--------+-------------+------+------+
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* | 0 1 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 0 1 1 1 | Rn | Rd |
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* +-----------------------+--------+-------------+------+------+
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*
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* size: encoded in imm5 (see ARM ARM LowestSetBit())
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* index: encoded in imm5<4:size+1>
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*/
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static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
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{
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int size = ctz32(imm5);
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int idx;
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if (size > 3) {
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unallocated_encoding(s);
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return;
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}
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if (!fp_access_check(s)) {
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return;
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}
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idx = extract32(imm5, 1 + size, 4 - size);
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write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
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/* INS is considered a 128-bit write for SVE. */
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clear_vec_high(s, true, rd);
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}
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/*
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* UMOV (General)
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* SMOV (General)
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*
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* 31 30 29 21 20 16 15 12 10 9 5 4 0
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* +---+---+-------------------+--------+-------------+------+------+
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* | 0 | Q | 0 0 1 1 1 0 0 0 0 | imm5 | 0 0 1 U 1 1 | Rn | Rd |
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* +---+---+-------------------+--------+-------------+------+------+
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*
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* U: unsigned when set
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* size: encoded in imm5 (see ARM ARM LowestSetBit())
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*/
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static void handle_simd_umov_smov(DisasContext *s, int is_q, int is_signed,
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int rn, int rd, int imm5)
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{
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int size = ctz32(imm5);
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int element;
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TCGv_i64 tcg_rd;
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/* Check for UnallocatedEncodings */
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if (is_signed) {
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if (size > 2 || (size == 2 && !is_q)) {
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unallocated_encoding(s);
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return;
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}
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} else {
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if (size > 3
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|| (size < 3 && is_q)
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|| (size == 3 && !is_q)) {
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unallocated_encoding(s);
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return;
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}
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}
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if (!fp_access_check(s)) {
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return;
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}
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element = extract32(imm5, 1+size, 4);
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tcg_rd = cpu_reg(s, rd);
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read_vec_element(s, tcg_rd, rn, element, size | (is_signed ? MO_SIGN : 0));
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if (is_signed && !is_q) {
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tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
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}
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}
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/* AdvSIMD copy
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* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
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* +---+---+----+-----------------+------+---+------+---+------+------+
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* | 0 | Q | op | 0 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
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* +---+---+----+-----------------+------+---+------+---+------+------+
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*/
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static void disas_simd_copy(DisasContext *s, uint32_t insn)
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{
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int imm4 = extract32(insn, 11, 4);
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int op = extract32(insn, 29, 1);
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int is_q = extract32(insn, 30, 1);
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int imm5 = extract32(insn, 16, 5);
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if (op) {
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if (is_q) {
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/* INS (element) */
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handle_simd_inse(s, rd, rn, imm4, imm5);
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} else {
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unallocated_encoding(s);
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}
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} else {
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switch (imm4) {
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case 0:
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/* DUP (element - vector) */
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handle_simd_dupe(s, is_q, rd, rn, imm5);
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break;
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case 1:
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/* DUP (general) */
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handle_simd_dupg(s, is_q, rd, rn, imm5);
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break;
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case 3:
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if (is_q) {
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/* INS (general) */
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handle_simd_insg(s, rd, rn, imm5);
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} else {
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unallocated_encoding(s);
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}
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break;
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case 5:
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case 7:
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/* UMOV/SMOV (is_q indicates 32/64; imm4 indicates signedness) */
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handle_simd_umov_smov(s, is_q, (imm4 == 5), rn, rd, imm5);
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break;
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default:
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unallocated_encoding(s);
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break;
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}
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}
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}
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/* AdvSIMD modified immediate
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* 31 30 29 28 19 18 16 15 12 11 10 9 5 4 0
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* +---+---+----+---------------------+-----+-------+----+---+-------+------+
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@ -8085,29 +7962,6 @@ static void disas_simd_mod_imm(DisasContext *s, uint32_t insn)
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}
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}
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/* AdvSIMD scalar copy
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* 31 30 29 28 21 20 16 15 14 11 10 9 5 4 0
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* +-----+----+-----------------+------+---+------+---+------+------+
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* | 0 1 | op | 1 1 1 1 0 0 0 0 | imm5 | 0 | imm4 | 1 | Rn | Rd |
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* +-----+----+-----------------+------+---+------+---+------+------+
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*/
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static void disas_simd_scalar_copy(DisasContext *s, uint32_t insn)
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{
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int imm4 = extract32(insn, 11, 4);
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int imm5 = extract32(insn, 16, 5);
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int op = extract32(insn, 29, 1);
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if (op != 0 || imm4 != 0) {
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unallocated_encoding(s);
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return;
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}
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/* DUP (element, scalar) */
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handle_simd_dupes(s, rd, rn, imm5);
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}
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/* AdvSIMD scalar pairwise
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* 31 30 29 28 24 23 22 21 17 16 12 11 10 9 5 4 0
|
||||
* +-----+---+-----------+------+-----------+--------+-----+------+------+
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@ -13614,7 +13468,6 @@ static const AArch64DecodeTable data_proc_simd[] = {
|
|||
{ 0x0e200000, 0x9f200c00, disas_simd_three_reg_diff },
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{ 0x0e200800, 0x9f3e0c00, disas_simd_two_reg_misc },
|
||||
{ 0x0e300800, 0x9f3e0c00, disas_simd_across_lanes },
|
||||
{ 0x0e000400, 0x9fe08400, disas_simd_copy },
|
||||
{ 0x0f000000, 0x9f000400, disas_simd_indexed }, /* vector indexed */
|
||||
/* simd_mod_imm decode is a subset of simd_shift_imm, so must precede it */
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||||
{ 0x0f000400, 0x9ff80400, disas_simd_mod_imm },
|
||||
|
|
@ -13627,7 +13480,6 @@ static const AArch64DecodeTable data_proc_simd[] = {
|
|||
{ 0x5e200000, 0xdf200c00, disas_simd_scalar_three_reg_diff },
|
||||
{ 0x5e200800, 0xdf3e0c00, disas_simd_scalar_two_reg_misc },
|
||||
{ 0x5e300800, 0xdf3e0c00, disas_simd_scalar_pairwise },
|
||||
{ 0x5e000400, 0xdfe08400, disas_simd_scalar_copy },
|
||||
{ 0x5f000000, 0xdf000400, disas_simd_indexed }, /* scalar indexed */
|
||||
{ 0x5f000400, 0xdf800400, disas_simd_scalar_shift_imm },
|
||||
{ 0x0e400400, 0x9f60c400, disas_simd_three_reg_same_fp16 },
|
||||
|
|
|
|||
Loading…
Reference in New Issue