mirror of https://github.com/xemu-project/xemu.git
sparc64: clean up pci bridge map
- remove unused host state and store pci bus pointer only - do not map host state access into unused 1fe.10000000 range - reorder pci region registration - assign pci i/o region to isa_mem_base Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Igor V. Kovalenko
Blue Swirl
parent
5910b047a0
commit
d63baf92e3
49
hw/apb_pci.c
49
hw/apb_pci.c
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@ -65,7 +65,7 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0)
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typedef struct APBState {
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SysBusDevice busdev;
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PCIHostState host_state;
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PCIBus *bus;
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ReadWriteHandler pci_config_handler;
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uint32_t iommu[4];
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uint32_t pci_control[16];
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@ -191,7 +191,7 @@ static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr,
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val = qemu_bswap_len(val, size);
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
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pci_data_write(s->host_state.bus, addr, val, size);
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pci_data_write(s->bus, addr, val, size);
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}
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static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
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@ -200,7 +200,7 @@ static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
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uint32_t ret;
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APBState *s = container_of(h, APBState, pci_config_handler);
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ret = pci_data_read(s->host_state.bus, addr, size);
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ret = pci_data_read(s->bus, addr, size);
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ret = qemu_bswap_len(ret, size);
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " -> %x\n", __func__, addr, ret);
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return ret;
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@ -331,37 +331,37 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base,
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s = sysbus_from_qdev(dev);
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/* apb_config */
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sysbus_mmio_map(s, 0, special_base);
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/* PCI configuration space */
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sysbus_mmio_map(s, 1, special_base + 0x1000000ULL);
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/* pci_ioport */
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sysbus_mmio_map(s, 1, special_base + 0x2000000ULL);
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/* pci_config */
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sysbus_mmio_map(s, 2, special_base + 0x1000000ULL);
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/* mem_data */
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sysbus_mmio_map(s, 3, mem_base);
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sysbus_mmio_map(s, 2, special_base + 0x2000000ULL);
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d = FROM_SYSBUS(APBState, s);
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d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
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d->bus = pci_register_bus(&d->busdev.qdev, "pci",
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pci_apb_set_irq, pci_pbm_map_irq, d,
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0, 32);
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pci_bus_set_mem_base(d->host_state.bus, mem_base);
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pci_bus_set_mem_base(d->bus, mem_base);
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for (i = 0; i < 32; i++) {
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sysbus_connect_irq(s, i, pic[i]);
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}
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pci_create_simple(d->host_state.bus, 0, "pbm");
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pci_create_simple(d->bus, 0, "pbm");
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/* APB secondary busses */
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*bus2 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 0),
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*bus2 = pci_bridge_init(d->bus, PCI_DEVFN(1, 0),
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PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
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pci_apb_map_irq,
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"Advanced PCI Bus secondary bridge 1");
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apb_pci_bridge_init(*bus2);
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*bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1),
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*bus3 = pci_bridge_init(d->bus, PCI_DEVFN(1, 1),
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PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA,
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pci_apb_map_irq,
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"Advanced PCI Bus secondary bridge 2");
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apb_pci_bridge_init(*bus3);
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return d->host_state.bus;
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return d->bus;
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}
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static void pci_pbm_reset(DeviceState *d)
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@ -382,7 +382,7 @@ static void pci_pbm_reset(DeviceState *d)
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static int pci_pbm_init_device(SysBusDevice *dev)
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{
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APBState *s;
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int pci_mem_data, apb_config, pci_ioport, pci_config;
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int pci_config, apb_config, pci_ioport;
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unsigned int i;
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s = FROM_SYSBUS(APBState, dev);
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@ -396,20 +396,23 @@ static int pci_pbm_init_device(SysBusDevice *dev)
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/* apb_config */
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apb_config = cpu_register_io_memory(apb_config_read,
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apb_config_write, s);
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/* at region 0 */
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sysbus_init_mmio(dev, 0x10000ULL, apb_config);
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/* pci_ioport */
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pci_ioport = cpu_register_io_memory(pci_apb_ioread,
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pci_apb_iowrite, s);
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sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
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/* pci_config */
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/* PCI configuration space */
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s->pci_config_handler.read = apb_pci_config_read;
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s->pci_config_handler.write = apb_pci_config_write;
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pci_config = cpu_register_io_memory_simple(&s->pci_config_handler);
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assert(pci_config >= 0);
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/* at region 1 */
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sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
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/* mem_data */
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pci_mem_data = pci_host_data_register_mmio(&s->host_state, 1);
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sysbus_init_mmio(dev, 0x10000000ULL, pci_mem_data);
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/* pci_ioport */
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pci_ioport = cpu_register_io_memory(pci_apb_ioread,
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pci_apb_iowrite, s);
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/* at region 2 */
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sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
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return 0;
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}
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@ -70,7 +70,7 @@
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#define PROM_VADDR 0x000ffd00000ULL
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#define APB_SPECIAL_BASE 0x1fe00000000ULL
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#define APB_MEM_BASE 0x1ff00000000ULL
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#define VGA_BASE (APB_MEM_BASE + 0x400000ULL)
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#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL)
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#define PROM_FILENAME "openbios-sparc64"
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#define NVRAM_SIZE 0x2000
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#define MAX_IDE_BUS 2
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@ -766,7 +766,7 @@ static void sun4uv_init(ram_addr_t RAM_size,
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irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
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pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
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&pci_bus3);
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isa_mem_base = VGA_BASE;
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isa_mem_base = APB_PCI_IO_BASE;
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pci_vga_init(pci_bus, 0, 0);
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// XXX Should be pci_bus3
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