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target/riscv: Simplify arguments for riscv_csrrw_check 

Remove RISCVCPU argument, and get cfg infomation from CPURISCVState
directly.

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20230309071329.45932-5-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Weiwei Li 2023-03-09 15:13:29 +08:00 committed by Alistair Francis
parent bbb9fc2591
commit d53ae79b28
1 changed files with 4 additions and 8 deletions
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12
target/riscv/csr.c
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@ -3756,15 +3756,14 @@ static RISCVException rmw_seed(CPURISCVState *env, int csrno,
static inline RISCVException riscv_csrrw_check(CPURISCVState *env, static inline RISCVException riscv_csrrw_check(CPURISCVState *env,
int csrno, int csrno,
bool write_mask, bool write_mask)
RISCVCPU *cpu)
{ {
/* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */ /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails */
bool read_only = get_field(csrno, 0xC00) == 3; bool read_only = get_field(csrno, 0xC00) == 3;
int csr_min_priv = csr_ops[csrno].min_priv_ver; int csr_min_priv = csr_ops[csrno].min_priv_ver;
/* ensure the CSR extension is enabled */ /* ensure the CSR extension is enabled */
if (!cpu->cfg.ext_icsr) { if (!riscv_cpu_cfg(env)->ext_icsr) {
return RISCV_EXCP_ILLEGAL_INST; return RISCV_EXCP_ILLEGAL_INST;
} }
@ -3860,9 +3859,7 @@ RISCVException riscv_csrrw(CPURISCVState *env, int csrno,
target_ulong *ret_value, target_ulong *ret_value,
target_ulong new_value, target_ulong write_mask) target_ulong new_value, target_ulong write_mask)
{ {
RISCVCPU *cpu = env_archcpu(env); RISCVException ret = riscv_csrrw_check(env, csrno, write_mask);
RISCVException ret = riscv_csrrw_check(env, csrno, write_mask, cpu);
if (ret != RISCV_EXCP_NONE) { if (ret != RISCV_EXCP_NONE) {
return ret; return ret;
} }
@ -3915,9 +3912,8 @@ RISCVException riscv_csrrw_i128(CPURISCVState *env, int csrno,
Int128 new_value, Int128 write_mask) Int128 new_value, Int128 write_mask)
{ {
RISCVException ret; RISCVException ret;
RISCVCPU *cpu = env_archcpu(env);
ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask), cpu); ret = riscv_csrrw_check(env, csrno, int128_nz(write_mask));
if (ret != RISCV_EXCP_NONE) { if (ret != RISCV_EXCP_NONE) {
return ret; return ret;
} }