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target/microblaze: Convert to 3-phase reset 

Convert the microblaze CPU class to use 3-phase reset, so it doesn't
need to use device_class_set_parent_reset() any more.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com>
Reviewed-by: Taylor Simpson <tsimpson@quicinc.com>
Message-id: 20221124115023.2437291-10-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-11-24 11:50:12 +00:00
parent bf90b345d7
commit d4bc6c1a79
2 changed files with 10 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
target/microblaze/cpu-qom.h
View File

@ -30,7 +30,7 @@ OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU)
/** /**
* MicroBlazeCPUClass: * MicroBlazeCPUClass:
* @parent_realize: The parent class' realize handler. * @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler. * @parent_phases: The parent class' reset phase handlers.
* *
* A MicroBlaze CPU model. * A MicroBlaze CPU model.
*/ */
@ -40,7 +40,7 @@ struct MicroBlazeCPUClass {
/*< public >*/ /*< public >*/
DeviceRealize parent_realize; DeviceRealize parent_realize;
DeviceReset parent_reset; ResettablePhases parent_phases;
}; };

12
target/microblaze/cpu.c
View File

@ -162,14 +162,16 @@ static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
} }
#endif #endif
static void mb_cpu_reset(DeviceState *dev) static void mb_cpu_reset_hold(Object *obj)
{ {
CPUState *s = CPU(dev); CPUState *s = CPU(obj);
MicroBlazeCPU *cpu = MICROBLAZE_CPU(s); MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
CPUMBState *env = &cpu->env; CPUMBState *env = &cpu->env;
mcc->parent_reset(dev); if (mcc->parent_phases.hold) {
mcc->parent_phases.hold(obj);
}
memset(env, 0, offsetof(CPUMBState, end_reset_fields)); memset(env, 0, offsetof(CPUMBState, end_reset_fields));
env->res_addr = RES_ADDR_NONE; env->res_addr = RES_ADDR_NONE;
@ -399,10 +401,12 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data)
DeviceClass *dc = DEVICE_CLASS(oc); DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc);
MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc); MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
ResettableClass *rc = RESETTABLE_CLASS(oc);
device_class_set_parent_realize(dc, mb_cpu_realizefn, device_class_set_parent_realize(dc, mb_cpu_realizefn,
&mcc->parent_realize); &mcc->parent_realize);
device_class_set_parent_reset(dc, mb_cpu_reset, &mcc->parent_reset); resettable_class_set_parent_phases(rc, NULL, mb_cpu_reset_hold, NULL,
&mcc->parent_phases);
cc->class_by_name = mb_cpu_class_by_name; cc->class_by_name = mb_cpu_class_by_name;
cc->has_work = mb_cpu_has_work; cc->has_work = mb_cpu_has_work;