mirror of https://github.com/xemu-project/xemu.git
target/mips: Advance pc after semihosting exception
Delay generating the exception until after we know the
insn length, and record that length in env->error_code.
Fixes: 8ec7e3c53d
("target/mips: Use an exception for semihosting")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1126
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
parent
430a388ef4
commit
d44971e725
|
@ -826,7 +826,7 @@ static void gen_pool16c_insn(DisasContext *ctx)
|
|||
break;
|
||||
case SDBBP16:
|
||||
if (is_uhi(extract32(ctx->opcode, 0, 4))) {
|
||||
generate_exception_end(ctx, EXCP_SEMIHOST);
|
||||
ctx->base.is_jmp = DISAS_SEMIHOST;
|
||||
} else {
|
||||
/*
|
||||
* XXX: not clear which exception should be raised
|
||||
|
@ -942,7 +942,7 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)
|
|||
case R6_SDBBP16:
|
||||
/* SDBBP16 */
|
||||
if (is_uhi(extract32(ctx->opcode, 6, 4))) {
|
||||
generate_exception_end(ctx, EXCP_SEMIHOST);
|
||||
ctx->base.is_jmp = DISAS_SEMIHOST;
|
||||
} else {
|
||||
if (ctx->hflags & MIPS_HFLAG_SBRI) {
|
||||
generate_exception(ctx, EXCP_RI);
|
||||
|
@ -1311,7 +1311,7 @@ static void gen_pool32axf(CPUMIPSState *env, DisasContext *ctx, int rt, int rs)
|
|||
break;
|
||||
case SDBBP:
|
||||
if (is_uhi(extract32(ctx->opcode, 16, 10))) {
|
||||
generate_exception_end(ctx, EXCP_SEMIHOST);
|
||||
ctx->base.is_jmp = DISAS_SEMIHOST;
|
||||
} else {
|
||||
check_insn(ctx, ISA_MIPS_R1);
|
||||
if (ctx->hflags & MIPS_HFLAG_SBRI) {
|
||||
|
|
|
@ -952,7 +952,7 @@ static int decode_ase_mips16e(CPUMIPSState *env, DisasContext *ctx)
|
|||
break;
|
||||
case RR_SDBBP:
|
||||
if (is_uhi(extract32(ctx->opcode, 5, 6))) {
|
||||
generate_exception_end(ctx, EXCP_SEMIHOST);
|
||||
ctx->base.is_jmp = DISAS_SEMIHOST;
|
||||
} else {
|
||||
/*
|
||||
* XXX: not clear which exception should be raised
|
||||
|
|
|
@ -3695,7 +3695,7 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx)
|
|||
break;
|
||||
case NM_SDBBP:
|
||||
if (is_uhi(extract32(ctx->opcode, 0, 19))) {
|
||||
generate_exception_end(ctx, EXCP_SEMIHOST);
|
||||
ctx->base.is_jmp = DISAS_SEMIHOST;
|
||||
} else {
|
||||
if (ctx->hflags & MIPS_HFLAG_SBRI) {
|
||||
gen_reserved_instruction(ctx);
|
||||
|
@ -4634,7 +4634,7 @@ static int decode_isa_nanomips(CPUMIPSState *env, DisasContext *ctx)
|
|||
break;
|
||||
case NM_SDBBP16:
|
||||
if (is_uhi(extract32(ctx->opcode, 0, 3))) {
|
||||
generate_exception_end(ctx, EXCP_SEMIHOST);
|
||||
ctx->base.is_jmp = DISAS_SEMIHOST;
|
||||
} else {
|
||||
if (ctx->hflags & MIPS_HFLAG_SBRI) {
|
||||
gen_reserved_instruction(ctx);
|
||||
|
|
|
@ -1056,6 +1056,7 @@ void mips_cpu_do_interrupt(CPUState *cs)
|
|||
case EXCP_SEMIHOST:
|
||||
cs->exception_index = EXCP_NONE;
|
||||
mips_semihosting(env);
|
||||
env->active_tc.PC += env->error_code;
|
||||
return;
|
||||
case EXCP_DSS:
|
||||
env->CP0_Debug |= 1 << CP0DB_DSS;
|
||||
|
|
|
@ -1213,9 +1213,6 @@ TCGv_i64 fpu_f64[32];
|
|||
|
||||
#include "exec/gen-icount.h"
|
||||
|
||||
#define DISAS_STOP DISAS_TARGET_0
|
||||
#define DISAS_EXIT DISAS_TARGET_1
|
||||
|
||||
static const char regnames_HI[][4] = {
|
||||
"HI0", "HI1", "HI2", "HI3",
|
||||
};
|
||||
|
@ -13902,7 +13899,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx)
|
|||
break;
|
||||
case R6_OPC_SDBBP:
|
||||
if (is_uhi(extract32(ctx->opcode, 6, 20))) {
|
||||
generate_exception_end(ctx, EXCP_SEMIHOST);
|
||||
ctx->base.is_jmp = DISAS_SEMIHOST;
|
||||
} else {
|
||||
if (ctx->hflags & MIPS_HFLAG_SBRI) {
|
||||
gen_reserved_instruction(ctx);
|
||||
|
@ -14314,7 +14311,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx)
|
|||
break;
|
||||
case OPC_SDBBP:
|
||||
if (is_uhi(extract32(ctx->opcode, 6, 20))) {
|
||||
generate_exception_end(ctx, EXCP_SEMIHOST);
|
||||
ctx->base.is_jmp = DISAS_SEMIHOST;
|
||||
} else {
|
||||
/*
|
||||
* XXX: not clear which exception should be raised
|
||||
|
@ -16098,6 +16095,9 @@ static void mips_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
|
|||
if (is_slot) {
|
||||
gen_branch(ctx, insn_bytes);
|
||||
}
|
||||
if (ctx->base.is_jmp == DISAS_SEMIHOST) {
|
||||
generate_exception_err(ctx, EXCP_SEMIHOST, insn_bytes);
|
||||
}
|
||||
ctx->base.pc_next += insn_bytes;
|
||||
|
||||
if (ctx->base.is_jmp != DISAS_NEXT) {
|
||||
|
|
|
@ -51,6 +51,10 @@ typedef struct DisasContext {
|
|||
int gi;
|
||||
} DisasContext;
|
||||
|
||||
#define DISAS_STOP DISAS_TARGET_0
|
||||
#define DISAS_EXIT DISAS_TARGET_1
|
||||
#define DISAS_SEMIHOST DISAS_TARGET_2
|
||||
|
||||
/* MIPS major opcodes */
|
||||
#define MASK_OP_MAJOR(op) (op & (0x3F << 26))
|
||||
|
||||
|
|
Loading…
Reference in New Issue