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target/mips: Add emulation of MMI instruction PCPYH 

Add emulation of MMI instruction PCPYH. The emulation is implemented
using TCG front end operations directly to achieve better performance.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com>
Message-Id: <1551712405-2530-2-git-send-email-mateja.marjanovic@rt-rk.com>
This commit is contained in:
Mateja Marjanovic 2019-03-04 16:13:13 +01:00 committed by Aleksandar Markovic
parent 60905286cb
commit d3434d9f78
1 changed files with 65 additions and 1 deletions
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66
target/mips/translate.c
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@ -24357,6 +24357,68 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
* PEXTUW * PEXTUW
*/ */
/*
* PCPYH rd, rt
*
* Parallel Copy Halfword
*
* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
* +-----------+---------+---------+---------+---------+-----------+
* | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 |
* +-----------+---------+---------+---------+---------+-----------+
*/
static void gen_mmi_pcpyh(DisasContext *ctx)
{
uint32_t pd, rt, rd;
uint32_t opcode;
opcode = ctx->opcode;
pd = extract32(opcode, 21, 5);
rt = extract32(opcode, 16, 5);
rd = extract32(opcode, 11, 5);
if (unlikely(pd != 0)) {
generate_exception_end(ctx, EXCP_RI);
} else if (rd == 0) {
/* nop */
} else if (rt == 0) {
tcg_gen_movi_i64(cpu_gpr[rd], 0);
tcg_gen_movi_i64(cpu_mmr[rd], 0);
} else {
TCGv_i64 t0 = tcg_temp_new();
TCGv_i64 t1 = tcg_temp_new();
uint64_t mask = (1ULL << 16) - 1;
tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
tcg_gen_movi_i64(t1, 0);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_mov_i64(cpu_gpr[rd], t1);
tcg_gen_andi_i64(t0, cpu_mmr[rt], mask);
tcg_gen_movi_i64(t1, 0);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_shli_i64(t0, t0, 16);
tcg_gen_or_i64(t1, t0, t1);
tcg_gen_mov_i64(cpu_mmr[rd], t1);
tcg_temp_free(t0);
tcg_temp_free(t1);
}
}
#endif #endif
@ -27409,10 +27471,12 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */ case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */ case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */ case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
case MMI_OPC_3_PCPYH: /* TODO: MMI_OPC_3_PCPYH */
case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */ case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */ generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
break; break;
case MMI_OPC_3_PCPYH:
gen_mmi_pcpyh(ctx);
break;
default: default:
MIPS_INVAL("TX79 MMI class MMI3"); MIPS_INVAL("TX79 MMI class MMI3");
generate_exception_end(ctx, EXCP_RI); generate_exception_end(ctx, EXCP_RI);