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target/mips: Add emulation of MMI instruction PCPYH
Add emulation of MMI instruction PCPYH. The emulation is implemented using TCG front end operations directly to achieve better performance. Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Message-Id: <1551712405-2530-2-git-send-email-mateja.marjanovic@rt-rk.com>
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@ -24357,6 +24357,68 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
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* PEXTUW
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*/
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/*
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* PCPYH rd, rt
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*
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* Parallel Copy Halfword
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*
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-----------+---------+---------+---------+---------+-----------+
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* | MMI |0 0 0 0 0| rt | rd | PCPYH | MMI3 |
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* +-----------+---------+---------+---------+---------+-----------+
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*/
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static void gen_mmi_pcpyh(DisasContext *ctx)
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{
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uint32_t pd, rt, rd;
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uint32_t opcode;
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opcode = ctx->opcode;
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pd = extract32(opcode, 21, 5);
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rt = extract32(opcode, 16, 5);
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rd = extract32(opcode, 11, 5);
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if (unlikely(pd != 0)) {
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generate_exception_end(ctx, EXCP_RI);
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} else if (rd == 0) {
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/* nop */
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} else if (rt == 0) {
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tcg_gen_movi_i64(cpu_gpr[rd], 0);
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tcg_gen_movi_i64(cpu_mmr[rd], 0);
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} else {
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TCGv_i64 t0 = tcg_temp_new();
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TCGv_i64 t1 = tcg_temp_new();
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uint64_t mask = (1ULL << 16) - 1;
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tcg_gen_andi_i64(t0, cpu_gpr[rt], mask);
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tcg_gen_movi_i64(t1, 0);
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tcg_gen_or_i64(t1, t0, t1);
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tcg_gen_shli_i64(t0, t0, 16);
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tcg_gen_or_i64(t1, t0, t1);
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tcg_gen_shli_i64(t0, t0, 16);
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tcg_gen_or_i64(t1, t0, t1);
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tcg_gen_shli_i64(t0, t0, 16);
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tcg_gen_or_i64(t1, t0, t1);
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tcg_gen_mov_i64(cpu_gpr[rd], t1);
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tcg_gen_andi_i64(t0, cpu_mmr[rt], mask);
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tcg_gen_movi_i64(t1, 0);
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tcg_gen_or_i64(t1, t0, t1);
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tcg_gen_shli_i64(t0, t0, 16);
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tcg_gen_or_i64(t1, t0, t1);
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tcg_gen_shli_i64(t0, t0, 16);
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tcg_gen_or_i64(t1, t0, t1);
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tcg_gen_shli_i64(t0, t0, 16);
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tcg_gen_or_i64(t1, t0, t1);
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tcg_gen_mov_i64(cpu_mmr[rd], t1);
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tcg_temp_free(t0);
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tcg_temp_free(t1);
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}
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}
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#endif
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@ -27409,10 +27471,12 @@ static void decode_mmi3(CPUMIPSState *env, DisasContext *ctx)
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case MMI_OPC_3_POR: /* TODO: MMI_OPC_3_POR */
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case MMI_OPC_3_PNOR: /* TODO: MMI_OPC_3_PNOR */
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case MMI_OPC_3_PEXCH: /* TODO: MMI_OPC_3_PEXCH */
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case MMI_OPC_3_PCPYH: /* TODO: MMI_OPC_3_PCPYH */
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case MMI_OPC_3_PEXCW: /* TODO: MMI_OPC_3_PEXCW */
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generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI3 */
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break;
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case MMI_OPC_3_PCPYH:
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gen_mmi_pcpyh(ctx);
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break;
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default:
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MIPS_INVAL("TX79 MMI class MMI3");
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generate_exception_end(ctx, EXCP_RI);
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