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target/ppc: Move xxpermdi to decodetree 

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Matheus Ferst <matheus.ferst@eldorado.org.br>
Message-Id: <20220225210936.1749575-32-matheus.ferst@eldorado.org.br>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
This commit is contained in:
Matheus Ferst 2022-03-02 06:51:38 +01:00 committed by Cédric Le Goater
parent 6a94bf196c
commit d31b2c1940
3 changed files with 36 additions and 41 deletions
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4
target/ppc/insn32.decode
View File

@ -155,6 +155,9 @@
&XX3 xt xa xb &XX3 xt xa xb
@XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb @XX3 ...... ..... ..... ..... ........ ... &XX3 xt=%xx_xt xa=%xx_xa xb=%xx_xb
&XX3_dm xt xa xb dm
@XX3_dm ...... ..... ..... ..... . dm:2 ..... ... &XX3_dm xt=%xx_xt xa=%xx_xa xb=%xx_xb
&XX4 xt xa xb xc &XX4 xt xa xb xc
@XX4 ...... ..... ..... ..... ..... .. .... &XX4 xt=%xx_xt xa=%xx_xa xb=%xx_xb xc=%xx_xc @XX4 ...... ..... ..... ..... ..... .. .... &XX4 xt=%xx_xt xa=%xx_xa xb=%xx_xb xc=%xx_xc
@ -608,6 +611,7 @@ XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2
XXPERM 111100 ..... ..... ..... 00011010 ... @XX3 XXPERM 111100 ..... ..... ..... 00011010 ... @XX3
XXPERMR 111100 ..... ..... ..... 00111010 ... @XX3 XXPERMR 111100 ..... ..... ..... 00111010 ... @XX3
XXPERMDI 111100 ..... ..... ..... 0 .. 01010 ... @XX3_dm
XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4 XXSEL 111100 ..... ..... ..... ..... 11 .... @XX4

71
target/ppc/translate/vsx-impl.c.inc
View File

@ -665,45 +665,6 @@ static void gen_mtvsrws(DisasContext *ctx)
#endif #endif
static void gen_xxpermdi(DisasContext *ctx)
{
TCGv_i64 xh, xl;
if (unlikely(!ctx->vsx_enabled)) {
gen_exception(ctx, POWERPC_EXCP_VSXU);
return;
}
xh = tcg_temp_new_i64();
xl = tcg_temp_new_i64();
if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
(xT(ctx->opcode) == xB(ctx->opcode)))) {
get_cpu_vsr(xh, xA(ctx->opcode), (DM(ctx->opcode) & 2) == 0);
get_cpu_vsr(xl, xB(ctx->opcode), (DM(ctx->opcode) & 1) == 0);
set_cpu_vsr(xT(ctx->opcode), xh, true);
set_cpu_vsr(xT(ctx->opcode), xl, false);
} else {
if ((DM(ctx->opcode) & 2) == 0) {
get_cpu_vsr(xh, xA(ctx->opcode), true);
set_cpu_vsr(xT(ctx->opcode), xh, true);
} else {
get_cpu_vsr(xh, xA(ctx->opcode), false);
set_cpu_vsr(xT(ctx->opcode), xh, true);
}
if ((DM(ctx->opcode) & 1) == 0) {
get_cpu_vsr(xl, xB(ctx->opcode), true);
set_cpu_vsr(xT(ctx->opcode), xl, false);
} else {
get_cpu_vsr(xl, xB(ctx->opcode), false);
set_cpu_vsr(xT(ctx->opcode), xl, false);
}
}
tcg_temp_free_i64(xh);
tcg_temp_free_i64(xl);
}
#define OP_ABS 1 #define OP_ABS 1
#define OP_NABS 2 #define OP_NABS 2
#define OP_NEG 3 #define OP_NEG 3
@ -1241,6 +1202,38 @@ static bool trans_XXPERMR(DisasContext *ctx, arg_XX3 *a)
return true; return true;
} }
static bool trans_XXPERMDI(DisasContext *ctx, arg_XX3_dm *a)
{
TCGv_i64 t0, t1;
REQUIRE_INSNS_FLAGS2(ctx, VSX);
REQUIRE_VSX(ctx);
t0 = tcg_temp_new_i64();
if (unlikely(a->xt == a->xa || a->xt == a->xb)) {
t1 = tcg_temp_new_i64();
get_cpu_vsr(t0, a->xa, (a->dm & 2) == 0);
get_cpu_vsr(t1, a->xb, (a->dm & 1) == 0);
set_cpu_vsr(a->xt, t0, true);
set_cpu_vsr(a->xt, t1, false);
tcg_temp_free_i64(t1);
} else {
get_cpu_vsr(t0, a->xa, (a->dm & 2) == 0);
set_cpu_vsr(a->xt, t0, true);
get_cpu_vsr(t0, a->xb, (a->dm & 1) == 0);
set_cpu_vsr(a->xt, t0, false);
}
tcg_temp_free_i64(t0);
return true;
}
#define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \ #define GEN_VSX_HELPER_VSX_MADD(name, op1, aop, mop, inval, type) \
static void gen_##name(DisasContext *ctx) \ static void gen_##name(DisasContext *ctx) \
{ \ { \

2
target/ppc/translate/vsx-ops.c.inc
View File

@ -344,5 +344,3 @@ GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300), GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300),
GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300), GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300),
GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),