ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Trivial m68k cleanup 

-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iEYEABECAAYFAlWRZoAACgkQNKT2yavzbFPXawCeMC6tErAzJjeyWYJ62+n3/DOg
 MXEAmgKOGSnDH8e7Rzxfo82H4PRz+cZR
 =kLox
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/vivier/tags/pull-m68k-20150629' into staging

Trivial m68k cleanup

# gpg: Signature made Mon Jun 29 16:38:40 2015 BST using DSA key ID ABF36C53
# gpg: Good signature from "Laurent Vivier <laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier <Laurent@vivier.eu>"
# gpg:                 aka "Laurent Vivier <Laurent@lvivier.info>"
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>"
# gpg:                 aka "[jpeg image of size 3881]"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 9EC7 B78A C0AC E697 5E4B  BDE3 34A4 F6C9 ABF3 6C53

* remotes/vivier/tags/pull-m68k-20150629:
  m68k: remove useless parameter op_size from gen_lea_indexed()
  m68k: remove useless file m68k-qreg.h
  m68k: is_mem is useless

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-06-29 17:03:20 +01:00
parent 2b464e13f0 a435612616
commit d2966f804d
2 changed files with 3 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
target-m68k/m68k-qreg.h
View File

@ -1,11 +0,0 @@
enum {
#define DEFO32(name, offset) QREG_##name,
#define DEFR(name, reg, mode) QREG_##name,
#define DEFF64(name, offset) QREG_##name,
QREG_NULL,
#include "qregs.def"
TARGET_NUM_QREGS = 0x100
#undef DEFO32
#undef DEFR
#undef DEFF64
};

14
target-m68k/translate.c
View File

@ -129,7 +129,6 @@ typedef struct DisasContext {
uint32_t fpcr; uint32_t fpcr;
struct TranslationBlock *tb; struct TranslationBlock *tb;
int singlestep_enabled; int singlestep_enabled;
int is_mem;
TCGv_i64 mactmp; TCGv_i64 mactmp;
int done_mac; int done_mac;
} DisasContext; } DisasContext;
@ -179,7 +178,6 @@ static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign)
{ {
TCGv tmp; TCGv tmp;
int index = IS_USER(s); int index = IS_USER(s);
s->is_mem = 1;
tmp = tcg_temp_new_i32(); tmp = tcg_temp_new_i32();
switch(opsize) { switch(opsize) {
case OS_BYTE: case OS_BYTE:
@ -209,7 +207,6 @@ static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
{ {
TCGv_i64 tmp; TCGv_i64 tmp;
int index = IS_USER(s); int index = IS_USER(s);
s->is_mem = 1;
tmp = tcg_temp_new_i64(); tmp = tcg_temp_new_i64();
tcg_gen_qemu_ldf64(tmp, addr, index); tcg_gen_qemu_ldf64(tmp, addr, index);
gen_throws_exception = gen_last_qop; gen_throws_exception = gen_last_qop;
@ -220,7 +217,6 @@ static inline TCGv_i64 gen_load64(DisasContext * s, TCGv addr)
static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val) static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
{ {
int index = IS_USER(s); int index = IS_USER(s);
s->is_mem = 1;
switch(opsize) { switch(opsize) {
case OS_BYTE: case OS_BYTE:
tcg_gen_qemu_st8(val, addr, index); tcg_gen_qemu_st8(val, addr, index);
@ -241,7 +237,6 @@ static inline void gen_store(DisasContext *s, int opsize, TCGv addr, TCGv val)
static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val) static inline void gen_store64(DisasContext *s, TCGv addr, TCGv_i64 val)
{ {
int index = IS_USER(s); int index = IS_USER(s);
s->is_mem = 1;
tcg_gen_qemu_stf64(val, addr, index); tcg_gen_qemu_stf64(val, addr, index);
gen_throws_exception = gen_last_qop; gen_throws_exception = gen_last_qop;
} }
@ -297,8 +292,7 @@ static TCGv gen_addr_index(uint16_t ext, TCGv tmp)
/* Handle a base + index + displacement effective addresss. /* Handle a base + index + displacement effective addresss.
A NULL_QREG base means pc-relative. */ A NULL_QREG base means pc-relative. */
static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, int opsize, static TCGv gen_lea_indexed(CPUM68KState *env, DisasContext *s, TCGv base)
TCGv base)
{ {
uint32_t offset; uint32_t offset;
uint16_t ext; uint16_t ext;
@ -529,7 +523,7 @@ static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
return tmp; return tmp;
case 6: /* Indirect index + displacement. */ case 6: /* Indirect index + displacement. */
reg = AREG(insn, 0); reg = AREG(insn, 0);
return gen_lea_indexed(env, s, opsize, reg); return gen_lea_indexed(env, s, reg);
case 7: /* Other */ case 7: /* Other */
switch (insn & 7) { switch (insn & 7) {
case 0: /* Absolute short. */ case 0: /* Absolute short. */
@ -545,7 +539,7 @@ static TCGv gen_lea(CPUM68KState *env, DisasContext *s, uint16_t insn,
s->pc += 2; s->pc += 2;
return tcg_const_i32(offset); return tcg_const_i32(offset);
case 3: /* pc index+displacement. */ case 3: /* pc index+displacement. */
return gen_lea_indexed(env, s, opsize, NULL_QREG); return gen_lea_indexed(env, s, NULL_QREG);
case 4: /* Immediate. */ case 4: /* Immediate. */
default: default:
return NULL_QREG; return NULL_QREG;
@ -2227,7 +2221,6 @@ DISAS_INSN(fpu)
mask = 0x80; mask = 0x80;
for (i = 0; i < 8; i++) { for (i = 0; i < 8; i++) {
if (ext & mask) { if (ext & mask) {
s->is_mem = 1;
dest = FREG(i, 0); dest = FREG(i, 0);
if (ext & (1 << 13)) { if (ext & (1 << 13)) {
/* store */ /* store */
@ -2999,7 +2992,6 @@ gen_intermediate_code_internal(M68kCPU *cpu, TranslationBlock *tb,
dc->singlestep_enabled = cs->singlestep_enabled; dc->singlestep_enabled = cs->singlestep_enabled;
dc->fpcr = env->fpcr; dc->fpcr = env->fpcr;
dc->user = (env->sr & SR_S) == 0; dc->user = (env->sr & SR_S) == 0;
dc->is_mem = 0;
dc->done_mac = 0; dc->done_mac = 0;
lj = -1; lj = -1;
num_insns = 0; num_insns = 0;