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target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. 

RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id
as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that
async flag check is performed before invoking semihosting logic.

Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-3-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Rajnesh Kanwal 2023-10-16 12:17:32 +01:00 committed by Alistair Francis
parent a7b6917025
commit d17bcae5f7
1 changed files with 4 additions and 6 deletions
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10
target/riscv/cpu_helper.c
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@ -1605,15 +1605,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong htval = 0; target_ulong htval = 0;
target_ulong mtval2 = 0; target_ulong mtval2 = 0;
if (cause == RISCV_EXCP_SEMIHOST) {
do_common_semihosting(cs);
env->pc += 4;
return;
}
if (!async) { if (!async) {
/* set tval to badaddr for traps with address information */ /* set tval to badaddr for traps with address information */
switch (cause) { switch (cause) {
case RISCV_EXCP_SEMIHOST:
do_common_semihosting(cs);
env->pc += 4;
return;
case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
case RISCV_EXCP_LOAD_ADDR_MIS: case RISCV_EXCP_LOAD_ADDR_MIS: