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target/sparc: Move CASA, CASXA to decodetree 

Remove gen_cas_asi, gen_casx_asi.
Rename gen_cas_asi0 to gen_cas_asi.

Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2023-10-05 00:09:36 -07:00
parent dca544b991
commit d0a11d25f0
2 changed files with 36 additions and 43 deletions
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7
target/sparc/insns.decode
View File

@ -240,6 +240,8 @@ RETRY 10 00001 111110 00000 0 0000000000000
@r_r_r_asi .. rd:5 ...... rs1:5 0 asi:8 rs2_or_imm:5 &r_r_ri_asi imm=0
@r_r_i_asi .. rd:5 ...... rs1:5 1 rs2_or_imm:s13 \
&r_r_ri_asi imm=1 asi=-2
@casa_imm .. rd:5 ...... rs1:5 1 00000000 rs2_or_imm:5 \
&r_r_ri_asi imm=1 asi=-2
LDUW 11 ..... 000000 ..... . ............. @r_r_ri_na
LDUB 11 ..... 000001 ..... . ............. @r_r_ri_na
@ -292,6 +294,11 @@ SWAP 11 ..... 001111 ..... . ............. @r_r_ri_na
SWAP 11 ..... 011111 ..... . ............. @r_r_r_asi # SWAPA
SWAP 11 ..... 011111 ..... . ............. @r_r_i_asi # SWAPA
CASA 11 ..... 111100 ..... . ............. @r_r_r_asi
CASA 11 ..... 111100 ..... . ............. @casa_imm
CASXA 11 ..... 111110 ..... . ............. @r_r_r_asi
CASXA 11 ..... 111110 ..... . ............. @casa_imm
NCP 10 ----- 110110 ----- --------- ----- # v8 CPop1
NCP 10 ----- 110111 ----- --------- ----- # v8 CPop2

72
target/sparc/translate.c
View File

@ -2268,8 +2268,8 @@ static void gen_swap_asi(DisasContext *dc, DisasASI *da,
}
}
static void gen_cas_asi0(DisasContext *dc, DisasASI *da,
TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr)
static void gen_cas_asi(DisasContext *dc, DisasASI *da,
TCGv oldv, TCGv newv, TCGv cmpv, TCGv addr)
{
switch (da->type) {
case GET_ASI_EXCP:
@ -2285,30 +2285,6 @@ static void gen_cas_asi0(DisasContext *dc, DisasASI *da,
}
}
static void __attribute__((unused))
gen_cas_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
{
DisasASI da = get_asi(dc, insn, MO_TEUL);
TCGv oldv = gen_dest_gpr(dc, rd);
TCGv newv = gen_load_gpr(dc, rd);
gen_address_mask(dc, addr);
gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr);
gen_store_gpr(dc, rd, oldv);
}
static void __attribute__((unused))
gen_casx_asi(DisasContext *dc, TCGv addr, TCGv cmpv, int insn, int rd)
{
DisasASI da = get_asi(dc, insn, MO_TEUQ);
TCGv oldv = gen_dest_gpr(dc, rd);
TCGv newv = gen_load_gpr(dc, rd);
gen_address_mask(dc, addr);
gen_cas_asi0(dc, &da, oldv, newv, cmpv, addr);
gen_store_gpr(dc, rd, oldv);
}
static void gen_ldstub_asi(DisasContext *dc, DisasASI *da, TCGv dst, TCGv addr)
{
switch (da->type) {
@ -2913,6 +2889,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
#ifdef TARGET_SPARC64
# define avail_32(C) false
# define avail_ASR17(C) false
# define avail_CASA(C) true
# define avail_DIV(C) true
# define avail_MUL(C) true
# define avail_POWERDOWN(C) false
@ -2922,6 +2899,7 @@ static void gen_faligndata(TCGv dst, TCGv gsr, TCGv s1, TCGv s2)
#else
# define avail_32(C) true
# define avail_ASR17(C) ((C)->def->features & CPU_FEATURE_ASR17)
# define avail_CASA(C) ((C)->def->features & CPU_FEATURE_CASA)
# define avail_DIV(C) ((C)->def->features & CPU_FEATURE_DIV)
# define avail_MUL(C) ((C)->def->features & CPU_FEATURE_MUL)
# define avail_POWERDOWN(C) ((C)->def->features & CPU_FEATURE_POWERDOWN)
@ -4616,6 +4594,28 @@ static bool trans_SWAP(DisasContext *dc, arg_r_r_ri_asi *a)
return advance_pc(dc);
}
static bool do_casa(DisasContext *dc, arg_r_r_ri_asi *a, MemOp mop)
{
TCGv addr, o, n, c;
DisasASI da;
addr = gen_ldst_addr(dc, a->rs1, true, 0);
if (addr == NULL) {
return false;
}
da = resolve_asi(dc, a->asi, mop);
o = gen_dest_gpr(dc, a->rd);
n = gen_load_gpr(dc, a->rd);
c = gen_load_gpr(dc, a->rs2_or_imm);
gen_cas_asi(dc, &da, o, n, c, addr);
gen_store_gpr(dc, a->rd, o);
return advance_pc(dc);
}
TRANS(CASA, CASA, do_casa, a, MO_TEUL)
TRANS(CASXA, 64, do_casa, a, MO_TEUQ)
#define CHECK_IU_FEATURE(dc, FEATURE) \
if (!((dc)->def->features & CPU_FEATURE_ ## FEATURE)) \
goto illegal_insn;
@ -5419,9 +5419,7 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
TCGv cpu_addr = tcg_temp_new();
tcg_gen_mov_tl(cpu_addr, get_src1(dc, insn));
if (xop == 0x3c || xop == 0x3e) {
/* V9 casa/casxa : no offset */
} else if (IS_IMM) { /* immediate */
if (IS_IMM) { /* immediate */
simm = GET_FIELDs(insn, 19, 31);
if (simm != 0) {
tcg_gen_addi_tl(cpu_addr, cpu_addr, simm);
@ -5634,22 +5632,10 @@ static void disas_sparc_legacy(DisasContext *dc, unsigned int insn)
}
gen_stf_asi(dc, cpu_addr, insn, 8, DFPREG(rd));
break;
#endif
case 0x3e: /* V9 casxa */
rs2 = GET_FIELD(insn, 27, 31);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_casx_asi(dc, cpu_addr, cpu_src2, insn, rd);
break;
#endif
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
case 0x3c: /* V9 or LEON3 casa */
#ifndef TARGET_SPARC64
CHECK_IU_FEATURE(dc, CASA);
#endif
rs2 = GET_FIELD(insn, 27, 31);
cpu_src2 = gen_load_gpr(dc, rs2);
gen_cas_asi(dc, cpu_addr, cpu_src2, insn, rd);
break;
#endif
goto illegal_insn; /* in decodetree */
default:
goto illegal_insn;
}