From 632fb2792b558219146eb48b3a8ee5b53026b3e5 Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Wed, 7 Nov 2018 21:51:45 +0000 Subject: [PATCH 1/4] hw/riscv/virt: Free the test device tree node name Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a137a503c..2b38f89070 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -240,6 +240,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); + g_free(nodename); nodename = g_strdup_printf("/uart@%lx", (long)memmap[VIRT_UART0].base); From 40cf6a54c92c475cb2f575561fe67044904c16b7 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Thu, 8 Nov 2018 13:06:27 +0100 Subject: [PATCH 2/4] target/riscv: Fix FCLASS_D being treated as RV64 only Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d147..5359088e24 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1237,13 +1237,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t0); break; -#if defined(TARGET_RISCV64) case OPC_RISC_FMV_X_D: /* also OPC_RISC_FCLASS_D */ switch (rm) { +#if defined(TARGET_RISCV64) case 0: /* FMV */ gen_set_gpr(rd, cpu_fpr[rs1]); break; +#endif case 1: t0 = tcg_temp_new(); gen_helper_fclass_d(t0, cpu_fpr[rs1]); @@ -1255,6 +1256,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } break; +#if defined(TARGET_RISCV64) case OPC_RISC_FMV_D_X: t0 = tcg_temp_new(); gen_get_gpr(t0, rs1); From 657377730647c2156f1e20087e28129dc32e1242 Mon Sep 17 00:00:00 2001 From: Bastian Koppelmann Date: Thu, 8 Nov 2018 13:06:28 +0100 Subject: [PATCH 3/4] target/riscv: Fix sfence.vm/a both available in any priv version sfence.vm has been replaced in priv v1.10 spec by sfence.vma. Reported-by: Richard Henderson Signed-off-by: Bastian Koppelmann Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/translate.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 5359088e24..f44eb9c41b 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1292,10 +1292,14 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, #ifndef CONFIG_USER_ONLY /* Extract funct7 value and check whether it matches SFENCE.VMA */ if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) { - /* sfence.vma */ - /* TODO: handle ASID specific fences */ - gen_helper_tlb_flush(cpu_env); - return; + if (env->priv_ver == PRIV_VERSION_1_10_0) { + /* sfence.vma */ + /* TODO: handle ASID specific fences */ + gen_helper_tlb_flush(cpu_env); + return; + } else { + gen_exception_illegal(ctx); + } } #endif @@ -1342,7 +1346,11 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, gen_helper_wfi(cpu_env); break; case 0x104: /* SFENCE.VM */ - gen_helper_tlb_flush(cpu_env); + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + gen_helper_tlb_flush(cpu_env); + } else { + gen_exception_illegal(ctx); + } break; #endif default: From 3502dc824a7b0218abb49f4350e80a49829748cf Mon Sep 17 00:00:00 2001 From: Palmer Dabbelt Date: Fri, 9 Nov 2018 10:56:50 -0800 Subject: [PATCH 4/4] RISC-V: Respect fences for user-only emulators Our current fence implementation ignores fences for the user-only configurations. This is incorrect but unlikely to manifest: it requires multi-threaded user-only code that takes advantage of the weakness in the host's memory model and can be inlined by TCG. This patch simply treats fences the same way for all our emulators. I've given it to testing as I don't want to construct a test that would actually trigger the failure. Our fence implementation has an additional deficiency where we map all RISC-V fences to full fences. Now that we have a formal memory model for RISC-V we can start to take advantage of the strength bits on our fence instructions. This requires a bit more though, so I'm going to split it out because the implementation is still correct without taking advantage of these weaker fences. Thanks to Richard Henderson for pointing out both of the issues. Signed-off-by: Palmer Dabbelt Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/translate.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index f44eb9c41b..312bf298b3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1776,7 +1776,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) GET_RM(ctx->opcode)); break; case OPC_RISC_FENCE: -#ifndef CONFIG_USER_ONLY if (ctx->opcode & 0x1000) { /* FENCE_I is a no-op in QEMU, * however we need to end the translation block */ @@ -1787,7 +1786,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) /* FENCE is a full memory barrier. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); } -#endif break; case OPC_RISC_SYSTEM: gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,