ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

sbi: convert to memory API 

Signed-off-by: Avi Kivity <avi@redhat.com>
This commit is contained in:
Avi Kivity 2011-10-16 16:11:06 +02:00
parent dc6c1b3732
commit cfee758cc7
1 changed files with 16 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

33
hw/sbi.c
View File

@ -39,6 +39,7 @@
typedef struct SBIState { typedef struct SBIState {
SysBusDevice busdev; SysBusDevice busdev;
MemoryRegion iomem;
uint32_t regs[SBI_NREGS]; uint32_t regs[SBI_NREGS];
uint32_t intreg_pending[MAX_CPUS]; uint32_t intreg_pending[MAX_CPUS];
qemu_irq cpu_irqs[MAX_CPUS]; qemu_irq cpu_irqs[MAX_CPUS];
@ -51,7 +52,8 @@ static void sbi_set_irq(void *opaque, int irq, int level)
{ {
} }
static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr) static uint64_t sbi_mem_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{ {
SBIState *s = opaque; SBIState *s = opaque;
uint32_t saddr, ret; uint32_t saddr, ret;
@ -67,13 +69,14 @@ static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
return ret; return ret;
} }
static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val) static void sbi_mem_write(void *opaque, target_phys_addr_t addr,
uint64_t val, unsigned dize)
{ {
SBIState *s = opaque; SBIState *s = opaque;
uint32_t saddr; uint32_t saddr;
saddr = addr >> 2; saddr = addr >> 2;
DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val); DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, (int)val);
switch (saddr) { switch (saddr) {
default: default:
s->regs[saddr] = val; s->regs[saddr] = val;
@ -81,16 +84,14 @@ static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
} }
} }
static CPUReadMemoryFunc * const sbi_mem_read[3] = { static const MemoryRegionOps sbi_mem_ops = {
NULL, .read = sbi_mem_read,
NULL, .write = sbi_mem_write,
sbi_mem_readl, .endianness = DEVICE_NATIVE_ENDIAN,
}; .valid = {
.min_access_size = 4,
static CPUWriteMemoryFunc * const sbi_mem_write[3] = { .max_access_size = 4,
NULL, },
NULL,
sbi_mem_writel,
}; };
static const VMStateDescription vmstate_sbi = { static const VMStateDescription vmstate_sbi = {
@ -117,7 +118,6 @@ static void sbi_reset(DeviceState *d)
static int sbi_init1(SysBusDevice *dev) static int sbi_init1(SysBusDevice *dev)
{ {
SBIState *s = FROM_SYSBUS(SBIState, dev); SBIState *s = FROM_SYSBUS(SBIState, dev);
int sbi_io_memory;
unsigned int i; unsigned int i;
qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS); qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS);
@ -125,9 +125,8 @@ static int sbi_init1(SysBusDevice *dev)
sysbus_init_irq(dev, &s->cpu_irqs[i]); sysbus_init_irq(dev, &s->cpu_irqs[i]);
} }
sbi_io_memory = cpu_register_io_memory(sbi_mem_read, sbi_mem_write, s, memory_region_init_io(&s->iomem, &sbi_mem_ops, s, "sbi", SBI_SIZE);
DEVICE_NATIVE_ENDIAN); sysbus_init_mmio_region(dev, &s->iomem);
sysbus_init_mmio(dev, SBI_SIZE, sbi_io_memory);
return 0; return 0;
} }