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target-mips: Use mul[us]2 in [D]MULT[U] insns 

Cc: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Richard Henderson 2013-02-19 23:52:10 -08:00 committed by Blue Swirl
parent 2de68a4900
commit ce1dd5d1bb
3 changed files with 20 additions and 42 deletions
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2
target-mips/helper.h
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@ -24,8 +24,6 @@ DEF_HELPER_FLAGS_1(clz, TCG_CALL_NO_RWG_SE, tl, tl)
#ifdef TARGET_MIPS64 #ifdef TARGET_MIPS64
DEF_HELPER_FLAGS_1(dclo, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(dclo, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_FLAGS_1(dclz, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(dclz, TCG_CALL_NO_RWG_SE, tl, tl)
DEF_HELPER_3(dmult, void, env, tl, tl)
DEF_HELPER_3(dmultu, void, env, tl, tl)
#endif #endif
DEF_HELPER_3(muls, tl, env, tl, tl) DEF_HELPER_3(muls, tl, env, tl, tl)

12
target-mips/op_helper.c
View File

@ -267,18 +267,6 @@ target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
(uint64_t)(uint32_t)arg2); (uint64_t)(uint32_t)arg2);
} }
#ifdef TARGET_MIPS64
void helper_dmult(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
{
muls64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
}
void helper_dmultu(CPUMIPSState *env, target_ulong arg1, target_ulong arg2)
{
mulu64(&(env->active_tc.LO[0]), &(env->active_tc.HI[0]), arg1, arg2);
}
#endif
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
static inline hwaddr do_translate_address(CPUMIPSState *env, static inline hwaddr do_translate_address(CPUMIPSState *env,

48
target-mips/translate.c
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@ -2715,47 +2715,39 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
break; break;
case OPC_MULT: case OPC_MULT:
{ {
TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i64 t3 = tcg_temp_new_i64(); TCGv_i32 t3 = tcg_temp_new_i32();
acc = ((ctx->opcode) >> 11) & 0x03; acc = ((ctx->opcode) >> 11) & 0x03;
if (acc != 0) { if (acc != 0) {
check_dsp(ctx); check_dsp(ctx);
} }
tcg_gen_ext_tl_i64(t2, t0); tcg_gen_trunc_tl_i32(t2, t0);
tcg_gen_ext_tl_i64(t3, t1); tcg_gen_trunc_tl_i32(t3, t1);
tcg_gen_mul_i64(t2, t2, t3); tcg_gen_muls2_i32(t2, t3, t2, t3);
tcg_temp_free_i64(t3); tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_trunc_i64_tl(t0, t2); tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
tcg_gen_shri_i64(t2, t2, 32); tcg_temp_free_i32(t2);
tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i32(t3);
tcg_temp_free_i64(t2);
tcg_gen_ext32s_tl(cpu_LO[acc], t0);
tcg_gen_ext32s_tl(cpu_HI[acc], t1);
} }
opn = "mult"; opn = "mult";
break; break;
case OPC_MULTU: case OPC_MULTU:
{ {
TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i32 t2 = tcg_temp_new_i32();
TCGv_i64 t3 = tcg_temp_new_i64(); TCGv_i32 t3 = tcg_temp_new_i32();
acc = ((ctx->opcode) >> 11) & 0x03; acc = ((ctx->opcode) >> 11) & 0x03;
if (acc != 0) { if (acc != 0) {
check_dsp(ctx); check_dsp(ctx);
} }
tcg_gen_ext32u_tl(t0, t0); tcg_gen_trunc_tl_i32(t2, t0);
tcg_gen_ext32u_tl(t1, t1); tcg_gen_trunc_tl_i32(t3, t1);
tcg_gen_extu_tl_i64(t2, t0); tcg_gen_mulu2_i32(t2, t3, t2, t3);
tcg_gen_extu_tl_i64(t3, t1); tcg_gen_ext_i32_tl(cpu_LO[acc], t2);
tcg_gen_mul_i64(t2, t2, t3); tcg_gen_ext_i32_tl(cpu_HI[acc], t3);
tcg_temp_free_i64(t3); tcg_temp_free_i32(t2);
tcg_gen_trunc_i64_tl(t0, t2); tcg_temp_free_i32(t3);
tcg_gen_shri_i64(t2, t2, 32);
tcg_gen_trunc_i64_tl(t1, t2);
tcg_temp_free_i64(t2);
tcg_gen_ext32s_tl(cpu_LO[acc], t0);
tcg_gen_ext32s_tl(cpu_HI[acc], t1);
} }
opn = "multu"; opn = "multu";
break; break;
@ -2791,11 +2783,11 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc,
opn = "ddivu"; opn = "ddivu";
break; break;
case OPC_DMULT: case OPC_DMULT:
gen_helper_dmult(cpu_env, t0, t1); tcg_gen_muls2_i64(cpu_LO[0], cpu_HI[0], t0, t1);
opn = "dmult"; opn = "dmult";
break; break;
case OPC_DMULTU: case OPC_DMULTU:
gen_helper_dmultu(cpu_env, t0, t1); tcg_gen_mulu2_i64(cpu_LO[0], cpu_HI[0], t0, t1);
opn = "dmultu"; opn = "dmultu";
break; break;
#endif #endif