From 0e8153dde7824e672127765914db30eb301f1aa4 Mon Sep 17 00:00:00 2001 From: Andre Beckus Date: Tue, 30 Oct 2012 07:45:07 +0000 Subject: [PATCH 001/291] hw/armv7m_nvic: Implement byte/halfword access for NVIC SCB_SHPRx registers Implement byte/halfword read and write for the NVIC SCB_SHPRx (System Handler Priority Registers). Do this by removing SHPR word access from nvic_readl/writel and adding common code to hande all access sizes in nvic_sysreg_read/write. Because the "nvic_state *s" variable now needs to be declared in nvic_sysreg_read/write, the "void *opaque" parameter of nvic_readl/writel is changed to "nvic_state *s". Signed-off-by: Andre Beckus Signed-off-by: Peter Maydell --- hw/armv7m_nvic.c | 58 +++++++++++++++++++++++------------------------- 1 file changed, 28 insertions(+), 30 deletions(-) diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 35c1aa67e2..8d8d0a4e8b 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -138,9 +138,8 @@ void armv7m_nvic_complete_irq(void *opaque, int irq) gic_complete_irq(&s->gic, 0, irq); } -static uint32_t nvic_readl(void *opaque, uint32_t offset) +static uint32_t nvic_readl(nvic_state *s, uint32_t offset) { - nvic_state *s = (nvic_state *)opaque; uint32_t val; int irq; @@ -216,14 +215,6 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset) case 0xd14: /* Configuration Control. */ /* TODO: Implement Configuration Control bits. */ return 0; - case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */ - irq = offset - 0xd14; - val = 0; - val |= s->gic.priority1[irq++][0]; - val |= s->gic.priority1[irq++][0] << 8; - val |= s->gic.priority1[irq++][0] << 16; - val |= s->gic.priority1[irq][0] << 24; - return val; case 0xd24: /* System Handler Status. */ val = 0; if (s->gic.irq_state[ARMV7M_EXCP_MEM].active) val |= (1 << 0); @@ -285,9 +276,8 @@ static uint32_t nvic_readl(void *opaque, uint32_t offset) } } -static void nvic_writel(void *opaque, uint32_t offset, uint32_t value) +static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) { - nvic_state *s = (nvic_state *)opaque; uint32_t oldval; switch (offset) { case 0x10: /* SysTick Control and Status. */ @@ -356,17 +346,6 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value) case 0xd14: /* Configuration Control. */ /* TODO: Implement control registers. */ goto bad_reg; - case 0xd18: case 0xd1c: case 0xd20: /* System Handler Priority. */ - { - int irq; - irq = offset - 0xd14; - s->gic.priority1[irq++][0] = value & 0xff; - s->gic.priority1[irq++][0] = (value >> 8) & 0xff; - s->gic.priority1[irq++][0] = (value >> 16) & 0xff; - s->gic.priority1[irq][0] = (value >> 24) & 0xff; - gic_update(&s->gic); - } - break; case 0xd24: /* System Handler Control. */ /* TODO: Real hardware allows you to set/clear the active bits under some circumstances. We don't implement this. */ @@ -395,19 +374,26 @@ static void nvic_writel(void *opaque, uint32_t offset, uint32_t value) static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, unsigned size) { - /* At the moment we only support the ID registers for byte/word access. - * This is not strictly correct as a few of the other registers also - * allow byte access. - */ + nvic_state *s = (nvic_state *)opaque; uint32_t offset = addr; - if (offset >= 0xfe0) { + int i; + uint32_t val; + + switch (offset) { + case 0xd18 ... 0xd23: /* System Handler Priority. */ + val = 0; + for (i = 0; i < size; i++) { + val |= s->gic.priority1[(offset - 0xd14) + i][0] << (i * 8); + } + return val; + case 0xfe0 ... 0xfff: /* ID. */ if (offset & 3) { return 0; } return nvic_id[(offset - 0xfe0) >> 2]; } if (size == 4) { - return nvic_readl(opaque, offset); + return nvic_readl(s, offset); } hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset); } @@ -415,9 +401,21 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, static void nvic_sysreg_write(void *opaque, hwaddr addr, uint64_t value, unsigned size) { + nvic_state *s = (nvic_state *)opaque; uint32_t offset = addr; + int i; + + switch (offset) { + case 0xd18 ... 0xd23: /* System Handler Priority. */ + for (i = 0; i < size; i++) { + s->gic.priority1[(offset - 0xd14) + i][0] = + (value >> (i * 8)) & 0xff; + } + gic_update(&s->gic); + return; + } if (size == 4) { - nvic_writel(opaque, offset, value); + nvic_writel(s, offset, value); return; } hw_error("NVIC: Bad write of size %d at offset 0x%x\n", size, offset); From f3cdbc329fa7621ece7e673f23c3101e6b0c952b Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:07 +0000 Subject: [PATCH 002/291] hw/vexpress.c: Don't prematurely explode QEMUMachineInitArgs Don't explode QEMUMachineInitArgs before passing it to the vexpress common init function. Signed-off-by: Peter Maydell --- hw/vexpress.c | 38 +++++++++----------------------------- 1 file changed, 9 insertions(+), 29 deletions(-) diff --git a/hw/vexpress.c b/hw/vexpress.c index 3f7cb66a6b..d93f057bff 100644 --- a/hw/vexpress.c +++ b/hw/vexpress.c @@ -348,12 +348,7 @@ static const VEDBoardInfo a15_daughterboard = { }; static void vexpress_common_init(const VEDBoardInfo *daughterboard, - ram_addr_t ram_size, - const char *boot_device, - const char *kernel_filename, - const char *kernel_cmdline, - const char *initrd_filename, - const char *cpu_model) + QEMUMachineInitArgs *args) { DeviceState *dev, *sysctl, *pl041; qemu_irq pic[64]; @@ -366,7 +361,8 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard, MemoryRegion *sram = g_new(MemoryRegion, 1); const hwaddr *map = daughterboard->motherboard_map; - daughterboard->init(daughterboard, ram_size, cpu_model, pic, &proc_id); + daughterboard->init(daughterboard, args->ram_size, args->cpu_model, + pic, &proc_id); /* Motherboard peripherals: the wiring is the same but the * addresses vary between the legacy and A-Series memory maps. @@ -454,10 +450,10 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard, /* VE_DAPROM: not modelled */ - vexpress_binfo.ram_size = ram_size; - vexpress_binfo.kernel_filename = kernel_filename; - vexpress_binfo.kernel_cmdline = kernel_cmdline; - vexpress_binfo.initrd_filename = initrd_filename; + vexpress_binfo.ram_size = args->ram_size; + vexpress_binfo.kernel_filename = args->kernel_filename; + vexpress_binfo.kernel_cmdline = args->kernel_cmdline; + vexpress_binfo.initrd_filename = args->initrd_filename; vexpress_binfo.nb_cpus = smp_cpus; vexpress_binfo.board_id = VEXPRESS_BOARD_ID; vexpress_binfo.loader_start = daughterboard->loader_start; @@ -469,28 +465,12 @@ static void vexpress_common_init(const VEDBoardInfo *daughterboard, static void vexpress_a9_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - vexpress_common_init(&a9_daughterboard, - ram_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); + vexpress_common_init(&a9_daughterboard, args); } static void vexpress_a15_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - vexpress_common_init(&a15_daughterboard, - ram_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model); + vexpress_common_init(&a15_daughterboard, args); } static QEMUMachine vexpress_a9_machine = { From db4ff6f111c42e2b33eddcf5f20cc53cceda60a2 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:07 +0000 Subject: [PATCH 003/291] hw/realview.c: Don't prematurely explode QEMUMachineInitArgs Don't explode QEMUMachineInitArgs in every realview init function; just pass it to the common realview_init() code instead. Signed-off-by: Peter Maydell --- hw/realview.c | 68 ++++++++++++++------------------------------------- 1 file changed, 19 insertions(+), 49 deletions(-) diff --git a/hw/realview.c b/hw/realview.c index b5cb08cb84..e789c159a9 100644 --- a/hw/realview.c +++ b/hw/realview.c @@ -44,11 +44,8 @@ static const int realview_board_id[] = { 0x76d }; -static void realview_init(ram_addr_t ram_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model, - enum realview_board_type board_type) +static void realview_init(QEMUMachineInitArgs *args, + enum realview_board_type board_type) { ARMCPU *cpu = NULL; CPUARMState *env; @@ -73,6 +70,7 @@ static void realview_init(ram_addr_t ram_size, uint32_t proc_id = 0; uint32_t sys_id; ram_addr_t low_ram_size; + ram_addr_t ram_size = args->ram_size; switch (board_type) { case BOARD_EB: @@ -89,7 +87,7 @@ static void realview_init(ram_addr_t ram_size, break; } for (n = 0; n < smp_cpus; n++) { - cpu = cpu_arm_init(cpu_model); + cpu = cpu_arm_init(args->cpu_model); if (!cpu) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); @@ -321,9 +319,9 @@ static void realview_init(ram_addr_t ram_size, memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); realview_binfo.ram_size = ram_size; - realview_binfo.kernel_filename = kernel_filename; - realview_binfo.kernel_cmdline = kernel_cmdline; - realview_binfo.initrd_filename = initrd_filename; + realview_binfo.kernel_filename = args->kernel_filename; + realview_binfo.kernel_cmdline = args->kernel_cmdline; + realview_binfo.initrd_filename = args->initrd_filename; realview_binfo.nb_cpus = smp_cpus; realview_binfo.board_id = realview_board_id[board_type]; realview_binfo.loader_start = (board_type == BOARD_PB_A8 ? 0x70000000 : 0); @@ -332,62 +330,34 @@ static void realview_init(ram_addr_t ram_size, static void realview_eb_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - if (!cpu_model) { - cpu_model = "arm926"; + if (!args->cpu_model) { + args->cpu_model = "arm926"; } - realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, - initrd_filename, cpu_model, BOARD_EB); + realview_init(args, BOARD_EB); } static void realview_eb_mpcore_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - if (!cpu_model) { - cpu_model = "arm11mpcore"; + if (!args->cpu_model) { + args->cpu_model = "arm11mpcore"; } - realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, - initrd_filename, cpu_model, BOARD_EB_MPCORE); + realview_init(args, BOARD_EB_MPCORE); } static void realview_pb_a8_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - if (!cpu_model) { - cpu_model = "cortex-a8"; + if (!args->cpu_model) { + args->cpu_model = "cortex-a8"; } - realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, - initrd_filename, cpu_model, BOARD_PB_A8); + realview_init(args, BOARD_PB_A8); } static void realview_pbx_a9_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - if (!cpu_model) { - cpu_model = "cortex-a9"; + if (!args->cpu_model) { + args->cpu_model = "cortex-a9"; } - realview_init(ram_size, boot_device, kernel_filename, kernel_cmdline, - initrd_filename, cpu_model, BOARD_PBX_A9); + realview_init(args, BOARD_PBX_A9); } static QEMUMachine realview_eb_machine = { From 1b523b5bfc83b4d7e3c1971e0a8d34aff0a9ecf6 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:07 +0000 Subject: [PATCH 004/291] hw/versatilepb: Don't prematurely explode QEMUMachineInitArgs Don't explode QEMUMachineInitArgs before passing it to the common versatile init function. Signed-off-by: Peter Maydell --- hw/versatilepb.c | 44 +++++++++++--------------------------------- 1 file changed, 11 insertions(+), 33 deletions(-) diff --git a/hw/versatilepb.c b/hw/versatilepb.c index e85f982897..25e652b1aa 100644 --- a/hw/versatilepb.c +++ b/hw/versatilepb.c @@ -167,11 +167,7 @@ static int vpb_sic_init(SysBusDevice *dev) static struct arm_boot_info versatile_binfo; -static void versatile_init(ram_addr_t ram_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model, - int board_id) +static void versatile_init(QEMUMachineInitArgs *args, int board_id) { ARMCPU *cpu; MemoryRegion *sysmem = get_system_memory(); @@ -189,15 +185,15 @@ static void versatile_init(ram_addr_t ram_size, int done_smc = 0; DriveInfo *dinfo; - if (!cpu_model) { - cpu_model = "arm926"; + if (!args->cpu_model) { + args->cpu_model = "arm926"; } - cpu = cpu_arm_init(cpu_model); + cpu = cpu_arm_init(args->cpu_model); if (!cpu) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - memory_region_init_ram(ram, "versatile.ram", ram_size); + memory_region_init_ram(ram, "versatile.ram", args->ram_size); vmstate_register_ram_global(ram); /* ??? RAM should repeat to fill physical memory space. */ /* SDRAM at address zero. */ @@ -340,40 +336,22 @@ static void versatile_init(ram_addr_t ram_size, fprintf(stderr, "qemu: Error registering flash memory.\n"); } - versatile_binfo.ram_size = ram_size; - versatile_binfo.kernel_filename = kernel_filename; - versatile_binfo.kernel_cmdline = kernel_cmdline; - versatile_binfo.initrd_filename = initrd_filename; + versatile_binfo.ram_size = args->ram_size; + versatile_binfo.kernel_filename = args->kernel_filename; + versatile_binfo.kernel_cmdline = args->kernel_cmdline; + versatile_binfo.initrd_filename = args->initrd_filename; versatile_binfo.board_id = board_id; arm_load_kernel(cpu, &versatile_binfo); } static void vpb_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - versatile_init(ram_size, - boot_device, - kernel_filename, kernel_cmdline, - initrd_filename, cpu_model, 0x183); + versatile_init(args, 0x183); } static void vab_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - versatile_init(ram_size, - boot_device, - kernel_filename, kernel_cmdline, - initrd_filename, cpu_model, 0x25e); + versatile_init(args, 0x25e); } static QEMUMachine versatilepb_machine = { From 72a9f5b7c33dfe8832951af1f1e67de10be1a0ce Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:07 +0000 Subject: [PATCH 005/291] hw/spitz: Don't prematurely explode QEMUMachineInitArgs Don't explode QEMUMachineInitArgs before calling common init function. Signed-off-by: Peter Maydell --- hw/spitz.c | 45 ++++++++++----------------------------------- 1 file changed, 10 insertions(+), 35 deletions(-) diff --git a/hw/spitz.c b/hw/spitz.c index 944c274a82..12e2815221 100644 --- a/hw/spitz.c +++ b/hw/spitz.c @@ -879,15 +879,14 @@ static struct arm_boot_info spitz_binfo = { .ram_size = 0x04000000, }; -static void spitz_common_init(ram_addr_t ram_size, - const char *kernel_filename, - const char *kernel_cmdline, const char *initrd_filename, - const char *cpu_model, enum spitz_model_e model, int arm_id) +static void spitz_common_init(QEMUMachineInitArgs *args, + enum spitz_model_e model, int arm_id) { PXA2xxState *mpu; DeviceState *scp0, *scp1 = NULL; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *rom = g_new(MemoryRegion, 1); + const char *cpu_model = args->cpu_model; if (!cpu_model) cpu_model = (model == terrier) ? "pxa270-c5" : "pxa270-c0"; @@ -928,9 +927,9 @@ static void spitz_common_init(ram_addr_t ram_size, /* A 4.0 GB microdrive is permanently sitting in CF slot 0. */ spitz_microdrive_attach(mpu, 0); - spitz_binfo.kernel_filename = kernel_filename; - spitz_binfo.kernel_cmdline = kernel_cmdline; - spitz_binfo.initrd_filename = initrd_filename; + spitz_binfo.kernel_filename = args->kernel_filename; + spitz_binfo.kernel_cmdline = args->kernel_cmdline; + spitz_binfo.initrd_filename = args->initrd_filename; spitz_binfo.board_id = arm_id; arm_load_kernel(mpu->cpu, &spitz_binfo); sl_bootparam_write(SL_PXA_PARAM_BASE); @@ -938,46 +937,22 @@ static void spitz_common_init(ram_addr_t ram_size, static void spitz_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - spitz_common_init(ram_size, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model, spitz, 0x2c9); + spitz_common_init(args, spitz, 0x2c9); } static void borzoi_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - spitz_common_init(ram_size, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model, borzoi, 0x33f); + spitz_common_init(args, borzoi, 0x33f); } static void akita_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - spitz_common_init(ram_size, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model, akita, 0x2e8); + spitz_common_init(args, akita, 0x2e8); } static void terrier_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - spitz_common_init(ram_size, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model, terrier, 0x33f); + spitz_common_init(args, terrier, 0x33f); } static QEMUMachine akitapda_machine = { From 6952625da87175ca9170335803633f91de7f2f2a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:08 +0000 Subject: [PATCH 006/291] hw/omap_sx1: Don't prematurely explode QEMUMachineInitArgs Don't explode QEMUMachineInitArgs before passing it to the omap_sx1 common init function. Signed-off-by: Peter Maydell --- hw/omap_sx1.c | 36 +++++++++--------------------------- 1 file changed, 9 insertions(+), 27 deletions(-) diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c index eb2bf0569c..21a5bbb006 100644 --- a/hw/omap_sx1.c +++ b/hw/omap_sx1.c @@ -97,11 +97,7 @@ static struct arm_boot_info sx1_binfo = { .board_id = 0x265, }; -static void sx1_init(ram_addr_t ram_size, - const char *boot_device, - const char *kernel_filename, const char *kernel_cmdline, - const char *initrd_filename, const char *cpu_model, - const int version) +static void sx1_init(QEMUMachineInitArgs *args, const int version) { struct omap_mpu_state_s *mpu; MemoryRegion *address_space = get_system_memory(); @@ -121,7 +117,7 @@ static void sx1_init(ram_addr_t ram_size, flash_size = flash2_size; } - mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, cpu_model); + mpu = omap310_mpu_init(address_space, sx1_binfo.ram_size, args->cpu_model); /* External Flash (EMIFS) */ memory_region_init_ram(flash, "omap_sx1.flash0-0", flash_size); @@ -192,16 +188,16 @@ static void sx1_init(ram_addr_t ram_size, OMAP_CS1_BASE, &cs[1]); } - if (!kernel_filename && !fl_idx) { + if (!args->kernel_filename && !fl_idx) { fprintf(stderr, "Kernel or Flash image must be specified\n"); exit(1); } /* Load the kernel. */ - if (kernel_filename) { - sx1_binfo.kernel_filename = kernel_filename; - sx1_binfo.kernel_cmdline = kernel_cmdline; - sx1_binfo.initrd_filename = initrd_filename; + if (args->kernel_filename) { + sx1_binfo.kernel_filename = args->kernel_filename; + sx1_binfo.kernel_cmdline = args->kernel_cmdline; + sx1_binfo.initrd_filename = args->initrd_filename; arm_load_kernel(mpu->cpu, &sx1_binfo); } @@ -211,26 +207,12 @@ static void sx1_init(ram_addr_t ram_size, static void sx1_init_v1(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - sx1_init(ram_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model, 1); + sx1_init(args, 1); } static void sx1_init_v2(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - sx1_init(ram_size, boot_device, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model, 2); + sx1_init(args, 2); } static QEMUMachine sx1_machine_v2 = { From 462b69bba32e35c546b6b588f299f1f794409d22 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:08 +0000 Subject: [PATCH 007/291] hw/nseries: Don't prematurely explode QEMUMachineInitArgs Don't explode QEMUMachineInitArgs before passing it to n8x0_init(). Signed-off-by: Peter Maydell --- hw/nseries.c | 39 +++++++++++---------------------------- 1 file changed, 11 insertions(+), 28 deletions(-) diff --git a/hw/nseries.c b/hw/nseries.c index 9306aa15a7..652d9da333 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -1284,17 +1284,15 @@ static int n810_atag_setup(const struct arm_boot_info *info, void *p) return n8x0_atag_setup(p, 810); } -static void n8x0_init(ram_addr_t ram_size, const char *boot_device, - const char *kernel_filename, - const char *kernel_cmdline, const char *initrd_filename, - const char *cpu_model, struct arm_boot_info *binfo, int model) +static void n8x0_init(QEMUMachineInitArgs *args, + struct arm_boot_info *binfo, int model) { MemoryRegion *sysmem = get_system_memory(); struct n800_s *s = (struct n800_s *) g_malloc0(sizeof(*s)); int sdram_size = binfo->ram_size; DisplayState *ds; - s->mpu = omap2420_mpu_init(sysmem, sdram_size, cpu_model); + s->mpu = omap2420_mpu_init(sysmem, sdram_size, args->cpu_model); /* Setup peripherals * @@ -1338,17 +1336,18 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device, n8x0_usb_setup(s); } - if (kernel_filename) { + if (args->kernel_filename) { /* Or at the linux loader. */ - binfo->kernel_filename = kernel_filename; - binfo->kernel_cmdline = kernel_cmdline; - binfo->initrd_filename = initrd_filename; + binfo->kernel_filename = args->kernel_filename; + binfo->kernel_cmdline = args->kernel_cmdline; + binfo->initrd_filename = args->initrd_filename; arm_load_kernel(s->mpu->cpu, binfo); qemu_register_reset(n8x0_boot_init, s); } - if (option_rom[0].name && (boot_device[0] == 'n' || !kernel_filename)) { + if (option_rom[0].name && + (args->boot_device[0] == 'n' || !args->kernel_filename)) { int rom_size; uint8_t nolo_tags[0x10000]; /* No, wait, better start at the ROM. */ @@ -1400,28 +1399,12 @@ static struct arm_boot_info n810_binfo = { static void n800_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - return n8x0_init(ram_size, boot_device, - kernel_filename, kernel_cmdline, initrd_filename, - cpu_model, &n800_binfo, 800); + return n8x0_init(args, &n800_binfo, 800); } static void n810_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - const char *boot_device = args->boot_device; - return n8x0_init(ram_size, boot_device, - kernel_filename, kernel_cmdline, initrd_filename, - cpu_model, &n810_binfo, 810); + return n8x0_init(args, &n810_binfo, 810); } static QEMUMachine n800_machine = { From 6efa6d50387f5f1401c6f1612fb80cba31f7dca4 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:08 +0000 Subject: [PATCH 008/291] hw/mainstone: Don't prematurely explode QEMUMachineInitArgs Don't explode QEMUMachineInitArgs before passing it to mainstone_init(). Signed-off-by: Peter Maydell --- hw/mainstone.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/hw/mainstone.c b/hw/mainstone.c index 3266946954..5bbecb7304 100644 --- a/hw/mainstone.c +++ b/hw/mainstone.c @@ -95,10 +95,8 @@ static struct arm_boot_info mainstone_binfo = { }; static void mainstone_common_init(MemoryRegion *address_space_mem, - ram_addr_t ram_size, - const char *kernel_filename, - const char *kernel_cmdline, const char *initrd_filename, - const char *cpu_model, enum mainstone_model_e model, int arm_id) + QEMUMachineInitArgs *args, + enum mainstone_model_e model, int arm_id) { uint32_t sector_len = 256 * 1024; hwaddr mainstone_flash_base[] = { MST_FLASH_0, MST_FLASH_1 }; @@ -108,6 +106,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem, int i; int be; MemoryRegion *rom = g_new(MemoryRegion, 1); + const char *cpu_model = args->cpu_model; if (!cpu_model) cpu_model = "pxa270-c5"; @@ -164,22 +163,16 @@ static void mainstone_common_init(MemoryRegion *address_space_mem, smc91c111_init(&nd_table[0], MST_ETH_PHYS, qdev_get_gpio_in(mst_irq, ETHERNET_IRQ)); - mainstone_binfo.kernel_filename = kernel_filename; - mainstone_binfo.kernel_cmdline = kernel_cmdline; - mainstone_binfo.initrd_filename = initrd_filename; + mainstone_binfo.kernel_filename = args->kernel_filename; + mainstone_binfo.kernel_cmdline = args->kernel_cmdline; + mainstone_binfo.initrd_filename = args->initrd_filename; mainstone_binfo.board_id = arm_id; arm_load_kernel(mpu->cpu, &mainstone_binfo); } static void mainstone_init(QEMUMachineInitArgs *args) { - ram_addr_t ram_size = args->ram_size; - const char *cpu_model = args->cpu_model; - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - mainstone_common_init(get_system_memory(), ram_size, kernel_filename, - kernel_cmdline, initrd_filename, cpu_model, mainstone, 0x196); + mainstone_common_init(get_system_memory(), args, mainstone, 0x196); } static QEMUMachine mainstone2_machine = { From 7f0f774003e4c6885b34d4c0006f7beff2b529eb Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:08 +0000 Subject: [PATCH 009/291] hw/exynos4_boards: Don't prematurely explode QEMUMachineInitArgs Don't explode QEMUMachineInitArgs before passing it to exynos4_boards_init_common(). Signed-off-by: Peter Maydell --- hw/exynos4_boards.c | 32 +++++++++++--------------------- 1 file changed, 11 insertions(+), 21 deletions(-) diff --git a/hw/exynos4_boards.c b/hw/exynos4_boards.c index 4951064c3f..bc815bbae3 100644 --- a/hw/exynos4_boards.c +++ b/hw/exynos4_boards.c @@ -93,11 +93,8 @@ static void lan9215_init(uint32_t base, qemu_irq irq) } } -static Exynos4210State *exynos4_boards_init_common( - const char *kernel_filename, - const char *kernel_cmdline, - const char *initrd_filename, - Exynos4BoardType board_type) +static Exynos4210State *exynos4_boards_init_common(QEMUMachineInitArgs *args, + Exynos4BoardType board_type) { if (smp_cpus != EXYNOS4210_NCPUS) { fprintf(stderr, "%s board supports only %d CPU cores. Ignoring smp_cpus" @@ -110,9 +107,9 @@ static Exynos4210State *exynos4_boards_init_common( exynos4_board_binfo.board_id = exynos4_board_id[board_type]; exynos4_board_binfo.smp_bootreg_addr = exynos4_board_smp_bootreg_addr[board_type]; - exynos4_board_binfo.kernel_filename = kernel_filename; - exynos4_board_binfo.initrd_filename = initrd_filename; - exynos4_board_binfo.kernel_cmdline = kernel_cmdline; + exynos4_board_binfo.kernel_filename = args->kernel_filename; + exynos4_board_binfo.initrd_filename = args->initrd_filename; + exynos4_board_binfo.kernel_cmdline = args->kernel_cmdline; exynos4_board_binfo.gic_cpu_if_addr = EXYNOS4210_SMP_PRIVATE_BASE_ADDR + 0x100; @@ -122,9 +119,9 @@ static Exynos4210State *exynos4_boards_init_common( " initrd_filename: %s\n", exynos4_board_ram_size[board_type] / 1048576, exynos4_board_ram_size[board_type], - kernel_filename, - kernel_cmdline, - initrd_filename); + args->kernel_filename, + args->kernel_cmdline, + args->initrd_filename); return exynos4210_init(get_system_memory(), exynos4_board_ram_size[board_type]); @@ -132,22 +129,15 @@ static Exynos4210State *exynos4_boards_init_common( static void nuri_init(QEMUMachineInitArgs *args) { - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - exynos4_boards_init_common(kernel_filename, kernel_cmdline, - initrd_filename, EXYNOS4_BOARD_NURI); + exynos4_boards_init_common(args, EXYNOS4_BOARD_NURI); arm_load_kernel(arm_env_get_cpu(first_cpu), &exynos4_board_binfo); } static void smdkc210_init(QEMUMachineInitArgs *args) { - const char *kernel_filename = args->kernel_filename; - const char *kernel_cmdline = args->kernel_cmdline; - const char *initrd_filename = args->initrd_filename; - Exynos4210State *s = exynos4_boards_init_common(kernel_filename, - kernel_cmdline, initrd_filename, EXYNOS4_BOARD_SMDKC210); + Exynos4210State *s = exynos4_boards_init_common(args, + EXYNOS4_BOARD_SMDKC210); lan9215_init(SMDK_LAN9118_BASE_ADDR, qemu_irq_invert(s->irq_table[exynos4210_get_irq(37, 1)])); From fbfecf43e9d354cfae04496563f7bb87d2ccde46 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:08 +0000 Subject: [PATCH 010/291] hw/pl050: Use LOG_GUEST_ERROR Use LOG_GUEST_ERROR for reporting guest attempts to access invalid register offsets. Signed-off-by: Peter Maydell --- hw/pl050.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/pl050.c b/hw/pl050.c index 470572eabb..47032f1260 100644 --- a/hw/pl050.c +++ b/hw/pl050.c @@ -95,7 +95,8 @@ static uint64_t pl050_read(void *opaque, hwaddr offset, case 4: /* KMIIR */ return s->pending | 2; default: - hw_error("pl050_read: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl050_read: Bad offset %x\n", (int)offset); return 0; } } @@ -123,7 +124,8 @@ static void pl050_write(void *opaque, hwaddr offset, s->clk = value; return; default: - hw_error("pl050_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl050_write: Bad offset %x\n", (int)offset); } } static const MemoryRegionOps pl050_ops = { From abff909c9456103b54277318675fff8997fd71af Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:09 +0000 Subject: [PATCH 011/291] hw/pl061: Use LOG_GUEST_ERROR Use LOG_GUEST_ERROR to report guest attempts to access bad register offsets. Signed-off-by: Peter Maydell --- hw/pl061.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/pl061.c b/hw/pl061.c index 7d182e7cdf..f1ed5ced1d 100644 --- a/hw/pl061.c +++ b/hw/pl061.c @@ -164,7 +164,8 @@ static uint64_t pl061_read(void *opaque, hwaddr offset, case 0x528: /* Analog mode select */ return s->amsel; default: - hw_error("pl061_read: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl061_read: Bad offset %x\n", (int)offset); return 0; } } @@ -239,7 +240,8 @@ static void pl061_write(void *opaque, hwaddr offset, s->amsel = value & 0xff; break; default: - hw_error("pl061_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl061_write: Bad offset %x\n", (int)offset); } pl061_update(s); } From df37416218a91a4ae962dfafbc8208af8087ebc0 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:09 +0000 Subject: [PATCH 012/291] hw/pl080: Use LOG_GUEST_ERROR and LOG_UNIMP Use LOG_GUEST_ERROR and LOG_UNIMP in preference to hw_error(). Signed-off-by: Peter Maydell --- hw/pl080.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/pl080.c b/hw/pl080.c index 6abe52857e..26150af757 100644 --- a/hw/pl080.c +++ b/hw/pl080.c @@ -281,7 +281,8 @@ static uint64_t pl080_read(void *opaque, hwaddr offset, return s->sync; default: bad_offset: - hw_error("pl080_read: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl080_read: Bad offset %x\n", (int)offset); return 0; } } @@ -327,12 +328,13 @@ static void pl080_write(void *opaque, hwaddr offset, case 10: /* SoftLBReq */ case 11: /* SoftLSReq */ /* ??? Implement these. */ - hw_error("pl080_write: Soft DMA not implemented\n"); + qemu_log_mask(LOG_UNIMP, "pl080_write: Soft DMA not implemented\n"); break; case 12: /* Configuration */ s->conf = value; if (s->conf & (PL080_CONF_M1 | PL080_CONF_M1)) { - hw_error("pl080_write: Big-endian DMA not implemented\n"); + qemu_log_mask(LOG_UNIMP, + "pl080_write: Big-endian DMA not implemented\n"); } pl080_run(s); break; @@ -341,7 +343,8 @@ static void pl080_write(void *opaque, hwaddr offset, break; default: bad_offset: - hw_error("pl080_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl080_write: Bad offset %x\n", (int)offset); } pl080_update(s); } From 375cb560295484b88898262ebf400eff9a011206 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:09 +0000 Subject: [PATCH 013/291] hw/pl110: Use LOG_GUEST_ERROR rather than hw_error() Use LOG_GUEST_ERROR to report guest accesses to invalid register offsets. Signed-off-by: Peter Maydell --- hw/pl110.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/pl110.c b/hw/pl110.c index 82486b0c14..d5472f4cce 100644 --- a/hw/pl110.c +++ b/hw/pl110.c @@ -349,7 +349,8 @@ static uint64_t pl110_read(void *opaque, hwaddr offset, case 12: /* LCDLPCURR */ return s->lpbase; default: - hw_error("pl110_read: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl110_read: Bad offset %x\n", (int)offset); return 0; } } @@ -417,7 +418,8 @@ static void pl110_write(void *opaque, hwaddr offset, pl110_update(s); break; default: - hw_error("pl110_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "pl110_write: Bad offset %x\n", (int)offset); } } From 2d746989bf5e146df9205de3fd4ad0d48a318165 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:09 +0000 Subject: [PATCH 014/291] hw/pl190: Use LOG_UNIMP rather than hw_error() Use LOG_UNIMP to report attempts to use the unimplemented test mode. Signed-off-by: Peter Maydell --- hw/pl190.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pl190.c b/hw/pl190.c index 213229b566..40199302a9 100644 --- a/hw/pl190.c +++ b/hw/pl190.c @@ -199,7 +199,7 @@ static void pl190_write(void *opaque, hwaddr offset, break; case 0xc0: /* ITCR */ if (val) { - hw_error("pl190: Test mode not implemented\n"); + qemu_log_mask(LOG_UNIMP, "pl190: Test mode not implemented\n"); } break; default: From f9fe7bdad82a1262e9352393b03d7f4586366209 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:09 +0000 Subject: [PATCH 015/291] hw/arm11mpcore: Use LOG_GUEST_ERROR rather than hw_error() Use LOG_GUEST_ERROR to report guest accesses to bad offsets. Signed-off-by: Peter Maydell --- hw/arm11mpcore.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c index 105f158fd4..640ed20a61 100644 --- a/hw/arm11mpcore.c +++ b/hw/arm11mpcore.c @@ -44,7 +44,9 @@ static uint64_t mpcore_scu_read(void *opaque, hwaddr offset, case 0x0c: /* Invalidate all. */ return 0; default: - hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "mpcore_priv_read: Bad offset %x\n", (int)offset); + return 0; } } @@ -61,7 +63,8 @@ static void mpcore_scu_write(void *opaque, hwaddr offset, /* This is a no-op as cache is not emulated. */ break; default: - hw_error("mpcore_priv_read: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "mpcore_priv_read: Bad offset %x\n", (int)offset); } } From 8c8dc39fa60f782f988bc08113f3abfddebbfebd Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:10 +0000 Subject: [PATCH 016/291] hw/arm_gic: Use LOG_GUEST_ERROR Use LOG_GUEST_ERROR to report guest accesses to bad offsets. Signed-off-by: Peter Maydell --- hw/arm_gic.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/arm_gic.c b/hw/arm_gic.c index ce16e8367f..f9e423f152 100644 --- a/hw/arm_gic.c +++ b/hw/arm_gic.c @@ -324,7 +324,8 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset) } return res; bad_reg: - hw_error("gic_dist_readb: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "gic_dist_readb: Bad offset %x\n", (int)offset); return 0; } @@ -487,7 +488,8 @@ static void gic_dist_writeb(void *opaque, hwaddr offset, gic_update(s); return; bad_reg: - hw_error("gic_dist_writeb: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "gic_dist_writeb: Bad offset %x\n", (int)offset); } static void gic_dist_writew(void *opaque, hwaddr offset, @@ -556,7 +558,8 @@ static uint32_t gic_cpu_read(GICState *s, int cpu, int offset) case 0x18: /* Highest Pending Interrupt */ return s->current_pending[cpu]; default: - hw_error("gic_cpu_read: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "gic_cpu_read: Bad offset %x\n", (int)offset); return 0; } } @@ -577,7 +580,8 @@ static void gic_cpu_write(GICState *s, int cpu, int offset, uint32_t value) case 0x10: /* End Of Interrupt */ return gic_complete_irq(s, cpu, value & 0x3ff); default: - hw_error("gic_cpu_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "gic_cpu_write: Bad offset %x\n", (int)offset); return; } gic_update(s); From edb94a41e30f1b2ca241bfdfd7f7e90badfa6192 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:10 +0000 Subject: [PATCH 017/291] hw/arm_timer: Use LOG_GUEST_ERROR and LOG_UNIMP Use LOG_GUEST_ERROR to report guest accesses to bad register offsets, and LOG_UNIMP for access to the unimplemented test registers. Signed-off-by: Peter Maydell --- hw/arm_timer.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/hw/arm_timer.c b/hw/arm_timer.c index 2e136216c6..af339d3d19 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -64,7 +64,8 @@ static uint32_t arm_timer_read(void *opaque, hwaddr offset) return 0; return s->int_level; default: - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset %x\n", __func__, (int)offset); return 0; } } @@ -131,7 +132,8 @@ static void arm_timer_write(void *opaque, hwaddr offset, arm_timer_recalibrate(s, 0); break; default: - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset %x\n", __func__, (int)offset); } arm_timer_update(s); } @@ -223,10 +225,14 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, /* Integration Test control registers, which we won't support */ case 0xf00: /* TimerITCR */ case 0xf04: /* TimerITOP (strictly write only but..) */ + qemu_log_mask(LOG_UNIMP, + "%s: integration test registers unimplemented\n", + __func__); return 0; } - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset %x\n", __func__, (int)offset); return 0; } @@ -246,7 +252,8 @@ static void sp804_write(void *opaque, hwaddr offset, } /* Technically we could be writing to the Test Registers, but not likely */ - hw_error("%s: Bad offset %x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", + __func__, (int)offset); } static const MemoryRegionOps sp804_ops = { @@ -300,7 +307,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offset, /* ??? Don't know the PrimeCell ID for this device. */ n = offset >> 8; if (n > 2) { - hw_error("%s: Bad timer %d\n", __func__, n); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); } return arm_timer_read(s->timer[n], offset & 0xff); @@ -314,7 +321,7 @@ static void icp_pit_write(void *opaque, hwaddr offset, n = offset >> 8; if (n > 2) { - hw_error("%s: Bad timer %d\n", __func__, n); + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); } arm_timer_write(s->timer[n], offset & 0xff, value); From e72e3ffc3d13176c44eb21af0c6468867458cb4a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:10 +0000 Subject: [PATCH 018/291] hw/armv7m_nvic: Use LOG_GUEST_ERROR and LOG_UNIMP Use LOG_GUEST_ERROR and LOG_UNIMP rather than hw_error() where appropriate. Signed-off-by: Peter Maydell --- hw/armv7m_nvic.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c index 8d8d0a4e8b..f0a2e7b5d2 100644 --- a/hw/armv7m_nvic.c +++ b/hw/armv7m_nvic.c @@ -234,7 +234,7 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) return val; case 0xd28: /* Configurable Fault Status. */ /* TODO: Implement Fault Status. */ - hw_error("Not implemented: Configurable Fault Status."); + qemu_log_mask(LOG_UNIMP, "Configurable Fault Status unimplemented\n"); return 0; case 0xd2c: /* Hard Fault Status. */ case 0xd30: /* Debug Fault Status. */ @@ -242,7 +242,8 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) case 0xd38: /* Bus Fault Address. */ case 0xd3c: /* Aux Fault Status. */ /* TODO: Implement fault status registers. */ - goto bad_reg; + qemu_log_mask(LOG_UNIMP, "Fault status registers unimplemented\n"); + return 0; case 0xd40: /* PFR0. */ return 0x00000030; case 0xd44: /* PRF1. */ @@ -271,8 +272,8 @@ static uint32_t nvic_readl(nvic_state *s, uint32_t offset) return 0x01310102; /* TODO: Implement debug registers. */ default: - bad_reg: - hw_error("NVIC: Bad read offset 0x%x\n", offset); + qemu_log_mask(LOG_GUEST_ERROR, "NVIC: Bad read offset 0x%x\n", offset); + return 0; } } @@ -335,17 +336,18 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) case 0xd0c: /* Application Interrupt/Reset Control. */ if ((value >> 16) == 0x05fa) { if (value & 2) { - hw_error("VECTCLRACTIVE not implemented"); + qemu_log_mask(LOG_UNIMP, "VECTCLRACTIVE unimplemented\n"); } if (value & 5) { - hw_error("System reset"); + qemu_log_mask(LOG_UNIMP, "AIRCR system reset unimplemented\n"); } } break; case 0xd10: /* System Control. */ case 0xd14: /* Configuration Control. */ /* TODO: Implement control registers. */ - goto bad_reg; + qemu_log_mask(LOG_UNIMP, "NVIC: SCR and CCR unimplemented\n"); + break; case 0xd24: /* System Handler Control. */ /* TODO: Real hardware allows you to set/clear the active bits under some circumstances. We don't implement this. */ @@ -359,15 +361,17 @@ static void nvic_writel(nvic_state *s, uint32_t offset, uint32_t value) case 0xd34: /* Mem Manage Address. */ case 0xd38: /* Bus Fault Address. */ case 0xd3c: /* Aux Fault Status. */ - goto bad_reg; + qemu_log_mask(LOG_UNIMP, + "NVIC: fault status registers unimplemented\n"); + break; case 0xf00: /* Software Triggered Interrupt Register */ if ((value & 0x1ff) < s->num_irq) { gic_set_pending_private(&s->gic, 0, value & 0x1ff); } break; default: - bad_reg: - hw_error("NVIC: Bad write offset 0x%x\n", offset); + qemu_log_mask(LOG_GUEST_ERROR, + "NVIC: Bad write offset 0x%x\n", offset); } } @@ -395,7 +399,9 @@ static uint64_t nvic_sysreg_read(void *opaque, hwaddr addr, if (size == 4) { return nvic_readl(s, offset); } - hw_error("NVIC: Bad read of size %d at offset 0x%x\n", size, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "NVIC: Bad read of size %d at offset 0x%x\n", size, offset); + return 0; } static void nvic_sysreg_write(void *opaque, hwaddr addr, @@ -418,7 +424,8 @@ static void nvic_sysreg_write(void *opaque, hwaddr addr, nvic_writel(s, offset, value); return; } - hw_error("NVIC: Bad write of size %d at offset 0x%x\n", size, offset); + qemu_log_mask(LOG_GUEST_ERROR, + "NVIC: Bad write of size %d at offset 0x%x\n", size, offset); } static const MemoryRegionOps nvic_sysreg_ops = { From 0c896f066213fcb06063f68ad7bfc75800591846 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:10 +0000 Subject: [PATCH 019/291] hw/arm_sysctl: Use LOG_GUEST_ERROR Use LOG_GUEST_ERROR to report bad guest accesses. Signed-off-by: Peter Maydell --- hw/arm_sysctl.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/hw/arm_sysctl.c b/hw/arm_sysctl.c index 26318e14d5..58eb98216d 100644 --- a/hw/arm_sysctl.c +++ b/hw/arm_sysctl.c @@ -184,7 +184,9 @@ static uint64_t arm_sysctl_read(void *opaque, hwaddr offset, return s->sys_cfgstat; default: bad_reg: - printf ("arm_sysctl_read: Bad register offset 0x%x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "arm_sysctl_read: Bad register offset 0x%x\n", + (int)offset); return 0; } } @@ -339,7 +341,9 @@ static void arm_sysctl_write(void *opaque, hwaddr offset, return; default: bad_reg: - printf ("arm_sysctl_write: Bad register offset 0x%x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "arm_sysctl_write: Bad register offset 0x%x\n", + (int)offset); return; } } From a35d4e422328eeb770b7b0c08bb073e8940b158e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:10 +0000 Subject: [PATCH 020/291] hw/arm_l2x0: Use LOG_GUEST_ERROR Use LOG_GUEST_ERROR to report bad guest accesses. Signed-off-by: Peter Maydell --- hw/arm_l2x0.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/arm_l2x0.c b/hw/arm_l2x0.c index 8f5921c3a6..6abf0ee160 100644 --- a/hw/arm_l2x0.c +++ b/hw/arm_l2x0.c @@ -87,7 +87,8 @@ static uint64_t l2x0_priv_read(void *opaque, hwaddr offset, case 0xF80: return 0; default: - fprintf(stderr, "l2x0_priv_read: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "l2x0_priv_read: Bad offset %x\n", (int)offset); break; } return 0; @@ -128,7 +129,8 @@ static void l2x0_priv_write(void *opaque, hwaddr offset, case 0xF80: return; default: - fprintf(stderr, "l2x0_priv_write: Bad offset %x\n", (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "l2x0_priv_write: Bad offset %x\n", (int)offset); break; } } From 5170d661dc1a2a28e1a242f6814bea4dcc29ad23 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:11 +0000 Subject: [PATCH 021/291] hw/versatile_i2c: Use LOG_GUEST_ERROR Use LOG_GUEST_ERROR to report bad guest accesses. Signed-off-by: Peter Maydell --- hw/versatile_i2c.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/versatile_i2c.c b/hw/versatile_i2c.c index 44e7e40f2f..ad71e9d92d 100644 --- a/hw/versatile_i2c.c +++ b/hw/versatile_i2c.c @@ -40,7 +40,8 @@ static uint64_t versatile_i2c_read(void *opaque, hwaddr offset, if (offset == 0) { return (s->out & 1) | (s->in << 1); } else { - hw_error("%s: Bad offset 0x%x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%x\n", __func__, (int)offset); return -1; } } @@ -58,7 +59,8 @@ static void versatile_i2c_write(void *opaque, hwaddr offset, s->out &= ~value; break; default: - hw_error("%s: Bad offset 0x%x\n", __func__, (int)offset); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%x\n", __func__, (int)offset); } bitbang_i2c_set(s->bitbang, BITBANG_I2C_SCL, (s->out & 1) != 0); s->in = bitbang_i2c_set(s->bitbang, BITBANG_I2C_SDA, (s->out & 2) != 0); From b7dff23a487fffccd7c395da95e9b02bebe48bee Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Tue, 30 Oct 2012 07:45:11 +0000 Subject: [PATCH 022/291] pflash_cfi0x: remove unused base field This field is completely unused. The base address should also be abstracted away from the device anyway. Removed. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/pflash_cfi01.c | 2 -- hw/pflash_cfi02.c | 4 +--- 2 files changed, 1 insertion(+), 5 deletions(-) diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c index 5e3a409c2b..2e29f8a38a 100644 --- a/hw/pflash_cfi01.c +++ b/hw/pflash_cfi01.c @@ -61,7 +61,6 @@ do { \ struct pflash_t { BlockDriverState *bs; - hwaddr base; hwaddr sector_len; hwaddr total_len; int width; @@ -594,7 +593,6 @@ pflash_t *pflash_cfi01_register(hwaddr base, } pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); - pfl->base = base; pfl->sector_len = sector_len; pfl->total_len = total_len; pfl->width = width; diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index 9f94c0623d..083718bad3 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -56,7 +56,6 @@ do { \ struct pflash_t { BlockDriverState *bs; - hwaddr base; uint32_t sector_len; uint32_t chip_len; int mappings; @@ -602,7 +601,6 @@ pflash_t *pflash_cfi02_register(hwaddr base, name, size); vmstate_register_ram(&pfl->orig_mem, qdev); pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); - pfl->base = base; pfl->chip_len = chip_len; pfl->mappings = nb_mappings; pfl->bs = bs; @@ -618,7 +616,7 @@ pflash_t *pflash_cfi02_register(hwaddr base, pflash_setup_mappings(pfl); pfl->rom_mode = 1; - memory_region_add_subregion(get_system_memory(), pfl->base, &pfl->mem); + memory_region_add_subregion(get_system_memory(), base, &pfl->mem); if (pfl->bs) { pfl->ro = bdrv_is_read_only(pfl->bs); From be65f89992afd1366ce51db95f26b63cc90e309d Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Tue, 30 Oct 2012 07:45:11 +0000 Subject: [PATCH 023/291] pflash_cfi01: remove unused total_len field This field is completely unused. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/pflash_cfi01.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c index 2e29f8a38a..b532054c53 100644 --- a/hw/pflash_cfi01.c +++ b/hw/pflash_cfi01.c @@ -62,7 +62,6 @@ do { \ struct pflash_t { BlockDriverState *bs; hwaddr sector_len; - hwaddr total_len; int width; int wcycle; /* if 0, the flash is read normally */ int bypass; @@ -594,7 +593,6 @@ pflash_t *pflash_cfi01_register(hwaddr base, pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); pfl->sector_len = sector_len; - pfl->total_len = total_len; pfl->width = width; pfl->wcycle = 0; pfl->cmd = 0; From 368a354f02b7c3845d8b4bcdebc0840a515e953b Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Tue, 30 Oct 2012 07:45:11 +0000 Subject: [PATCH 024/291] pflash_cfi0x: QOMified QOMified the pflash_cfi0x so machine models can connect them up in custom ways. Kept the pflash_cfi0x_register functions as is. They can still be used to create a flash straight onto system memory. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/pflash_cfi01.c | 141 ++++++++++++++++++++++++++++------------ hw/pflash_cfi02.c | 160 +++++++++++++++++++++++++++++++++------------- 2 files changed, 214 insertions(+), 87 deletions(-) diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c index b532054c53..d30d43c318 100644 --- a/hw/pflash_cfi01.c +++ b/hw/pflash_cfi01.c @@ -42,6 +42,7 @@ #include "qemu-timer.h" #include "exec-memory.h" #include "host-utils.h" +#include "sysbus.h" #define PFLASH_BUG(fmt, ...) \ do { \ @@ -60,21 +61,28 @@ do { \ #endif struct pflash_t { + SysBusDevice busdev; BlockDriverState *bs; - hwaddr sector_len; - int width; + uint32_t nb_blocs; + uint64_t sector_len; + uint8_t width; + uint8_t be; int wcycle; /* if 0, the flash is read normally */ int bypass; int ro; uint8_t cmd; uint8_t status; - uint16_t ident[4]; + uint16_t ident0; + uint16_t ident1; + uint16_t ident2; + uint16_t ident3; uint8_t cfi_len; uint8_t cfi_table[0x52]; hwaddr counter; unsigned int writeblock_size; QEMUTimer *timer; MemoryRegion mem; + char *name; void *storage; }; @@ -166,11 +174,11 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, case 0x90: switch (boff) { case 0: - ret = pfl->ident[0] << 8 | pfl->ident[1]; + ret = pfl->ident0 << 8 | pfl->ident1; DPRINTF("%s: Manufacturer Code %04x\n", __func__, ret); break; case 1: - ret = pfl->ident[2] << 8 | pfl->ident[3]; + ret = pfl->ident2 << 8 | pfl->ident3; DPRINTF("%s: Device ID Code %04x\n", __func__, ret); break; default: @@ -277,9 +285,8 @@ static void pflash_write(pflash_t *pfl, hwaddr offset, p = pfl->storage; offset &= ~(pfl->sector_len - 1); - DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes " - TARGET_FMT_plx "\n", - __func__, offset, pfl->sector_len); + DPRINTF("%s: block erase at " TARGET_FMT_plx " bytes %x\n", + __func__, offset, (unsigned)pfl->sector_len); if (!pfl->ro) { memset(p + offset, 0xff, pfl->sector_len); @@ -541,19 +548,13 @@ static const MemoryRegionOps pflash_cfi01_ops_le = { .endianness = DEVICE_NATIVE_ENDIAN, }; -pflash_t *pflash_cfi01_register(hwaddr base, - DeviceState *qdev, const char *name, - hwaddr size, - BlockDriverState *bs, uint32_t sector_len, - int nb_blocs, int width, - uint16_t id0, uint16_t id1, - uint16_t id2, uint16_t id3, int be) +static int pflash_cfi01_init(SysBusDevice *dev) { - pflash_t *pfl; - hwaddr total_len; + pflash_t *pfl = FROM_SYSBUS(typeof(*pfl), dev); + uint64_t total_len; int ret; - total_len = sector_len * nb_blocs; + total_len = pfl->sector_len * pfl->nb_blocs; /* XXX: to be fixed */ #if 0 @@ -562,27 +563,22 @@ pflash_t *pflash_cfi01_register(hwaddr base, return NULL; #endif - pfl = g_malloc0(sizeof(pflash_t)); - memory_region_init_rom_device( - &pfl->mem, be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl, - name, size); - vmstate_register_ram(&pfl->mem, qdev); + &pfl->mem, pfl->be ? &pflash_cfi01_ops_be : &pflash_cfi01_ops_le, pfl, + pfl->name, total_len); + vmstate_register_ram(&pfl->mem, DEVICE(pfl)); pfl->storage = memory_region_get_ram_ptr(&pfl->mem); - memory_region_add_subregion(get_system_memory(), base, &pfl->mem); + sysbus_init_mmio(dev, &pfl->mem); - pfl->bs = bs; if (pfl->bs) { /* read the initial flash content */ ret = bdrv_read(pfl->bs, 0, pfl->storage, total_len >> 9); + if (ret < 0) { - memory_region_del_subregion(get_system_memory(), &pfl->mem); - vmstate_unregister_ram(&pfl->mem, qdev); + vmstate_unregister_ram(&pfl->mem, DEVICE(pfl)); memory_region_destroy(&pfl->mem); - g_free(pfl); - return NULL; + return 1; } - bdrv_attach_dev_nofail(pfl->bs, pfl); } if (pfl->bs) { @@ -592,15 +588,9 @@ pflash_t *pflash_cfi01_register(hwaddr base, } pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); - pfl->sector_len = sector_len; - pfl->width = width; pfl->wcycle = 0; pfl->cmd = 0; pfl->status = 0; - pfl->ident[0] = id0; - pfl->ident[1] = id1; - pfl->ident[2] = id2; - pfl->ident[3] = id3; /* Hardcoded CFI table */ pfl->cfi_len = 0x52; /* Standard "QRY" string */ @@ -649,7 +639,7 @@ pflash_t *pflash_cfi01_register(hwaddr base, pfl->cfi_table[0x28] = 0x02; pfl->cfi_table[0x29] = 0x00; /* Max number of bytes in multi-bytes write */ - if (width == 1) { + if (pfl->width == 1) { pfl->cfi_table[0x2A] = 0x08; } else { pfl->cfi_table[0x2A] = 0x0B; @@ -660,10 +650,10 @@ pflash_t *pflash_cfi01_register(hwaddr base, /* Number of erase block regions (uniform) */ pfl->cfi_table[0x2C] = 0x01; /* Erase block region 1 */ - pfl->cfi_table[0x2D] = nb_blocs - 1; - pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; - pfl->cfi_table[0x2F] = sector_len >> 8; - pfl->cfi_table[0x30] = sector_len >> 16; + pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; + pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; + pfl->cfi_table[0x2F] = pfl->sector_len >> 8; + pfl->cfi_table[0x30] = pfl->sector_len >> 16; /* Extended */ pfl->cfi_table[0x31] = 'P'; @@ -685,6 +675,75 @@ pflash_t *pflash_cfi01_register(hwaddr base, pfl->cfi_table[0x3f] = 0x01; /* Number of protection fields */ + return 0; +} + +static Property pflash_cfi01_properties[] = { + DEFINE_PROP_DRIVE("drive", struct pflash_t, bs), + DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), + DEFINE_PROP_UINT64("sector-length", struct pflash_t, sector_len, 0), + DEFINE_PROP_UINT8("width", struct pflash_t, width, 0), + DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), + DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), + DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), + DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0), + DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0), + DEFINE_PROP_STRING("name", struct pflash_t, name), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pflash_cfi01_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = pflash_cfi01_init; + dc->props = pflash_cfi01_properties; +} + + +static const TypeInfo pflash_cfi01_info = { + .name = "cfi.pflash01", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(struct pflash_t), + .class_init = pflash_cfi01_class_init, +}; + +static void pflash_cfi01_register_types(void) +{ + type_register_static(&pflash_cfi01_info); +} + +type_init(pflash_cfi01_register_types) + +pflash_t *pflash_cfi01_register(hwaddr base, + DeviceState *qdev, const char *name, + hwaddr size, + BlockDriverState *bs, + uint32_t sector_len, int nb_blocs, int width, + uint16_t id0, uint16_t id1, + uint16_t id2, uint16_t id3, int be) +{ + DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); + SysBusDevice *busdev = sysbus_from_qdev(dev); + pflash_t *pfl = (pflash_t *)object_dynamic_cast(OBJECT(dev), + "cfi.pflash01"); + + if (bs && qdev_prop_set_drive(dev, "drive", bs)) { + abort(); + } + qdev_prop_set_uint32(dev, "num-blocks", nb_blocs); + qdev_prop_set_uint64(dev, "sector-length", sector_len); + qdev_prop_set_uint8(dev, "width", width); + qdev_prop_set_uint8(dev, "big-endian", !!be); + qdev_prop_set_uint16(dev, "id0", id0); + qdev_prop_set_uint16(dev, "id1", id1); + qdev_prop_set_uint16(dev, "id2", id2); + qdev_prop_set_uint16(dev, "id3", id3); + qdev_prop_set_string(dev, "name", name); + qdev_init_nofail(dev); + + sysbus_mmio_map(busdev, 0, base); return pfl; } diff --git a/hw/pflash_cfi02.c b/hw/pflash_cfi02.c index 083718bad3..f918e36580 100644 --- a/hw/pflash_cfi02.c +++ b/hw/pflash_cfi02.c @@ -41,6 +41,7 @@ #include "block.h" #include "exec-memory.h" #include "host-utils.h" +#include "sysbus.h" //#define PFLASH_DEBUG #ifdef PFLASH_DEBUG @@ -55,18 +56,26 @@ do { \ #define PFLASH_LAZY_ROMD_THRESHOLD 42 struct pflash_t { + SysBusDevice busdev; BlockDriverState *bs; uint32_t sector_len; + uint32_t nb_blocs; uint32_t chip_len; - int mappings; - int width; + uint8_t mappings; + uint8_t width; + uint8_t be; int wcycle; /* if 0, the flash is read normally */ int bypass; int ro; uint8_t cmd; uint8_t status; - uint16_t ident[4]; - uint16_t unlock_addr[2]; + /* FIXME: implement array device properties */ + uint16_t ident0; + uint16_t ident1; + uint16_t ident2; + uint16_t ident3; + uint16_t unlock_addr0; + uint16_t unlock_addr1; uint8_t cfi_len; uint8_t cfi_table[0x52]; QEMUTimer *timer; @@ -79,6 +88,7 @@ struct pflash_t { MemoryRegion orig_mem; int rom_mode; int read_counter; /* used for lazy switch-back to rom mode */ + char *name; void *storage; }; @@ -189,16 +199,17 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, switch (boff) { case 0x00: case 0x01: - ret = pfl->ident[boff & 0x01]; + ret = boff & 0x01 ? pfl->ident1 : pfl->ident0; break; case 0x02: ret = 0x00; /* Pretend all sectors are unprotected */ break; case 0x0E: case 0x0F: - if (pfl->ident[2 + (boff & 0x01)] == (uint8_t)-1) + ret = boff & 0x01 ? pfl->ident3 : pfl->ident2; + if (ret == (uint8_t)-1) { goto flash_read; - ret = pfl->ident[2 + (boff & 0x01)]; + } break; default: goto flash_read; @@ -282,9 +293,9 @@ static void pflash_write (pflash_t *pfl, hwaddr offset, pfl->cmd = 0x98; return; } - if (boff != pfl->unlock_addr[0] || cmd != 0xAA) { + if (boff != pfl->unlock_addr0 || cmd != 0xAA) { DPRINTF("%s: unlock0 failed " TARGET_FMT_plx " %02x %04x\n", - __func__, boff, cmd, pfl->unlock_addr[0]); + __func__, boff, cmd, pfl->unlock_addr0); goto reset_flash; } DPRINTF("%s: unlock sequence started\n", __func__); @@ -292,7 +303,7 @@ static void pflash_write (pflash_t *pfl, hwaddr offset, case 1: /* We started an unlock sequence */ check_unlock1: - if (boff != pfl->unlock_addr[1] || cmd != 0x55) { + if (boff != pfl->unlock_addr1 || cmd != 0x55) { DPRINTF("%s: unlock1 failed " TARGET_FMT_plx " %02x\n", __func__, boff, cmd); goto reset_flash; @@ -301,7 +312,7 @@ static void pflash_write (pflash_t *pfl, hwaddr offset, break; case 2: /* We finished an unlock sequence */ - if (!pfl->bypass && boff != pfl->unlock_addr[0]) { + if (!pfl->bypass && boff != pfl->unlock_addr0) { DPRINTF("%s: command failed " TARGET_FMT_plx " %02x\n", __func__, boff, cmd); goto reset_flash; @@ -399,7 +410,7 @@ static void pflash_write (pflash_t *pfl, hwaddr offset, case 5: switch (cmd) { case 0x10: - if (boff != pfl->unlock_addr[0]) { + if (boff != pfl->unlock_addr0) { DPRINTF("%s: chip erase: invalid address " TARGET_FMT_plx "\n", __func__, offset); goto reset_flash; @@ -574,49 +585,38 @@ static const MemoryRegionOps pflash_cfi02_ops_le = { .endianness = DEVICE_NATIVE_ENDIAN, }; -pflash_t *pflash_cfi02_register(hwaddr base, - DeviceState *qdev, const char *name, - hwaddr size, - BlockDriverState *bs, uint32_t sector_len, - int nb_blocs, int nb_mappings, int width, - uint16_t id0, uint16_t id1, - uint16_t id2, uint16_t id3, - uint16_t unlock_addr0, uint16_t unlock_addr1, - int be) +static int pflash_cfi02_init(SysBusDevice *dev) { - pflash_t *pfl; - int32_t chip_len; + pflash_t *pfl = FROM_SYSBUS(typeof(*pfl), dev); + uint32_t chip_len; int ret; - chip_len = sector_len * nb_blocs; + chip_len = pfl->sector_len * pfl->nb_blocs; /* XXX: to be fixed */ #if 0 if (total_len != (8 * 1024 * 1024) && total_len != (16 * 1024 * 1024) && total_len != (32 * 1024 * 1024) && total_len != (64 * 1024 * 1024)) return NULL; #endif - pfl = g_malloc0(sizeof(pflash_t)); - memory_region_init_rom_device( - &pfl->orig_mem, be ? &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, pfl, - name, size); - vmstate_register_ram(&pfl->orig_mem, qdev); + + memory_region_init_rom_device(&pfl->orig_mem, pfl->be ? + &pflash_cfi02_ops_be : &pflash_cfi02_ops_le, + pfl, pfl->name, chip_len); + vmstate_register_ram(&pfl->orig_mem, DEVICE(pfl)); pfl->storage = memory_region_get_ram_ptr(&pfl->orig_mem); pfl->chip_len = chip_len; - pfl->mappings = nb_mappings; - pfl->bs = bs; if (pfl->bs) { /* read the initial flash content */ ret = bdrv_read(pfl->bs, 0, pfl->storage, chip_len >> 9); if (ret < 0) { g_free(pfl); - return NULL; + return 1; } - bdrv_attach_dev_nofail(pfl->bs, pfl); } pflash_setup_mappings(pfl); pfl->rom_mode = 1; - memory_region_add_subregion(get_system_memory(), base, &pfl->mem); + sysbus_init_mmio(dev, &pfl->mem); if (pfl->bs) { pfl->ro = bdrv_is_read_only(pfl->bs); @@ -625,17 +625,9 @@ pflash_t *pflash_cfi02_register(hwaddr base, } pfl->timer = qemu_new_timer_ns(vm_clock, pflash_timer, pfl); - pfl->sector_len = sector_len; - pfl->width = width; pfl->wcycle = 0; pfl->cmd = 0; pfl->status = 0; - pfl->ident[0] = id0; - pfl->ident[1] = id1; - pfl->ident[2] = id2; - pfl->ident[3] = id3; - pfl->unlock_addr[0] = unlock_addr0; - pfl->unlock_addr[1] = unlock_addr1; /* Hardcoded CFI table (mostly from SG29 Spansion flash) */ pfl->cfi_len = 0x52; /* Standard "QRY" string */ @@ -691,10 +683,10 @@ pflash_t *pflash_cfi02_register(hwaddr base, /* Number of erase block regions (uniform) */ pfl->cfi_table[0x2C] = 0x01; /* Erase block region 1 */ - pfl->cfi_table[0x2D] = nb_blocs - 1; - pfl->cfi_table[0x2E] = (nb_blocs - 1) >> 8; - pfl->cfi_table[0x2F] = sector_len >> 8; - pfl->cfi_table[0x30] = sector_len >> 16; + pfl->cfi_table[0x2D] = pfl->nb_blocs - 1; + pfl->cfi_table[0x2E] = (pfl->nb_blocs - 1) >> 8; + pfl->cfi_table[0x2F] = pfl->sector_len >> 8; + pfl->cfi_table[0x30] = pfl->sector_len >> 16; /* Extended */ pfl->cfi_table[0x31] = 'P'; @@ -714,5 +706,81 @@ pflash_t *pflash_cfi02_register(hwaddr base, pfl->cfi_table[0x3b] = 0x00; pfl->cfi_table[0x3c] = 0x00; + return 0; +} + +static Property pflash_cfi02_properties[] = { + DEFINE_PROP_DRIVE("drive", struct pflash_t, bs), + DEFINE_PROP_UINT32("num-blocks", struct pflash_t, nb_blocs, 0), + DEFINE_PROP_UINT32("sector-length", struct pflash_t, sector_len, 0), + DEFINE_PROP_UINT8("width", struct pflash_t, width, 0), + DEFINE_PROP_UINT8("mappings", struct pflash_t, mappings, 0), + DEFINE_PROP_UINT8("big-endian", struct pflash_t, be, 0), + DEFINE_PROP_UINT16("id0", struct pflash_t, ident0, 0), + DEFINE_PROP_UINT16("id1", struct pflash_t, ident1, 0), + DEFINE_PROP_UINT16("id2", struct pflash_t, ident2, 0), + DEFINE_PROP_UINT16("id3", struct pflash_t, ident3, 0), + DEFINE_PROP_UINT16("unlock-addr0", struct pflash_t, unlock_addr0, 0), + DEFINE_PROP_UINT16("unlock-addr1", struct pflash_t, unlock_addr1, 0), + DEFINE_PROP_STRING("name", struct pflash_t, name), + DEFINE_PROP_END_OF_LIST(), +}; + +static void pflash_cfi02_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = pflash_cfi02_init; + dc->props = pflash_cfi02_properties; +} + +static const TypeInfo pflash_cfi02_info = { + .name = "cfi.pflash02", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(struct pflash_t), + .class_init = pflash_cfi02_class_init, +}; + +static void pflash_cfi02_register_types(void) +{ + type_register_static(&pflash_cfi02_info); +} + +type_init(pflash_cfi02_register_types) + +pflash_t *pflash_cfi02_register(hwaddr base, + DeviceState *qdev, const char *name, + hwaddr size, + BlockDriverState *bs, uint32_t sector_len, + int nb_blocs, int nb_mappings, int width, + uint16_t id0, uint16_t id1, + uint16_t id2, uint16_t id3, + uint16_t unlock_addr0, uint16_t unlock_addr1, + int be) +{ + DeviceState *dev = qdev_create(NULL, "cfi.pflash02"); + SysBusDevice *busdev = sysbus_from_qdev(dev); + pflash_t *pfl = (pflash_t *)object_dynamic_cast(OBJECT(dev), + "cfi.pflash02"); + + if (bs && qdev_prop_set_drive(dev, "drive", bs)) { + abort(); + } + qdev_prop_set_uint32(dev, "num-blocks", nb_blocs); + qdev_prop_set_uint32(dev, "sector-length", sector_len); + qdev_prop_set_uint8(dev, "width", width); + qdev_prop_set_uint8(dev, "mappings", nb_mappings); + qdev_prop_set_uint8(dev, "big-endian", !!be); + qdev_prop_set_uint16(dev, "id0", id0); + qdev_prop_set_uint16(dev, "id1", id1); + qdev_prop_set_uint16(dev, "id2", id2); + qdev_prop_set_uint16(dev, "id3", id3); + qdev_prop_set_uint16(dev, "unlock-addr0", unlock_addr0); + qdev_prop_set_uint16(dev, "unlock-addr1", unlock_addr1); + qdev_prop_set_string(dev, "name", name); + qdev_init_nofail(dev); + + sysbus_mmio_map(busdev, 0, base); return pfl; } From fc5b64d0829297c7a525ddf6c0bb08ef0a9af5b6 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Tue, 30 Oct 2012 07:45:11 +0000 Subject: [PATCH 025/291] pflash_cfi01: Fix debug mode printfery This DPRINTF was throwing a warning due to a missing cast. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/pflash_cfi01.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/pflash_cfi01.c b/hw/pflash_cfi01.c index d30d43c318..7d040b508a 100644 --- a/hw/pflash_cfi01.c +++ b/hw/pflash_cfi01.c @@ -182,7 +182,8 @@ static uint32_t pflash_read (pflash_t *pfl, hwaddr offset, DPRINTF("%s: Device ID Code %04x\n", __func__, ret); break; default: - DPRINTF("%s: Read Device Information boff=%x\n", __func__, boff); + DPRINTF("%s: Read Device Information boff=%x\n", __func__, + (unsigned)boff); ret = 0; break; } From f2d189d38436a8ccdedd94de01673b04aa008e11 Mon Sep 17 00:00:00 2001 From: Igor Mitsyanko Date: Tue, 30 Oct 2012 07:45:12 +0000 Subject: [PATCH 026/291] hw/sd.c: Fix erase for high capacity cards Standard capacity cards SDSC use byte unit address while SDHC and SDXC cards use block unit address (512 bytes) when setting ERASE_START and ERASE_END with CMD32 and CMD33, we have to account for this. Signed-off-by: Igor Mitsyanko Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/sd.c | 17 +++++++++++++---- hw/sd.h | 1 + 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/hw/sd.c b/hw/sd.c index 297580aabe..b2f211c13a 100644 --- a/hw/sd.c +++ b/hw/sd.c @@ -476,19 +476,28 @@ void sd_set_cb(SDState *sd, qemu_irq readonly, qemu_irq insert) static void sd_erase(SDState *sd) { - int i, start, end; + int i; + uint64_t erase_start = sd->erase_start; + uint64_t erase_end = sd->erase_end; + if (!sd->erase_start || !sd->erase_end) { sd->card_status |= ERASE_SEQ_ERROR; return; } - start = sd_addr_to_wpnum(sd->erase_start); - end = sd_addr_to_wpnum(sd->erase_end); + if (extract32(sd->ocr, OCR_CCS_BITN, 1)) { + /* High capacity memory card: erase units are 512 byte blocks */ + erase_start *= 512; + erase_end *= 512; + } + + erase_start = sd_addr_to_wpnum(erase_start); + erase_end = sd_addr_to_wpnum(erase_end); sd->erase_start = 0; sd->erase_end = 0; sd->csd[14] |= 0x40; - for (i = start; i <= end; i++) { + for (i = erase_start; i <= erase_end; i++) { if (test_bit(i, sd->wp_groups)) { sd->card_status |= WP_ERASE_SKIP; } diff --git a/hw/sd.h b/hw/sd.h index 4eb9679acd..d9b97e4466 100644 --- a/hw/sd.h +++ b/hw/sd.h @@ -50,6 +50,7 @@ #define READY_FOR_DATA (1 << 8) #define APP_CMD (1 << 5) #define AKE_SEQ_ERROR (1 << 3) +#define OCR_CCS_BITN 30 typedef enum { sd_none = -1, From 08e99e296fbe695d13c8ac944867d9def7f7c5d0 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Tue, 30 Oct 2012 07:45:12 +0000 Subject: [PATCH 027/291] vmstate: Add support for saving/loading bitmaps Add support for saving/loading bitmap.h bitmaps in vmstate. Signed-off-by: Peter Maydell Tested-by: Igor Mitsyanko Reviewed-by: Juan Quintela --- savevm.c | 41 +++++++++++++++++++++++++++++++++++++++++ vmstate.h | 13 +++++++++++++ 2 files changed, 54 insertions(+) diff --git a/savevm.c b/savevm.c index b080d37258..43d3d1bbeb 100644 --- a/savevm.c +++ b/savevm.c @@ -86,6 +86,7 @@ #include "memory.h" #include "qmp-commands.h" #include "trace.h" +#include "bitops.h" #define SELF_ANNOUNCE_ROUNDS 5 @@ -1132,6 +1133,46 @@ const VMStateInfo vmstate_info_unused_buffer = { .put = put_unused_buffer, }; +/* bitmaps (as defined by bitmap.h). Note that size here is the size + * of the bitmap in bits. The on-the-wire format of a bitmap is 64 + * bit words with the bits in big endian order. The in-memory format + * is an array of 'unsigned long', which may be either 32 or 64 bits. + */ +/* This is the number of 64 bit words sent over the wire */ +#define BITS_TO_U64S(nr) DIV_ROUND_UP(nr, 64) +static int get_bitmap(QEMUFile *f, void *pv, size_t size) +{ + unsigned long *bmp = pv; + int i, idx = 0; + for (i = 0; i < BITS_TO_U64S(size); i++) { + uint64_t w = qemu_get_be64(f); + bmp[idx++] = w; + if (sizeof(unsigned long) == 4 && idx < BITS_TO_LONGS(size)) { + bmp[idx++] = w >> 32; + } + } + return 0; +} + +static void put_bitmap(QEMUFile *f, void *pv, size_t size) +{ + unsigned long *bmp = pv; + int i, idx = 0; + for (i = 0; i < BITS_TO_U64S(size); i++) { + uint64_t w = bmp[idx++]; + if (sizeof(unsigned long) == 4 && idx < BITS_TO_LONGS(size)) { + w |= ((uint64_t)bmp[idx++]) << 32; + } + qemu_put_be64(f, w); + } +} + +const VMStateInfo vmstate_info_bitmap = { + .name = "bitmap", + .get = get_bitmap, + .put = put_bitmap, +}; + typedef struct CompatEntry { char idstr[256]; int instance_id; diff --git a/vmstate.h b/vmstate.h index c9c320e62e..623af0a29a 100644 --- a/vmstate.h +++ b/vmstate.h @@ -139,6 +139,7 @@ extern const VMStateInfo vmstate_info_uint64; extern const VMStateInfo vmstate_info_timer; extern const VMStateInfo vmstate_info_buffer; extern const VMStateInfo vmstate_info_unused_buffer; +extern const VMStateInfo vmstate_info_bitmap; #define type_check_array(t1,t2,n) ((t1(*)[n])0 - (t2*)0) #define type_check_pointer(t1,t2) ((t1**)0 - (t2*)0) @@ -411,6 +412,18 @@ extern const VMStateInfo vmstate_info_unused_buffer; .flags = VMS_BUFFER, \ } +/* _field_size should be a int32_t field in the _state struct giving the + * size of the bitmap _field in bits. + */ +#define VMSTATE_BITMAP(_field, _state, _version, _field_size) { \ + .name = (stringify(_field)), \ + .version_id = (_version), \ + .size_offset = vmstate_offset_value(_state, _field_size, int32_t),\ + .info = &vmstate_info_bitmap, \ + .flags = VMS_VBUFFER|VMS_POINTER, \ + .offset = offsetof(_state, _field), \ +} + /* _f : field name _f_n : num of elements field_name _n : num of elements From 50a5be6c3d50c7684a417da4eb5f9587dace0a44 Mon Sep 17 00:00:00 2001 From: Igor Mitsyanko Date: Tue, 30 Oct 2012 07:45:12 +0000 Subject: [PATCH 028/291] hw/sd.c: add SD card save/load support This patch updates SD card model to support save/load of card's state. Signed-off-by: Igor Mitsyanko Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/sd.c | 89 +++++++++++++++++++++++++++++++++++++++++---------------- 1 file changed, 64 insertions(+), 25 deletions(-) diff --git a/hw/sd.c b/hw/sd.c index b2f211c13a..3c34d43ad4 100644 --- a/hw/sd.c +++ b/hw/sd.c @@ -55,24 +55,28 @@ typedef enum { sd_illegal = -2, } sd_rsp_type_t; +enum SDCardModes { + sd_inactive, + sd_card_identification_mode, + sd_data_transfer_mode, +}; + +enum SDCardStates { + sd_inactive_state = -1, + sd_idle_state = 0, + sd_ready_state, + sd_identification_state, + sd_standby_state, + sd_transfer_state, + sd_sendingdata_state, + sd_receivingdata_state, + sd_programming_state, + sd_disconnect_state, +}; + struct SDState { - enum { - sd_inactive, - sd_card_identification_mode, - sd_data_transfer_mode, - } mode; - enum { - sd_inactive_state = -1, - sd_idle_state = 0, - sd_ready_state, - sd_identification_state, - sd_standby_state, - sd_transfer_state, - sd_sendingdata_state, - sd_receivingdata_state, - sd_programming_state, - sd_disconnect_state, - } state; + uint32_t mode; /* current card mode, one of SDCardModes */ + int32_t state; /* current card state, one of SDCardStates */ uint32_t ocr; uint8_t scr[8]; uint8_t cid[16]; @@ -83,21 +87,22 @@ struct SDState { uint32_t vhs; bool wp_switch; unsigned long *wp_groups; + int32_t wpgrps_size; uint64_t size; - int blk_len; + uint32_t blk_len; uint32_t erase_start; uint32_t erase_end; uint8_t pwd[16]; - int pwd_len; - int function_group[6]; + uint32_t pwd_len; + uint8_t function_group[6]; bool spi; - int current_cmd; + uint8_t current_cmd; /* True if we will handle the next command as an ACMD. Note that this does * *not* track the APP_CMD status bit! */ bool expecting_acmd; - int blk_written; + uint32_t blk_written; uint64_t data_start; uint32_t data_offset; uint8_t data[512]; @@ -421,8 +426,9 @@ static void sd_reset(SDState *sd, BlockDriverState *bdrv) if (sd->wp_groups) g_free(sd->wp_groups); sd->wp_switch = bdrv ? bdrv_is_read_only(bdrv) : false; - sd->wp_groups = bitmap_new(sect); - memset(sd->function_group, 0, sizeof(int) * 6); + sd->wpgrps_size = sect; + sd->wp_groups = bitmap_new(sd->wpgrps_size); + memset(sd->function_group, 0, sizeof(sd->function_group)); sd->erase_start = 0; sd->erase_end = 0; sd->size = size; @@ -446,6 +452,38 @@ static const BlockDevOps sd_block_ops = { .change_media_cb = sd_cardchange, }; +static const VMStateDescription sd_vmstate = { + .name = "sd-card", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(mode, SDState), + VMSTATE_INT32(state, SDState), + VMSTATE_UINT8_ARRAY(cid, SDState, 16), + VMSTATE_UINT8_ARRAY(csd, SDState, 16), + VMSTATE_UINT16(rca, SDState), + VMSTATE_UINT32(card_status, SDState), + VMSTATE_PARTIAL_BUFFER(sd_status, SDState, 1), + VMSTATE_UINT32(vhs, SDState), + VMSTATE_BITMAP(wp_groups, SDState, 0, wpgrps_size), + VMSTATE_UINT32(blk_len, SDState), + VMSTATE_UINT32(erase_start, SDState), + VMSTATE_UINT32(erase_end, SDState), + VMSTATE_UINT8_ARRAY(pwd, SDState, 16), + VMSTATE_UINT32(pwd_len, SDState), + VMSTATE_UINT8_ARRAY(function_group, SDState, 6), + VMSTATE_UINT8(current_cmd, SDState), + VMSTATE_BOOL(expecting_acmd, SDState), + VMSTATE_UINT32(blk_written, SDState), + VMSTATE_UINT64(data_start, SDState), + VMSTATE_UINT32(data_offset, SDState), + VMSTATE_UINT8_ARRAY(data, SDState, 512), + VMSTATE_BUFFER_UNSAFE(buf, SDState, 1, 512), + VMSTATE_BOOL(enable, SDState), + VMSTATE_END_OF_LIST() + } +}; + /* We do not model the chip select pin, so allow the board to select whether card should be in SSI or MMC/SD mode. It is also up to the board to ensure that ssi transfers only occur when the chip select @@ -463,6 +501,7 @@ SDState *sd_init(BlockDriverState *bs, bool is_spi) bdrv_attach_dev_nofail(sd->bdrv, sd); bdrv_set_dev_ops(sd->bdrv, &sd_block_ops, sd); } + vmstate_register(NULL, -1, &sd_vmstate, sd); return sd; } @@ -576,7 +615,7 @@ static void sd_lock_command(SDState *sd) sd->card_status |= LOCK_UNLOCK_FAILED; return; } - bitmap_zero(sd->wp_groups, sd_addr_to_wpnum(sd->size) + 1); + bitmap_zero(sd->wp_groups, sd->wpgrps_size); sd->csd[14] &= ~0x10; sd->card_status &= ~CARD_IS_LOCKED; sd->pwd_len = 0; From 0191253ceaf442e595cdd12ce80233b9de28cd13 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 24 Oct 2012 14:58:39 +0200 Subject: [PATCH 029/291] janitor: move iovector functions out of cutils.c This removes the dependency of cutils.c on iov.c, and lets us remove iov.o from several builds. Signed-off-by: Paolo Bonzini --- Makefile | 2 +- Makefile.objs | 4 +- cutils.c | 103 ------------------------------------------------- iov.c | 103 +++++++++++++++++++++++++++++++++++++++++++++++++ tests/Makefile | 2 +- 5 files changed, 107 insertions(+), 107 deletions(-) diff --git a/Makefile b/Makefile index 17e2d58ce5..ca716017cf 100644 --- a/Makefile +++ b/Makefile @@ -161,7 +161,7 @@ qemu-img.o: qemu-img-cmds.h tools-obj-y = $(oslib-obj-y) $(trace-obj-y) qemu-tool.o qemu-timer.o \ qemu-timer-common.o main-loop.o notify.o \ - iohandler.o cutils.o iov.o async.o error.o + iohandler.o cutils.o async.o error.o tools-obj-$(CONFIG_POSIX) += compatfd.o qemu-img$(EXESUF): qemu-img.o $(tools-obj-y) $(block-obj-y) diff --git a/Makefile.objs b/Makefile.objs index 9eca179903..99a268e7bf 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -92,7 +92,7 @@ common-obj-y += ui/ common-obj-y += bt-host.o bt-vhci.o common-obj-y += dma-helpers.o -common-obj-y += iov.o acl.o +common-obj-y += acl.o common-obj-$(CONFIG_POSIX) += compatfd.o common-obj-y += event_notifier.o common-obj-y += qemu-timer.o qemu-timer-common.o @@ -113,7 +113,7 @@ endif user-obj-y = user-obj-y += envlist.o path.o user-obj-y += tcg-runtime.o host-utils.o -user-obj-y += cutils.o iov.o cache-utils.o +user-obj-y += cutils.o cache-utils.o user-obj-y += module.o user-obj-y += qemu-user.o user-obj-y += $(trace-obj-y) diff --git a/cutils.c b/cutils.c index 8edd8fa13c..6f9f799bd3 100644 --- a/cutils.c +++ b/cutils.c @@ -142,109 +142,6 @@ int qemu_fdatasync(int fd) #endif } -/* io vectors */ - -void qemu_iovec_init(QEMUIOVector *qiov, int alloc_hint) -{ - qiov->iov = g_malloc(alloc_hint * sizeof(struct iovec)); - qiov->niov = 0; - qiov->nalloc = alloc_hint; - qiov->size = 0; -} - -void qemu_iovec_init_external(QEMUIOVector *qiov, struct iovec *iov, int niov) -{ - int i; - - qiov->iov = iov; - qiov->niov = niov; - qiov->nalloc = -1; - qiov->size = 0; - for (i = 0; i < niov; i++) - qiov->size += iov[i].iov_len; -} - -void qemu_iovec_add(QEMUIOVector *qiov, void *base, size_t len) -{ - assert(qiov->nalloc != -1); - - if (qiov->niov == qiov->nalloc) { - qiov->nalloc = 2 * qiov->nalloc + 1; - qiov->iov = g_realloc(qiov->iov, qiov->nalloc * sizeof(struct iovec)); - } - qiov->iov[qiov->niov].iov_base = base; - qiov->iov[qiov->niov].iov_len = len; - qiov->size += len; - ++qiov->niov; -} - -/* - * Concatenates (partial) iovecs from src to the end of dst. - * It starts copying after skipping `soffset' bytes at the - * beginning of src and adds individual vectors from src to - * dst copies up to `sbytes' bytes total, or up to the end - * of src if it comes first. This way, it is okay to specify - * very large value for `sbytes' to indicate "up to the end - * of src". - * Only vector pointers are processed, not the actual data buffers. - */ -void qemu_iovec_concat(QEMUIOVector *dst, - QEMUIOVector *src, size_t soffset, size_t sbytes) -{ - int i; - size_t done; - struct iovec *siov = src->iov; - assert(dst->nalloc != -1); - assert(src->size >= soffset); - for (i = 0, done = 0; done < sbytes && i < src->niov; i++) { - if (soffset < siov[i].iov_len) { - size_t len = MIN(siov[i].iov_len - soffset, sbytes - done); - qemu_iovec_add(dst, siov[i].iov_base + soffset, len); - done += len; - soffset = 0; - } else { - soffset -= siov[i].iov_len; - } - } - /* return done; */ -} - -void qemu_iovec_destroy(QEMUIOVector *qiov) -{ - assert(qiov->nalloc != -1); - - qemu_iovec_reset(qiov); - g_free(qiov->iov); - qiov->nalloc = 0; - qiov->iov = NULL; -} - -void qemu_iovec_reset(QEMUIOVector *qiov) -{ - assert(qiov->nalloc != -1); - - qiov->niov = 0; - qiov->size = 0; -} - -size_t qemu_iovec_to_buf(QEMUIOVector *qiov, size_t offset, - void *buf, size_t bytes) -{ - return iov_to_buf(qiov->iov, qiov->niov, offset, buf, bytes); -} - -size_t qemu_iovec_from_buf(QEMUIOVector *qiov, size_t offset, - const void *buf, size_t bytes) -{ - return iov_from_buf(qiov->iov, qiov->niov, offset, buf, bytes); -} - -size_t qemu_iovec_memset(QEMUIOVector *qiov, size_t offset, - int fillc, size_t bytes) -{ - return iov_memset(qiov->iov, qiov->niov, offset, fillc, bytes); -} - /* * Checks if a buffer is all zeroes * diff --git a/iov.c b/iov.c index c6a66f0afe..ae17e7dff6 100644 --- a/iov.c +++ b/iov.c @@ -228,3 +228,106 @@ void iov_hexdump(const struct iovec *iov, const unsigned int iov_cnt, fprintf(fp, "\n"); } } + +/* io vectors */ + +void qemu_iovec_init(QEMUIOVector *qiov, int alloc_hint) +{ + qiov->iov = g_malloc(alloc_hint * sizeof(struct iovec)); + qiov->niov = 0; + qiov->nalloc = alloc_hint; + qiov->size = 0; +} + +void qemu_iovec_init_external(QEMUIOVector *qiov, struct iovec *iov, int niov) +{ + int i; + + qiov->iov = iov; + qiov->niov = niov; + qiov->nalloc = -1; + qiov->size = 0; + for (i = 0; i < niov; i++) + qiov->size += iov[i].iov_len; +} + +void qemu_iovec_add(QEMUIOVector *qiov, void *base, size_t len) +{ + assert(qiov->nalloc != -1); + + if (qiov->niov == qiov->nalloc) { + qiov->nalloc = 2 * qiov->nalloc + 1; + qiov->iov = g_realloc(qiov->iov, qiov->nalloc * sizeof(struct iovec)); + } + qiov->iov[qiov->niov].iov_base = base; + qiov->iov[qiov->niov].iov_len = len; + qiov->size += len; + ++qiov->niov; +} + +/* + * Concatenates (partial) iovecs from src to the end of dst. + * It starts copying after skipping `soffset' bytes at the + * beginning of src and adds individual vectors from src to + * dst copies up to `sbytes' bytes total, or up to the end + * of src if it comes first. This way, it is okay to specify + * very large value for `sbytes' to indicate "up to the end + * of src". + * Only vector pointers are processed, not the actual data buffers. + */ +void qemu_iovec_concat(QEMUIOVector *dst, + QEMUIOVector *src, size_t soffset, size_t sbytes) +{ + int i; + size_t done; + struct iovec *siov = src->iov; + assert(dst->nalloc != -1); + assert(src->size >= soffset); + for (i = 0, done = 0; done < sbytes && i < src->niov; i++) { + if (soffset < siov[i].iov_len) { + size_t len = MIN(siov[i].iov_len - soffset, sbytes - done); + qemu_iovec_add(dst, siov[i].iov_base + soffset, len); + done += len; + soffset = 0; + } else { + soffset -= siov[i].iov_len; + } + } + /* return done; */ +} + +void qemu_iovec_destroy(QEMUIOVector *qiov) +{ + assert(qiov->nalloc != -1); + + qemu_iovec_reset(qiov); + g_free(qiov->iov); + qiov->nalloc = 0; + qiov->iov = NULL; +} + +void qemu_iovec_reset(QEMUIOVector *qiov) +{ + assert(qiov->nalloc != -1); + + qiov->niov = 0; + qiov->size = 0; +} + +size_t qemu_iovec_to_buf(QEMUIOVector *qiov, size_t offset, + void *buf, size_t bytes) +{ + return iov_to_buf(qiov->iov, qiov->niov, offset, buf, bytes); +} + +size_t qemu_iovec_from_buf(QEMUIOVector *qiov, size_t offset, + const void *buf, size_t bytes) +{ + return iov_from_buf(qiov->iov, qiov->niov, offset, buf, bytes); +} + +size_t qemu_iovec_memset(QEMUIOVector *qiov, size_t offset, + int fillc, size_t bytes) +{ + return iov_memset(qiov->iov, qiov->niov, offset, fillc, bytes); +} diff --git a/tests/Makefile b/tests/Makefile index 86c9b79ebe..945c82311e 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -48,7 +48,7 @@ tests/check-qdict$(EXESUF): tests/check-qdict.o qdict.o qfloat.o qint.o qstring. tests/check-qlist$(EXESUF): tests/check-qlist.o qlist.o qint.o tests/check-qfloat$(EXESUF): tests/check-qfloat.o qfloat.o tests/check-qjson$(EXESUF): tests/check-qjson.o $(qobject-obj-y) $(tools-obj-y) -tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(coroutine-obj-y) $(tools-obj-y) +tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(coroutine-obj-y) $(tools-obj-y) iov.o tests/test-iov$(EXESUF): tests/test-iov.o iov.o tests/test-qapi-types.c tests/test-qapi-types.h :\ From f3192e8fb28529dd4fd777f916c437f49098ad39 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 15:40:03 +0100 Subject: [PATCH 030/291] build: move cutils.o and qemu-timer-common.o to oslib-obj-y Signed-off-by: Paolo Bonzini --- Makefile | 3 +-- Makefile.objs | 6 +++--- 2 files changed, 4 insertions(+), 5 deletions(-) diff --git a/Makefile b/Makefile index ca716017cf..4bfeeab80f 100644 --- a/Makefile +++ b/Makefile @@ -160,8 +160,7 @@ endif qemu-img.o: qemu-img-cmds.h tools-obj-y = $(oslib-obj-y) $(trace-obj-y) qemu-tool.o qemu-timer.o \ - qemu-timer-common.o main-loop.o notify.o \ - iohandler.o cutils.o async.o error.o + main-loop.o notify.o iohandler.o async.o error.o tools-obj-$(CONFIG_POSIX) += compatfd.o qemu-img$(EXESUF): qemu-img.o $(tools-obj-y) $(block-obj-y) diff --git a/Makefile.objs b/Makefile.objs index 99a268e7bf..9e36166e8b 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -19,7 +19,7 @@ universal-obj-y += $(qom-obj-y) ####################################################################### # oslib-obj-y is code depending on the OS (win32 vs posix) -oslib-obj-y = osdep.o +oslib-obj-y = osdep.o cutils.o qemu-timer-common.o oslib-obj-$(CONFIG_WIN32) += oslib-win32.o qemu-thread-win32.o oslib-obj-$(CONFIG_POSIX) += oslib-posix.o qemu-thread-posix.o @@ -41,7 +41,7 @@ coroutine-obj-$(CONFIG_WIN32) += coroutine-win32.o ####################################################################### # block-obj-y is code used by both qemu system emulation and qemu-img -block-obj-y = cutils.o iov.o cache-utils.o qemu-option.o module.o async.o +block-obj-y = iov.o cache-utils.o qemu-option.o module.o async.o block-obj-y += nbd.o block.o blockjob.o aio.o aes.o qemu-config.o block-obj-y += qemu-progress.o qemu-sockets.o uri.o notify.o block-obj-y += $(coroutine-obj-y) $(qobject-obj-y) $(version-obj-y) @@ -113,7 +113,7 @@ endif user-obj-y = user-obj-y += envlist.o path.o user-obj-y += tcg-runtime.o host-utils.o -user-obj-y += cutils.o cache-utils.o +user-obj-y += cache-utils.o user-obj-y += module.o user-obj-y += qemu-user.o user-obj-y += $(trace-obj-y) From 67d223be90178f7142b4f566358cea446af8df74 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 15:11:30 +0100 Subject: [PATCH 031/291] compiler: use weak aliases to provide default definitions This is simpler and more portable. Signed-off-by: Paolo Bonzini --- arch_init.h | 2 +- compiler.h | 11 ++++------- qmp.c | 3 ++- 3 files changed, 7 insertions(+), 9 deletions(-) diff --git a/arch_init.h b/arch_init.h index d9c572aee8..5fc780c63d 100644 --- a/arch_init.h +++ b/arch_init.h @@ -34,6 +34,6 @@ int tcg_available(void); int kvm_available(void); int xen_available(void); -CpuDefinitionInfoList GCC_WEAK_DECL *arch_query_cpu_definitions(Error **errp); +CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp); #endif diff --git a/compiler.h b/compiler.h index c734a71c67..58865d65e8 100644 --- a/compiler.h +++ b/compiler.h @@ -50,16 +50,13 @@ # define __printf__ __gnu_printf__ # endif # endif -#if defined(_WIN32) -#define GCC_WEAK __attribute__((weak)) -#define GCC_WEAK_DECL GCC_WEAK -#else -#define GCC_WEAK __attribute__((weak)) -#define GCC_WEAK_DECL -#endif +# define QEMU_WEAK_ALIAS(newname, oldname) \ + typeof(oldname) newname __attribute__((weak, alias (#oldname))) #else #define GCC_ATTR /**/ #define GCC_FMT_ATTR(n, m) +#define QEMU_WEAK_ALIAS(newname, oldname) \ + _Pragma("weak " #newname "=" #oldname) #endif #endif /* COMPILER_H */ diff --git a/qmp.c b/qmp.c index 31bc3bfdd1..df952b60bc 100644 --- a/qmp.c +++ b/qmp.c @@ -466,11 +466,12 @@ DevicePropertyInfoList *qmp_device_list_properties(const char *typename, return prop_list; } -CpuDefinitionInfoList GCC_WEAK *arch_query_cpu_definitions(Error **errp) +static CpuDefinitionInfoList *default_arch_query_cpu_definitions(Error **errp) { error_set(errp, QERR_NOT_SUPPORTED); return NULL; } +QEMU_WEAK_ALIAS(arch_query_cpu_definitions, default_arch_query_cpu_definitions); CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) { From d249e1fc4fda57399fe64b3c0290d5d585fdf2e5 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 15:15:15 +0100 Subject: [PATCH 032/291] sockets: use weak aliases instead of qemu-tool.c qemu-tool.c has its own (largeish) set of dependencies. Weak aliases can be placed directly where people use them, and do not contribute to increasing the dependencies of generic utility files. Signed-off-by: Paolo Bonzini --- qemu-sockets.c | 7 +++++++ qemu-tool.c | 6 ------ 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/qemu-sockets.c b/qemu-sockets.c index cfed9c5a5b..225cd0c162 100644 --- a/qemu-sockets.c +++ b/qemu-sockets.c @@ -967,3 +967,10 @@ int socket_init(void) #endif return 0; } + +static int default_monitor_get_fd(Monitor *mon, const char *name, Error **errp) +{ + error_setg(errp, "only QEMU supports file descriptor passing"); + return -1; +} +QEMU_WEAK_ALIAS(monitor_get_fd, default_monitor_get_fd); diff --git a/qemu-tool.c b/qemu-tool.c index da4c05aaf7..f2f98138ce 100644 --- a/qemu-tool.c +++ b/qemu-tool.c @@ -38,12 +38,6 @@ const char *qemu_get_vm_name(void) Monitor *cur_mon; -int monitor_get_fd(Monitor *mon, const char *name, Error **errp) -{ - error_setg(errp, "only QEMU supports file descriptor passing"); - return -1; -} - void vm_stop(RunState state) { abort(); From 0100fbbe73f1455ac66ec172627ff251a1f25302 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 15:19:18 +0100 Subject: [PATCH 033/291] fdsets: use weak aliases instead of qemu-tool.c/qemu-user.c Signed-off-by: Paolo Bonzini --- cutils.c | 5 ----- osdep.c | 30 ++++++++++++++++++++++++++++++ qemu-common.h | 1 - qemu-tool.c | 20 -------------------- qemu-user.c | 20 -------------------- 5 files changed, 30 insertions(+), 46 deletions(-) diff --git a/cutils.c b/cutils.c index 6f9f799bd3..4f0692f78e 100644 --- a/cutils.c +++ b/cutils.c @@ -280,11 +280,6 @@ int qemu_parse_fd(const char *param) return fd; } -int qemu_parse_fdset(const char *param) -{ - return qemu_parse_fd(param); -} - /* round down to the nearest power of 2*/ int64_t pow2floor(int64_t value) { diff --git a/osdep.c b/osdep.c index 3b25297a25..0061f7473f 100644 --- a/osdep.c +++ b/osdep.c @@ -144,6 +144,11 @@ fail: errno = serrno; return -1; } + +static int qemu_parse_fdset(const char *param) +{ + return qemu_parse_fd(param); +} #endif /* @@ -404,3 +409,28 @@ bool fips_get_state(void) { return fips_enabled; } + + +static int default_fdset_get_fd(int64_t fdset_id, int flags) +{ + return -1; +} +QEMU_WEAK_ALIAS(monitor_fdset_get_fd, default_fdset_get_fd); + +static int default_fdset_dup_fd_add(int64_t fdset_id, int dup_fd) +{ + return -1; +} +QEMU_WEAK_ALIAS(monitor_fdset_dup_fd_add, default_fdset_dup_fd_add); + +static int default_fdset_dup_fd_remove(int dup_fd) +{ + return -1; +} +QEMU_WEAK_ALIAS(monitor_fdset_dup_fd_remove, default_fdset_dup_fd_remove); + +static int default_fdset_dup_fd_find(int dup_fd) +{ + return -1; +} +QEMU_WEAK_ALIAS(monitor_fdset_dup_fd_find, default_fdset_dup_fd_find); diff --git a/qemu-common.h b/qemu-common.h index b54612b1a5..36ce522066 100644 --- a/qemu-common.h +++ b/qemu-common.h @@ -167,7 +167,6 @@ int qemu_fls(int i); int qemu_fdatasync(int fd); int fcntl_setfl(int fd, int flag); int qemu_parse_fd(const char *param); -int qemu_parse_fdset(const char *param); /* * strtosz() suffixes used to specify the default treatment of an diff --git a/qemu-tool.c b/qemu-tool.c index f2f98138ce..84273ae077 100644 --- a/qemu-tool.c +++ b/qemu-tool.c @@ -68,26 +68,6 @@ void monitor_protocol_event(MonitorEvent event, QObject *data) { } -int monitor_fdset_get_fd(int64_t fdset_id, int flags) -{ - return -1; -} - -int monitor_fdset_dup_fd_add(int64_t fdset_id, int dup_fd) -{ - return -1; -} - -int monitor_fdset_dup_fd_remove(int dup_fd) -{ - return -1; -} - -int monitor_fdset_dup_fd_find(int dup_fd) -{ - return -1; -} - int64_t cpu_get_clock(void) { return qemu_get_clock_ns(rt_clock); diff --git a/qemu-user.c b/qemu-user.c index 13fb9ae77b..08ccb0fe8e 100644 --- a/qemu-user.c +++ b/qemu-user.c @@ -35,23 +35,3 @@ void monitor_vprintf(Monitor *mon, const char *fmt, va_list ap) void monitor_set_error(Monitor *mon, QError *qerror) { } - -int monitor_fdset_get_fd(int64_t fdset_id, int flags) -{ - return -1; -} - -int monitor_fdset_dup_fd_add(int64_t fdset_id, int dup_fd) -{ - return -1; -} - -int monitor_fdset_dup_fd_remove(int dup_fd) -{ - return -1; -} - -int monitor_fdset_dup_fd_find(int dup_fd) -{ - return -1; -} From 462016d2da393b743ba97552521378e7de2a4c7f Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 15:23:16 +0100 Subject: [PATCH 034/291] iohandler: add weak alias in qemu-sockets.c, for qemu-ga Signed-off-by: Paolo Bonzini --- qemu-sockets.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/qemu-sockets.c b/qemu-sockets.c index 225cd0c162..f2a637165b 100644 --- a/qemu-sockets.c +++ b/qemu-sockets.c @@ -974,3 +974,14 @@ static int default_monitor_get_fd(Monitor *mon, const char *name, Error **errp) return -1; } QEMU_WEAK_ALIAS(monitor_get_fd, default_monitor_get_fd); + +static int default_qemu_set_fd_handler2(int fd, + IOCanReadHandler *fd_read_poll, + IOHandler *fd_read, + IOHandler *fd_write, + void *opaque) + +{ + abort(); +} +QEMU_WEAK_ALIAS(qemu_set_fd_handler2, default_qemu_set_fd_handler2); From dbb5f3802e20af9a9971aa98d27c58839ea79a94 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 18:55:03 +0100 Subject: [PATCH 035/291] win32: add weak version of qemu_fd_register Signed-off-by: Paolo Bonzini --- oslib-win32.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/oslib-win32.c b/oslib-win32.c index 51b33e8b20..9ca83df011 100644 --- a/oslib-win32.c +++ b/oslib-win32.c @@ -150,3 +150,8 @@ int qemu_get_thread_id(void) { return GetCurrentThreadId(); } + +static void default_qemu_fd_register(int fd) +{ +} +QEMU_WEAK_ALIAS(qemu_fd_register, default_qemu_fd_register); From 744ca8e3754e6808c6b5331d287adc533fca0ad3 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 15:26:28 +0100 Subject: [PATCH 036/291] qemu-timer: make initialization functions idempotent Signed-off-by: Paolo Bonzini --- qemu-timer.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/qemu-timer.c b/qemu-timer.c index 908a1030b6..b71e9a6e62 100644 --- a/qemu-timer.c +++ b/qemu-timer.c @@ -430,9 +430,11 @@ void qemu_unregister_clock_reset_notifier(QEMUClock *clock, Notifier *notifier) void init_clocks(void) { - rt_clock = qemu_new_clock(QEMU_CLOCK_REALTIME); - vm_clock = qemu_new_clock(QEMU_CLOCK_VIRTUAL); - host_clock = qemu_new_clock(QEMU_CLOCK_HOST); + if (!rt_clock) { + rt_clock = qemu_new_clock(QEMU_CLOCK_REALTIME); + vm_clock = qemu_new_clock(QEMU_CLOCK_VIRTUAL); + host_clock = qemu_new_clock(QEMU_CLOCK_HOST); + } } uint64_t qemu_timer_expire_time_ns(QEMUTimer *ts) @@ -745,6 +747,10 @@ int init_timer_alarm(void) struct qemu_alarm_timer *t = NULL; int i, err = -1; + if (alarm_timer) { + return 0; + } + for (i = 0; alarm_timers[i].name; i++) { t = &alarm_timers[i]; From 172061a0a0d98c974ea8d5ed715195237bc44225 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 15:28:36 +0100 Subject: [PATCH 037/291] main-loop: unify qemu_init_main_loop between QEMU and tools Signed-off-by: Paolo Bonzini --- main-loop.c | 5 ++++- main-loop.h | 10 ---------- qemu-tool.c | 7 ------- vl.c | 5 ----- 4 files changed, 4 insertions(+), 23 deletions(-) diff --git a/main-loop.c b/main-loop.c index eb3b6e6253..baefe413d1 100644 --- a/main-loop.c +++ b/main-loop.c @@ -199,10 +199,13 @@ static int qemu_signal_init(void) } #endif -int main_loop_init(void) +int qemu_init_main_loop(void) { int ret; + init_clocks(); + init_timer_alarm(); + qemu_mutex_lock_iothread(); ret = qemu_signal_init(); if (ret) { diff --git a/main-loop.h b/main-loop.h index dce1cd9d7c..91a0aff9c7 100644 --- a/main-loop.h +++ b/main-loop.h @@ -42,16 +42,6 @@ */ int qemu_init_main_loop(void); -/** - * main_loop_init: Initializes main loop - * - * Internal (but shared for compatibility reasons) initialization routine - * for the main loop. This should not be used by applications directly, - * use qemu_init_main_loop() instead. - * - */ -int main_loop_init(void); - /** * main_loop_wait: Run one iteration of the main loop. * diff --git a/qemu-tool.c b/qemu-tool.c index 84273ae077..28a4e8d42a 100644 --- a/qemu-tool.c +++ b/qemu-tool.c @@ -92,13 +92,6 @@ void qemu_clock_warp(QEMUClock *clock) { } -int qemu_init_main_loop(void) -{ - init_clocks(); - init_timer_alarm(); - return main_loop_init(); -} - void slirp_update_timeout(uint32_t *timeout) { } diff --git a/vl.c b/vl.c index 9f99ef4763..b3186fa425 100644 --- a/vl.c +++ b/vl.c @@ -2357,11 +2357,6 @@ static void free_and_trace(gpointer mem) free(mem); } -int qemu_init_main_loop(void) -{ - return main_loop_init(); -} - int main(int argc, char **argv, char **envp) { int i; From 3f4cdf151145f7eaa3480aea5d81d7def2f85a68 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 18:03:10 +0100 Subject: [PATCH 038/291] qemu-tool: do not depend on qemu-timer.c Signed-off-by: Paolo Bonzini --- qemu-tool.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu-tool.c b/qemu-tool.c index 28a4e8d42a..b46631e422 100644 --- a/qemu-tool.c +++ b/qemu-tool.c @@ -70,7 +70,7 @@ void monitor_protocol_event(MonitorEvent event, QObject *data) int64_t cpu_get_clock(void) { - return qemu_get_clock_ns(rt_clock); + return get_clock_realtime(); } int64_t cpu_get_icount(void) From 63186e56c8b5f1c988bfb0d707e76f0f0dceef90 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 30 Oct 2012 09:30:17 +0100 Subject: [PATCH 039/291] build: opts-visitor is not really part of QAPI It is only used by QEMU itself, do not build it into the tests. Signed-off-by: Paolo Bonzini --- qapi/Makefile.objs | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/qapi/Makefile.objs b/qapi/Makefile.objs index 5f5846e767..f9bd3b9910 100644 --- a/qapi/Makefile.objs +++ b/qapi/Makefile.objs @@ -1,3 +1,5 @@ qapi-obj-y = qapi-visit-core.o qapi-dealloc-visitor.o qmp-input-visitor.o qapi-obj-y += qmp-output-visitor.o qmp-registry.o qmp-dispatch.o -qapi-obj-y += string-input-visitor.o string-output-visitor.o opts-visitor.o +qapi-obj-y += string-input-visitor.o string-output-visitor.o + +common-obj-y += opts-visitor.o From 136594f19aa6370e77a50bd9bba5db77def6ec8f Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 15:46:15 +0100 Subject: [PATCH 040/291] build: do not include main loop where it is not actually used Signed-off-by: Paolo Bonzini --- Makefile | 6 +++--- Makefile.objs | 5 ++--- tests/Makefile | 8 ++++---- 3 files changed, 9 insertions(+), 10 deletions(-) diff --git a/Makefile b/Makefile index 4bfeeab80f..3ff63df732 100644 --- a/Makefile +++ b/Makefile @@ -160,7 +160,7 @@ endif qemu-img.o: qemu-img-cmds.h tools-obj-y = $(oslib-obj-y) $(trace-obj-y) qemu-tool.o qemu-timer.o \ - main-loop.o notify.o iohandler.o async.o error.o + main-loop.o iohandler.o error.o tools-obj-$(CONFIG_POSIX) += compatfd.o qemu-img$(EXESUF): qemu-img.o $(tools-obj-y) $(block-obj-y) @@ -169,7 +169,7 @@ qemu-io$(EXESUF): qemu-io.o cmd.o $(tools-obj-y) $(block-obj-y) qemu-bridge-helper$(EXESUF): qemu-bridge-helper.o -vscclient$(EXESUF): $(libcacard-y) $(oslib-obj-y) $(trace-obj-y) $(tools-obj-y) qemu-timer-common.o libcacard/vscclient.o +vscclient$(EXESUF): $(libcacard-y) $(oslib-obj-y) $(trace-obj-y) libcacard/vscclient.o $(call quiet-command,$(CC) $(LDFLAGS) -o $@ $^ $(libcacard_libs) $(LIBS)," LINK $@") fsdev/virtfs-proxy-helper$(EXESUF): fsdev/virtfs-proxy-helper.o fsdev/virtio-9p-marshal.o oslib-posix.o $(trace-obj-y) @@ -212,7 +212,7 @@ $(SRC_PATH)/qapi-schema.json $(SRC_PATH)/scripts/qapi-commands.py $(qapi-py) QGALIB_GEN=$(addprefix qga/qapi-generated/, qga-qapi-types.h qga-qapi-visit.h qga-qmp-commands.h) $(qga-obj-y) qemu-ga.o: $(QGALIB_GEN) -qemu-ga$(EXESUF): qemu-ga.o $(qga-obj-y) $(tools-obj-y) $(qapi-obj-y) $(qobject-obj-y) $(version-obj-y) +qemu-ga$(EXESUF): qemu-ga.o $(qga-obj-y) $(oslib-obj-y) $(trace-obj-y) $(qapi-obj-y) $(qobject-obj-y) $(version-obj-y) QEMULIBS=libuser libdis libdis-user diff --git a/Makefile.objs b/Makefile.objs index 9e36166e8b..54daa9f110 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -228,9 +228,8 @@ universal-obj-y += $(qapi-obj-y) ###################################################################### # guest agent -qga-obj-y = qga/ qemu-ga.o module.o -qga-obj-$(CONFIG_WIN32) += oslib-win32.o -qga-obj-$(CONFIG_POSIX) += oslib-posix.o qemu-sockets.o qemu-option.o +qga-obj-y = qga/ qemu-ga.o module.o qemu-tool.o +qga-obj-$(CONFIG_POSIX) += qemu-sockets.o qemu-option.o vl.o: QEMU_CFLAGS+=$(GPROF_CFLAGS) diff --git a/tests/Makefile b/tests/Makefile index 945c82311e..9bf0765de3 100644 --- a/tests/Makefile +++ b/tests/Makefile @@ -36,7 +36,7 @@ test-obj-y = tests/check-qint.o tests/check-qstring.o tests/check-qdict.o \ tests/test-qmp-input-visitor.o tests/test-qmp-input-strict.o \ tests/test-qmp-commands.o tests/test-visitor-serialization.o -test-qapi-obj-y = $(qobject-obj-y) $(qapi-obj-y) $(tools-obj-y) +test-qapi-obj-y = $(qobject-obj-y) $(qapi-obj-y) qemu-tool.o test-qapi-obj-y += tests/test-qapi-visit.o tests/test-qapi-types.o test-qapi-obj-y += module.o @@ -47,8 +47,8 @@ tests/check-qstring$(EXESUF): tests/check-qstring.o qstring.o tests/check-qdict$(EXESUF): tests/check-qdict.o qdict.o qfloat.o qint.o qstring.o qbool.o qlist.o tests/check-qlist$(EXESUF): tests/check-qlist.o qlist.o qint.o tests/check-qfloat$(EXESUF): tests/check-qfloat.o qfloat.o -tests/check-qjson$(EXESUF): tests/check-qjson.o $(qobject-obj-y) $(tools-obj-y) -tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(coroutine-obj-y) $(tools-obj-y) iov.o +tests/check-qjson$(EXESUF): tests/check-qjson.o $(qobject-obj-y) qemu-tool.o +tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(coroutine-obj-y) $(tools-obj-y) $(block-obj-y) iov.o tests/test-iov$(EXESUF): tests/test-iov.o iov.o tests/test-qapi-types.c tests/test-qapi-types.h :\ @@ -81,7 +81,7 @@ TARGETS=$(patsubst %-softmmu,%, $(filter %-softmmu,$(TARGET_DIRS))) QTEST_TARGETS=$(foreach TARGET,$(TARGETS), $(if $(check-qtest-$(TARGET)-y), $(TARGET),)) check-qtest-$(CONFIG_POSIX)=$(foreach TARGET,$(TARGETS), $(check-qtest-$(TARGET)-y)) -qtest-obj-y = tests/libqtest.o $(oslib-obj-y) $(tools-obj-y) +qtest-obj-y = tests/libqtest.o $(oslib-obj-y) $(check-qtest-y): $(qtest-obj-y) .PHONY: check-help From fc97a652de3e54394ca4d0e5e5d689fd8aba8b6f Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 24 May 2010 17:26:13 +0200 Subject: [PATCH 041/291] event_notifier: add Win32 implementation Signed-off-by: Paolo Bonzini --- Makefile.objs | 3 +- event_notifier.c => event_notifier-posix.c | 0 event_notifier-win32.c | 59 ++++++++++++++++++++++ event_notifier.h | 17 ++++++- qemu-os-win32.h | 1 - 5 files changed, 76 insertions(+), 4 deletions(-) rename event_notifier.c => event_notifier-posix.c (100%) create mode 100644 event_notifier-win32.c diff --git a/Makefile.objs b/Makefile.objs index 54daa9f110..5b39c33560 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -94,7 +94,8 @@ common-obj-y += bt-host.o bt-vhci.o common-obj-y += dma-helpers.o common-obj-y += acl.o common-obj-$(CONFIG_POSIX) += compatfd.o -common-obj-y += event_notifier.o +common-obj-$(CONFIG_POSIX) += event_notifier-posix.o +common-obj-$(CONFIG_WIN32) += event_notifier-win32.o common-obj-y += qemu-timer.o qemu-timer-common.o common-obj-y += qtest.o common-obj-y += vl.o diff --git a/event_notifier.c b/event_notifier-posix.c similarity index 100% rename from event_notifier.c rename to event_notifier-posix.c diff --git a/event_notifier-win32.c b/event_notifier-win32.c new file mode 100644 index 0000000000..c723dadf31 --- /dev/null +++ b/event_notifier-win32.c @@ -0,0 +1,59 @@ +/* + * event notifier support + * + * Copyright Red Hat, Inc. 2010 + * + * Authors: + * Michael S. Tsirkin + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu-common.h" +#include "event_notifier.h" +#include "main-loop.h" + +int event_notifier_init(EventNotifier *e, int active) +{ + e->event = CreateEvent(NULL, FALSE, FALSE, NULL); + assert(e->event); + return 0; +} + +void event_notifier_cleanup(EventNotifier *e) +{ + CloseHandle(e->event); +} + +HANDLE event_notifier_get_handle(EventNotifier *e) +{ + return e->event; +} + +int event_notifier_set_handler(EventNotifier *e, + EventNotifierHandler *handler) +{ + if (handler) { + return qemu_add_wait_object(e->event, (IOHandler *)handler, e); + } else { + qemu_del_wait_object(e->event, (IOHandler *)handler, e); + return 0; + } +} + +int event_notifier_set(EventNotifier *e) +{ + SetEvent(e->event); + return 0; +} + +int event_notifier_test_and_clear(EventNotifier *e) +{ + int ret = WaitForSingleObject(e->event, 0); + if (ret == WAIT_OBJECT_0) { + ResetEvent(e->event); + return true; + } + return false; +} diff --git a/event_notifier.h b/event_notifier.h index f0ec2f2171..b283a497ce 100644 --- a/event_notifier.h +++ b/event_notifier.h @@ -15,18 +15,31 @@ #include "qemu-common.h" +#ifdef _WIN32 +#include +#endif + struct EventNotifier { +#ifdef _WIN32 + HANDLE event; +#else int fd; +#endif }; typedef void EventNotifierHandler(EventNotifier *); -void event_notifier_init_fd(EventNotifier *, int fd); int event_notifier_init(EventNotifier *, int active); void event_notifier_cleanup(EventNotifier *); -int event_notifier_get_fd(EventNotifier *); int event_notifier_set(EventNotifier *); int event_notifier_test_and_clear(EventNotifier *); int event_notifier_set_handler(EventNotifier *, EventNotifierHandler *); +#ifdef CONFIG_POSIX +void event_notifier_init_fd(EventNotifier *, int fd); +int event_notifier_get_fd(EventNotifier *); +#else +HANDLE event_notifier_get_handle(EventNotifier *); +#endif + #endif diff --git a/qemu-os-win32.h b/qemu-os-win32.h index 8ba466dbfb..d0e9234d24 100644 --- a/qemu-os-win32.h +++ b/qemu-os-win32.h @@ -28,7 +28,6 @@ #include #include -#include "main-loop.h" /* Workaround for older versions of MinGW. */ #ifndef ECONNREFUSED From d0cc2fbfa607678866475383c508be84818ceb64 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 24 May 2010 17:17:04 +0200 Subject: [PATCH 042/291] event_notifier: enable it to use pipes This takes the eventfd emulation code from the main loop. When the EventNotifier is used for the main loop too, we need this compatibility code. Without CONFIG_EVENTFD, event_notifier_get_fd is only usable for the "read" side of the notifier, for example to set a select() handler. The return value of event_notifier_set changes to the cleaner 0/-errno. No caller is actually checking the return value. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- event_notifier-posix.c | 85 ++++++++++++++++++++++++++++++++++-------- event_notifier.h | 3 +- 2 files changed, 71 insertions(+), 17 deletions(-) diff --git a/event_notifier-posix.c b/event_notifier-posix.c index 2c207e1399..6f3239a3fc 100644 --- a/event_notifier-posix.c +++ b/event_notifier-posix.c @@ -20,48 +20,101 @@ void event_notifier_init_fd(EventNotifier *e, int fd) { - e->fd = fd; + e->rfd = fd; + e->wfd = fd; } int event_notifier_init(EventNotifier *e, int active) { + int fds[2]; + int ret; + #ifdef CONFIG_EVENTFD - int fd = eventfd(!!active, EFD_NONBLOCK | EFD_CLOEXEC); - if (fd < 0) - return -errno; - e->fd = fd; - return 0; + ret = eventfd(0, EFD_NONBLOCK | EFD_CLOEXEC); #else - return -ENOSYS; + ret = -1; + errno = ENOSYS; #endif + if (ret >= 0) { + e->rfd = e->wfd = ret; + } else { + if (errno != ENOSYS) { + return -errno; + } + if (qemu_pipe(fds) < 0) { + return -errno; + } + ret = fcntl_setfl(fds[0], O_NONBLOCK); + if (ret < 0) { + ret = -errno; + goto fail; + } + ret = fcntl_setfl(fds[1], O_NONBLOCK); + if (ret < 0) { + ret = -errno; + goto fail; + } + e->rfd = fds[0]; + e->wfd = fds[1]; + } + if (active) { + event_notifier_set(e); + } + return 0; + +fail: + close(fds[0]); + close(fds[1]); + return ret; } void event_notifier_cleanup(EventNotifier *e) { - close(e->fd); + if (e->rfd != e->wfd) { + close(e->rfd); + } + close(e->wfd); } int event_notifier_get_fd(EventNotifier *e) { - return e->fd; + return e->rfd; } int event_notifier_set_handler(EventNotifier *e, EventNotifierHandler *handler) { - return qemu_set_fd_handler(e->fd, (IOHandler *)handler, NULL, e); + return qemu_set_fd_handler(e->rfd, (IOHandler *)handler, NULL, e); } int event_notifier_set(EventNotifier *e) { - uint64_t value = 1; - int r = write(e->fd, &value, sizeof(value)); - return r == sizeof(value); + static const uint64_t value = 1; + ssize_t ret; + + do { + ret = write(e->wfd, &value, sizeof(value)); + } while (ret < 0 && errno == EINTR); + + /* EAGAIN is fine, a read must be pending. */ + if (ret < 0 && errno != EAGAIN) { + return -errno; + } + return 0; } int event_notifier_test_and_clear(EventNotifier *e) { - uint64_t value; - int r = read(e->fd, &value, sizeof(value)); - return r == sizeof(value); + int value; + ssize_t len; + char buffer[512]; + + /* Drain the notify pipe. For eventfd, only 8 bytes will be read. */ + value = 0; + do { + len = read(e->rfd, buffer, sizeof(buffer)); + value |= (len > 0); + } while ((len == -1 && errno == EINTR) || len == sizeof(buffer)); + + return value; } diff --git a/event_notifier.h b/event_notifier.h index b283a497ce..88b57af7ce 100644 --- a/event_notifier.h +++ b/event_notifier.h @@ -23,7 +23,8 @@ struct EventNotifier { #ifdef _WIN32 HANDLE event; #else - int fd; + int rfd; + int wfd; #endif }; From 1c53786fbdbdf20a3a6c556e09abb4d63ee7843e Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 30 Oct 2012 00:17:12 +0100 Subject: [PATCH 043/291] vl: init main loop earlier Otherwise, chardevs will not be able to create a bottom half as soon as that will require an AioContext. Signed-off-by: Paolo Bonzini --- vl.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/vl.c b/vl.c index b3186fa425..f84e969a03 100644 --- a/vl.c +++ b/vl.c @@ -3311,6 +3311,12 @@ int main(int argc, char **argv, char **envp) } loc_set_none(); + qemu_init_cpu_loop(); + if (qemu_init_main_loop()) { + fprintf(stderr, "qemu_init_main_loop failed\n"); + exit(1); + } + if (qemu_opts_foreach(qemu_find_opts("sandbox"), parse_sandbox, NULL, 0)) { exit(1); } @@ -3463,12 +3469,6 @@ int main(int argc, char **argv, char **envp) configure_accelerator(); - qemu_init_cpu_loop(); - if (qemu_init_main_loop()) { - fprintf(stderr, "qemu_init_main_loop failed\n"); - exit(1); - } - machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); if (machine_opts) { kernel_filename = qemu_opt_get(machine_opts, "kernel"); From b078dc3cfec2d6d037caef91204ebf0a78e7ac06 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 13 Sep 2012 13:43:38 +0200 Subject: [PATCH 044/291] aio: change qemu_aio_set_fd_handler to return void Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- aio.c | 12 +++++------- qemu-aio.h | 10 +++++----- 2 files changed, 10 insertions(+), 12 deletions(-) diff --git a/aio.c b/aio.c index c738a4e15d..e062aab2af 100644 --- a/aio.c +++ b/aio.c @@ -53,11 +53,11 @@ static AioHandler *find_aio_handler(int fd) return NULL; } -int qemu_aio_set_fd_handler(int fd, - IOHandler *io_read, - IOHandler *io_write, - AioFlushHandler *io_flush, - void *opaque) +void qemu_aio_set_fd_handler(int fd, + IOHandler *io_read, + IOHandler *io_write, + AioFlushHandler *io_flush, + void *opaque) { AioHandler *node; @@ -93,8 +93,6 @@ int qemu_aio_set_fd_handler(int fd, } qemu_set_fd_handler2(fd, NULL, io_read, io_write, opaque); - - return 0; } void qemu_aio_flush(void) diff --git a/qemu-aio.h b/qemu-aio.h index bfdd35f02c..27a7e21220 100644 --- a/qemu-aio.h +++ b/qemu-aio.h @@ -60,10 +60,10 @@ bool qemu_aio_wait(void); * Code that invokes AIO completion functions should rely on this function * instead of qemu_set_fd_handler[2]. */ -int qemu_aio_set_fd_handler(int fd, - IOHandler *io_read, - IOHandler *io_write, - AioFlushHandler *io_flush, - void *opaque); +void qemu_aio_set_fd_handler(int fd, + IOHandler *io_read, + IOHandler *io_write, + AioFlushHandler *io_flush, + void *opaque); #endif From 9958c351eee5b34051fd8061fe24f490ceca1334 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Sat, 9 Jun 2012 03:44:00 +0200 Subject: [PATCH 045/291] aio: provide platform-independent API This adds to aio.c a platform-independent API based on EventNotifiers, that can be used by both POSIX and Win32. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- Makefile.objs | 4 ++-- aio.c | 9 +++++++++ qemu-aio.h | 19 ++++++++++++++++++- 3 files changed, 29 insertions(+), 3 deletions(-) diff --git a/Makefile.objs b/Makefile.objs index 5b39c33560..98046fc64a 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -46,6 +46,8 @@ block-obj-y += nbd.o block.o blockjob.o aio.o aes.o qemu-config.o block-obj-y += qemu-progress.o qemu-sockets.o uri.o notify.o block-obj-y += $(coroutine-obj-y) $(qobject-obj-y) $(version-obj-y) block-obj-$(CONFIG_POSIX) += posix-aio-compat.o +block-obj-$(CONFIG_POSIX) += event_notifier-posix.o +block-obj-$(CONFIG_WIN32) += event_notifier-win32.o block-obj-$(CONFIG_LINUX_AIO) += linux-aio.o block-obj-y += block/ block-obj-y += $(qapi-obj-y) qapi-types.o qapi-visit.o @@ -94,8 +96,6 @@ common-obj-y += bt-host.o bt-vhci.o common-obj-y += dma-helpers.o common-obj-y += acl.o common-obj-$(CONFIG_POSIX) += compatfd.o -common-obj-$(CONFIG_POSIX) += event_notifier-posix.o -common-obj-$(CONFIG_WIN32) += event_notifier-win32.o common-obj-y += qemu-timer.o qemu-timer-common.o common-obj-y += qtest.o common-obj-y += vl.o diff --git a/aio.c b/aio.c index e062aab2af..44214e1ffc 100644 --- a/aio.c +++ b/aio.c @@ -95,6 +95,15 @@ void qemu_aio_set_fd_handler(int fd, qemu_set_fd_handler2(fd, NULL, io_read, io_write, opaque); } +void qemu_aio_set_event_notifier(EventNotifier *notifier, + EventNotifierHandler *io_read, + AioFlushEventNotifierHandler *io_flush) +{ + qemu_aio_set_fd_handler(event_notifier_get_fd(notifier), + (IOHandler *)io_read, NULL, + (AioFlushHandler *)io_flush, notifier); +} + void qemu_aio_flush(void) { while (qemu_aio_wait()); diff --git a/qemu-aio.h b/qemu-aio.h index 27a7e21220..dc416a5239 100644 --- a/qemu-aio.h +++ b/qemu-aio.h @@ -16,6 +16,7 @@ #include "qemu-common.h" #include "qemu-char.h" +#include "event_notifier.h" typedef struct BlockDriverAIOCB BlockDriverAIOCB; typedef void BlockDriverCompletionFunc(void *opaque, int ret); @@ -39,7 +40,7 @@ void *qemu_aio_get(AIOPool *pool, BlockDriverState *bs, void qemu_aio_release(void *p); /* Returns 1 if there are still outstanding AIO requests; 0 otherwise */ -typedef int (AioFlushHandler)(void *opaque); +typedef int (AioFlushEventNotifierHandler)(EventNotifier *e); /* Flush any pending AIO operation. This function will block until all * outstanding AIO operations have been completed or cancelled. */ @@ -53,6 +54,10 @@ void qemu_aio_flush(void); * Return whether there is still any pending AIO operation. */ bool qemu_aio_wait(void); +#ifdef CONFIG_POSIX +/* Returns 1 if there are still outstanding AIO requests; 0 otherwise */ +typedef int (AioFlushHandler)(void *opaque); + /* Register a file descriptor and associated callbacks. Behaves very similarly * to qemu_set_fd_handler2. Unlike qemu_set_fd_handler2, these callbacks will * be invoked when using either qemu_aio_wait() or qemu_aio_flush(). @@ -65,5 +70,17 @@ void qemu_aio_set_fd_handler(int fd, IOHandler *io_write, AioFlushHandler *io_flush, void *opaque); +#endif + +/* Register an event notifier and associated callbacks. Behaves very similarly + * to event_notifier_set_handler. Unlike event_notifier_set_handler, these callbacks + * will be invoked when using either qemu_aio_wait() or qemu_aio_flush(). + * + * Code that invokes AIO completion functions should rely on this function + * instead of event_notifier_set_handler. + */ +void qemu_aio_set_event_notifier(EventNotifier *notifier, + EventNotifierHandler *io_read, + AioFlushEventNotifierHandler *io_flush); #endif From f627aab1ccea119fd94ca9e9df120cea6aab0c67 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 29 Oct 2012 23:45:23 +0100 Subject: [PATCH 046/291] aio: introduce AioContext, move bottom halves there Start introducing AioContext, which will let us remove globals from aio.c/async.c, and introduce multiple I/O threads. The bottom half functions now take an additional AioContext argument. A bottom half is created with a specific AioContext that remains the same throughout the lifetime. qemu_bh_new is just a wrapper that uses a global context. Signed-off-by: Paolo Bonzini --- aio.c | 2 -- async.c | 30 ++++++++-------- hw/hw.h | 1 + iohandler.c | 1 + linux-aio.c | 1 + main-loop.c | 18 +++++++++- main-loop.h | 55 ++---------------------------- qemu-aio.h | 79 ++++++++++++++++++++++++++++++++++++++++++- qemu-char.h | 1 + qemu-common.h | 1 + qemu-coroutine-lock.c | 2 +- 11 files changed, 119 insertions(+), 72 deletions(-) diff --git a/aio.c b/aio.c index 44214e1ffc..7e3fe708d2 100644 --- a/aio.c +++ b/aio.c @@ -18,8 +18,6 @@ #include "qemu-queue.h" #include "qemu_socket.h" -typedef struct AioHandler AioHandler; - /* The list of registered AIO handlers */ static QLIST_HEAD(, AioHandler) aio_handlers; diff --git a/async.c b/async.c index 85cc6410c5..189ee1beb5 100644 --- a/async.c +++ b/async.c @@ -26,9 +26,6 @@ #include "qemu-aio.h" #include "main-loop.h" -/* Anchor of the list of Bottom Halves belonging to the context */ -static struct QEMUBH *first_bh; - /***********************************************************/ /* bottom halves (can be seen as timers which expire ASAP) */ @@ -41,27 +38,26 @@ struct QEMUBH { bool deleted; }; -QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque) +QEMUBH *aio_bh_new(AioContext *ctx, QEMUBHFunc *cb, void *opaque) { QEMUBH *bh; bh = g_malloc0(sizeof(QEMUBH)); bh->cb = cb; bh->opaque = opaque; - bh->next = first_bh; - first_bh = bh; + bh->next = ctx->first_bh; + ctx->first_bh = bh; return bh; } -int qemu_bh_poll(void) +int aio_bh_poll(AioContext *ctx) { QEMUBH *bh, **bhp, *next; int ret; - static int nesting = 0; - nesting++; + ctx->walking_bh++; ret = 0; - for (bh = first_bh; bh; bh = next) { + for (bh = ctx->first_bh; bh; bh = next) { next = bh->next; if (!bh->deleted && bh->scheduled) { bh->scheduled = 0; @@ -72,11 +68,11 @@ int qemu_bh_poll(void) } } - nesting--; + ctx->walking_bh--; /* remove deleted bhs */ - if (!nesting) { - bhp = &first_bh; + if (!ctx->walking_bh) { + bhp = &ctx->first_bh; while (*bhp) { bh = *bhp; if (bh->deleted) { @@ -120,11 +116,11 @@ void qemu_bh_delete(QEMUBH *bh) bh->deleted = 1; } -void qemu_bh_update_timeout(uint32_t *timeout) +void aio_bh_update_timeout(AioContext *ctx, uint32_t *timeout) { QEMUBH *bh; - for (bh = first_bh; bh; bh = bh->next) { + for (bh = ctx->first_bh; bh; bh = bh->next) { if (!bh->deleted && bh->scheduled) { if (bh->idle) { /* idle bottom halves will be polled at least @@ -140,3 +136,7 @@ void qemu_bh_update_timeout(uint32_t *timeout) } } +AioContext *aio_context_new(void) +{ + return g_new0(AioContext, 1); +} diff --git a/hw/hw.h b/hw/hw.h index b337ee3042..f530f6f41a 100644 --- a/hw/hw.h +++ b/hw/hw.h @@ -10,6 +10,7 @@ #include "ioport.h" #include "irq.h" +#include "qemu-aio.h" #include "qemu-file.h" #include "vmstate.h" #include "qemu-log.h" diff --git a/iohandler.c b/iohandler.c index a2d871bb91..60460a6f88 100644 --- a/iohandler.c +++ b/iohandler.c @@ -26,6 +26,7 @@ #include "qemu-common.h" #include "qemu-char.h" #include "qemu-queue.h" +#include "qemu-aio.h" #include "main-loop.h" #ifndef _WIN32 diff --git a/linux-aio.c b/linux-aio.c index ce9b5d4be8..f3d8ef33ca 100644 --- a/linux-aio.c +++ b/linux-aio.c @@ -9,6 +9,7 @@ */ #include "qemu-common.h" #include "qemu-aio.h" +#include "qemu-queue.h" #include "block/raw-posix-aio.h" #include diff --git a/main-loop.c b/main-loop.c index baefe413d1..40fdbd3770 100644 --- a/main-loop.c +++ b/main-loop.c @@ -26,6 +26,7 @@ #include "qemu-timer.h" #include "slirp/slirp.h" #include "main-loop.h" +#include "qemu-aio.h" #ifndef _WIN32 @@ -199,6 +200,8 @@ static int qemu_signal_init(void) } #endif +static AioContext *qemu_aio_context; + int qemu_init_main_loop(void) { int ret; @@ -218,6 +221,7 @@ int qemu_init_main_loop(void) return ret; } + qemu_aio_context = aio_context_new(); return 0; } @@ -481,7 +485,7 @@ int main_loop_wait(int nonblocking) if (nonblocking) { timeout = 0; } else { - qemu_bh_update_timeout(&timeout); + aio_bh_update_timeout(qemu_aio_context, &timeout); } /* poll any events */ @@ -510,3 +514,15 @@ int main_loop_wait(int nonblocking) return ret; } + +/* Functions to operate on the main QEMU AioContext. */ + +QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque) +{ + return aio_bh_new(qemu_aio_context, cb, opaque); +} + +int qemu_bh_poll(void) +{ + return aio_bh_poll(qemu_aio_context); +} diff --git a/main-loop.h b/main-loop.h index 91a0aff9c7..1d1a56b858 100644 --- a/main-loop.h +++ b/main-loop.h @@ -25,6 +25,8 @@ #ifndef QEMU_MAIN_LOOP_H #define QEMU_MAIN_LOOP_H 1 +#include "qemu-aio.h" + #define SIG_IPI SIGUSR1 /** @@ -163,7 +165,6 @@ void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size); typedef int IOCanReadHandler(void *opaque); -typedef void IOHandler(void *opaque); /** * qemu_set_fd_handler2: Register a file descriptor with the main loop @@ -244,56 +245,6 @@ int qemu_set_fd_handler(int fd, IOHandler *fd_write, void *opaque); -typedef struct QEMUBH QEMUBH; -typedef void QEMUBHFunc(void *opaque); - -/** - * qemu_bh_new: Allocate a new bottom half structure. - * - * Bottom halves are lightweight callbacks whose invocation is guaranteed - * to be wait-free, thread-safe and signal-safe. The #QEMUBH structure - * is opaque and must be allocated prior to its use. - */ -QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque); - -/** - * qemu_bh_schedule: Schedule a bottom half. - * - * Scheduling a bottom half interrupts the main loop and causes the - * execution of the callback that was passed to qemu_bh_new. - * - * Bottom halves that are scheduled from a bottom half handler are instantly - * invoked. This can create an infinite loop if a bottom half handler - * schedules itself. - * - * @bh: The bottom half to be scheduled. - */ -void qemu_bh_schedule(QEMUBH *bh); - -/** - * qemu_bh_cancel: Cancel execution of a bottom half. - * - * Canceling execution of a bottom half undoes the effect of calls to - * qemu_bh_schedule without freeing its resources yet. While cancellation - * itself is also wait-free and thread-safe, it can of course race with the - * loop that executes bottom halves unless you are holding the iothread - * mutex. This makes it mostly useless if you are not holding the mutex. - * - * @bh: The bottom half to be canceled. - */ -void qemu_bh_cancel(QEMUBH *bh); - -/** - *qemu_bh_delete: Cancel execution of a bottom half and free its resources. - * - * Deleting a bottom half frees the memory that was allocated for it by - * qemu_bh_new. It also implies canceling the bottom half if it was - * scheduled. - * - * @bh: The bottom half to be deleted. - */ -void qemu_bh_delete(QEMUBH *bh); - #ifdef CONFIG_POSIX /** * qemu_add_child_watch: Register a child process for reaping. @@ -349,8 +300,8 @@ void qemu_fd_register(int fd); void qemu_iohandler_fill(int *pnfds, fd_set *readfds, fd_set *writefds, fd_set *xfds); void qemu_iohandler_poll(fd_set *readfds, fd_set *writefds, fd_set *xfds, int rc); +QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque); void qemu_bh_schedule_idle(QEMUBH *bh); int qemu_bh_poll(void); -void qemu_bh_update_timeout(uint32_t *timeout); #endif diff --git a/qemu-aio.h b/qemu-aio.h index dc416a5239..2ed6ad3723 100644 --- a/qemu-aio.h +++ b/qemu-aio.h @@ -15,7 +15,6 @@ #define QEMU_AIO_H #include "qemu-common.h" -#include "qemu-char.h" #include "event_notifier.h" typedef struct BlockDriverAIOCB BlockDriverAIOCB; @@ -39,9 +38,87 @@ void *qemu_aio_get(AIOPool *pool, BlockDriverState *bs, BlockDriverCompletionFunc *cb, void *opaque); void qemu_aio_release(void *p); +typedef struct AioHandler AioHandler; +typedef void QEMUBHFunc(void *opaque); +typedef void IOHandler(void *opaque); + +typedef struct AioContext { + /* Anchor of the list of Bottom Halves belonging to the context */ + struct QEMUBH *first_bh; + + /* A simple lock used to protect the first_bh list, and ensure that + * no callbacks are removed while we're walking and dispatching callbacks. + */ + int walking_bh; +} AioContext; + /* Returns 1 if there are still outstanding AIO requests; 0 otherwise */ typedef int (AioFlushEventNotifierHandler)(EventNotifier *e); +/** + * aio_context_new: Allocate a new AioContext. + * + * AioContext provide a mini event-loop that can be waited on synchronously. + * They also provide bottom halves, a service to execute a piece of code + * as soon as possible. + */ +AioContext *aio_context_new(void); + +/** + * aio_bh_new: Allocate a new bottom half structure. + * + * Bottom halves are lightweight callbacks whose invocation is guaranteed + * to be wait-free, thread-safe and signal-safe. The #QEMUBH structure + * is opaque and must be allocated prior to its use. + */ +QEMUBH *aio_bh_new(AioContext *ctx, QEMUBHFunc *cb, void *opaque); + +/** + * aio_bh_poll: Poll bottom halves for an AioContext. + * + * These are internal functions used by the QEMU main loop. + */ +int aio_bh_poll(AioContext *ctx); +void aio_bh_update_timeout(AioContext *ctx, uint32_t *timeout); + +/** + * qemu_bh_schedule: Schedule a bottom half. + * + * Scheduling a bottom half interrupts the main loop and causes the + * execution of the callback that was passed to qemu_bh_new. + * + * Bottom halves that are scheduled from a bottom half handler are instantly + * invoked. This can create an infinite loop if a bottom half handler + * schedules itself. + * + * @bh: The bottom half to be scheduled. + */ +void qemu_bh_schedule(QEMUBH *bh); + +/** + * qemu_bh_cancel: Cancel execution of a bottom half. + * + * Canceling execution of a bottom half undoes the effect of calls to + * qemu_bh_schedule without freeing its resources yet. While cancellation + * itself is also wait-free and thread-safe, it can of course race with the + * loop that executes bottom halves unless you are holding the iothread + * mutex. This makes it mostly useless if you are not holding the mutex. + * + * @bh: The bottom half to be canceled. + */ +void qemu_bh_cancel(QEMUBH *bh); + +/** + *qemu_bh_delete: Cancel execution of a bottom half and free its resources. + * + * Deleting a bottom half frees the memory that was allocated for it by + * qemu_bh_new. It also implies canceling the bottom half if it was + * scheduled. + * + * @bh: The bottom half to be deleted. + */ +void qemu_bh_delete(QEMUBH *bh); + /* Flush any pending AIO operation. This function will block until all * outstanding AIO operations have been completed or cancelled. */ void qemu_aio_flush(void); diff --git a/qemu-char.h b/qemu-char.h index 486644b3bd..5087168bd7 100644 --- a/qemu-char.h +++ b/qemu-char.h @@ -5,6 +5,7 @@ #include "qemu-queue.h" #include "qemu-option.h" #include "qemu-config.h" +#include "qemu-aio.h" #include "qobject.h" #include "qstring.h" #include "main-loop.h" diff --git a/qemu-common.h b/qemu-common.h index 36ce522066..24e13ccb5e 100644 --- a/qemu-common.h +++ b/qemu-common.h @@ -14,6 +14,7 @@ typedef struct QEMUTimer QEMUTimer; typedef struct QEMUFile QEMUFile; +typedef struct QEMUBH QEMUBH; typedef struct DeviceState DeviceState; struct Monitor; diff --git a/qemu-coroutine-lock.c b/qemu-coroutine-lock.c index 26ad76bf50..9dda3f86c9 100644 --- a/qemu-coroutine-lock.c +++ b/qemu-coroutine-lock.c @@ -26,7 +26,7 @@ #include "qemu-coroutine.h" #include "qemu-coroutine-int.h" #include "qemu-queue.h" -#include "main-loop.h" +#include "qemu-aio.h" #include "trace.h" static QTAILQ_HEAD(, Coroutine) unlock_bh_queue = From a915f4bc977c4f3aab08a78023c1303664d1c606 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 13 Sep 2012 12:28:51 +0200 Subject: [PATCH 047/291] aio: add I/O handlers to the AioContext interface With this patch, I/O handlers (including event notifier handlers) can be attached to a single AioContext. Signed-off-by: Paolo Bonzini --- aio.c | 68 +++++++++++++++++++++-------------------------------- async.c | 6 +++++ main-loop.c | 33 ++++++++++++++++++++++++++ qemu-aio.h | 42 +++++++++++++++++++++++++++------ 4 files changed, 101 insertions(+), 48 deletions(-) diff --git a/aio.c b/aio.c index 7e3fe708d2..c89f1e95c1 100644 --- a/aio.c +++ b/aio.c @@ -18,15 +18,6 @@ #include "qemu-queue.h" #include "qemu_socket.h" -/* The list of registered AIO handlers */ -static QLIST_HEAD(, AioHandler) aio_handlers; - -/* This is a simple lock used to protect the aio_handlers list. Specifically, - * it's used to ensure that no callbacks are removed while we're walking and - * dispatching callbacks. - */ -static int walking_handlers; - struct AioHandler { int fd; @@ -38,11 +29,11 @@ struct AioHandler QLIST_ENTRY(AioHandler) node; }; -static AioHandler *find_aio_handler(int fd) +static AioHandler *find_aio_handler(AioContext *ctx, int fd) { AioHandler *node; - QLIST_FOREACH(node, &aio_handlers, node) { + QLIST_FOREACH(node, &ctx->aio_handlers, node) { if (node->fd == fd) if (!node->deleted) return node; @@ -51,21 +42,22 @@ static AioHandler *find_aio_handler(int fd) return NULL; } -void qemu_aio_set_fd_handler(int fd, - IOHandler *io_read, - IOHandler *io_write, - AioFlushHandler *io_flush, - void *opaque) +void aio_set_fd_handler(AioContext *ctx, + int fd, + IOHandler *io_read, + IOHandler *io_write, + AioFlushHandler *io_flush, + void *opaque) { AioHandler *node; - node = find_aio_handler(fd); + node = find_aio_handler(ctx, fd); /* Are we deleting the fd handler? */ if (!io_read && !io_write) { if (node) { /* If the lock is held, just mark the node as deleted */ - if (walking_handlers) + if (ctx->walking_handlers) node->deleted = 1; else { /* Otherwise, delete it for real. We can't just mark it as @@ -81,7 +73,7 @@ void qemu_aio_set_fd_handler(int fd, /* Alloc and insert if it's not already there */ node = g_malloc0(sizeof(AioHandler)); node->fd = fd; - QLIST_INSERT_HEAD(&aio_handlers, node, node); + QLIST_INSERT_HEAD(&ctx->aio_handlers, node, node); } /* Update handler with latest information */ node->io_read = io_read; @@ -89,25 +81,19 @@ void qemu_aio_set_fd_handler(int fd, node->io_flush = io_flush; node->opaque = opaque; } - - qemu_set_fd_handler2(fd, NULL, io_read, io_write, opaque); } -void qemu_aio_set_event_notifier(EventNotifier *notifier, - EventNotifierHandler *io_read, - AioFlushEventNotifierHandler *io_flush) +void aio_set_event_notifier(AioContext *ctx, + EventNotifier *notifier, + EventNotifierHandler *io_read, + AioFlushEventNotifierHandler *io_flush) { - qemu_aio_set_fd_handler(event_notifier_get_fd(notifier), - (IOHandler *)io_read, NULL, - (AioFlushHandler *)io_flush, notifier); + aio_set_fd_handler(ctx, event_notifier_get_fd(notifier), + (IOHandler *)io_read, NULL, + (AioFlushHandler *)io_flush, notifier); } -void qemu_aio_flush(void) -{ - while (qemu_aio_wait()); -} - -bool qemu_aio_wait(void) +bool aio_wait(AioContext *ctx) { AioHandler *node; fd_set rdfds, wrfds; @@ -120,18 +106,18 @@ bool qemu_aio_wait(void) * Do not call select in this case, because it is possible that the caller * does not need a complete flush (as is the case for qemu_aio_wait loops). */ - if (qemu_bh_poll()) { + if (aio_bh_poll(ctx)) { return true; } - walking_handlers++; + ctx->walking_handlers++; FD_ZERO(&rdfds); FD_ZERO(&wrfds); /* fill fd sets */ busy = false; - QLIST_FOREACH(node, &aio_handlers, node) { + QLIST_FOREACH(node, &ctx->aio_handlers, node) { /* If there aren't pending AIO operations, don't invoke callbacks. * Otherwise, if there are no AIO requests, qemu_aio_wait() would * wait indefinitely. @@ -152,7 +138,7 @@ bool qemu_aio_wait(void) } } - walking_handlers--; + ctx->walking_handlers--; /* No AIO operations? Get us out of here */ if (!busy) { @@ -166,11 +152,11 @@ bool qemu_aio_wait(void) if (ret > 0) { /* we have to walk very carefully in case * qemu_aio_set_fd_handler is called while we're walking */ - node = QLIST_FIRST(&aio_handlers); + node = QLIST_FIRST(&ctx->aio_handlers); while (node) { AioHandler *tmp; - walking_handlers++; + ctx->walking_handlers++; if (!node->deleted && FD_ISSET(node->fd, &rdfds) && @@ -186,9 +172,9 @@ bool qemu_aio_wait(void) tmp = node; node = QLIST_NEXT(node, node); - walking_handlers--; + ctx->walking_handlers--; - if (!walking_handlers && tmp->deleted) { + if (!ctx->walking_handlers && tmp->deleted) { QLIST_REMOVE(tmp, node); g_free(tmp); } diff --git a/async.c b/async.c index 189ee1beb5..c99db79ac7 100644 --- a/async.c +++ b/async.c @@ -136,7 +136,13 @@ void aio_bh_update_timeout(AioContext *ctx, uint32_t *timeout) } } + AioContext *aio_context_new(void) { return g_new0(AioContext, 1); } + +void aio_flush(AioContext *ctx) +{ + while (aio_wait(ctx)); +} diff --git a/main-loop.c b/main-loop.c index 40fdbd3770..8f0117e7aa 100644 --- a/main-loop.c +++ b/main-loop.c @@ -526,3 +526,36 @@ int qemu_bh_poll(void) { return aio_bh_poll(qemu_aio_context); } + +void qemu_aio_flush(void) +{ + aio_flush(qemu_aio_context); +} + +bool qemu_aio_wait(void) +{ + return aio_wait(qemu_aio_context); +} + +void qemu_aio_set_fd_handler(int fd, + IOHandler *io_read, + IOHandler *io_write, + AioFlushHandler *io_flush, + void *opaque) +{ + aio_set_fd_handler(qemu_aio_context, fd, io_read, io_write, io_flush, + opaque); + + qemu_set_fd_handler2(fd, NULL, io_read, io_write, opaque); +} + +#ifdef CONFIG_POSIX +void qemu_aio_set_event_notifier(EventNotifier *notifier, + EventNotifierHandler *io_read, + AioFlushEventNotifierHandler *io_flush) +{ + qemu_aio_set_fd_handler(event_notifier_get_fd(notifier), + (IOHandler *)io_read, NULL, + (AioFlushHandler *)io_flush, notifier); +} +#endif diff --git a/qemu-aio.h b/qemu-aio.h index 2ed6ad3723..f8a93d8fb9 100644 --- a/qemu-aio.h +++ b/qemu-aio.h @@ -15,6 +15,7 @@ #define QEMU_AIO_H #include "qemu-common.h" +#include "qemu-queue.h" #include "event_notifier.h" typedef struct BlockDriverAIOCB BlockDriverAIOCB; @@ -43,6 +44,15 @@ typedef void QEMUBHFunc(void *opaque); typedef void IOHandler(void *opaque); typedef struct AioContext { + /* The list of registered AIO handlers */ + QLIST_HEAD(, AioHandler) aio_handlers; + + /* This is a simple lock used to protect the aio_handlers list. + * Specifically, it's used to ensure that no callbacks are removed while + * we're walking and dispatching callbacks. + */ + int walking_handlers; + /* Anchor of the list of Bottom Halves belonging to the context */ struct QEMUBH *first_bh; @@ -121,7 +131,7 @@ void qemu_bh_delete(QEMUBH *bh); /* Flush any pending AIO operation. This function will block until all * outstanding AIO operations have been completed or cancelled. */ -void qemu_aio_flush(void); +void aio_flush(AioContext *ctx); /* Wait for a single AIO completion to occur. This function will wait * until a single AIO event has completed and it will ensure something @@ -129,7 +139,7 @@ void qemu_aio_flush(void); * result of executing I/O completion or bh callbacks. * * Return whether there is still any pending AIO operation. */ -bool qemu_aio_wait(void); +bool aio_wait(AioContext *ctx); #ifdef CONFIG_POSIX /* Returns 1 if there are still outstanding AIO requests; 0 otherwise */ @@ -142,11 +152,12 @@ typedef int (AioFlushHandler)(void *opaque); * Code that invokes AIO completion functions should rely on this function * instead of qemu_set_fd_handler[2]. */ -void qemu_aio_set_fd_handler(int fd, - IOHandler *io_read, - IOHandler *io_write, - AioFlushHandler *io_flush, - void *opaque); +void aio_set_fd_handler(AioContext *ctx, + int fd, + IOHandler *io_read, + IOHandler *io_write, + AioFlushHandler *io_flush, + void *opaque); #endif /* Register an event notifier and associated callbacks. Behaves very similarly @@ -156,8 +167,25 @@ void qemu_aio_set_fd_handler(int fd, * Code that invokes AIO completion functions should rely on this function * instead of event_notifier_set_handler. */ +void aio_set_event_notifier(AioContext *ctx, + EventNotifier *notifier, + EventNotifierHandler *io_read, + AioFlushEventNotifierHandler *io_flush); + +/* Functions to operate on the main QEMU AioContext. */ + +void qemu_aio_flush(void); +bool qemu_aio_wait(void); void qemu_aio_set_event_notifier(EventNotifier *notifier, EventNotifierHandler *io_read, AioFlushEventNotifierHandler *io_flush); +#ifdef CONFIG_POSIX +void qemu_aio_set_fd_handler(int fd, + IOHandler *io_read, + IOHandler *io_write, + AioFlushHandler *io_flush, + void *opaque); +#endif + #endif From 4231c88d27d9e46e6ad6e6b7bbb6e442bcf9cd05 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 26 Sep 2012 15:21:36 +0200 Subject: [PATCH 048/291] aio: test node->deleted before calling io_flush Otherwise, there could be a case where io_flush accesses freed memory because it should not have been called. Signed-off-by: Paolo Bonzini --- aio.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/aio.c b/aio.c index c89f1e95c1..734d2cfa0b 100644 --- a/aio.c +++ b/aio.c @@ -122,7 +122,7 @@ bool aio_wait(AioContext *ctx) * Otherwise, if there are no AIO requests, qemu_aio_wait() would * wait indefinitely. */ - if (node->io_flush) { + if (!node->deleted && node->io_flush) { if (node->io_flush(node->opaque) == 0) { continue; } From 7c0628b20e7c56b7e04abb8b5f8d7da3f7cb87e8 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 24 Sep 2012 14:37:53 +0200 Subject: [PATCH 049/291] aio: add non-blocking variant of aio_wait This will be used when polling the GSource attached to an AioContext. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- aio.c | 20 +++++++++++++++----- async.c | 2 +- main-loop.c | 2 +- qemu-aio.h | 21 +++++++++++++++------ 4 files changed, 32 insertions(+), 13 deletions(-) diff --git a/aio.c b/aio.c index 734d2cfa0b..1d5e0c62ce 100644 --- a/aio.c +++ b/aio.c @@ -93,13 +93,16 @@ void aio_set_event_notifier(AioContext *ctx, (AioFlushHandler *)io_flush, notifier); } -bool aio_wait(AioContext *ctx) +bool aio_poll(AioContext *ctx, bool blocking) { + static struct timeval tv0; AioHandler *node; fd_set rdfds, wrfds; int max_fd = -1; int ret; - bool busy; + bool busy, progress; + + progress = false; /* * If there are callbacks left that have been queued, we need to call then. @@ -107,6 +110,11 @@ bool aio_wait(AioContext *ctx) * does not need a complete flush (as is the case for qemu_aio_wait loops). */ if (aio_bh_poll(ctx)) { + blocking = false; + progress = true; + } + + if (progress && !blocking) { return true; } @@ -142,11 +150,11 @@ bool aio_wait(AioContext *ctx) /* No AIO operations? Get us out of here */ if (!busy) { - return false; + return progress; } /* wait until next event */ - ret = select(max_fd, &rdfds, &wrfds, NULL, NULL); + ret = select(max_fd, &rdfds, &wrfds, NULL, blocking ? NULL : &tv0); /* if we have any readable fds, dispatch event */ if (ret > 0) { @@ -161,11 +169,13 @@ bool aio_wait(AioContext *ctx) if (!node->deleted && FD_ISSET(node->fd, &rdfds) && node->io_read) { + progress = true; node->io_read(node->opaque); } if (!node->deleted && FD_ISSET(node->fd, &wrfds) && node->io_write) { + progress = true; node->io_write(node->opaque); } @@ -181,5 +191,5 @@ bool aio_wait(AioContext *ctx) } } - return true; + return progress; } diff --git a/async.c b/async.c index c99db79ac7..513bdd7aa2 100644 --- a/async.c +++ b/async.c @@ -144,5 +144,5 @@ AioContext *aio_context_new(void) void aio_flush(AioContext *ctx) { - while (aio_wait(ctx)); + while (aio_poll(ctx, true)); } diff --git a/main-loop.c b/main-loop.c index 8f0117e7aa..1fdc3bdf2e 100644 --- a/main-loop.c +++ b/main-loop.c @@ -534,7 +534,7 @@ void qemu_aio_flush(void) bool qemu_aio_wait(void) { - return aio_wait(qemu_aio_context); + return aio_poll(qemu_aio_context, true); } void qemu_aio_set_fd_handler(int fd, diff --git a/qemu-aio.h b/qemu-aio.h index f8a93d8fb9..f19201e7ca 100644 --- a/qemu-aio.h +++ b/qemu-aio.h @@ -133,13 +133,22 @@ void qemu_bh_delete(QEMUBH *bh); * outstanding AIO operations have been completed or cancelled. */ void aio_flush(AioContext *ctx); -/* Wait for a single AIO completion to occur. This function will wait - * until a single AIO event has completed and it will ensure something - * has moved before returning. This can issue new pending aio as - * result of executing I/O completion or bh callbacks. +/* Progress in completing AIO work to occur. This can issue new pending + * aio as a result of executing I/O completion or bh callbacks. * - * Return whether there is still any pending AIO operation. */ -bool aio_wait(AioContext *ctx); + * If there is no pending AIO operation or completion (bottom half), + * return false. If there are pending bottom halves, return true. + * + * If there are no pending bottom halves, but there are pending AIO + * operations, it may not be possible to make any progress without + * blocking. If @blocking is true, this function will wait until one + * or more AIO events have completed, to ensure something has moved + * before returning. + * + * If @blocking is false, this function will also return false if the + * function cannot make any progress without blocking. + */ +bool aio_poll(AioContext *ctx, bool blocking); #ifdef CONFIG_POSIX /* Returns 1 if there are still outstanding AIO requests; 0 otherwise */ From cd9ba1ebcf0439457f22b75b38533f6634f23c5f Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 24 Sep 2012 14:57:22 +0200 Subject: [PATCH 050/291] aio: prepare for introducing GSource-based dispatch This adds a GPollFD to each AioHandler. It will then be possible to attach these GPollFDs to a GSource, and from there to the main loop. aio_wait examines the GPollFDs and avoids calling select() if any is set (similar to what it does if bottom halves are available). Signed-off-by: Paolo Bonzini --- aio.c | 93 ++++++++++++++++++++++++++++++++++++++++++++++-------- qemu-aio.h | 7 ++++ 2 files changed, 87 insertions(+), 13 deletions(-) diff --git a/aio.c b/aio.c index 1d5e0c62ce..44247224e2 100644 --- a/aio.c +++ b/aio.c @@ -20,7 +20,7 @@ struct AioHandler { - int fd; + GPollFD pfd; IOHandler *io_read; IOHandler *io_write; AioFlushHandler *io_flush; @@ -34,7 +34,7 @@ static AioHandler *find_aio_handler(AioContext *ctx, int fd) AioHandler *node; QLIST_FOREACH(node, &ctx->aio_handlers, node) { - if (node->fd == fd) + if (node->pfd.fd == fd) if (!node->deleted) return node; } @@ -57,9 +57,10 @@ void aio_set_fd_handler(AioContext *ctx, if (!io_read && !io_write) { if (node) { /* If the lock is held, just mark the node as deleted */ - if (ctx->walking_handlers) + if (ctx->walking_handlers) { node->deleted = 1; - else { + node->pfd.revents = 0; + } else { /* Otherwise, delete it for real. We can't just mark it as * deleted because deleted nodes are only cleaned up after * releasing the walking_handlers lock. @@ -72,7 +73,7 @@ void aio_set_fd_handler(AioContext *ctx, if (node == NULL) { /* Alloc and insert if it's not already there */ node = g_malloc0(sizeof(AioHandler)); - node->fd = fd; + node->pfd.fd = fd; QLIST_INSERT_HEAD(&ctx->aio_handlers, node, node); } /* Update handler with latest information */ @@ -80,6 +81,9 @@ void aio_set_fd_handler(AioContext *ctx, node->io_write = io_write; node->io_flush = io_flush; node->opaque = opaque; + + node->pfd.events = (io_read ? G_IO_IN | G_IO_HUP : 0); + node->pfd.events |= (io_write ? G_IO_OUT : 0); } } @@ -93,6 +97,32 @@ void aio_set_event_notifier(AioContext *ctx, (AioFlushHandler *)io_flush, notifier); } +bool aio_pending(AioContext *ctx) +{ + AioHandler *node; + + QLIST_FOREACH(node, &ctx->aio_handlers, node) { + int revents; + + /* + * FIXME: right now we cannot get G_IO_HUP and G_IO_ERR because + * main-loop.c is still select based (due to the slirp legacy). + * If main-loop.c ever switches to poll, G_IO_ERR should be + * tested too. Dispatching G_IO_ERR to both handlers should be + * okay, since handlers need to be ready for spurious wakeups. + */ + revents = node->pfd.revents & node->pfd.events; + if (revents & (G_IO_IN | G_IO_HUP | G_IO_ERR) && node->io_read) { + return true; + } + if (revents & (G_IO_OUT | G_IO_ERR) && node->io_write) { + return true; + } + } + + return false; +} + bool aio_poll(AioContext *ctx, bool blocking) { static struct timeval tv0; @@ -114,6 +144,43 @@ bool aio_poll(AioContext *ctx, bool blocking) progress = true; } + /* + * Then dispatch any pending callbacks from the GSource. + * + * We have to walk very carefully in case qemu_aio_set_fd_handler is + * called while we're walking. + */ + node = QLIST_FIRST(&ctx->aio_handlers); + while (node) { + AioHandler *tmp; + int revents; + + ctx->walking_handlers++; + + revents = node->pfd.revents & node->pfd.events; + node->pfd.revents = 0; + + /* See comment in aio_pending. */ + if (revents & (G_IO_IN | G_IO_HUP | G_IO_ERR) && node->io_read) { + node->io_read(node->opaque); + progress = true; + } + if (revents & (G_IO_OUT | G_IO_ERR) && node->io_write) { + node->io_write(node->opaque); + progress = true; + } + + tmp = node; + node = QLIST_NEXT(node, node); + + ctx->walking_handlers--; + + if (!ctx->walking_handlers && tmp->deleted) { + QLIST_REMOVE(tmp, node); + g_free(tmp); + } + } + if (progress && !blocking) { return true; } @@ -137,12 +204,12 @@ bool aio_poll(AioContext *ctx, bool blocking) busy = true; } if (!node->deleted && node->io_read) { - FD_SET(node->fd, &rdfds); - max_fd = MAX(max_fd, node->fd + 1); + FD_SET(node->pfd.fd, &rdfds); + max_fd = MAX(max_fd, node->pfd.fd + 1); } if (!node->deleted && node->io_write) { - FD_SET(node->fd, &wrfds); - max_fd = MAX(max_fd, node->fd + 1); + FD_SET(node->pfd.fd, &wrfds); + max_fd = MAX(max_fd, node->pfd.fd + 1); } } @@ -167,16 +234,16 @@ bool aio_poll(AioContext *ctx, bool blocking) ctx->walking_handlers++; if (!node->deleted && - FD_ISSET(node->fd, &rdfds) && + FD_ISSET(node->pfd.fd, &rdfds) && node->io_read) { - progress = true; node->io_read(node->opaque); + progress = true; } if (!node->deleted && - FD_ISSET(node->fd, &wrfds) && + FD_ISSET(node->pfd.fd, &wrfds) && node->io_write) { - progress = true; node->io_write(node->opaque); + progress = true; } tmp = node; diff --git a/qemu-aio.h b/qemu-aio.h index f19201e7ca..ac248962fe 100644 --- a/qemu-aio.h +++ b/qemu-aio.h @@ -133,6 +133,13 @@ void qemu_bh_delete(QEMUBH *bh); * outstanding AIO operations have been completed or cancelled. */ void aio_flush(AioContext *ctx); +/* Return whether there are any pending callbacks from the GSource + * attached to the AioContext. + * + * This is used internally in the implementation of the GSource. + */ +bool aio_pending(AioContext *ctx); + /* Progress in completing AIO work to occur. This can issue new pending * aio as a result of executing I/O completion or bh callbacks. * From f42b22077bc63a482d7a8755b54e33475ab78541 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Sat, 9 Jun 2012 04:01:51 +0200 Subject: [PATCH 051/291] aio: add Win32 implementation The Win32 implementation will only accept EventNotifiers, thus a few drivers are disabled under Windows. EventNotifiers are a good match for the GSource implementation, too, because the Win32 port of glib allows to place their HANDLEs in a GPollFD. Signed-off-by: Paolo Bonzini --- Makefile.objs | 6 +- aio.c => aio-posix.c | 0 aio-win32.c | 209 +++++++++++++++++++++++++++++++++++++++++++ block/Makefile.objs | 6 +- main-loop.c | 2 +- 5 files changed, 218 insertions(+), 5 deletions(-) rename aio.c => aio-posix.c (100%) create mode 100644 aio-win32.c diff --git a/Makefile.objs b/Makefile.objs index 98046fc64a..a8ade04c02 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -42,12 +42,12 @@ coroutine-obj-$(CONFIG_WIN32) += coroutine-win32.o # block-obj-y is code used by both qemu system emulation and qemu-img block-obj-y = iov.o cache-utils.o qemu-option.o module.o async.o -block-obj-y += nbd.o block.o blockjob.o aio.o aes.o qemu-config.o +block-obj-y += nbd.o block.o blockjob.o aes.o qemu-config.o block-obj-y += qemu-progress.o qemu-sockets.o uri.o notify.o block-obj-y += $(coroutine-obj-y) $(qobject-obj-y) $(version-obj-y) block-obj-$(CONFIG_POSIX) += posix-aio-compat.o -block-obj-$(CONFIG_POSIX) += event_notifier-posix.o -block-obj-$(CONFIG_WIN32) += event_notifier-win32.o +block-obj-$(CONFIG_POSIX) += event_notifier-posix.o aio-posix.o +block-obj-$(CONFIG_WIN32) += event_notifier-win32.o aio-win32.o block-obj-$(CONFIG_LINUX_AIO) += linux-aio.o block-obj-y += block/ block-obj-y += $(qapi-obj-y) qapi-types.o qapi-visit.o diff --git a/aio.c b/aio-posix.c similarity index 100% rename from aio.c rename to aio-posix.c diff --git a/aio-win32.c b/aio-win32.c new file mode 100644 index 0000000000..9881fdbca7 --- /dev/null +++ b/aio-win32.c @@ -0,0 +1,209 @@ +/* + * QEMU aio implementation + * + * Copyright IBM Corp., 2008 + * Copyright Red Hat Inc., 2012 + * + * Authors: + * Anthony Liguori + * Paolo Bonzini + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#include "qemu-common.h" +#include "block.h" +#include "qemu-queue.h" +#include "qemu_socket.h" + +struct AioHandler { + EventNotifier *e; + EventNotifierHandler *io_notify; + AioFlushEventNotifierHandler *io_flush; + GPollFD pfd; + int deleted; + QLIST_ENTRY(AioHandler) node; +}; + +void aio_set_event_notifier(AioContext *ctx, + EventNotifier *e, + EventNotifierHandler *io_notify, + AioFlushEventNotifierHandler *io_flush) +{ + AioHandler *node; + + QLIST_FOREACH(node, &ctx->aio_handlers, node) { + if (node->e == e && !node->deleted) { + break; + } + } + + /* Are we deleting the fd handler? */ + if (!io_notify) { + if (node) { + /* If the lock is held, just mark the node as deleted */ + if (ctx->walking_handlers) { + node->deleted = 1; + node->pfd.revents = 0; + } else { + /* Otherwise, delete it for real. We can't just mark it as + * deleted because deleted nodes are only cleaned up after + * releasing the walking_handlers lock. + */ + QLIST_REMOVE(node, node); + g_free(node); + } + } + } else { + if (node == NULL) { + /* Alloc and insert if it's not already there */ + node = g_malloc0(sizeof(AioHandler)); + node->e = e; + node->pfd.fd = (uintptr_t)event_notifier_get_handle(e); + node->pfd.events = G_IO_IN; + QLIST_INSERT_HEAD(&ctx->aio_handlers, node, node); + } + /* Update handler with latest information */ + node->io_notify = io_notify; + node->io_flush = io_flush; + } +} + +bool aio_pending(AioContext *ctx) +{ + AioHandler *node; + + QLIST_FOREACH(node, &ctx->aio_handlers, node) { + if (node->pfd.revents && node->io_notify) { + return true; + } + } + + return false; +} + +bool aio_poll(AioContext *ctx, bool blocking) +{ + AioHandler *node; + HANDLE events[MAXIMUM_WAIT_OBJECTS + 1]; + bool busy, progress; + int count; + + progress = false; + + /* + * If there are callbacks left that have been queued, we need to call then. + * Do not call select in this case, because it is possible that the caller + * does not need a complete flush (as is the case for qemu_aio_wait loops). + */ + if (aio_bh_poll(ctx)) { + blocking = false; + progress = true; + } + + /* + * Then dispatch any pending callbacks from the GSource. + * + * We have to walk very carefully in case qemu_aio_set_fd_handler is + * called while we're walking. + */ + node = QLIST_FIRST(&ctx->aio_handlers); + while (node) { + AioHandler *tmp; + + ctx->walking_handlers++; + + if (node->pfd.revents && node->io_notify) { + node->pfd.revents = 0; + node->io_notify(node->e); + progress = true; + } + + tmp = node; + node = QLIST_NEXT(node, node); + + ctx->walking_handlers--; + + if (!ctx->walking_handlers && tmp->deleted) { + QLIST_REMOVE(tmp, node); + g_free(tmp); + } + } + + if (progress && !blocking) { + return true; + } + + ctx->walking_handlers++; + + /* fill fd sets */ + busy = false; + count = 0; + QLIST_FOREACH(node, &ctx->aio_handlers, node) { + /* If there aren't pending AIO operations, don't invoke callbacks. + * Otherwise, if there are no AIO requests, qemu_aio_wait() would + * wait indefinitely. + */ + if (!node->deleted && node->io_flush) { + if (node->io_flush(node->e) == 0) { + continue; + } + busy = true; + } + if (!node->deleted && node->io_notify) { + events[count++] = event_notifier_get_handle(node->e); + } + } + + ctx->walking_handlers--; + + /* No AIO operations? Get us out of here */ + if (!busy) { + return progress; + } + + /* wait until next event */ + for (;;) { + int timeout = blocking ? INFINITE : 0; + int ret = WaitForMultipleObjects(count, events, FALSE, timeout); + + /* if we have any signaled events, dispatch event */ + if ((DWORD) (ret - WAIT_OBJECT_0) >= count) { + break; + } + + blocking = false; + + /* we have to walk very carefully in case + * qemu_aio_set_fd_handler is called while we're walking */ + node = QLIST_FIRST(&ctx->aio_handlers); + while (node) { + AioHandler *tmp; + + ctx->walking_handlers++; + + if (!node->deleted && + event_notifier_get_handle(node->e) == events[ret - WAIT_OBJECT_0] && + node->io_notify) { + node->io_notify(node->e); + progress = true; + } + + tmp = node; + node = QLIST_NEXT(node, node); + + ctx->walking_handlers--; + + if (!ctx->walking_handlers && tmp->deleted) { + QLIST_REMOVE(tmp, node); + g_free(tmp); + } + } + } + + return progress; +} diff --git a/block/Makefile.objs b/block/Makefile.objs index 554f429d05..684765bf63 100644 --- a/block/Makefile.objs +++ b/block/Makefile.objs @@ -2,13 +2,17 @@ block-obj-y += raw.o cow.o qcow.o vdi.o vmdk.o cloop.o dmg.o bochs.o vpc.o vvfat block-obj-y += qcow2.o qcow2-refcount.o qcow2-cluster.o qcow2-snapshot.o qcow2-cache.o block-obj-y += qed.o qed-gencb.o qed-l2-cache.o qed-table.o qed-cluster.o block-obj-y += qed-check.o -block-obj-y += parallels.o nbd.o blkdebug.o sheepdog.o blkverify.o +block-obj-y += parallels.o blkdebug.o blkverify.o block-obj-$(CONFIG_WIN32) += raw-win32.o block-obj-$(CONFIG_POSIX) += raw-posix.o + +ifeq ($(CONFIG_POSIX),y) +block-obj-y += nbd.o sheepdog.o block-obj-$(CONFIG_LIBISCSI) += iscsi.o block-obj-$(CONFIG_CURL) += curl.o block-obj-$(CONFIG_RBD) += rbd.o block-obj-$(CONFIG_GLUSTERFS) += gluster.o +endif common-obj-y += stream.o common-obj-y += commit.o diff --git a/main-loop.c b/main-loop.c index 1fdc3bdf2e..a86c275149 100644 --- a/main-loop.c +++ b/main-loop.c @@ -537,6 +537,7 @@ bool qemu_aio_wait(void) return aio_poll(qemu_aio_context, true); } +#ifdef CONFIG_POSIX void qemu_aio_set_fd_handler(int fd, IOHandler *io_read, IOHandler *io_write, @@ -549,7 +550,6 @@ void qemu_aio_set_fd_handler(int fd, qemu_set_fd_handler2(fd, NULL, io_read, io_write, opaque); } -#ifdef CONFIG_POSIX void qemu_aio_set_event_notifier(EventNotifier *notifier, EventNotifierHandler *io_read, AioFlushEventNotifierHandler *io_flush) From e3713e001fb7d4d82f6de82800c1463e758e4289 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 24 Sep 2012 14:57:41 +0200 Subject: [PATCH 052/291] aio: make AioContexts GSources This lets AioContexts be used (optionally) with a glib main loop. Signed-off-by: Paolo Bonzini --- aio-posix.c | 4 ++++ aio-win32.c | 4 ++++ async.c | 65 ++++++++++++++++++++++++++++++++++++++++++++++++++++- qemu-aio.h | 23 +++++++++++++++++++ 4 files changed, 95 insertions(+), 1 deletion(-) diff --git a/aio-posix.c b/aio-posix.c index 44247224e2..65b26073f0 100644 --- a/aio-posix.c +++ b/aio-posix.c @@ -56,6 +56,8 @@ void aio_set_fd_handler(AioContext *ctx, /* Are we deleting the fd handler? */ if (!io_read && !io_write) { if (node) { + g_source_remove_poll(&ctx->source, &node->pfd); + /* If the lock is held, just mark the node as deleted */ if (ctx->walking_handlers) { node->deleted = 1; @@ -75,6 +77,8 @@ void aio_set_fd_handler(AioContext *ctx, node = g_malloc0(sizeof(AioHandler)); node->pfd.fd = fd; QLIST_INSERT_HEAD(&ctx->aio_handlers, node, node); + + g_source_add_poll(&ctx->source, &node->pfd); } /* Update handler with latest information */ node->io_read = io_read; diff --git a/aio-win32.c b/aio-win32.c index 9881fdbca7..e460bd848a 100644 --- a/aio-win32.c +++ b/aio-win32.c @@ -45,6 +45,8 @@ void aio_set_event_notifier(AioContext *ctx, /* Are we deleting the fd handler? */ if (!io_notify) { if (node) { + g_source_remove_poll(&ctx->source, &node->pfd); + /* If the lock is held, just mark the node as deleted */ if (ctx->walking_handlers) { node->deleted = 1; @@ -66,6 +68,8 @@ void aio_set_event_notifier(AioContext *ctx, node->pfd.fd = (uintptr_t)event_notifier_get_handle(e); node->pfd.events = G_IO_IN; QLIST_INSERT_HEAD(&ctx->aio_handlers, node, node); + + g_source_add_poll(&ctx->source, &node->pfd); } /* Update handler with latest information */ node->io_notify = io_notify; diff --git a/async.c b/async.c index 513bdd7aa2..4ffdd986f1 100644 --- a/async.c +++ b/async.c @@ -136,10 +136,73 @@ void aio_bh_update_timeout(AioContext *ctx, uint32_t *timeout) } } +static gboolean +aio_ctx_prepare(GSource *source, gint *timeout) +{ + AioContext *ctx = (AioContext *) source; + uint32_t wait = -1; + aio_bh_update_timeout(ctx, &wait); + + if (wait != -1) { + *timeout = MIN(*timeout, wait); + return wait == 0; + } + + return false; +} + +static gboolean +aio_ctx_check(GSource *source) +{ + AioContext *ctx = (AioContext *) source; + QEMUBH *bh; + + for (bh = ctx->first_bh; bh; bh = bh->next) { + if (!bh->deleted && bh->scheduled) { + return true; + } + } + return aio_pending(ctx); +} + +static gboolean +aio_ctx_dispatch(GSource *source, + GSourceFunc callback, + gpointer user_data) +{ + AioContext *ctx = (AioContext *) source; + + assert(callback == NULL); + aio_poll(ctx, false); + return true; +} + +static GSourceFuncs aio_source_funcs = { + aio_ctx_prepare, + aio_ctx_check, + aio_ctx_dispatch, + NULL +}; + +GSource *aio_get_g_source(AioContext *ctx) +{ + g_source_ref(&ctx->source); + return &ctx->source; +} AioContext *aio_context_new(void) { - return g_new0(AioContext, 1); + return (AioContext *) g_source_new(&aio_source_funcs, sizeof(AioContext)); +} + +void aio_context_ref(AioContext *ctx) +{ + g_source_ref(&ctx->source); +} + +void aio_context_unref(AioContext *ctx) +{ + g_source_unref(&ctx->source); } void aio_flush(AioContext *ctx) diff --git a/qemu-aio.h b/qemu-aio.h index ac248962fe..aedf66cfa1 100644 --- a/qemu-aio.h +++ b/qemu-aio.h @@ -44,6 +44,8 @@ typedef void QEMUBHFunc(void *opaque); typedef void IOHandler(void *opaque); typedef struct AioContext { + GSource source; + /* The list of registered AIO handlers */ QLIST_HEAD(, AioHandler) aio_handlers; @@ -74,6 +76,22 @@ typedef int (AioFlushEventNotifierHandler)(EventNotifier *e); */ AioContext *aio_context_new(void); +/** + * aio_context_ref: + * @ctx: The AioContext to operate on. + * + * Add a reference to an AioContext. + */ +void aio_context_ref(AioContext *ctx); + +/** + * aio_context_unref: + * @ctx: The AioContext to operate on. + * + * Drop a reference to an AioContext. + */ +void aio_context_unref(AioContext *ctx); + /** * aio_bh_new: Allocate a new bottom half structure. * @@ -188,6 +206,11 @@ void aio_set_event_notifier(AioContext *ctx, EventNotifierHandler *io_read, AioFlushEventNotifierHandler *io_flush); +/* Return a GSource that lets the main loop poll the file descriptors attached + * to this AioContext. + */ +GSource *aio_get_g_source(AioContext *ctx); + /* Functions to operate on the main QEMU AioContext. */ void qemu_aio_flush(void); From 2f4dc3c1b2a453a8255d9b97c7cb87860123e495 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 24 Sep 2012 18:44:14 +0200 Subject: [PATCH 053/291] aio: add aio_notify With this change async.c does not rely anymore on any service from main-loop.c, i.e. it is completely self-contained. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- async.c | 30 ++++++++++++++++++++++++++---- qemu-aio.h | 18 ++++++++++++++++++ 2 files changed, 44 insertions(+), 4 deletions(-) diff --git a/async.c b/async.c index 4ffdd986f1..564526f57f 100644 --- a/async.c +++ b/async.c @@ -30,6 +30,7 @@ /* bottom halves (can be seen as timers which expire ASAP) */ struct QEMUBH { + AioContext *ctx; QEMUBHFunc *cb; void *opaque; QEMUBH *next; @@ -42,6 +43,7 @@ QEMUBH *aio_bh_new(AioContext *ctx, QEMUBHFunc *cb, void *opaque) { QEMUBH *bh; bh = g_malloc0(sizeof(QEMUBH)); + bh->ctx = ctx; bh->cb = cb; bh->opaque = opaque; bh->next = ctx->first_bh; @@ -101,8 +103,7 @@ void qemu_bh_schedule(QEMUBH *bh) return; bh->scheduled = 1; bh->idle = 0; - /* stop the currently executing CPU to execute the BH ASAP */ - qemu_notify_event(); + aio_notify(bh->ctx); } void qemu_bh_cancel(QEMUBH *bh) @@ -177,11 +178,20 @@ aio_ctx_dispatch(GSource *source, return true; } +static void +aio_ctx_finalize(GSource *source) +{ + AioContext *ctx = (AioContext *) source; + + aio_set_event_notifier(ctx, &ctx->notifier, NULL, NULL); + event_notifier_cleanup(&ctx->notifier); +} + static GSourceFuncs aio_source_funcs = { aio_ctx_prepare, aio_ctx_check, aio_ctx_dispatch, - NULL + aio_ctx_finalize }; GSource *aio_get_g_source(AioContext *ctx) @@ -190,9 +200,21 @@ GSource *aio_get_g_source(AioContext *ctx) return &ctx->source; } +void aio_notify(AioContext *ctx) +{ + event_notifier_set(&ctx->notifier); +} + AioContext *aio_context_new(void) { - return (AioContext *) g_source_new(&aio_source_funcs, sizeof(AioContext)); + AioContext *ctx; + ctx = (AioContext *) g_source_new(&aio_source_funcs, sizeof(AioContext)); + event_notifier_init(&ctx->notifier, false); + aio_set_event_notifier(ctx, &ctx->notifier, + (EventNotifierHandler *) + event_notifier_test_and_clear, NULL); + + return ctx; } void aio_context_ref(AioContext *ctx) diff --git a/qemu-aio.h b/qemu-aio.h index aedf66cfa1..2354617ed1 100644 --- a/qemu-aio.h +++ b/qemu-aio.h @@ -62,6 +62,9 @@ typedef struct AioContext { * no callbacks are removed while we're walking and dispatching callbacks. */ int walking_bh; + + /* Used for aio_notify. */ + EventNotifier notifier; } AioContext; /* Returns 1 if there are still outstanding AIO requests; 0 otherwise */ @@ -101,6 +104,21 @@ void aio_context_unref(AioContext *ctx); */ QEMUBH *aio_bh_new(AioContext *ctx, QEMUBHFunc *cb, void *opaque); +/** + * aio_notify: Force processing of pending events. + * + * Similar to signaling a condition variable, aio_notify forces + * aio_wait to exit, so that the next call will re-examine pending events. + * The caller of aio_notify will usually call aio_wait again very soon, + * or go through another iteration of the GLib main loop. Hence, aio_notify + * also has the side effect of recalculating the sets of file descriptors + * that the main loop waits for. + * + * Calling aio_notify is rarely necessary, because for example scheduling + * a bottom half calls it already. + */ +void aio_notify(AioContext *ctx); + /** * aio_bh_poll: Poll bottom halves for an AioContext. * From 7ed2b24ce17f8fb7e36e4e8d113f2a30cbea142f Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 25 Sep 2012 10:22:39 +0200 Subject: [PATCH 054/291] aio: call aio_notify after setting I/O handlers In the current code, this is done by qemu_set_fd_handler2, which is called by qemu_aio_set_fd_handler. We need to keep the same behavior even after removing the call to qemu_set_fd_handler2. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- aio-posix.c | 2 ++ aio-win32.c | 2 ++ 2 files changed, 4 insertions(+) diff --git a/aio-posix.c b/aio-posix.c index 65b26073f0..05cc84e121 100644 --- a/aio-posix.c +++ b/aio-posix.c @@ -89,6 +89,8 @@ void aio_set_fd_handler(AioContext *ctx, node->pfd.events = (io_read ? G_IO_IN | G_IO_HUP : 0); node->pfd.events |= (io_write ? G_IO_OUT : 0); } + + aio_notify(ctx); } void aio_set_event_notifier(AioContext *ctx, diff --git a/aio-win32.c b/aio-win32.c index e460bd848a..a84eb71246 100644 --- a/aio-win32.c +++ b/aio-win32.c @@ -75,6 +75,8 @@ void aio_set_event_notifier(AioContext *ctx, node->io_notify = io_notify; node->io_flush = io_flush; } + + aio_notify(ctx); } bool aio_pending(AioContext *ctx) From 82cbbdc6a0958b49c77639a60906e30d02e6bb7b Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 24 Sep 2012 15:07:08 +0200 Subject: [PATCH 055/291] main-loop: use GSource to poll AIO file descriptors This lets us remove the hooks for the main loop in async.c. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- main-loop.c | 23 ++++++----------------- main-loop.h | 1 - 2 files changed, 6 insertions(+), 18 deletions(-) diff --git a/main-loop.c b/main-loop.c index a86c275149..365c9d3261 100644 --- a/main-loop.c +++ b/main-loop.c @@ -205,6 +205,7 @@ static AioContext *qemu_aio_context; int qemu_init_main_loop(void) { int ret; + GSource *src; init_clocks(); init_timer_alarm(); @@ -222,6 +223,9 @@ int qemu_init_main_loop(void) } qemu_aio_context = aio_context_new(); + src = aio_get_g_source(qemu_aio_context); + g_source_attach(src, NULL); + g_source_unref(src); return 0; } @@ -484,8 +488,6 @@ int main_loop_wait(int nonblocking) if (nonblocking) { timeout = 0; - } else { - aio_bh_update_timeout(qemu_aio_context, &timeout); } /* poll any events */ @@ -508,10 +510,6 @@ int main_loop_wait(int nonblocking) qemu_run_all_timers(); - /* Check bottom-halves last in case any of the earlier events triggered - them. */ - qemu_bh_poll(); - return ret; } @@ -522,11 +520,6 @@ QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque) return aio_bh_new(qemu_aio_context, cb, opaque); } -int qemu_bh_poll(void) -{ - return aio_bh_poll(qemu_aio_context); -} - void qemu_aio_flush(void) { aio_flush(qemu_aio_context); @@ -546,16 +539,12 @@ void qemu_aio_set_fd_handler(int fd, { aio_set_fd_handler(qemu_aio_context, fd, io_read, io_write, io_flush, opaque); - - qemu_set_fd_handler2(fd, NULL, io_read, io_write, opaque); } +#endif void qemu_aio_set_event_notifier(EventNotifier *notifier, EventNotifierHandler *io_read, AioFlushEventNotifierHandler *io_flush) { - qemu_aio_set_fd_handler(event_notifier_get_fd(notifier), - (IOHandler *)io_read, NULL, - (AioFlushHandler *)io_flush, notifier); + aio_set_event_notifier(qemu_aio_context, notifier, io_read, io_flush); } -#endif diff --git a/main-loop.h b/main-loop.h index 1d1a56b858..326c74269c 100644 --- a/main-loop.h +++ b/main-loop.h @@ -302,6 +302,5 @@ void qemu_iohandler_poll(fd_set *readfds, fd_set *writefds, fd_set *xfds, int rc QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque); void qemu_bh_schedule_idle(QEMUBH *bh); -int qemu_bh_poll(void); #endif From 4c8d0d27676778febad3802a95218d5ceaca171e Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 24 May 2010 17:27:14 +0200 Subject: [PATCH 056/291] main-loop: use aio_notify for qemu_notify_event Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- main-loop.c | 110 +++++----------------------------------------------- 1 file changed, 10 insertions(+), 100 deletions(-) diff --git a/main-loop.c b/main-loop.c index 365c9d3261..e43c7c8e8d 100644 --- a/main-loop.c +++ b/main-loop.c @@ -32,70 +32,6 @@ #include "compatfd.h" -static int io_thread_fd = -1; - -void qemu_notify_event(void) -{ - /* Write 8 bytes to be compatible with eventfd. */ - static const uint64_t val = 1; - ssize_t ret; - - if (io_thread_fd == -1) { - return; - } - do { - ret = write(io_thread_fd, &val, sizeof(val)); - } while (ret < 0 && errno == EINTR); - - /* EAGAIN is fine, a read must be pending. */ - if (ret < 0 && errno != EAGAIN) { - fprintf(stderr, "qemu_notify_event: write() failed: %s\n", - strerror(errno)); - exit(1); - } -} - -static void qemu_event_read(void *opaque) -{ - int fd = (intptr_t)opaque; - ssize_t len; - char buffer[512]; - - /* Drain the notify pipe. For eventfd, only 8 bytes will be read. */ - do { - len = read(fd, buffer, sizeof(buffer)); - } while ((len == -1 && errno == EINTR) || len == sizeof(buffer)); -} - -static int qemu_event_init(void) -{ - int err; - int fds[2]; - - err = qemu_eventfd(fds); - if (err == -1) { - return -errno; - } - err = fcntl_setfl(fds[0], O_NONBLOCK); - if (err < 0) { - goto fail; - } - err = fcntl_setfl(fds[1], O_NONBLOCK); - if (err < 0) { - goto fail; - } - qemu_set_fd_handler2(fds[0], NULL, qemu_event_read, NULL, - (void *)(intptr_t)fds[0]); - - io_thread_fd = fds[1]; - return 0; - -fail: - close(fds[0]); - close(fds[1]); - return err; -} - /* If we have signalfd, we mask out the signals we want to handle and then * use signalfd to listen for them. We rely on whatever the current signal * handler is to dispatch the signals when we receive them. @@ -165,35 +101,6 @@ static int qemu_signal_init(void) #else /* _WIN32 */ -static HANDLE qemu_event_handle = NULL; - -static void dummy_event_handler(void *opaque) -{ -} - -static int qemu_event_init(void) -{ - qemu_event_handle = CreateEvent(NULL, FALSE, FALSE, NULL); - if (!qemu_event_handle) { - fprintf(stderr, "Failed CreateEvent: %ld\n", GetLastError()); - return -1; - } - qemu_add_wait_object(qemu_event_handle, dummy_event_handler, NULL); - return 0; -} - -void qemu_notify_event(void) -{ - if (!qemu_event_handle) { - return; - } - if (!SetEvent(qemu_event_handle)) { - fprintf(stderr, "qemu_notify_event: SetEvent failed: %ld\n", - GetLastError()); - exit(1); - } -} - static int qemu_signal_init(void) { return 0; @@ -202,6 +109,14 @@ static int qemu_signal_init(void) static AioContext *qemu_aio_context; +void qemu_notify_event(void) +{ + if (!qemu_aio_context) { + return; + } + aio_notify(qemu_aio_context); +} + int qemu_init_main_loop(void) { int ret; @@ -216,12 +131,6 @@ int qemu_init_main_loop(void) return ret; } - /* Note eventfd must be drained before signalfd handlers run */ - ret = qemu_event_init(); - if (ret) { - return ret; - } - qemu_aio_context = aio_context_new(); src = aio_get_g_source(qemu_aio_context); g_source_attach(src, NULL); @@ -411,7 +320,8 @@ void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque) void qemu_fd_register(int fd) { - WSAEventSelect(fd, qemu_event_handle, FD_READ | FD_ACCEPT | FD_CLOSE | + WSAEventSelect(fd, event_notifier_get_handle(&qemu_aio_context->notifier), + FD_READ | FD_ACCEPT | FD_CLOSE | FD_CONNECT | FD_WRITE | FD_OOB); } From 22bfa75eafc21522afbb265091faa9cc0649e9fb Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 24 Sep 2012 15:11:48 +0200 Subject: [PATCH 057/291] aio: clean up now-unused functions Some cleanups can now be made, now that the main loop does not anymore need hooks into the bottom half code. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- async.c | 23 +++++++---------------- oslib-posix.c | 31 ------------------------------- qemu-aio.h | 1 - qemu-common.h | 1 - 4 files changed, 7 insertions(+), 49 deletions(-) diff --git a/async.c b/async.c index 564526f57f..04f9dcbb4d 100644 --- a/async.c +++ b/async.c @@ -117,16 +117,20 @@ void qemu_bh_delete(QEMUBH *bh) bh->deleted = 1; } -void aio_bh_update_timeout(AioContext *ctx, uint32_t *timeout) +static gboolean +aio_ctx_prepare(GSource *source, gint *timeout) { + AioContext *ctx = (AioContext *) source; QEMUBH *bh; + bool scheduled = false; for (bh = ctx->first_bh; bh; bh = bh->next) { if (!bh->deleted && bh->scheduled) { + scheduled = true; if (bh->idle) { /* idle bottom halves will be polled at least * every 10ms */ - *timeout = MIN(10, *timeout); + *timeout = 10; } else { /* non-idle bottom halves will be executed * immediately */ @@ -135,21 +139,8 @@ void aio_bh_update_timeout(AioContext *ctx, uint32_t *timeout) } } } -} -static gboolean -aio_ctx_prepare(GSource *source, gint *timeout) -{ - AioContext *ctx = (AioContext *) source; - uint32_t wait = -1; - aio_bh_update_timeout(ctx, &wait); - - if (wait != -1) { - *timeout = MIN(*timeout, wait); - return wait == 0; - } - - return false; + return scheduled; } static gboolean diff --git a/oslib-posix.c b/oslib-posix.c index dbeb6272b8..9db9c3d8af 100644 --- a/oslib-posix.c +++ b/oslib-posix.c @@ -61,9 +61,6 @@ static int running_on_valgrind = -1; #ifdef CONFIG_LINUX #include #endif -#ifdef CONFIG_EVENTFD -#include -#endif int qemu_get_thread_id(void) { @@ -183,34 +180,6 @@ int qemu_pipe(int pipefd[2]) return ret; } -/* - * Creates an eventfd that looks like a pipe and has EFD_CLOEXEC set. - */ -int qemu_eventfd(int fds[2]) -{ -#ifdef CONFIG_EVENTFD - int ret; - - ret = eventfd(0, 0); - if (ret >= 0) { - fds[0] = ret; - fds[1] = dup(ret); - if (fds[1] == -1) { - close(ret); - return -1; - } - qemu_set_cloexec(ret); - qemu_set_cloexec(fds[1]); - return 0; - } - if (errno != ENOSYS) { - return -1; - } -#endif - - return qemu_pipe(fds); -} - int qemu_utimens(const char *path, const struct timespec *times) { struct timeval tv[2], tv_now; diff --git a/qemu-aio.h b/qemu-aio.h index 2354617ed1..1b7eb6ef5b 100644 --- a/qemu-aio.h +++ b/qemu-aio.h @@ -125,7 +125,6 @@ void aio_notify(AioContext *ctx); * These are internal functions used by the QEMU main loop. */ int aio_bh_poll(AioContext *ctx); -void aio_bh_update_timeout(AioContext *ctx, uint32_t *timeout); /** * qemu_bh_schedule: Schedule a bottom half. diff --git a/qemu-common.h b/qemu-common.h index 24e13ccb5e..c3328d230a 100644 --- a/qemu-common.h +++ b/qemu-common.h @@ -218,7 +218,6 @@ ssize_t qemu_recv_full(int fd, void *buf, size_t count, int flags) QEMU_WARN_UNUSED_RESULT; #ifndef _WIN32 -int qemu_eventfd(int pipefd[2]); int qemu_pipe(int pipefd[2]); #endif From c90caf25e2b6945ae13560476a5ecd7992e9f945 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 24 Feb 2012 08:39:02 +0100 Subject: [PATCH 058/291] linux-aio: use event notifiers Since linux-aio already uses an eventfd, converting it to use the EventNotifier-based API simplifies the code even though it is not meant to be portable. Reviewed-by: Anthony Liguori Signed-off-by: Paolo Bonzini --- linux-aio.c | 49 +++++++++++++++++++------------------------------ 1 file changed, 19 insertions(+), 30 deletions(-) diff --git a/linux-aio.c b/linux-aio.c index f3d8ef33ca..d1afb460c2 100644 --- a/linux-aio.c +++ b/linux-aio.c @@ -11,8 +11,8 @@ #include "qemu-aio.h" #include "qemu-queue.h" #include "block/raw-posix-aio.h" +#include "event_notifier.h" -#include #include /* @@ -38,7 +38,7 @@ struct qemu_laiocb { struct qemu_laio_state { io_context_t ctx; - int efd; + EventNotifier e; int count; }; @@ -77,29 +77,17 @@ static void qemu_laio_process_completion(struct qemu_laio_state *s, qemu_aio_release(laiocb); } -static void qemu_laio_completion_cb(void *opaque) +static void qemu_laio_completion_cb(EventNotifier *e) { - struct qemu_laio_state *s = opaque; + struct qemu_laio_state *s = container_of(e, struct qemu_laio_state, e); - while (1) { + while (event_notifier_test_and_clear(&s->e)) { struct io_event events[MAX_EVENTS]; - uint64_t val; - ssize_t ret; struct timespec ts = { 0 }; int nevents, i; do { - ret = read(s->efd, &val, sizeof(val)); - } while (ret == -1 && errno == EINTR); - - if (ret == -1 && errno == EAGAIN) - break; - - if (ret != 8) - break; - - do { - nevents = io_getevents(s->ctx, val, MAX_EVENTS, events, &ts); + nevents = io_getevents(s->ctx, MAX_EVENTS, MAX_EVENTS, events, &ts); } while (nevents == -EINTR); for (i = 0; i < nevents; i++) { @@ -113,9 +101,9 @@ static void qemu_laio_completion_cb(void *opaque) } } -static int qemu_laio_flush_cb(void *opaque) +static int qemu_laio_flush_cb(EventNotifier *e) { - struct qemu_laio_state *s = opaque; + struct qemu_laio_state *s = container_of(e, struct qemu_laio_state, e); return (s->count > 0) ? 1 : 0; } @@ -147,8 +135,9 @@ static void laio_cancel(BlockDriverAIOCB *blockacb) * We might be able to do this slightly more optimal by removing the * O_NONBLOCK flag. */ - while (laiocb->ret == -EINPROGRESS) - qemu_laio_completion_cb(laiocb->ctx); + while (laiocb->ret == -EINPROGRESS) { + qemu_laio_completion_cb(&laiocb->ctx->e); + } } static AIOPool laio_pool = { @@ -187,7 +176,7 @@ BlockDriverAIOCB *laio_submit(BlockDriverState *bs, void *aio_ctx, int fd, __func__, type); goto out_free_aiocb; } - io_set_eventfd(&laiocb->iocb, s->efd); + io_set_eventfd(&laiocb->iocb, event_notifier_get_fd(&s->e)); s->count++; if (io_submit(s->ctx, 1, &iocbs) < 0) @@ -206,21 +195,21 @@ void *laio_init(void) struct qemu_laio_state *s; s = g_malloc0(sizeof(*s)); - s->efd = eventfd(0, 0); - if (s->efd == -1) + if (event_notifier_init(&s->e, false) < 0) { goto out_free_state; - fcntl(s->efd, F_SETFL, O_NONBLOCK); + } - if (io_setup(MAX_EVENTS, &s->ctx) != 0) + if (io_setup(MAX_EVENTS, &s->ctx) != 0) { goto out_close_efd; + } - qemu_aio_set_fd_handler(s->efd, qemu_laio_completion_cb, NULL, - qemu_laio_flush_cb, s); + qemu_aio_set_event_notifier(&s->e, qemu_laio_completion_cb, + qemu_laio_flush_cb); return s; out_close_efd: - close(s->efd); + event_notifier_cleanup(&s->e); out_free_state: g_free(s); return NULL; From 18eb473f892642ae869f77403289167f30de2022 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Tue, 2 Oct 2012 17:36:54 +0200 Subject: [PATCH 059/291] target-i386: cpu_x86_register(): report error from property setter MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Igor Mammedov Reviewed-by: Eduardo Habkost Signed-off-by: Andreas Färber --- target-i386/cpu.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index d4f2e65cd9..f3a31212eb 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1427,7 +1427,8 @@ int cpu_x86_register(X86CPU *cpu, const char *cpu_model) env->cpuid_svm_features &= TCG_SVM_FEATURES; } object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error); - if (error_is_set(&error)) { + if (error) { + fprintf(stderr, "%s\n", error_get_pretty(error)); error_free(error); return -1; } From ff287bbdda016b37990be7ed52339750aaa8a5e4 Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Tue, 2 Oct 2012 17:36:55 +0200 Subject: [PATCH 060/291] target-i386: If x86_cpu_realize() failed, report error and do cleanup MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Igor Mammedov Signed-off-by: Andreas Färber --- target-i386/helper.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index c5d42c5916..0424ccf6fb 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1243,6 +1243,7 @@ X86CPU *cpu_x86_init(const char *cpu_model) { X86CPU *cpu; CPUX86State *env; + Error *error = NULL; cpu = X86_CPU(object_new(TYPE_X86_CPU)); env = &cpu->env; @@ -1253,8 +1254,12 @@ X86CPU *cpu_x86_init(const char *cpu_model) return NULL; } - x86_cpu_realize(OBJECT(cpu), NULL); - + x86_cpu_realize(OBJECT(cpu), &error); + if (error) { + error_free(error); + object_delete(OBJECT(cpu)); + return NULL; + } return cpu; } From bdeec802170d5dc9f0f8a01235c3488dca3ff83b Mon Sep 17 00:00:00 2001 From: Igor Mammedov Date: Sat, 13 Oct 2012 22:35:39 +0200 Subject: [PATCH 061/291] target-i386: Initialize APIC at CPU level MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit (L)APIC is a part of cpu [1] so move APIC initialization inside of x86_cpu object. Since cpu_model and override flags currently specify whether APIC should be created or not, APIC creation&initialization is moved into x86_cpu_apic_init() which is called from x86_cpu_realize(). [1] - all x86 cpus have integrated APIC if we overlook existence of i486, and it's more convenient to model after majority of them. Signed-off-by: Igor Mammedov Signed-off-by: Andreas Färber --- hw/pc.c | 56 +++++----------------------------------------- target-i386/cpu.c | 57 +++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 62 insertions(+), 51 deletions(-) diff --git a/hw/pc.c b/hw/pc.c index a02b397a24..4aca4986dd 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -71,8 +71,6 @@ #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) -#define MSI_ADDR_BASE 0xfee00000 - #define E820_NR_ENTRIES 16 struct e820_entry { @@ -849,35 +847,6 @@ DeviceState *cpu_get_current_apic(void) } } -static DeviceState *apic_init(void *env, uint8_t apic_id) -{ - DeviceState *dev; - static int apic_mapped; - - if (kvm_irqchip_in_kernel()) { - dev = qdev_create(NULL, "kvm-apic"); - } else if (xen_enabled()) { - dev = qdev_create(NULL, "xen-apic"); - } else { - dev = qdev_create(NULL, "apic"); - } - - qdev_prop_set_uint8(dev, "id", apic_id); - qdev_prop_set_ptr(dev, "cpu_env", env); - qdev_init_nofail(dev); - - /* XXX: mapping more APICs at the same memory location */ - if (apic_mapped == 0) { - /* NOTE: the APIC is directly connected to the CPU - it is not - on the global memory bus. */ - /* XXX: what if the base changes? */ - sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE); - apic_mapped = 1; - } - - return dev; -} - void pc_acpi_smi_interrupt(void *opaque, int irq, int level) { CPUX86State *s = opaque; @@ -887,24 +856,6 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level) } } -static X86CPU *pc_new_cpu(const char *cpu_model) -{ - X86CPU *cpu; - CPUX86State *env; - - cpu = cpu_x86_init(cpu_model); - if (cpu == NULL) { - fprintf(stderr, "Unable to find x86 CPU definition\n"); - exit(1); - } - env = &cpu->env; - if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { - env->apic_state = apic_init(env, env->cpuid_apic_id); - } - cpu_reset(CPU(cpu)); - return cpu; -} - void pc_cpus_init(const char *cpu_model) { int i; @@ -918,8 +869,11 @@ void pc_cpus_init(const char *cpu_model) #endif } - for(i = 0; i < smp_cpus; i++) { - pc_new_cpu(cpu_model); + for (i = 0; i < smp_cpus; i++) { + if (!cpu_x86_init(cpu_model)) { + fprintf(stderr, "Unable to find x86 CPU definition\n"); + exit(1); + } } } diff --git a/target-i386/cpu.c b/target-i386/cpu.c index f3a31212eb..18b8549a6f 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -37,6 +37,12 @@ #include #endif +#include "sysemu.h" +#ifndef CONFIG_USER_ONLY +#include "hw/xen.h" +#include "hw/sysbus.h" +#endif + /* feature flags taken from "Intel Processor Identification and the CPUID * Instruction" and AMD's "CPUID Specification". In cases of disagreement * between feature naming conventions, aliases may be added. @@ -1879,12 +1885,63 @@ static void mce_init(X86CPU *cpu) } } +#define MSI_ADDR_BASE 0xfee00000 + +#ifndef CONFIG_USER_ONLY +static void x86_cpu_apic_init(X86CPU *cpu, Error **errp) +{ + static int apic_mapped; + CPUX86State *env = &cpu->env; + const char *apic_type = "apic"; + + if (kvm_irqchip_in_kernel()) { + apic_type = "kvm-apic"; + } else if (xen_enabled()) { + apic_type = "xen-apic"; + } + + env->apic_state = qdev_try_create(NULL, apic_type); + if (env->apic_state == NULL) { + error_setg(errp, "APIC device '%s' could not be created", apic_type); + return; + } + + object_property_add_child(OBJECT(cpu), "apic", + OBJECT(env->apic_state), NULL); + qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id); + /* TODO: convert to link<> */ + qdev_prop_set_ptr(env->apic_state, "cpu_env", env); + + if (qdev_init(env->apic_state)) { + error_setg(errp, "APIC device '%s' could not be initialized", + object_get_typename(OBJECT(env->apic_state))); + return; + } + + /* XXX: mapping more APICs at the same memory location */ + if (apic_mapped == 0) { + /* NOTE: the APIC is directly connected to the CPU - it is not + on the global memory bus. */ + /* XXX: what if the base changes? */ + sysbus_mmio_map(sysbus_from_qdev(env->apic_state), 0, MSI_ADDR_BASE); + apic_mapped = 1; + } +} +#endif + void x86_cpu_realize(Object *obj, Error **errp) { X86CPU *cpu = X86_CPU(obj); #ifndef CONFIG_USER_ONLY qemu_register_reset(x86_cpu_machine_reset_cb, cpu); + + if (cpu->env.cpuid_features & CPUID_APIC || smp_cpus > 1) { + x86_cpu_apic_init(cpu, errp); + if (error_is_set(errp)) { + return; + } + } #endif mce_init(cpu); From 449994eb58a4175a2e7656175b18c65ead6c09ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 10 Oct 2012 12:18:02 +0200 Subject: [PATCH 062/291] target-i386: Inline APIC cpu_env property setting MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This prepares for changing the variable type from void*. Signed-off-by: Andreas Färber Reviewed-by: Igor Mammedov --- hw/apic_common.c | 1 - target-i386/cpu.c | 5 ++++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/apic_common.c b/hw/apic_common.c index d68116d490..b13f23c991 100644 --- a/hw/apic_common.c +++ b/hw/apic_common.c @@ -368,7 +368,6 @@ static const VMStateDescription vmstate_apic_common = { static Property apic_properties_common[] = { DEFINE_PROP_UINT8("id", APICCommonState, id, -1), - DEFINE_PROP_PTR("cpu_env", APICCommonState, cpu_env), DEFINE_PROP_BIT("vapic", APICCommonState, vapic_control, VAPIC_ENABLE_BIT, true), DEFINE_PROP_END_OF_LIST(), diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 18b8549a6f..c30cc799de 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -41,6 +41,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/xen.h" #include "hw/sysbus.h" +#include "hw/apic_internal.h" #endif /* feature flags taken from "Intel Processor Identification and the CPUID @@ -1892,6 +1893,7 @@ static void x86_cpu_apic_init(X86CPU *cpu, Error **errp) { static int apic_mapped; CPUX86State *env = &cpu->env; + APICCommonState *apic; const char *apic_type = "apic"; if (kvm_irqchip_in_kernel()) { @@ -1910,7 +1912,8 @@ static void x86_cpu_apic_init(X86CPU *cpu, Error **errp) OBJECT(env->apic_state), NULL); qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id); /* TODO: convert to link<> */ - qdev_prop_set_ptr(env->apic_state, "cpu_env", env); + apic = APIC_COMMON(env->apic_state); + apic->cpu_env = env; if (qdev_init(env->apic_state)) { error_setg(errp, "APIC device '%s' could not be initialized", From 60671e583c2bfb09746f59268fdc7d88eaa24deb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 10 Oct 2012 14:10:07 +0200 Subject: [PATCH 063/291] apic: Store X86CPU in APICCommonState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Prepares for using a link<> property to connect APIC with CPU and for changing the CPU APIs to CPUState. Resolve Coding Style warnings by moving the closing parenthesis of foreach_apic() macro to next line. Signed-off-by: Andreas Färber Reviewed-by: Igor Mammedov --- hw/apic.c | 38 +++++++++++++++++++++----------------- hw/apic_common.c | 4 ++-- hw/apic_internal.h | 3 ++- hw/kvm/apic.c | 8 ++++---- target-i386/cpu.c | 2 +- 5 files changed, 30 insertions(+), 25 deletions(-) diff --git a/hw/apic.c b/hw/apic.c index 49f00152ae..99e84f948b 100644 --- a/hw/apic.c +++ b/hw/apic.c @@ -107,7 +107,7 @@ static void apic_sync_vapic(APICCommonState *s, int sync_type) length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); if (sync_type & SYNC_TO_VAPIC) { - assert(qemu_cpu_is_self(s->cpu_env)); + assert(qemu_cpu_is_self(&s->cpu->env)); vapic_state.tpr = s->tpr; vapic_state.enabled = 1; @@ -151,15 +151,15 @@ static void apic_local_deliver(APICCommonState *s, int vector) switch ((lvt >> 8) & 7) { case APIC_DM_SMI: - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SMI); break; case APIC_DM_NMI: - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_NMI); break; case APIC_DM_EXTINT: - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); break; case APIC_DM_FIXED: @@ -187,7 +187,7 @@ void apic_deliver_pic_intr(DeviceState *d, int level) reset_bit(s->irr, lvt & 0xff); /* fall through */ case APIC_DM_EXTINT: - cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); break; } } @@ -248,18 +248,22 @@ static void apic_bus_deliver(const uint32_t *deliver_bitmask, case APIC_DM_SMI: foreach_apic(apic_iter, deliver_bitmask, - cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) ); + cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_SMI) + ); return; case APIC_DM_NMI: foreach_apic(apic_iter, deliver_bitmask, - cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) ); + cpu_interrupt(&apic_iter->cpu->env, CPU_INTERRUPT_NMI) + ); return; case APIC_DM_INIT: /* normal INIT IPI sent to processors */ foreach_apic(apic_iter, deliver_bitmask, - cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) ); + cpu_interrupt(&apic_iter->cpu->env, + CPU_INTERRUPT_INIT) + ); return; case APIC_DM_EXTINT: @@ -293,7 +297,7 @@ static void apic_set_base(APICCommonState *s, uint64_t val) /* if disabled, cannot be enabled again */ if (!(val & MSR_IA32_APICBASE_ENABLE)) { s->apicbase &= ~MSR_IA32_APICBASE_ENABLE; - cpu_clear_apic_feature(s->cpu_env); + cpu_clear_apic_feature(&s->cpu->env); s->spurious_vec &= ~APIC_SV_ENABLE; } } @@ -362,10 +366,10 @@ static void apic_update_irq(APICCommonState *s) if (!(s->spurious_vec & APIC_SV_ENABLE)) { return; } - if (!qemu_cpu_is_self(s->cpu_env)) { - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_POLL); + if (!qemu_cpu_is_self(&s->cpu->env)) { + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_POLL); } else if (apic_irq_pending(s) > 0) { - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); } } @@ -472,18 +476,18 @@ static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask, static void apic_startup(APICCommonState *s, int vector_num) { s->sipi_vector = vector_num; - cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI); } void apic_sipi(DeviceState *d) { APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); - cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI); + cpu_reset_interrupt(&s->cpu->env, CPU_INTERRUPT_SIPI); if (!s->wait_for_sipi) return; - cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector); + cpu_x86_load_seg_cache_sipi(&s->cpu->env, s->sipi_vector); s->wait_for_sipi = 0; } @@ -672,7 +676,7 @@ static uint32_t apic_mem_readl(void *opaque, hwaddr addr) case 0x08: apic_sync_vapic(s, SYNC_FROM_VAPIC); if (apic_report_tpr_access) { - cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_READ); + cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_READ); } val = s->tpr; break; @@ -774,7 +778,7 @@ static void apic_mem_writel(void *opaque, hwaddr addr, uint32_t val) break; case 0x08: if (apic_report_tpr_access) { - cpu_report_tpr_access(s->cpu_env, TPR_ACCESS_WRITE); + cpu_report_tpr_access(&s->cpu->env, TPR_ACCESS_WRITE); } s->tpr = val; apic_sync_vapic(s, SYNC_TO_VAPIC); diff --git a/hw/apic_common.c b/hw/apic_common.c index b13f23c991..5f542764eb 100644 --- a/hw/apic_common.c +++ b/hw/apic_common.c @@ -103,7 +103,7 @@ void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, { APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); - vapic_report_tpr_access(s->vapic, s->cpu_env, ip, access); + vapic_report_tpr_access(s->vapic, &s->cpu->env, ip, access); } void apic_report_irq_delivered(int delivered) @@ -217,7 +217,7 @@ static void apic_reset_common(DeviceState *d) APICCommonClass *info = APIC_COMMON_GET_CLASS(s); bool bsp; - bsp = cpu_is_bsp(x86_env_get_cpu(s->cpu_env)); + bsp = cpu_is_bsp(s->cpu); s->apicbase = 0xfee00000 | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; diff --git a/hw/apic_internal.h b/hw/apic_internal.h index 30932a303a..79e2de2243 100644 --- a/hw/apic_internal.h +++ b/hw/apic_internal.h @@ -95,8 +95,9 @@ typedef struct APICCommonClass struct APICCommonState { SysBusDevice busdev; + MemoryRegion io_memory; - void *cpu_env; + X86CPU *cpu; uint32_t apicbase; uint8_t id; uint8_t arb_id; diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c index dbac7fff50..e4a7307ca5 100644 --- a/hw/kvm/apic.c +++ b/hw/kvm/apic.c @@ -104,7 +104,7 @@ static void kvm_apic_enable_tpr_reporting(APICCommonState *s, bool enable) .enabled = enable }; - kvm_vcpu_ioctl(s->cpu_env, KVM_TPR_ACCESS_REPORTING, &ctl); + kvm_vcpu_ioctl(&s->cpu->env, KVM_TPR_ACCESS_REPORTING, &ctl); } static void kvm_apic_vapic_base_update(APICCommonState *s) @@ -114,7 +114,7 @@ static void kvm_apic_vapic_base_update(APICCommonState *s) }; int ret; - ret = kvm_vcpu_ioctl(s->cpu_env, KVM_SET_VAPIC_ADDR, &vapid_addr); + ret = kvm_vcpu_ioctl(&s->cpu->env, KVM_SET_VAPIC_ADDR, &vapid_addr); if (ret < 0) { fprintf(stderr, "KVM: setting VAPIC address failed (%s)\n", strerror(-ret)); @@ -125,7 +125,7 @@ static void kvm_apic_vapic_base_update(APICCommonState *s) static void do_inject_external_nmi(void *data) { APICCommonState *s = data; - CPUX86State *env = s->cpu_env; + CPUX86State *env = &s->cpu->env; uint32_t lvt; int ret; @@ -143,7 +143,7 @@ static void do_inject_external_nmi(void *data) static void kvm_apic_external_nmi(APICCommonState *s) { - run_on_cpu(s->cpu_env, do_inject_external_nmi, s); + run_on_cpu(&s->cpu->env, do_inject_external_nmi, s); } static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr, diff --git a/target-i386/cpu.c b/target-i386/cpu.c index c30cc799de..156e9199ed 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1913,7 +1913,7 @@ static void x86_cpu_apic_init(X86CPU *cpu, Error **errp) qdev_prop_set_uint8(env->apic_state, "id", env->cpuid_apic_id); /* TODO: convert to link<> */ apic = APIC_COMMON(env->apic_state); - apic->cpu_env = env; + apic->cpu = cpu; if (qdev_init(env->apic_state)) { error_setg(errp, "APIC device '%s' could not be initialized", From e9f9d6b16510776ae3d07e91b1cfb4d412701270 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 15:37:01 +0200 Subject: [PATCH 064/291] target-i386: Pass X86CPU to cpu_x86_load_seg_cache_sipi() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Simplifies the call in apic_sipi() again and needed for moving halted field to CPUState. Signed-off-by: Andreas Färber Reviewed-by: Igor Mammedov --- hw/apic.c | 2 +- target-i386/cpu.h | 4 +++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/apic.c b/hw/apic.c index 99e84f948b..4bc14e0c36 100644 --- a/hw/apic.c +++ b/hw/apic.c @@ -487,7 +487,7 @@ void apic_sipi(DeviceState *d) if (!s->wait_for_sipi) return; - cpu_x86_load_seg_cache_sipi(&s->cpu->env, s->sipi_vector); + cpu_x86_load_seg_cache_sipi(s->cpu, s->sipi_vector); s->wait_for_sipi = 0; } diff --git a/target-i386/cpu.h b/target-i386/cpu.h index de33303dea..d840914ebf 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -907,9 +907,11 @@ static inline void cpu_x86_load_seg_cache(CPUX86State *env, } } -static inline void cpu_x86_load_seg_cache_sipi(CPUX86State *env, +static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu, int sipi_vector) { + CPUX86State *env = &cpu->env; + env->eip = 0; cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8, sipi_vector << 12, From 60e82579c75068cb49af95595aa99d727e657a0a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 2 May 2012 22:23:49 +0200 Subject: [PATCH 065/291] cpus: Pass CPUState to qemu_cpu_is_self() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change return type to bool, move to include/qemu/cpu.h and add documentation. Signed-off-by: Andreas Färber Reviewed-by: Igor Mammedov [AF: Updated new caller qemu_in_vcpu_thread()] --- cpus.c | 12 +++++------- exec.c | 3 ++- hw/apic.c | 6 ++++-- include/qemu/cpu.h | 10 ++++++++++ kvm-all.c | 4 +++- qemu-common.h | 1 - target-i386/kvm.c | 6 ++++-- 7 files changed, 28 insertions(+), 14 deletions(-) diff --git a/cpus.c b/cpus.c index 191cbf5f6d..1f3ac9177c 100644 --- a/cpus.c +++ b/cpus.c @@ -638,9 +638,10 @@ void qemu_init_cpu_loop(void) void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data) { + CPUState *cpu = ENV_GET_CPU(env); struct qemu_work_item wi; - if (qemu_cpu_is_self(env)) { + if (qemu_cpu_is_self(cpu)) { func(data); return; } @@ -855,7 +856,7 @@ static void qemu_cpu_kick_thread(CPUArchState *env) exit(1); } #else /* _WIN32 */ - if (!qemu_cpu_is_self(env)) { + if (!qemu_cpu_is_self(cpu)) { SuspendThread(cpu->hThread); cpu_signal(0); ResumeThread(cpu->hThread); @@ -890,17 +891,14 @@ void qemu_cpu_kick_self(void) #endif } -int qemu_cpu_is_self(void *_env) +bool qemu_cpu_is_self(CPUState *cpu) { - CPUArchState *env = _env; - CPUState *cpu = ENV_GET_CPU(env); - return qemu_thread_is_self(cpu->thread); } static bool qemu_in_vcpu_thread(void) { - return cpu_single_env && qemu_cpu_is_self(cpu_single_env); + return cpu_single_env && qemu_cpu_is_self(ENV_GET_CPU(cpu_single_env)); } void qemu_mutex_lock_iothread(void) diff --git a/exec.c b/exec.c index b0ed5939e9..a85a9b1fd2 100644 --- a/exec.c +++ b/exec.c @@ -1693,6 +1693,7 @@ static void cpu_unlink_tb(CPUArchState *env) /* mask must never be zero, except for A20 change call */ static void tcg_handle_interrupt(CPUArchState *env, int mask) { + CPUState *cpu = ENV_GET_CPU(env); int old_mask; old_mask = env->interrupt_request; @@ -1702,7 +1703,7 @@ static void tcg_handle_interrupt(CPUArchState *env, int mask) * If called from iothread context, wake the target cpu in * case its halted. */ - if (!qemu_cpu_is_self(env)) { + if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(env); return; } diff --git a/hw/apic.c b/hw/apic.c index 4bc14e0c36..f73fc877aa 100644 --- a/hw/apic.c +++ b/hw/apic.c @@ -107,7 +107,7 @@ static void apic_sync_vapic(APICCommonState *s, int sync_type) length = offsetof(VAPICState, enabled) - offsetof(VAPICState, isr); if (sync_type & SYNC_TO_VAPIC) { - assert(qemu_cpu_is_self(&s->cpu->env)); + assert(qemu_cpu_is_self(CPU(s->cpu))); vapic_state.tpr = s->tpr; vapic_state.enabled = 1; @@ -363,10 +363,12 @@ static int apic_irq_pending(APICCommonState *s) /* signal the CPU if an irq is pending */ static void apic_update_irq(APICCommonState *s) { + CPUState *cpu = CPU(s->cpu); + if (!(s->spurious_vec & APIC_SV_ENABLE)) { return; } - if (!qemu_cpu_is_self(&s->cpu->env)) { + if (!qemu_cpu_is_self(cpu)) { cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_POLL); } else if (apic_irq_pending(s) > 0) { cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HARD); diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index ad706a6dbd..7be983d89c 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -78,5 +78,15 @@ struct CPUState { */ void cpu_reset(CPUState *cpu); +/** + * qemu_cpu_is_self: + * @cpu: The vCPU to check against. + * + * Checks whether the caller is executing on the vCPU thread. + * + * Returns: %true if called from @cpu's thread, %false otherwise. + */ +bool qemu_cpu_is_self(CPUState *cpu); + #endif diff --git a/kvm-all.c b/kvm-all.c index 961e1dbb71..74d2652f02 100644 --- a/kvm-all.c +++ b/kvm-all.c @@ -828,9 +828,11 @@ static MemoryListener kvm_io_listener = { static void kvm_handle_interrupt(CPUArchState *env, int mask) { + CPUState *cpu = ENV_GET_CPU(env); + env->interrupt_request |= mask; - if (!qemu_cpu_is_self(env)) { + if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(env); } } diff --git a/qemu-common.h b/qemu-common.h index b54612b1a5..2094742f2b 100644 --- a/qemu-common.h +++ b/qemu-common.h @@ -326,7 +326,6 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id); /* Unblock cpu */ void qemu_cpu_kick(void *env); void qemu_cpu_kick_self(void); -int qemu_cpu_is_self(void *env); /* work queue */ struct qemu_work_item { diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 3aa62b20ff..c13f196e05 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1552,9 +1552,10 @@ static int kvm_get_debugregs(CPUX86State *env) int kvm_arch_put_registers(CPUX86State *env, int level) { + CPUState *cpu = ENV_GET_CPU(env); int ret; - assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); + assert(cpu_is_stopped(env) || qemu_cpu_is_self(cpu)); ret = kvm_getput_regs(env, 1); if (ret < 0) { @@ -1609,9 +1610,10 @@ int kvm_arch_put_registers(CPUX86State *env, int level) int kvm_arch_get_registers(CPUX86State *env) { + CPUState *cpu = ENV_GET_CPU(env); int ret; - assert(cpu_is_stopped(env) || qemu_cpu_is_self(env)); + assert(cpu_is_stopped(env) || qemu_cpu_is_self(cpu)); ret = kvm_getput_regs(env, 0); if (ret < 0) { From 2ff09a40a8399a6f9807ebdb72423ec0a581c3b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 00:23:30 +0200 Subject: [PATCH 066/291] cpus: Pass CPUState to qemu_cpu_kick_thread() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPUArchState is no longer needed there. Signed-off-by: Andreas Färber Reviewed-by: Igor Mammedov --- cpus.c | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/cpus.c b/cpus.c index 1f3ac9177c..3946d49cff 100644 --- a/cpus.c +++ b/cpus.c @@ -844,9 +844,8 @@ static void *qemu_tcg_cpu_thread_fn(void *arg) return NULL; } -static void qemu_cpu_kick_thread(CPUArchState *env) +static void qemu_cpu_kick_thread(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); #ifndef _WIN32 int err; @@ -871,7 +870,7 @@ void qemu_cpu_kick(void *_env) qemu_cond_broadcast(env->halt_cond); if (!tcg_enabled() && !cpu->thread_kicked) { - qemu_cpu_kick_thread(env); + qemu_cpu_kick_thread(cpu); cpu->thread_kicked = true; } } @@ -883,7 +882,7 @@ void qemu_cpu_kick_self(void) CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env); if (!cpu_single_cpu->thread_kicked) { - qemu_cpu_kick_thread(cpu_single_env); + qemu_cpu_kick_thread(cpu_single_cpu); cpu_single_cpu->thread_kicked = true; } #else @@ -908,7 +907,7 @@ void qemu_mutex_lock_iothread(void) } else { iothread_requesting_mutex = true; if (qemu_mutex_trylock(&qemu_global_mutex)) { - qemu_cpu_kick_thread(first_cpu); + qemu_cpu_kick_thread(ENV_GET_CPU(first_cpu)); qemu_mutex_lock(&qemu_global_mutex); } iothread_requesting_mutex = false; From 61a4621784a808f5ad7d63f60e2c5e8b2488c213 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 2 May 2012 22:49:36 +0200 Subject: [PATCH 067/291] cpu: Move created field to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change its type to bool. Signed-off-by: Andreas Färber --- cpu-defs.h | 1 - cpus.c | 13 +++++++------ include/qemu/cpu.h | 2 ++ 3 files changed, 9 insertions(+), 7 deletions(-) diff --git a/cpu-defs.h b/cpu-defs.h index a7965775b2..3b8bc20329 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -205,7 +205,6 @@ typedef struct CPUWatchpoint { /* user data */ \ void *opaque; \ \ - uint32_t created; \ uint32_t stop; /* Stop request */ \ uint32_t stopped; /* Artificially stopped */ \ struct QemuCond *halt_cond; \ diff --git a/cpus.c b/cpus.c index 3946d49cff..8abaa69d41 100644 --- a/cpus.c +++ b/cpus.c @@ -746,7 +746,7 @@ static void *qemu_kvm_cpu_thread_fn(void *arg) qemu_kvm_init_cpu_signals(env); /* signal CPU creation */ - env->created = 1; + cpu->created = true; qemu_cond_signal(&qemu_cpu_cond); while (1) { @@ -781,7 +781,7 @@ static void *qemu_dummy_cpu_thread_fn(void *arg) sigaddset(&waitset, SIG_IPI); /* signal CPU creation */ - env->created = 1; + cpu->created = true; qemu_cond_signal(&qemu_cpu_cond); cpu_single_env = env; @@ -818,8 +818,9 @@ static void *qemu_tcg_cpu_thread_fn(void *arg) /* signal CPU creation */ qemu_mutex_lock(&qemu_global_mutex); for (env = first_cpu; env != NULL; env = env->next_cpu) { + cpu = ENV_GET_CPU(env); env->thread_id = qemu_get_thread_id(); - env->created = 1; + cpu->created = true; } qemu_cond_signal(&qemu_cpu_cond); @@ -996,7 +997,7 @@ static void qemu_tcg_init_vcpu(void *_env) #ifdef _WIN32 cpu->hThread = qemu_thread_get_handle(cpu->thread); #endif - while (env->created == 0) { + while (!cpu->created) { qemu_cond_wait(&qemu_cpu_cond, &qemu_global_mutex); } tcg_cpu_thread = cpu->thread; @@ -1015,7 +1016,7 @@ static void qemu_kvm_start_vcpu(CPUArchState *env) qemu_cond_init(env->halt_cond); qemu_thread_create(cpu->thread, qemu_kvm_cpu_thread_fn, env, QEMU_THREAD_JOINABLE); - while (env->created == 0) { + while (!cpu->created) { qemu_cond_wait(&qemu_cpu_cond, &qemu_global_mutex); } } @@ -1029,7 +1030,7 @@ static void qemu_dummy_start_vcpu(CPUArchState *env) qemu_cond_init(env->halt_cond); qemu_thread_create(cpu->thread, qemu_dummy_cpu_thread_fn, env, QEMU_THREAD_JOINABLE); - while (env->created == 0) { + while (!cpu->created) { qemu_cond_wait(&qemu_cpu_cond, &qemu_global_mutex); } } diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index 7be983d89c..3ab2e2567f 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -54,6 +54,7 @@ typedef struct CPUClass { /** * CPUState: + * @created: Indicates whether the CPU thread has been successfully created. * * State of one CPU core or thread. */ @@ -67,6 +68,7 @@ struct CPUState { HANDLE hThread; #endif bool thread_kicked; + bool created; /* TODO Move common fields from CPUArchState here. */ }; From 4fdeee7cd4c8f90ef765537b9346a195d9483ab5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 2 May 2012 23:10:09 +0200 Subject: [PATCH 068/291] cpu: Move stop field to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change its type to bool. Signed-off-by: Andreas Färber --- cpu-defs.h | 1 - cpus.c | 27 ++++++++++++++++++--------- include/qemu/cpu.h | 2 ++ 3 files changed, 20 insertions(+), 10 deletions(-) diff --git a/cpu-defs.h b/cpu-defs.h index 3b8bc20329..7a6378c5a1 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -205,7 +205,6 @@ typedef struct CPUWatchpoint { /* user data */ \ void *opaque; \ \ - uint32_t stop; /* Stop request */ \ uint32_t stopped; /* Artificially stopped */ \ struct QemuCond *halt_cond; \ struct qemu_work_item *queued_work_first, *queued_work_last; \ diff --git a/cpus.c b/cpus.c index 8abaa69d41..2341ebb68c 100644 --- a/cpus.c +++ b/cpus.c @@ -64,7 +64,9 @@ static CPUArchState *next_cpu; static bool cpu_thread_is_idle(CPUArchState *env) { - if (env->stop || env->queued_work_first) { + CPUState *cpu = ENV_GET_CPU(env); + + if (cpu->stop || env->queued_work_first) { return false; } if (env->stopped || !runstate_is_running()) { @@ -448,7 +450,9 @@ static void do_vm_stop(RunState state) static int cpu_can_run(CPUArchState *env) { - if (env->stop) { + CPUState *cpu = ENV_GET_CPU(env); + + if (cpu->stop) { return 0; } if (env->stopped || !runstate_is_running()) { @@ -687,8 +691,8 @@ static void qemu_wait_io_event_common(CPUArchState *env) { CPUState *cpu = ENV_GET_CPU(env); - if (env->stop) { - env->stop = 0; + if (cpu->stop) { + cpu->stop = false; env->stopped = 1; qemu_cond_signal(&qemu_pause_cond); } @@ -941,7 +945,8 @@ void pause_all_vcpus(void) qemu_clock_enable(vm_clock, false); while (penv) { - penv->stop = 1; + CPUState *pcpu = ENV_GET_CPU(penv); + pcpu->stop = true; qemu_cpu_kick(penv); penv = penv->next_cpu; } @@ -950,7 +955,8 @@ void pause_all_vcpus(void) cpu_stop_current(); if (!kvm_enabled()) { while (penv) { - penv->stop = 0; + CPUState *pcpu = ENV_GET_CPU(penv); + pcpu->stop = 0; penv->stopped = 1; penv = penv->next_cpu; } @@ -974,7 +980,8 @@ void resume_all_vcpus(void) qemu_clock_enable(vm_clock, true); while (penv) { - penv->stop = 0; + CPUState *pcpu = ENV_GET_CPU(penv); + pcpu->stop = false; penv->stopped = 0; qemu_cpu_kick(penv); penv = penv->next_cpu; @@ -1054,7 +1061,8 @@ void qemu_init_vcpu(void *_env) void cpu_stop_current(void) { if (cpu_single_env) { - cpu_single_env->stop = 0; + CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env); + cpu_single_cpu->stop = false; cpu_single_env->stopped = 1; cpu_exit(cpu_single_env); qemu_cond_signal(&qemu_pause_cond); @@ -1136,6 +1144,7 @@ static void tcg_exec_all(void) } for (; next_cpu != NULL && !exit_request; next_cpu = next_cpu->next_cpu) { CPUArchState *env = next_cpu; + CPUState *cpu = ENV_GET_CPU(env); qemu_clock_enable(vm_clock, (env->singlestep_enabled & SSTEP_NOTIMER) == 0); @@ -1146,7 +1155,7 @@ static void tcg_exec_all(void) cpu_handle_guest_debug(env); break; } - } else if (env->stop || env->stopped) { + } else if (cpu->stop || env->stopped) { break; } } diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index 3ab2e2567f..04c7848b8f 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -55,6 +55,7 @@ typedef struct CPUClass { /** * CPUState: * @created: Indicates whether the CPU thread has been successfully created. + * @stop: Indicates a pending stop request. * * State of one CPU core or thread. */ @@ -69,6 +70,7 @@ struct CPUState { #endif bool thread_kicked; bool created; + bool stop; /* TODO Move common fields from CPUArchState here. */ }; From b6444a42c06371d5abba78d2553a088a8490a65b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 00:34:15 +0200 Subject: [PATCH 069/291] ppce500_spin: Store PowerPCCPU in SpinKick MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for moving stopped field to CPUState. Signed-off-by: Andreas Färber --- hw/ppce500_spin.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/ppce500_spin.c b/hw/ppce500_spin.c index 55aa9dc8a2..04e7e65d44 100644 --- a/hw/ppce500_spin.c +++ b/hw/ppce500_spin.c @@ -49,7 +49,7 @@ typedef struct spin_state { } SpinState; typedef struct spin_kick { - CPUPPCState *env; + PowerPCCPU *cpu; SpinInfo *spin; } SpinKick; @@ -92,7 +92,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, static void spin_kick(void *data) { SpinKick *kick = data; - CPUPPCState *env = kick->env; + CPUPPCState *env = &kick->cpu->env; SpinInfo *curspin = kick->spin; hwaddr map_size = 64 * 1024 * 1024; hwaddr map_start; @@ -158,7 +158,7 @@ static void spin_write(void *opaque, hwaddr addr, uint64_t value, if (!(ldq_p(&curspin->addr) & 1)) { /* run CPU */ SpinKick kick = { - .env = env, + .cpu = ppc_env_get_cpu(env), .spin = curspin, }; From f324e7667a3c1f1aed9a5169a63aaac628feef47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 2 May 2012 23:26:21 +0200 Subject: [PATCH 070/291] cpu: Move stopped field to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change its type to bool. Signed-off-by: Andreas Färber --- cpu-defs.h | 1 - cpus.c | 30 ++++++++++++++++++------------ hw/ppce500_spin.c | 3 ++- include/qemu/cpu.h | 2 ++ 4 files changed, 22 insertions(+), 14 deletions(-) diff --git a/cpu-defs.h b/cpu-defs.h index 7a6378c5a1..83bf1089a6 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -205,7 +205,6 @@ typedef struct CPUWatchpoint { /* user data */ \ void *opaque; \ \ - uint32_t stopped; /* Artificially stopped */ \ struct QemuCond *halt_cond; \ struct qemu_work_item *queued_work_first, *queued_work_last; \ const char *cpu_model_str; \ diff --git a/cpus.c b/cpus.c index 2341ebb68c..4654f0878b 100644 --- a/cpus.c +++ b/cpus.c @@ -69,7 +69,7 @@ static bool cpu_thread_is_idle(CPUArchState *env) if (cpu->stop || env->queued_work_first) { return false; } - if (env->stopped || !runstate_is_running()) { + if (cpu->stopped || !runstate_is_running()) { return true; } if (!env->halted || qemu_cpu_has_work(env) || @@ -432,7 +432,9 @@ void cpu_synchronize_all_post_init(void) int cpu_is_stopped(CPUArchState *env) { - return !runstate_is_running() || env->stopped; + CPUState *cpu = ENV_GET_CPU(env); + + return !runstate_is_running() || cpu->stopped; } static void do_vm_stop(RunState state) @@ -455,7 +457,7 @@ static int cpu_can_run(CPUArchState *env) if (cpu->stop) { return 0; } - if (env->stopped || !runstate_is_running()) { + if (cpu->stopped || !runstate_is_running()) { return 0; } return 1; @@ -463,9 +465,11 @@ static int cpu_can_run(CPUArchState *env) static void cpu_handle_guest_debug(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); + gdb_set_stop_cpu(env); qemu_system_debug_request(); - env->stopped = 1; + cpu->stopped = true; } static void cpu_signal(int sig) @@ -693,7 +697,7 @@ static void qemu_wait_io_event_common(CPUArchState *env) if (cpu->stop) { cpu->stop = false; - env->stopped = 1; + cpu->stopped = true; qemu_cond_signal(&qemu_pause_cond); } flush_queued_work(env); @@ -829,7 +833,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg) qemu_cond_signal(&qemu_cpu_cond); /* wait for initial kick-off after machine start */ - while (first_cpu->stopped) { + while (ENV_GET_CPU(first_cpu)->stopped) { qemu_cond_wait(tcg_halt_cond, &qemu_global_mutex); /* process any pending work */ @@ -930,7 +934,8 @@ static int all_vcpus_paused(void) CPUArchState *penv = first_cpu; while (penv) { - if (!penv->stopped) { + CPUState *pcpu = ENV_GET_CPU(penv); + if (!pcpu->stopped) { return 0; } penv = penv->next_cpu; @@ -957,7 +962,7 @@ void pause_all_vcpus(void) while (penv) { CPUState *pcpu = ENV_GET_CPU(penv); pcpu->stop = 0; - penv->stopped = 1; + pcpu->stopped = true; penv = penv->next_cpu; } return; @@ -982,7 +987,7 @@ void resume_all_vcpus(void) while (penv) { CPUState *pcpu = ENV_GET_CPU(penv); pcpu->stop = false; - penv->stopped = 0; + pcpu->stopped = false; qemu_cpu_kick(penv); penv = penv->next_cpu; } @@ -1045,10 +1050,11 @@ static void qemu_dummy_start_vcpu(CPUArchState *env) void qemu_init_vcpu(void *_env) { CPUArchState *env = _env; + CPUState *cpu = ENV_GET_CPU(env); env->nr_cores = smp_cores; env->nr_threads = smp_threads; - env->stopped = 1; + cpu->stopped = true; if (kvm_enabled()) { qemu_kvm_start_vcpu(env); } else if (tcg_enabled()) { @@ -1063,7 +1069,7 @@ void cpu_stop_current(void) if (cpu_single_env) { CPUState *cpu_single_cpu = ENV_GET_CPU(cpu_single_env); cpu_single_cpu->stop = false; - cpu_single_env->stopped = 1; + cpu_single_cpu->stopped = true; cpu_exit(cpu_single_env); qemu_cond_signal(&qemu_pause_cond); } @@ -1155,7 +1161,7 @@ static void tcg_exec_all(void) cpu_handle_guest_debug(env); break; } - } else if (cpu->stop || env->stopped) { + } else if (cpu->stop || cpu->stopped) { break; } } diff --git a/hw/ppce500_spin.c b/hw/ppce500_spin.c index 04e7e65d44..fb5461d588 100644 --- a/hw/ppce500_spin.c +++ b/hw/ppce500_spin.c @@ -92,6 +92,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, static void spin_kick(void *data) { SpinKick *kick = data; + CPUState *cpu = CPU(kick->cpu); CPUPPCState *env = &kick->cpu->env; SpinInfo *curspin = kick->spin; hwaddr map_size = 64 * 1024 * 1024; @@ -113,7 +114,7 @@ static void spin_kick(void *data) env->halted = 0; env->exception_index = -1; - env->stopped = 0; + cpu->stopped = false; qemu_cpu_kick(env); } diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index 04c7848b8f..83378c54ae 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -56,6 +56,7 @@ typedef struct CPUClass { * CPUState: * @created: Indicates whether the CPU thread has been successfully created. * @stop: Indicates a pending stop request. + * @stopped: Indicates the CPU has been artificially stopped. * * State of one CPU core or thread. */ @@ -71,6 +72,7 @@ struct CPUState { bool thread_kicked; bool created; bool stop; + bool stopped; /* TODO Move common fields from CPUArchState here. */ }; From 2fa45344a92444439c081cad2342ffc048c381ad Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 2 May 2012 23:38:39 +0200 Subject: [PATCH 071/291] cpus: Pass CPUState to cpu_is_stopped() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPUArchState is no longer needed there. Also change the return type to bool. Signed-off-by: Andreas Färber --- cpu-all.h | 1 - cpus.c | 4 +--- include/qemu/cpu.h | 11 +++++++++++ target-i386/kvm.c | 4 ++-- 4 files changed, 14 insertions(+), 6 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index 6606432944..d19ec127e1 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -466,7 +466,6 @@ void cpu_watchpoint_remove_all(CPUArchState *env, int mask); #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ void cpu_single_step(CPUArchState *env, int enabled); -int cpu_is_stopped(CPUArchState *env); void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data); #if !defined(CONFIG_USER_ONLY) diff --git a/cpus.c b/cpus.c index 4654f0878b..0721a96831 100644 --- a/cpus.c +++ b/cpus.c @@ -430,10 +430,8 @@ void cpu_synchronize_all_post_init(void) } } -int cpu_is_stopped(CPUArchState *env) +bool cpu_is_stopped(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); - return !runstate_is_running() || cpu->stopped; } diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index 83378c54ae..4e62032463 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -94,5 +94,16 @@ void cpu_reset(CPUState *cpu); */ bool qemu_cpu_is_self(CPUState *cpu); +/** + * cpu_is_stopped: + * @cpu: The CPU to check. + * + * Checks whether the CPU is stopped. + * + * Returns: %true if run state is not running or if artificially stopped; + * %false otherwise. + */ +bool cpu_is_stopped(CPUState *cpu); + #endif diff --git a/target-i386/kvm.c b/target-i386/kvm.c index c13f196e05..a3491a4fa1 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1555,7 +1555,7 @@ int kvm_arch_put_registers(CPUX86State *env, int level) CPUState *cpu = ENV_GET_CPU(env); int ret; - assert(cpu_is_stopped(env) || qemu_cpu_is_self(cpu)); + assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); ret = kvm_getput_regs(env, 1); if (ret < 0) { @@ -1613,7 +1613,7 @@ int kvm_arch_get_registers(CPUX86State *env) CPUState *cpu = ENV_GET_CPU(env); int ret; - assert(cpu_is_stopped(env) || qemu_cpu_is_self(cpu)); + assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); ret = kvm_getput_regs(env, 0); if (ret < 0) { From a1fcaa73b1be5d8f0c6682d0f8d268f6e3194ead Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Wed, 2 May 2012 23:42:26 +0200 Subject: [PATCH 072/291] cpus: Pass CPUState to cpu_can_run() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPUArchState is no longer needed there. Also change its return type to bool. Signed-off-by: Andreas Färber --- cpus.c | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/cpus.c b/cpus.c index 0721a96831..45877ee838 100644 --- a/cpus.c +++ b/cpus.c @@ -448,17 +448,15 @@ static void do_vm_stop(RunState state) } } -static int cpu_can_run(CPUArchState *env) +static bool cpu_can_run(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); - if (cpu->stop) { - return 0; + return false; } if (cpu->stopped || !runstate_is_running()) { - return 0; + return false; } - return 1; + return true; } static void cpu_handle_guest_debug(CPUArchState *env) @@ -756,7 +754,7 @@ static void *qemu_kvm_cpu_thread_fn(void *arg) qemu_cond_signal(&qemu_cpu_cond); while (1) { - if (cpu_can_run(env)) { + if (cpu_can_run(cpu)) { r = kvm_cpu_exec(env); if (r == EXCP_DEBUG) { cpu_handle_guest_debug(env); @@ -1153,7 +1151,7 @@ static void tcg_exec_all(void) qemu_clock_enable(vm_clock, (env->singlestep_enabled & SSTEP_NOTIMER) == 0); - if (cpu_can_run(env)) { + if (cpu_can_run(cpu)) { r = tcg_cpu_exec(env); if (r == EXCP_DEBUG) { cpu_handle_guest_debug(env); From f5c121b85832f69fde5ad8939274e04ad21c1bd6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 01:22:49 +0200 Subject: [PATCH 073/291] cpu: Move halt_cond to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-defs.h | 1 - cpus.c | 22 ++++++++++++---------- include/qemu/cpu.h | 1 + 3 files changed, 13 insertions(+), 11 deletions(-) diff --git a/cpu-defs.h b/cpu-defs.h index 83bf1089a6..76c76f6c62 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -205,7 +205,6 @@ typedef struct CPUWatchpoint { /* user data */ \ void *opaque; \ \ - struct QemuCond *halt_cond; \ struct qemu_work_item *queued_work_first, *queued_work_last; \ const char *cpu_model_str; \ struct KVMState *kvm_state; \ diff --git a/cpus.c b/cpus.c index 45877ee838..5a80bfa984 100644 --- a/cpus.c +++ b/cpus.c @@ -722,8 +722,10 @@ static void qemu_tcg_wait_io_event(void) static void qemu_kvm_wait_io_event(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); + while (cpu_thread_is_idle(env)) { - qemu_cond_wait(env->halt_cond, &qemu_global_mutex); + qemu_cond_wait(cpu->halt_cond, &qemu_global_mutex); } qemu_kvm_eat_signals(env); @@ -873,7 +875,7 @@ void qemu_cpu_kick(void *_env) CPUArchState *env = _env; CPUState *cpu = ENV_GET_CPU(env); - qemu_cond_broadcast(env->halt_cond); + qemu_cond_broadcast(cpu->halt_cond); if (!tcg_enabled() && !cpu->thread_kicked) { qemu_cpu_kick_thread(cpu); cpu->thread_kicked = true; @@ -997,9 +999,9 @@ static void qemu_tcg_init_vcpu(void *_env) /* share a single thread for all cpus with TCG */ if (!tcg_cpu_thread) { cpu->thread = g_malloc0(sizeof(QemuThread)); - env->halt_cond = g_malloc0(sizeof(QemuCond)); - qemu_cond_init(env->halt_cond); - tcg_halt_cond = env->halt_cond; + cpu->halt_cond = g_malloc0(sizeof(QemuCond)); + qemu_cond_init(cpu->halt_cond); + tcg_halt_cond = cpu->halt_cond; qemu_thread_create(cpu->thread, qemu_tcg_cpu_thread_fn, env, QEMU_THREAD_JOINABLE); #ifdef _WIN32 @@ -1011,7 +1013,7 @@ static void qemu_tcg_init_vcpu(void *_env) tcg_cpu_thread = cpu->thread; } else { cpu->thread = tcg_cpu_thread; - env->halt_cond = tcg_halt_cond; + cpu->halt_cond = tcg_halt_cond; } } @@ -1020,8 +1022,8 @@ static void qemu_kvm_start_vcpu(CPUArchState *env) CPUState *cpu = ENV_GET_CPU(env); cpu->thread = g_malloc0(sizeof(QemuThread)); - env->halt_cond = g_malloc0(sizeof(QemuCond)); - qemu_cond_init(env->halt_cond); + cpu->halt_cond = g_malloc0(sizeof(QemuCond)); + qemu_cond_init(cpu->halt_cond); qemu_thread_create(cpu->thread, qemu_kvm_cpu_thread_fn, env, QEMU_THREAD_JOINABLE); while (!cpu->created) { @@ -1034,8 +1036,8 @@ static void qemu_dummy_start_vcpu(CPUArchState *env) CPUState *cpu = ENV_GET_CPU(env); cpu->thread = g_malloc0(sizeof(QemuThread)); - env->halt_cond = g_malloc0(sizeof(QemuCond)); - qemu_cond_init(env->halt_cond); + cpu->halt_cond = g_malloc0(sizeof(QemuCond)); + qemu_cond_init(cpu->halt_cond); qemu_thread_create(cpu->thread, qemu_dummy_cpu_thread_fn, env, QEMU_THREAD_JOINABLE); while (!cpu->created) { diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index 4e62032463..75e0f8dc68 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -69,6 +69,7 @@ struct CPUState { #ifdef _WIN32 HANDLE hThread; #endif + struct QemuCond *halt_cond; bool thread_kicked; bool created; bool stop; From c3586ba73fd4523a38c658f730cc38ec17b60491 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 01:41:24 +0200 Subject: [PATCH 074/291] cpus: Pass CPUState to qemu_tcg_cpu_thread_fn MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPUArchState is no longer needed except for iterating the CPUs. Needed for qemu_tcg_init_vcpu(). KVM and dummy threads still need CPUArchState for cpu_single_env. Signed-off-by: Andreas Färber --- cpus.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cpus.c b/cpus.c index 5a80bfa984..068fa12287 100644 --- a/cpus.c +++ b/cpus.c @@ -815,8 +815,8 @@ static void tcg_exec_all(void); static void *qemu_tcg_cpu_thread_fn(void *arg) { - CPUArchState *env = arg; - CPUState *cpu = ENV_GET_CPU(env); + CPUState *cpu = arg; + CPUArchState *env; qemu_tcg_init_cpu_signals(); qemu_thread_get_self(cpu->thread); @@ -1002,7 +1002,7 @@ static void qemu_tcg_init_vcpu(void *_env) cpu->halt_cond = g_malloc0(sizeof(QemuCond)); qemu_cond_init(cpu->halt_cond); tcg_halt_cond = cpu->halt_cond; - qemu_thread_create(cpu->thread, qemu_tcg_cpu_thread_fn, env, + qemu_thread_create(cpu->thread, qemu_tcg_cpu_thread_fn, cpu, QEMU_THREAD_JOINABLE); #ifdef _WIN32 cpu->hThread = qemu_thread_get_handle(cpu->thread); From e5ab30a2e6ee5f649af0639f93b6e8f6587e7ba1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 01:50:44 +0200 Subject: [PATCH 075/291] cpus: Pass CPUState to qemu_tcg_init_vcpu() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPUArchState is no longer needed. Signed-off-by: Andreas Färber --- cpus.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/cpus.c b/cpus.c index 068fa12287..5f915239ac 100644 --- a/cpus.c +++ b/cpus.c @@ -991,11 +991,8 @@ void resume_all_vcpus(void) } } -static void qemu_tcg_init_vcpu(void *_env) +static void qemu_tcg_init_vcpu(CPUState *cpu) { - CPUArchState *env = _env; - CPUState *cpu = ENV_GET_CPU(env); - /* share a single thread for all cpus with TCG */ if (!tcg_cpu_thread) { cpu->thread = g_malloc0(sizeof(QemuThread)); @@ -1056,7 +1053,7 @@ void qemu_init_vcpu(void *_env) if (kvm_enabled()) { qemu_kvm_start_vcpu(env); } else if (tcg_enabled()) { - qemu_tcg_init_vcpu(env); + qemu_tcg_init_vcpu(cpu); } else { qemu_dummy_start_vcpu(env); } From a096124571b71f02d49a97ca99f4bf7b97b6912a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 02:48:44 +0200 Subject: [PATCH 076/291] ppc: Pass PowerPCCPU to {ppc6xx,ppc970,power7,ppc40x,ppce500}_set_irq() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for changing qemu_cpu_kick() argument type to CPUState and for moving halted field into CPUState. Signed-off-by: Andreas Färber --- hw/ppc.c | 55 +++++++++++++++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 20 deletions(-) diff --git a/hw/ppc.c b/hw/ppc.c index 98546de991..ada100b1c5 100644 --- a/hw/ppc.c +++ b/hw/ppc.c @@ -75,9 +75,10 @@ void ppc_set_irq(CPUPPCState *env, int n_IRQ, int level) } /* PowerPC 6xx / 7xx internal IRQ controller */ -static void ppc6xx_set_irq (void *opaque, int pin, int level) +static void ppc6xx_set_irq(void *opaque, int pin, int level) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -151,17 +152,20 @@ static void ppc6xx_set_irq (void *opaque, int pin, int level) } } -void ppc6xx_irq_init (CPUPPCState *env) +void ppc6xx_irq_init(CPUPPCState *env) { - env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, env, + PowerPCCPU *cpu = ppc_env_get_cpu(env); + + env->irq_inputs = (void **)qemu_allocate_irqs(&ppc6xx_set_irq, cpu, PPC6xx_INPUT_NB); } #if defined(TARGET_PPC64) /* PowerPC 970 internal IRQ controller */ -static void ppc970_set_irq (void *opaque, int pin, int level) +static void ppc970_set_irq(void *opaque, int pin, int level) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -233,16 +237,19 @@ static void ppc970_set_irq (void *opaque, int pin, int level) } } -void ppc970_irq_init (CPUPPCState *env) +void ppc970_irq_init(CPUPPCState *env) { - env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, env, + PowerPCCPU *cpu = ppc_env_get_cpu(env); + + env->irq_inputs = (void **)qemu_allocate_irqs(&ppc970_set_irq, cpu, PPC970_INPUT_NB); } /* POWER7 internal IRQ controller */ -static void power7_set_irq (void *opaque, int pin, int level) +static void power7_set_irq(void *opaque, int pin, int level) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, env, pin, level); @@ -266,17 +273,20 @@ static void power7_set_irq (void *opaque, int pin, int level) } } -void ppcPOWER7_irq_init (CPUPPCState *env) +void ppcPOWER7_irq_init(CPUPPCState *env) { - env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, env, + PowerPCCPU *cpu = ppc_env_get_cpu(env); + + env->irq_inputs = (void **)qemu_allocate_irqs(&power7_set_irq, cpu, POWER7_INPUT_NB); } #endif /* defined(TARGET_PPC64) */ /* PowerPC 40x internal IRQ controller */ -static void ppc40x_set_irq (void *opaque, int pin, int level) +static void ppc40x_set_irq(void *opaque, int pin, int level) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -346,16 +356,19 @@ static void ppc40x_set_irq (void *opaque, int pin, int level) } } -void ppc40x_irq_init (CPUPPCState *env) +void ppc40x_irq_init(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + env->irq_inputs = (void **)qemu_allocate_irqs(&ppc40x_set_irq, - env, PPC40x_INPUT_NB); + cpu, PPC40x_INPUT_NB); } /* PowerPC E500 internal IRQ controller */ -static void ppce500_set_irq (void *opaque, int pin, int level) +static void ppce500_set_irq(void *opaque, int pin, int level) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; int cur_level; LOG_IRQ("%s: env %p pin %d level %d\n", __func__, @@ -407,10 +420,12 @@ static void ppce500_set_irq (void *opaque, int pin, int level) } } -void ppce500_irq_init (CPUPPCState *env) +void ppce500_irq_init(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); + env->irq_inputs = (void **)qemu_allocate_irqs(&ppce500_set_irq, - env, PPCE500_INPUT_NB); + cpu, PPCE500_INPUT_NB); } /*****************************************************************************/ /* PowerPC time base and decrementer emulation */ From d5a6814697014561dd0a2e2871df0e6c62a0ce59 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 04:02:03 +0200 Subject: [PATCH 077/291] target-ppc: Rename kvm_kick_{env => cpu} and pass PowerPCCPU MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for changing qemu_cpu_kick() argument type to CPUState. Signed-off-by: Andreas Färber --- target-ppc/kvm.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 5cbe98a164..d7d8e8fef0 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -73,8 +73,11 @@ static int cap_hior; */ static QEMUTimer *idle_timer; -static void kvm_kick_env(void *env) +static void kvm_kick_cpu(void *opaque) { + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; + qemu_cpu_kick(env); } @@ -375,6 +378,7 @@ static inline void kvm_fixup_page_sizes(CPUPPCState *env) int kvm_arch_init_vcpu(CPUPPCState *cenv) { + PowerPCCPU *cpu = ppc_env_get_cpu(cenv); int ret; /* Gather server mmu info from KVM and update the CPU state */ @@ -386,7 +390,7 @@ int kvm_arch_init_vcpu(CPUPPCState *cenv) return ret; } - idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_env, cenv); + idle_timer = qemu_new_timer_ns(vm_clock, kvm_kick_cpu, cpu); /* Some targets support access to KVM's guest TLB. */ switch (cenv->mmu_model) { From c08d7424d600dce915a5506e95d55a359c243c66 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 04:34:15 +0200 Subject: [PATCH 078/291] cpus: Pass CPUState to qemu_cpu_kick() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPUArchState is no longer needed there. Signed-off-by: Andreas Färber --- cpus.c | 13 +++++-------- exec.c | 2 +- hw/ppc.c | 4 ++-- hw/ppce500_spin.c | 2 +- hw/spapr_rtas.c | 5 ++++- hw/sun4m.c | 2 +- hw/sun4u.c | 2 +- include/qemu/cpu.h | 8 ++++++++ kvm-all.c | 2 +- qemu-common.h | 1 - target-ppc/kvm.c | 3 +-- target-s390x/kvm.c | 2 +- 12 files changed, 26 insertions(+), 20 deletions(-) diff --git a/cpus.c b/cpus.c index 5f915239ac..b802d38885 100644 --- a/cpus.c +++ b/cpus.c @@ -661,7 +661,7 @@ void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data) wi.next = NULL; wi.done = false; - qemu_cpu_kick(env); + qemu_cpu_kick(cpu); while (!wi.done) { CPUArchState *self_env = cpu_single_env; @@ -870,11 +870,8 @@ static void qemu_cpu_kick_thread(CPUState *cpu) #endif } -void qemu_cpu_kick(void *_env) +void qemu_cpu_kick(CPUState *cpu) { - CPUArchState *env = _env; - CPUState *cpu = ENV_GET_CPU(env); - qemu_cond_broadcast(cpu->halt_cond); if (!tcg_enabled() && !cpu->thread_kicked) { qemu_cpu_kick_thread(cpu); @@ -950,7 +947,7 @@ void pause_all_vcpus(void) while (penv) { CPUState *pcpu = ENV_GET_CPU(penv); pcpu->stop = true; - qemu_cpu_kick(penv); + qemu_cpu_kick(pcpu); penv = penv->next_cpu; } @@ -971,7 +968,7 @@ void pause_all_vcpus(void) qemu_cond_wait(&qemu_pause_cond, &qemu_global_mutex); penv = first_cpu; while (penv) { - qemu_cpu_kick(penv); + qemu_cpu_kick(ENV_GET_CPU(penv)); penv = penv->next_cpu; } } @@ -986,7 +983,7 @@ void resume_all_vcpus(void) CPUState *pcpu = ENV_GET_CPU(penv); pcpu->stop = false; pcpu->stopped = false; - qemu_cpu_kick(penv); + qemu_cpu_kick(pcpu); penv = penv->next_cpu; } } diff --git a/exec.c b/exec.c index a85a9b1fd2..038e40d09b 100644 --- a/exec.c +++ b/exec.c @@ -1704,7 +1704,7 @@ static void tcg_handle_interrupt(CPUArchState *env, int mask) * case its halted. */ if (!qemu_cpu_is_self(cpu)) { - qemu_cpu_kick(env); + qemu_cpu_kick(cpu); return; } diff --git a/hw/ppc.c b/hw/ppc.c index ada100b1c5..fa7ae74f0d 100644 --- a/hw/ppc.c +++ b/hw/ppc.c @@ -206,7 +206,7 @@ static void ppc970_set_irq(void *opaque, int pin, int level) } else { LOG_IRQ("%s: restart the CPU\n", __func__); env->halted = 0; - qemu_cpu_kick(env); + qemu_cpu_kick(CPU(cpu)); } break; case PPC970_INPUT_HRESET: @@ -335,7 +335,7 @@ static void ppc40x_set_irq(void *opaque, int pin, int level) } else { LOG_IRQ("%s: restart the CPU\n", __func__); env->halted = 0; - qemu_cpu_kick(env); + qemu_cpu_kick(CPU(cpu)); } break; case PPC40x_INPUT_DEBUG: diff --git a/hw/ppce500_spin.c b/hw/ppce500_spin.c index fb5461d588..7f8c8428b6 100644 --- a/hw/ppce500_spin.c +++ b/hw/ppce500_spin.c @@ -115,7 +115,7 @@ static void spin_kick(void *data) env->halted = 0; env->exception_index = -1; cpu->stopped = false; - qemu_cpu_kick(env); + qemu_cpu_kick(cpu); } static void spin_write(void *opaque, hwaddr addr, uint64_t value, diff --git a/hw/spapr_rtas.c b/hw/spapr_rtas.c index ce76c5856a..6d5c48a740 100644 --- a/hw/spapr_rtas.c +++ b/hw/spapr_rtas.c @@ -163,6 +163,7 @@ static void rtas_start_cpu(sPAPREnvironment *spapr, uint32_t nret, target_ulong rets) { target_ulong id, start, r3; + CPUState *cpu; CPUPPCState *env; if (nargs != 3 || nret != 1) { @@ -175,6 +176,8 @@ static void rtas_start_cpu(sPAPREnvironment *spapr, r3 = rtas_ld(args, 2); for (env = first_cpu; env; env = env->next_cpu) { + cpu = ENV_GET_CPU(env); + if (env->cpu_index != id) { continue; } @@ -194,7 +197,7 @@ static void rtas_start_cpu(sPAPREnvironment *spapr, env->gpr[3] = r3; env->halted = 0; - qemu_cpu_kick(env); + qemu_cpu_kick(cpu); rtas_st(rets, 0, 0); return; diff --git a/hw/sun4m.c b/hw/sun4m.c index 02673b228e..1a786762aa 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -259,7 +259,7 @@ static void cpu_kick_irq(SPARCCPU *cpu) env->halted = 0; cpu_check_irqs(env); - qemu_cpu_kick(env); + qemu_cpu_kick(CPU(cpu)); } static void cpu_set_irq(void *opaque, int irq, int level) diff --git a/hw/sun4u.c b/hw/sun4u.c index 162117129c..b2b51e30c2 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -317,7 +317,7 @@ static void cpu_kick_irq(SPARCCPU *cpu) env->halted = 0; cpu_check_irqs(env); - qemu_cpu_kick(env); + qemu_cpu_kick(CPU(cpu)); } static void cpu_set_ivec_irq(void *opaque, int irq, int level) diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index 75e0f8dc68..bfeb2245ab 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -95,6 +95,14 @@ void cpu_reset(CPUState *cpu); */ bool qemu_cpu_is_self(CPUState *cpu); +/** + * qemu_cpu_kick: + * @cpu: The vCPU to kick. + * + * Kicks @cpu's thread. + */ +void qemu_cpu_kick(CPUState *cpu); + /** * cpu_is_stopped: * @cpu: The CPU to check. diff --git a/kvm-all.c b/kvm-all.c index 74d2652f02..e41e1c9531 100644 --- a/kvm-all.c +++ b/kvm-all.c @@ -833,7 +833,7 @@ static void kvm_handle_interrupt(CPUArchState *env, int mask) env->interrupt_request |= mask; if (!qemu_cpu_is_self(cpu)) { - qemu_cpu_kick(env); + qemu_cpu_kick(cpu); } } diff --git a/qemu-common.h b/qemu-common.h index 2094742f2b..2011c00fe2 100644 --- a/qemu-common.h +++ b/qemu-common.h @@ -324,7 +324,6 @@ void cpu_save(QEMUFile *f, void *opaque); int cpu_load(QEMUFile *f, void *opaque, int version_id); /* Unblock cpu */ -void qemu_cpu_kick(void *env); void qemu_cpu_kick_self(void); /* work queue */ diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index d7d8e8fef0..6aacff0624 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -76,9 +76,8 @@ static QEMUTimer *idle_timer; static void kvm_kick_cpu(void *opaque) { PowerPCCPU *cpu = opaque; - CPUPPCState *env = &cpu->env; - qemu_cpu_kick(env); + qemu_cpu_kick(CPU(cpu)); } int kvm_arch_init(KVMState *s) diff --git a/target-s390x/kvm.c b/target-s390x/kvm.c index a66ac4341c..94de764264 100644 --- a/target-s390x/kvm.c +++ b/target-s390x/kvm.c @@ -403,7 +403,7 @@ static int s390_cpu_restart(S390CPU *cpu) kvm_s390_interrupt(env, KVM_S390_RESTART, 0); s390_add_running_cpu(env); - qemu_cpu_kick(env); + qemu_cpu_kick(CPU(cpu)); dprintf("DONE: SIGP cpu restart: %p\n", env); return 0; } From c64ca8140e9c21cd0d44c10fbe1247cb4ade8e6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 02:11:45 +0200 Subject: [PATCH 079/291] cpu: Move queued_work_{first,last} to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-defs.h | 1 - cpus.c | 19 ++++++++++--------- include/qemu/cpu.h | 1 + 3 files changed, 11 insertions(+), 10 deletions(-) diff --git a/cpu-defs.h b/cpu-defs.h index 76c76f6c62..b30a8e91bb 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -205,7 +205,6 @@ typedef struct CPUWatchpoint { /* user data */ \ void *opaque; \ \ - struct qemu_work_item *queued_work_first, *queued_work_last; \ const char *cpu_model_str; \ struct KVMState *kvm_state; \ struct kvm_run *kvm_run; \ diff --git a/cpus.c b/cpus.c index b802d38885..307c1f286c 100644 --- a/cpus.c +++ b/cpus.c @@ -66,7 +66,7 @@ static bool cpu_thread_is_idle(CPUArchState *env) { CPUState *cpu = ENV_GET_CPU(env); - if (cpu->stop || env->queued_work_first) { + if (cpu->stop || cpu->queued_work_first) { return false; } if (cpu->stopped || !runstate_is_running()) { @@ -652,12 +652,12 @@ void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data) wi.func = func; wi.data = data; - if (!env->queued_work_first) { - env->queued_work_first = &wi; + if (cpu->queued_work_first == NULL) { + cpu->queued_work_first = &wi; } else { - env->queued_work_last->next = &wi; + cpu->queued_work_last->next = &wi; } - env->queued_work_last = &wi; + cpu->queued_work_last = &wi; wi.next = NULL; wi.done = false; @@ -672,18 +672,19 @@ void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data) static void flush_queued_work(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); struct qemu_work_item *wi; - if (!env->queued_work_first) { + if (cpu->queued_work_first == NULL) { return; } - while ((wi = env->queued_work_first)) { - env->queued_work_first = wi->next; + while ((wi = cpu->queued_work_first)) { + cpu->queued_work_first = wi->next; wi->func(wi->data); wi->done = true; } - env->queued_work_last = NULL; + cpu->queued_work_last = NULL; qemu_cond_broadcast(&qemu_work_cond); } diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index bfeb2245ab..eea6175cb9 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -70,6 +70,7 @@ struct CPUState { HANDLE hThread; #endif struct QemuCond *halt_cond; + struct qemu_work_item *queued_work_first, *queued_work_last; bool thread_kicked; bool created; bool stop; From 6d45b109a6869084abd0f9aba01fa5107e926b60 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 02:13:22 +0200 Subject: [PATCH 080/291] cpus: Pass CPUState to flush_queued_work() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPUArchState is no longer needed there. Signed-off-by: Andreas Färber --- cpus.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/cpus.c b/cpus.c index 307c1f286c..e40823c6f1 100644 --- a/cpus.c +++ b/cpus.c @@ -670,9 +670,8 @@ void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data) } } -static void flush_queued_work(CPUArchState *env) +static void flush_queued_work(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); struct qemu_work_item *wi; if (cpu->queued_work_first == NULL) { @@ -697,7 +696,7 @@ static void qemu_wait_io_event_common(CPUArchState *env) cpu->stopped = true; qemu_cond_signal(&qemu_pause_cond); } - flush_queued_work(env); + flush_queued_work(cpu); cpu->thread_kicked = false; } From 509a0d78c7c3927b9ec8e176abef09ddd28ff0b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 02:18:09 +0200 Subject: [PATCH 081/291] cpus: Pass CPUState to qemu_wait_io_event_common() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPUArchState is no longer needed there. Signed-off-by: Andreas Färber --- cpus.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/cpus.c b/cpus.c index e40823c6f1..6baf2bcb35 100644 --- a/cpus.c +++ b/cpus.c @@ -687,10 +687,8 @@ static void flush_queued_work(CPUState *cpu) qemu_cond_broadcast(&qemu_work_cond); } -static void qemu_wait_io_event_common(CPUArchState *env) +static void qemu_wait_io_event_common(CPUState *cpu) { - CPUState *cpu = ENV_GET_CPU(env); - if (cpu->stop) { cpu->stop = false; cpu->stopped = true; @@ -716,7 +714,7 @@ static void qemu_tcg_wait_io_event(void) } for (env = first_cpu; env != NULL; env = env->next_cpu) { - qemu_wait_io_event_common(env); + qemu_wait_io_event_common(ENV_GET_CPU(env)); } } @@ -729,7 +727,7 @@ static void qemu_kvm_wait_io_event(CPUArchState *env) } qemu_kvm_eat_signals(env); - qemu_wait_io_event_common(env); + qemu_wait_io_event_common(cpu); } static void *qemu_kvm_cpu_thread_fn(void *arg) @@ -804,7 +802,7 @@ static void *qemu_dummy_cpu_thread_fn(void *arg) } qemu_mutex_lock_iothread(); cpu_single_env = env; - qemu_wait_io_event_common(env); + qemu_wait_io_event_common(cpu); } return NULL; @@ -836,7 +834,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg) /* process any pending work */ for (env = first_cpu; env != NULL; env = env->next_cpu) { - qemu_wait_io_event_common(env); + qemu_wait_io_event_common(ENV_GET_CPU(env)); } } From 79bbf20bcaf2ee5d8e3f93a5151d992fc9a5fd89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 06:41:02 +0200 Subject: [PATCH 082/291] xtensa_pic: Pass XtensaCPU to xtensa_ccompare_cb() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for changing cpu_has_work() argument type to CPUState. Signed-off-by: Andreas Färber Acked-by: Max Filippov --- hw/xtensa_pic.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/xtensa_pic.c b/hw/xtensa_pic.c index 653ded6820..8b9c0510f9 100644 --- a/hw/xtensa_pic.c +++ b/hw/xtensa_pic.c @@ -125,7 +125,8 @@ void xtensa_rearm_ccompare_timer(CPUXtensaState *env) static void xtensa_ccompare_cb(void *opaque) { - CPUXtensaState *env = opaque; + XtensaCPU *cpu = opaque; + CPUXtensaState *env = &cpu->env; if (env->halted) { env->halt_clock = qemu_get_clock_ns(vm_clock); @@ -139,12 +140,14 @@ static void xtensa_ccompare_cb(void *opaque) void xtensa_irq_init(CPUXtensaState *env) { + XtensaCPU *cpu = xtensa_env_get_cpu(env); + env->irq_inputs = (void **)qemu_allocate_irqs( xtensa_set_irq, env, env->config->ninterrupt); if (xtensa_option_enabled(env->config, XTENSA_OPTION_TIMER_INTERRUPT) && env->config->nccompare > 0) { env->ccompare_timer = - qemu_new_timer_ns(vm_clock, &xtensa_ccompare_cb, env); + qemu_new_timer_ns(vm_clock, &xtensa_ccompare_cb, cpu); } } From 5c26a5b3033fbbbfc033f7d8d0b50713c31517d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 05:55:58 +0200 Subject: [PATCH 083/291] target-ppc: Pass PowerPCCPU to powerpc_excp() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for changing cpu_ppc_hypercall() argument type to PowerPCCPU. Signed-off-by: Andreas Färber --- target-ppc/excp_helper.c | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 1a593f6f3f..d19a46b364 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -63,8 +63,9 @@ static inline void dump_syscall(CPUPPCState *env) /* Note that this function should be greatly optimized * when called with a constant excp, from ppc_hw_interrupt */ -static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) +static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) { + CPUPPCState *env = &cpu->env; target_ulong msr, new_msr, vector; int srr0, srr1, asrr0, asrr1; int lpes0, lpes1, lev; @@ -643,11 +644,14 @@ static inline void powerpc_excp(CPUPPCState *env, int excp_model, int excp) void do_interrupt(CPUPPCState *env) { - powerpc_excp(env, env->excp_model, env->exception_index); + PowerPCCPU *cpu = ppc_env_get_cpu(env); + + powerpc_excp(cpu, env->excp_model, env->exception_index); } void ppc_hw_interrupt(CPUPPCState *env) { + PowerPCCPU *cpu = ppc_env_get_cpu(env); int hdice; #if 0 @@ -658,20 +662,20 @@ void ppc_hw_interrupt(CPUPPCState *env) /* External reset */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_RESET)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_RESET); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_RESET); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_RESET); return; } /* Machine check exception */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_MCK)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_MCK); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_MCHECK); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_MCHECK); return; } #if 0 /* TODO */ /* External debug exception */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_DEBUG)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DEBUG); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_DEBUG); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DEBUG); return; } #endif @@ -685,7 +689,7 @@ void ppc_hw_interrupt(CPUPPCState *env) /* Hypervisor decrementer exception */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_HDECR); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_HDECR); return; } } @@ -698,7 +702,7 @@ void ppc_hw_interrupt(CPUPPCState *env) #if 0 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CEXT); #endif - powerpc_excp(env, env->excp_model, POWERPC_EXCP_CRITICAL); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_CRITICAL); return; } } @@ -706,30 +710,30 @@ void ppc_hw_interrupt(CPUPPCState *env) /* Watchdog timer on embedded PowerPC */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_WDT)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_WDT); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_WDT); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_WDT); return; } if (env->pending_interrupts & (1 << PPC_INTERRUPT_CDOORBELL)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_CDOORBELL); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORCI); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORCI); return; } /* Fixed interval timer on embedded PowerPC */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_FIT)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_FIT); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_FIT); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_FIT); return; } /* Programmable interval timer on embedded PowerPC */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_PIT)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PIT); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_PIT); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PIT); return; } /* Decrementer exception */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_DECR)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DECR); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_DECR); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DECR); return; } /* External interrupt */ @@ -740,23 +744,23 @@ void ppc_hw_interrupt(CPUPPCState *env) #if 0 env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EXT); #endif - powerpc_excp(env, env->excp_model, POWERPC_EXCP_EXTERNAL); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_EXTERNAL); return; } if (env->pending_interrupts & (1 << PPC_INTERRUPT_DOORBELL)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_DOORBELL); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_DOORI); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_DOORI); return; } if (env->pending_interrupts & (1 << PPC_INTERRUPT_PERFM)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_PERFM); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_PERFM); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_PERFM); return; } /* Thermal interrupt */ if (env->pending_interrupts & (1 << PPC_INTERRUPT_THERM)) { env->pending_interrupts &= ~(1 << PPC_INTERRUPT_THERM); - powerpc_excp(env, env->excp_model, POWERPC_EXCP_THERM); + powerpc_excp(cpu, env->excp_model, POWERPC_EXCP_THERM); return; } } From 1b14670a38a2265d3dd573b5e2d611621a5929f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 06:03:45 +0200 Subject: [PATCH 084/291] target-ppc: Pass PowerPCCPU to cpu_ppc_hypercall MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Adapt emulate_spapr_hypercall() accordingly. Needed for changing spapr_hypercall() argument type to PowerPCCPU. Signed-off-by: Andreas Färber --- hw/spapr.c | 4 +++- target-ppc/cpu.h | 2 +- target-ppc/excp_helper.c | 4 ++-- 3 files changed, 6 insertions(+), 4 deletions(-) diff --git a/hw/spapr.c b/hw/spapr.c index 8d0ad3cfe9..30707eecaf 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -576,8 +576,10 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR; } -static void emulate_spapr_hypercall(CPUPPCState *env) +static void emulate_spapr_hypercall(PowerPCCPU *cpu) { + CPUPPCState *env = &cpu->env; + if (msr_pr) { hcall_dprintf("Hypercall made with MSR[PR]=1\n"); env->gpr[3] = H_PRIVILEGE; diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 286f42a808..5574042a87 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2220,7 +2220,7 @@ static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) return msr & (1ULL << MSR_SF); } -extern void (*cpu_ppc_hypercall)(CPUPPCState *); +extern void (*cpu_ppc_hypercall)(PowerPCCPU *); static inline bool cpu_has_work(CPUPPCState *env) { diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index d19a46b364..5e34ad08a8 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -33,7 +33,7 @@ /*****************************************************************************/ /* PowerPC Hypercall emulation */ -void (*cpu_ppc_hypercall)(CPUPPCState *); +void (*cpu_ppc_hypercall)(PowerPCCPU *); /*****************************************************************************/ /* Exception processing */ @@ -239,7 +239,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int excp_model, int excp) dump_syscall(env); lev = env->error_code; if ((lev == 1) && cpu_ppc_hypercall) { - cpu_ppc_hypercall(env); + cpu_ppc_hypercall(cpu); return; } if (lev == 1 || (lpes0 == 0 && lpes1 == 0)) { From aa100fa4c9901c6a88d24f48d485dbe0147b317d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 06:13:14 +0200 Subject: [PATCH 085/291] spapr: Pass PowerPCCPU to spapr_hypercall() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for changing the hypercall handlers' argument type to PowerPCCPU. Signed-off-by: Andreas Färber --- hw/spapr.c | 2 +- hw/spapr.h | 2 +- hw/spapr_hcall.c | 4 +++- target-ppc/kvm.c | 3 ++- 4 files changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/spapr.c b/hw/spapr.c index 30707eecaf..ad3f0ea7fc 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -584,7 +584,7 @@ static void emulate_spapr_hypercall(PowerPCCPU *cpu) hcall_dprintf("Hypercall made with MSR[PR]=1\n"); env->gpr[3] = H_PRIVILEGE; } else { - env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]); + env->gpr[3] = spapr_hypercall(cpu, env->gpr[3], &env->gpr[4]); } } diff --git a/hw/spapr.h b/hw/spapr.h index 51c709ea10..f11028de9a 100644 --- a/hw/spapr.h +++ b/hw/spapr.h @@ -291,7 +291,7 @@ typedef target_ulong (*spapr_hcall_fn)(CPUPPCState *env, sPAPREnvironment *spapr target_ulong *args); void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn); -target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode, +target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, target_ulong *args); int spapr_allocate_irq(int hint, bool lsi); diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c index 621dabdfb1..b1e8704775 100644 --- a/hw/spapr_hcall.c +++ b/hw/spapr_hcall.c @@ -679,9 +679,11 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) *slot = fn; } -target_ulong spapr_hypercall(CPUPPCState *env, target_ulong opcode, +target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, target_ulong *args) { + CPUPPCState *env = &cpu->env; + if ((opcode <= MAX_HCALL_OPCODE) && ((opcode & 0x3) == 0)) { spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c index 6aacff0624..3f5df5772f 100644 --- a/target-ppc/kvm.c +++ b/target-ppc/kvm.c @@ -817,7 +817,8 @@ int kvm_arch_handle_exit(CPUPPCState *env, struct kvm_run *run) #ifdef CONFIG_PSERIES case KVM_EXIT_PAPR_HCALL: dprintf("handle PAPR hypercall\n"); - run->papr_hcall.ret = spapr_hypercall(env, run->papr_hcall.nr, + run->papr_hcall.ret = spapr_hypercall(ppc_env_get_cpu(env), + run->papr_hcall.nr, run->papr_hcall.args); ret = 0; break; From b13ce26d3e8c6682044ae84920f2417b30ce356b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 06:23:01 +0200 Subject: [PATCH 086/291] spapr: Pass PowerPCCPU to hypercalls MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for changing cpu_has_work() argument type to CPUState, used in h_cede(). Signed-off-by: Andreas Färber --- hw/spapr.h | 2 +- hw/spapr_hcall.c | 38 +++++++++++++++++++++----------------- hw/spapr_iommu.c | 2 +- hw/spapr_llan.c | 10 +++++----- hw/spapr_vio.c | 10 +++++----- hw/spapr_vty.c | 4 ++-- hw/xics.c | 11 +++++++---- 7 files changed, 42 insertions(+), 35 deletions(-) diff --git a/hw/spapr.h b/hw/spapr.h index f11028de9a..efe7f5758f 100644 --- a/hw/spapr.h +++ b/hw/spapr.h @@ -286,7 +286,7 @@ extern sPAPREnvironment *spapr; do { } while (0) #endif -typedef target_ulong (*spapr_hcall_fn)(CPUPPCState *env, sPAPREnvironment *spapr, +typedef target_ulong (*spapr_hcall_fn)(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args); diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c index b1e8704775..c6d55da7a6 100644 --- a/hw/spapr_hcall.c +++ b/hw/spapr_hcall.c @@ -75,9 +75,10 @@ static target_ulong compute_tlbie_rb(target_ulong v, target_ulong r, return rb; } -static target_ulong h_enter(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_enter(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { + CPUPPCState *env = &cpu->env; target_ulong flags = args[0]; target_ulong pte_index = args[1]; target_ulong pteh = args[2]; @@ -192,9 +193,10 @@ static target_ulong remove_hpte(CPUPPCState *env, target_ulong ptex, return REMOVE_SUCCESS; } -static target_ulong h_remove(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { + CPUPPCState *env = &cpu->env; target_ulong flags = args[0]; target_ulong pte_index = args[1]; target_ulong avpn = args[2]; @@ -238,9 +240,10 @@ static target_ulong h_remove(CPUPPCState *env, sPAPREnvironment *spapr, #define H_BULK_REMOVE_MAX_BATCH 4 -static target_ulong h_bulk_remove(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_bulk_remove(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { + CPUPPCState *env = &cpu->env; int i; for (i = 0; i < H_BULK_REMOVE_MAX_BATCH; i++) { @@ -284,9 +287,10 @@ static target_ulong h_bulk_remove(CPUPPCState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_protect(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_protect(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { + CPUPPCState *env = &cpu->env; target_ulong flags = args[0]; target_ulong pte_index = args[1]; target_ulong avpn = args[2]; @@ -321,7 +325,7 @@ static target_ulong h_protect(CPUPPCState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_set_dabr(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_set_dabr(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { /* FIXME: actually implement this */ @@ -457,7 +461,7 @@ static target_ulong deregister_dtl(CPUPPCState *env, target_ulong addr) return H_SUCCESS; } -static target_ulong h_register_vpa(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_register_vpa(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong flags = args[0]; @@ -505,9 +509,11 @@ static target_ulong h_register_vpa(CPUPPCState *env, sPAPREnvironment *spapr, return ret; } -static target_ulong h_cede(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { + CPUPPCState *env = &cpu->env; + env->msr |= (1ULL << MSR_EE); hreg_compute_hflags(env); if (!cpu_has_work(env)) { @@ -518,7 +524,7 @@ static target_ulong h_cede(CPUPPCState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_rtas(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_rtas(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong rtas_r3 = args[0]; @@ -530,7 +536,7 @@ static target_ulong h_rtas(CPUPPCState *env, sPAPREnvironment *spapr, nret, rtas_r3 + 12 + 4*nargs); } -static target_ulong h_logical_load(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_load(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong size = args[0]; @@ -553,7 +559,7 @@ static target_ulong h_logical_load(CPUPPCState *env, sPAPREnvironment *spapr, return H_PARAMETER; } -static target_ulong h_logical_store(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_store(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong size = args[0]; @@ -577,7 +583,7 @@ static target_ulong h_logical_store(CPUPPCState *env, sPAPREnvironment *spapr, return H_PARAMETER; } -static target_ulong h_logical_memop(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_memop(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong dst = args[0]; /* Destination address */ @@ -644,14 +650,14 @@ static target_ulong h_logical_memop(CPUPPCState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_logical_icbi(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_icbi(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { /* Nothing to do on emulation, KVM will trap this in the kernel */ return H_SUCCESS; } -static target_ulong h_logical_dcbf(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_logical_dcbf(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { /* Nothing to do on emulation, KVM will trap this in the kernel */ @@ -682,21 +688,19 @@ void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn) target_ulong spapr_hypercall(PowerPCCPU *cpu, target_ulong opcode, target_ulong *args) { - CPUPPCState *env = &cpu->env; - if ((opcode <= MAX_HCALL_OPCODE) && ((opcode & 0x3) == 0)) { spapr_hcall_fn fn = papr_hypercall_table[opcode / 4]; if (fn) { - return fn(env, spapr, opcode, args); + return fn(cpu, spapr, opcode, args); } } else if ((opcode >= KVMPPC_HCALL_BASE) && (opcode <= KVMPPC_HCALL_MAX)) { spapr_hcall_fn fn = kvmppc_hypercall_table[opcode - KVMPPC_HCALL_BASE]; if (fn) { - return fn(env, spapr, opcode, args); + return fn(cpu, spapr, opcode, args); } } diff --git a/hw/spapr_iommu.c b/hw/spapr_iommu.c index 86dc8f92e2..02d78ccf28 100644 --- a/hw/spapr_iommu.c +++ b/hw/spapr_iommu.c @@ -204,7 +204,7 @@ static target_ulong put_tce_emu(sPAPRTCETable *tcet, target_ulong ioba, return H_SUCCESS; } -static target_ulong h_put_tce(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_put_tce(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong liobn = args[0]; diff --git a/hw/spapr_llan.c b/hw/spapr_llan.c index bd3f131d7e..09ad69f6b5 100644 --- a/hw/spapr_llan.c +++ b/hw/spapr_llan.c @@ -264,7 +264,7 @@ static int check_bd(VIOsPAPRVLANDevice *dev, vlan_bd_t bd, return 0; } -static target_ulong h_register_logical_lan(CPUPPCState *env, +static target_ulong h_register_logical_lan(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) @@ -328,7 +328,7 @@ static target_ulong h_register_logical_lan(CPUPPCState *env, } -static target_ulong h_free_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_free_logical_lan(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -349,7 +349,7 @@ static target_ulong h_free_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr return H_SUCCESS; } -static target_ulong h_add_logical_lan_buffer(CPUPPCState *env, +static target_ulong h_add_logical_lan_buffer(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) @@ -398,7 +398,7 @@ static target_ulong h_add_logical_lan_buffer(CPUPPCState *env, return H_SUCCESS; } -static target_ulong h_send_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_send_logical_lan(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -467,7 +467,7 @@ static target_ulong h_send_logical_lan(CPUPPCState *env, sPAPREnvironment *spapr return H_SUCCESS; } -static target_ulong h_multicast_ctrl(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_multicast_ctrl(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; diff --git a/hw/spapr_vio.c b/hw/spapr_vio.c index 848806d3f1..1f19fedd0e 100644 --- a/hw/spapr_vio.c +++ b/hw/spapr_vio.c @@ -161,7 +161,7 @@ static int vio_make_devnode(VIOsPAPRDevice *dev, /* * CRQ handling */ -static target_ulong h_reg_crq(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_reg_crq(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -219,7 +219,7 @@ static target_ulong free_crq(VIOsPAPRDevice *dev) return H_SUCCESS; } -static target_ulong h_free_crq(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_free_crq(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -233,7 +233,7 @@ static target_ulong h_free_crq(CPUPPCState *env, sPAPREnvironment *spapr, return free_crq(dev); } -static target_ulong h_send_crq(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_send_crq(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -256,7 +256,7 @@ static target_ulong h_send_crq(CPUPPCState *env, sPAPREnvironment *spapr, return H_HARDWARE; } -static target_ulong h_enable_crq(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_enable_crq(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -463,7 +463,7 @@ static int spapr_vio_busdev_init(DeviceState *qdev) return pc->init(dev); } -static target_ulong h_vio_signal(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_vio_signal(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { diff --git a/hw/spapr_vty.c b/hw/spapr_vty.c index 5da17a3ff4..14f862fba1 100644 --- a/hw/spapr_vty.c +++ b/hw/spapr_vty.c @@ -70,7 +70,7 @@ static int spapr_vty_init(VIOsPAPRDevice *sdev) } /* Forward declaration */ -static target_ulong h_put_term_char(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_put_term_char(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; @@ -97,7 +97,7 @@ static target_ulong h_put_term_char(CPUPPCState *env, sPAPREnvironment *spapr, return H_SUCCESS; } -static target_ulong h_get_term_char(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_get_term_char(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong reg = args[0]; diff --git a/hw/xics.c b/hw/xics.c index ce88aa750b..91e4e6bbf5 100644 --- a/hw/xics.c +++ b/hw/xics.c @@ -342,16 +342,17 @@ void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi) icp->ics->irqs[irq - icp->ics->offset].lsi = lsi; } -static target_ulong h_cppr(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_cppr(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { + CPUPPCState *env = &cpu->env; target_ulong cppr = args[0]; icp_set_cppr(spapr->icp, env->cpu_index, cppr); return H_SUCCESS; } -static target_ulong h_ipi(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_ipi(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { target_ulong server = args[0]; @@ -366,18 +367,20 @@ static target_ulong h_ipi(CPUPPCState *env, sPAPREnvironment *spapr, } -static target_ulong h_xirr(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_xirr(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { + CPUPPCState *env = &cpu->env; uint32_t xirr = icp_accept(spapr->icp->ss + env->cpu_index); args[0] = xirr; return H_SUCCESS; } -static target_ulong h_eoi(CPUPPCState *env, sPAPREnvironment *spapr, +static target_ulong h_eoi(PowerPCCPU *cpu, sPAPREnvironment *spapr, target_ulong opcode, target_ulong *args) { + CPUPPCState *env = &cpu->env; target_ulong xirr = args[0]; icp_eoi(spapr->icp, env->cpu_index, xirr); From 7b46e5ce81d5107927685e7645b1bd39a1e1cd63 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:48:53 -0300 Subject: [PATCH 087/291] i386: kvm: kvm_arch_get_supported_cpuid: move R_EDX hack outside of for loop The for loop will become a separate function, so clean it up so it can become independent from the bit hacking for R_EDX. No behavior change[1], just code movement. [1] Well, only if the kernel returned CPUID leafs 1 or 0x80000001 as unsupported, but there's no kernel version that does that. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 31 ++++++++++++++++++------------- 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 3aa62b20ff..b7490f92d9 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -155,24 +155,29 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, break; case R_EDX: ret = cpuid->entries[i].edx; - switch (function) { - case 1: - /* KVM before 2.6.30 misreports the following features */ - ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; - break; - case 0x80000001: - /* On Intel, kvm returns cpuid according to the Intel spec, - * so add missing bits according to the AMD spec: - */ - cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); - ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; - break; - } break; } } } + /* Fixups for the data returned by KVM, below */ + + if (reg == R_EDX) { + switch (function) { + case 1: + /* KVM before 2.6.30 misreports the following features */ + ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; + break; + case 0x80000001: + /* On Intel, kvm returns cpuid according to the Intel spec, + * so add missing bits according to the AMD spec: + */ + cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); + ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; + break; + } + } + g_free(cpuid); /* fallback for older kernels */ From 8c723b7958127b8f204dd4b278ad3c8f6f48ae17 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:48:54 -0300 Subject: [PATCH 088/291] i386: kvm: kvm_arch_get_supported_cpuid: clean up has_kvm_features check Instead of a function-specific has_kvm_features variable, simply use a "found" variable that will be checked in case we have to use the legacy get_para_features() interface. No behavior change, just code cleanup. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index b7490f92d9..56addf1866 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -130,7 +130,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, int i, max; uint32_t ret = 0; uint32_t cpuid_1_edx; - int has_kvm_features = 0; + bool found = false; max = 1; while ((cpuid = try_get_cpuid(s, max)) == NULL) { @@ -140,9 +140,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, for (i = 0; i < cpuid->nent; ++i) { if (cpuid->entries[i].function == function && cpuid->entries[i].index == index) { - if (cpuid->entries[i].function == KVM_CPUID_FEATURES) { - has_kvm_features = 1; - } + found = true; switch (reg) { case R_EAX: ret = cpuid->entries[i].eax; @@ -181,7 +179,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, g_free(cpuid); /* fallback for older kernels */ - if (!has_kvm_features && (function == KVM_CPUID_FEATURES)) { + if ((function == KVM_CPUID_FEATURES) && !found) { ret = get_para_features(s); } From 47111e2cfa1a83a99ac10ed19c7c8b02be4fe973 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:48:55 -0300 Subject: [PATCH 089/291] i386: kvm: kvm_arch_get_supported_cpuid: use 'entry' variable The reg switch will be moved to a separate function, so store the entry pointer in a variable. No behavior change, just code movement. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 56addf1866..18782e49db 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -140,19 +140,20 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, for (i = 0; i < cpuid->nent; ++i) { if (cpuid->entries[i].function == function && cpuid->entries[i].index == index) { + struct kvm_cpuid_entry2 *entry = &cpuid->entries[i]; found = true; switch (reg) { case R_EAX: - ret = cpuid->entries[i].eax; + ret = entry->eax; break; case R_EBX: - ret = cpuid->entries[i].ebx; + ret = entry->ebx; break; case R_ECX: - ret = cpuid->entries[i].ecx; + ret = entry->ecx; break; case R_EDX: - ret = cpuid->entries[i].edx; + ret = entry->edx; break; } } From 829ae2f9fa37bf026de556f50d58ef14a7dab9b3 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:48:56 -0300 Subject: [PATCH 090/291] i386: kvm: extract register switch to cpuid_entry_get_reg() function No behavior change: just code movement. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 37 +++++++++++++++++++++++-------------- 1 file changed, 23 insertions(+), 14 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 18782e49db..695deb9f93 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -123,6 +123,28 @@ static int get_para_features(KVMState *s) } +/* Returns the value for a specific register on the cpuid entry + */ +static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) +{ + uint32_t ret = 0; + switch (reg) { + case R_EAX: + ret = entry->eax; + break; + case R_EBX: + ret = entry->ebx; + break; + case R_ECX: + ret = entry->ecx; + break; + case R_EDX: + ret = entry->edx; + break; + } + return ret; +} + uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, uint32_t index, int reg) { @@ -142,20 +164,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, cpuid->entries[i].index == index) { struct kvm_cpuid_entry2 *entry = &cpuid->entries[i]; found = true; - switch (reg) { - case R_EAX: - ret = entry->eax; - break; - case R_EBX: - ret = entry->ebx; - break; - case R_ECX: - ret = entry->ecx; - break; - case R_EDX: - ret = entry->edx; - break; - } + ret = cpuid_entry_get_reg(entry, reg); } } From 4fb73f1d3be285caeb52a58fa5eaea49bd918650 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:48:57 -0300 Subject: [PATCH 091/291] i386: kvm: extract CPUID entry lookup to cpuid_find_entry() function No behavior change, just code movement. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 695deb9f93..c94897f5d3 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -145,11 +145,28 @@ static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2 *entry, int reg) return ret; } +/* Find matching entry for function/index on kvm_cpuid2 struct + */ +static struct kvm_cpuid_entry2 *cpuid_find_entry(struct kvm_cpuid2 *cpuid, + uint32_t function, + uint32_t index) +{ + int i; + for (i = 0; i < cpuid->nent; ++i) { + if (cpuid->entries[i].function == function && + cpuid->entries[i].index == index) { + return &cpuid->entries[i]; + } + } + /* not found: */ + return NULL; +} + uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, uint32_t index, int reg) { struct kvm_cpuid2 *cpuid; - int i, max; + int max; uint32_t ret = 0; uint32_t cpuid_1_edx; bool found = false; @@ -159,13 +176,10 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, max *= 2; } - for (i = 0; i < cpuid->nent; ++i) { - if (cpuid->entries[i].function == function && - cpuid->entries[i].index == index) { - struct kvm_cpuid_entry2 *entry = &cpuid->entries[i]; - found = true; - ret = cpuid_entry_get_reg(entry, reg); - } + struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); + if (entry) { + found = true; + ret = cpuid_entry_get_reg(entry, reg); } /* Fixups for the data returned by KVM, below */ From dd87f8a690330777363f9a8680fce8f2ec544414 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:48:58 -0300 Subject: [PATCH 092/291] i386: kvm: extract try_get_cpuid() loop to get_supported_cpuid() function No behavior change, just code movement. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index c94897f5d3..d74dbc152c 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -98,6 +98,19 @@ static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max) return cpuid; } +/* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough + * for all entries. + */ +static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) +{ + struct kvm_cpuid2 *cpuid; + int max = 1; + while ((cpuid = try_get_cpuid(s, max)) == NULL) { + max *= 2; + } + return cpuid; +} + struct kvm_para_features { int cap; int feature; @@ -166,15 +179,11 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, uint32_t index, int reg) { struct kvm_cpuid2 *cpuid; - int max; uint32_t ret = 0; uint32_t cpuid_1_edx; bool found = false; - max = 1; - while ((cpuid = try_get_cpuid(s, max)) == NULL) { - max *= 2; - } + cpuid = get_supported_cpuid(s); struct kvm_cpuid_entry2 *entry = cpuid_find_entry(cpuid, function, index); if (entry) { From c2acb022c83fbaf7fdd7ab9538d44ae6e0e94f94 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:48:59 -0300 Subject: [PATCH 093/291] i386: kvm: kvm_arch_get_supported_cpuid: replace if+switch with single 'if' Additional fixups will be added, and making them a single 'if/else if' chain makes it clearer than two nested switch statements. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 23 +++++++++-------------- 1 file changed, 9 insertions(+), 14 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index d74dbc152c..1f943c5c5a 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -193,20 +193,15 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, /* Fixups for the data returned by KVM, below */ - if (reg == R_EDX) { - switch (function) { - case 1: - /* KVM before 2.6.30 misreports the following features */ - ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; - break; - case 0x80000001: - /* On Intel, kvm returns cpuid according to the Intel spec, - * so add missing bits according to the AMD spec: - */ - cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); - ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; - break; - } + if (function == 1 && reg == R_EDX) { + /* KVM before 2.6.30 misreports the following features */ + ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; + } else if (function == 0x80000001 && reg == R_EDX) { + /* On Intel, kvm returns cpuid according to the Intel spec, + * so add missing bits according to the AMD spec: + */ + cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); + ret |= cpuid_1_edx & CPUID_EXT2_AMD_ALIASES; } g_free(cpuid); From 84bd945cf298650096691509e7e9170036605e02 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:49:00 -0300 Subject: [PATCH 094/291] i386: kvm: set CPUID_EXT_HYPERVISOR on kvm_arch_get_supported_cpuid() Full grep for kvm_arch_get_supported_cpuid: kvm.h:uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function, target-i386/cpu.c: x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX); target-i386/cpu.c: *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); target-i386/cpu.c: *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); target-i386/cpu.c: *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); target-i386/cpu.c: *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); target-i386/cpu.c: *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX); target-i386/cpu.c: *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX); target-i386/cpu.c: *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX); target-i386/cpu.c: *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX); target-i386/kvm.c:uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, target-i386/kvm.c: cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); target-i386/kvm.c: env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); * target-i386/kvm.c: env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); target-i386/kvm.c: env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, target-i386/kvm.c: env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, target-i386/kvm.c: env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A, target-i386/kvm.c: kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); target-i386/kvm.c: kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX); Note that there is only one call for CPUID[1].ECX above (*), and it is the one that gets hacked to include CPUID_EXT_HYPERVISOR, so we can simply make kvm_arch_get_supported_cpuid() set it, to let the rest of the code automatically know that the flag can be safely set by QEMU. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 1f943c5c5a..aabac72a66 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -196,6 +196,11 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, if (function == 1 && reg == R_EDX) { /* KVM before 2.6.30 misreports the following features */ ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA; + } else if (function == 1 && reg == R_ECX) { + /* We can set the hypervisor flag, even if KVM does not return it on + * GET_SUPPORTED_CPUID + */ + ret |= CPUID_EXT_HYPERVISOR; } else if (function == 0x80000001 && reg == R_EDX) { /* On Intel, kvm returns cpuid according to the Intel spec, * so add missing bits according to the AMD spec: @@ -399,10 +404,8 @@ int kvm_arch_init_vcpu(CPUX86State *env) env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); - i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR; j = env->cpuid_ext_features & CPUID_EXT_TSC_DEADLINE_TIMER; env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); - env->cpuid_ext_features |= i; if (j && kvm_irqchip_in_kernel() && kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { env->cpuid_ext_features |= CPUID_EXT_TSC_DEADLINE_TIMER; From ac67ee260ae8e353314b6995ed5dccf1bb94fa9d Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:49:01 -0300 Subject: [PATCH 095/291] i386: kvm: set CPUID_EXT_TSC_DEADLINE_TIMER on kvm_arch_get_supported_cpuid() This moves the CPUID_EXT_TSC_DEADLINE_TIMER CPUID flag hacking from kvm_arch_init_vcpu() to kvm_arch_get_supported_cpuid(). Full git grep for kvm_arch_get_supported_cpuid: kvm.h:uint32_t kvm_arch_get_supported_cpuid(KVMState *env, uint32_t function, target-i386/cpu.c: x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX); target-i386/cpu.c: *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX); target-i386/cpu.c: *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX); target-i386/cpu.c: *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX); target-i386/cpu.c: *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX); target-i386/cpu.c: *eax = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EAX); target-i386/cpu.c: *ebx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EBX); target-i386/cpu.c: *ecx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_ECX); target-i386/cpu.c: *edx = kvm_arch_get_supported_cpuid(s, 0xd, count, R_EDX); target-i386/kvm.c:uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, target-i386/kvm.c: cpuid_1_edx = kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); target-i386/kvm.c: env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); * target-i386/kvm.c: env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); target-i386/kvm.c: env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, target-i386/kvm.c: env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, target-i386/kvm.c: env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A, target-i386/kvm.c: kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); target-i386/kvm.c: kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX); Note that there is only one call for CPUID[1].ECX above (*), and it is the one that gets hacked to include CPUID_EXT_TSC_DEADLINE_TIMER, so we can simply make kvm_arch_get_supported_cpuid() set it, to let the rest of the code know the flag can be safely set by QEMU. One thing I was worrying about when doing this is that now kvm_arch_get_supported_cpuid() depends on kvm_irqchip_in_kernel(). But the 'kvm_kernel_irqchip' global variable is initialized during kvm_init(), that is called very early, and kvm_init() is already a requirement to run the GET_SUPPORTED_CPUID ioctl() (as kvm_init() is the function that initializes the 'kvm_state' global variable). Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index aabac72a66..aae8af22dd 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -201,6 +201,14 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, * GET_SUPPORTED_CPUID */ ret |= CPUID_EXT_HYPERVISOR; + /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it + * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER, + * and the irqchip is in the kernel. + */ + if (kvm_irqchip_in_kernel() && + kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { + ret |= CPUID_EXT_TSC_DEADLINE_TIMER; + } } else if (function == 0x80000001 && reg == R_EDX) { /* On Intel, kvm returns cpuid according to the Intel spec, * so add missing bits according to the AMD spec: @@ -404,12 +412,7 @@ int kvm_arch_init_vcpu(CPUX86State *env) env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); - j = env->cpuid_ext_features & CPUID_EXT_TSC_DEADLINE_TIMER; env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); - if (j && kvm_irqchip_in_kernel() && - kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { - env->cpuid_ext_features |= CPUID_EXT_TSC_DEADLINE_TIMER; - } env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX); From 41e5e76db07b52591d9c9b88826278b8a5112258 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:49:02 -0300 Subject: [PATCH 096/291] i386: kvm: x2apic is not supported without in-kernel irqchip This is necessary so that x2apic is not improperly enabled when the in-kernel irqchip is disabled. This won't generate a warning with "-cpu ...,check" because the current check/enforce code is broken (it checks the host CPU data directly, instead of using kvm_arch_get_supported_cpuid()), but it will be eventually fixed to properly report the missing x2apic flag. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index aae8af22dd..4e96b046da 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -209,6 +209,13 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint32_t function, kvm_check_extension(s, KVM_CAP_TSC_DEADLINE_TIMER)) { ret |= CPUID_EXT_TSC_DEADLINE_TIMER; } + + /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled + * without the in-kernel irqchip + */ + if (!kvm_irqchip_in_kernel()) { + ret &= ~CPUID_EXT_X2APIC; + } } else if (function == 0x80000001 && reg == R_EDX) { /* On Intel, kvm returns cpuid according to the Intel spec, * so add missing bits according to the AMD spec: From ea85c9e45655c5e3a665a5295e5338b995e4a29c Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:49:03 -0300 Subject: [PATCH 097/291] i386: kvm: mask cpuid_kvm_features earlier Instead of masking the KVM feature bits very late (while building the KVM_SET_CPUID2 data), mask it out on env->cpuid_kvm_features, at the same point where the other feature words are masked out. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 4e96b046da..8eb61a02e7 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -428,6 +428,9 @@ int kvm_arch_init_vcpu(CPUX86State *env) env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX); + env->cpuid_kvm_features &= + kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); + cpuid_i = 0; /* Paravirtualization CPUIDs */ @@ -448,8 +451,7 @@ int kvm_arch_init_vcpu(CPUX86State *env) c = &cpuid_data.entries[cpuid_i++]; memset(c, 0, sizeof(*c)); c->function = KVM_CPUID_FEATURES; - c->eax = env->cpuid_kvm_features & - kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); + c->eax = env->cpuid_kvm_features; if (hyperv_enabled()) { memcpy(signature, "Hv#1\0\0\0\0\0\0\0\0", 12); From c9da8382c1432fbafb8705e7faecdf783c0b1821 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:49:04 -0300 Subject: [PATCH 098/291] i386: kvm: mask cpuid_ext4_features bits earlier This way all the filtering by GET_SUPPORTED_CPUID is being done at the same place in the code. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/kvm.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 8eb61a02e7..be37a1f7ba 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -431,6 +431,9 @@ int kvm_arch_init_vcpu(CPUX86State *env) env->cpuid_kvm_features &= kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); + env->cpuid_ext4_features &= kvm_arch_get_supported_cpuid(s, 0xC0000001, + 0, R_EDX); + cpuid_i = 0; /* Paravirtualization CPUIDs */ @@ -572,8 +575,6 @@ int kvm_arch_init_vcpu(CPUX86State *env) /* Call Centaur's CPUID instructions they are supported. */ if (env->cpuid_xlevel2 > 0) { - env->cpuid_ext4_features &= - kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX); cpu_x86_cpuid(env, 0xC0000000, 0, &limit, &unused, &unused, &unused); for (i = 0xC0000000; i <= limit; i++) { From bc74b7db86bc84d3e027ac7b536e8e39140d984f Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:49:05 -0300 Subject: [PATCH 099/291] i386: kvm: filter CPUID feature words earlier, on cpu.c cpu.c contains the code that will check if all requested CPU features are available, so the filtering of KVM features must be there, so we can implement "check" and "enforce" properly. The only point where kvm_arch_init_vcpu() is called on i386 is: - cpu_x86_init() - x86_cpu_realize() (after cpu_x86_register() is called) - qemu_init_vcpu() - qemu_kvm_start_vcpu() - qemu_kvm_thread_fn() (on a new thread) - kvm_init_vcpu() - kvm_arch_init_vcpu() With this patch, the filtering will be done earlier, at: - cpu_x86_init() - cpu_x86_register() (before x86_cpu_realize() is called) Also, the KVM CPUID filtering will now be done at the same place where the TCG CPUID feature filtering is done. Later, the code can be changed to use the same filtering code for the "check" and "enforce" modes, as now the cpu.c code knows exactly which CPU features are going to be exposed to the guest (and much earlier). One thing I was worrying about when doing this is that kvm_arch_get_supported_cpuid() depends on kvm_irqchip_in_kernel(), and maybe the 'kvm_kernel_irqchip' global variable wasn't initialized yet at CPU creation time. But kvm_kernel_irqchip is initialized during kvm_init(), that is called very early (much earlier than the machine init function), and kvm_init() is already a requirement to run the GET_SUPPORTED_CPUID ioctl() (as kvm_init() initializes the kvm_state global variable). Side note: it would be nice to keep KVM-specific code inside kvm.c. The problem is that properly implementing -cpu check/enforce code (that's inside cpu.c) depends directly on the feature bit filtering done using kvm_arch_get_supported_cpuid(). Currently -cpu check/enforce is broken because it simply uses the host CPU feature bits instead of GET_SUPPORTED_CPUID, and we need to fix that. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- kvm.h | 1 + target-i386/cpu.c | 30 ++++++++++++++++++++++++++++++ target-i386/kvm.c | 18 ------------------ 3 files changed, 31 insertions(+), 18 deletions(-) diff --git a/kvm.h b/kvm.h index 2b26dcb9bb..1e7f244561 100644 --- a/kvm.h +++ b/kvm.h @@ -20,6 +20,7 @@ #ifdef CONFIG_KVM #include +#include #endif extern int kvm_allowed; diff --git a/target-i386/cpu.c b/target-i386/cpu.c index d4f2e65cd9..78876f632b 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1368,6 +1368,32 @@ CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp) return cpu_list; } +#ifdef CONFIG_KVM +static void filter_features_for_kvm(X86CPU *cpu) +{ + CPUX86State *env = &cpu->env; + KVMState *s = kvm_state; + + env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); + + env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); + + env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, + 0, R_EDX); + env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, + 0, R_ECX); + env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A, + 0, R_EDX); + + env->cpuid_kvm_features &= + kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); + + env->cpuid_ext4_features &= kvm_arch_get_supported_cpuid(s, 0xC0000001, + 0, R_EDX); + +} +#endif + int cpu_x86_register(X86CPU *cpu, const char *cpu_model) { CPUX86State *env = &cpu->env; @@ -1425,6 +1451,10 @@ int cpu_x86_register(X86CPU *cpu, const char *cpu_model) ); env->cpuid_ext3_features &= TCG_EXT3_FEATURES; env->cpuid_svm_features &= TCG_SVM_FEATURES; + } else { +#ifdef CONFIG_KVM + filter_features_for_kvm(cpu); +#endif } object_property_set_str(OBJECT(cpu), def->model_id, "model-id", &error); if (error_is_set(&error)) { diff --git a/target-i386/kvm.c b/target-i386/kvm.c index be37a1f7ba..593e9d3e0f 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -410,30 +410,12 @@ int kvm_arch_init_vcpu(CPUX86State *env) struct kvm_cpuid2 cpuid; struct kvm_cpuid_entry2 entries[100]; } QEMU_PACKED cpuid_data; - KVMState *s = env->kvm_state; uint32_t limit, i, j, cpuid_i; uint32_t unused; struct kvm_cpuid_entry2 *c; uint32_t signature[3]; int r; - env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); - - env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); - - env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, - 0, R_EDX); - env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, - 0, R_ECX); - env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A, - 0, R_EDX); - - env->cpuid_kvm_features &= - kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); - - env->cpuid_ext4_features &= kvm_arch_get_supported_cpuid(s, 0xC0000001, - 0, R_EDX); - cpuid_i = 0; /* Paravirtualization CPUIDs */ From b8091f245d36da604219db42552cc28400698446 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:49:06 -0300 Subject: [PATCH 100/291] i386: kvm: reformat filter_features_for_kvm() code Cosmetic, but it will also help to make futher patches easier to review. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/cpu.c | 28 +++++++++++++--------------- 1 file changed, 13 insertions(+), 15 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 78876f632b..be16898e37 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1374,22 +1374,20 @@ static void filter_features_for_kvm(X86CPU *cpu) CPUX86State *env = &cpu->env; KVMState *s = kvm_state; - env->cpuid_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); - - env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); - - env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, - 0, R_EDX); - env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(s, 0x80000001, - 0, R_ECX); - env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A, - 0, R_EDX); - + env->cpuid_features &= + kvm_arch_get_supported_cpuid(s, 1, 0, R_EDX); + env->cpuid_ext_features &= + kvm_arch_get_supported_cpuid(s, 1, 0, R_ECX); + env->cpuid_ext2_features &= + kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX); + env->cpuid_ext3_features &= + kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX); + env->cpuid_svm_features &= + kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX); env->cpuid_kvm_features &= - kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); - - env->cpuid_ext4_features &= kvm_arch_get_supported_cpuid(s, 0xC0000001, - 0, R_EDX); + kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); + env->cpuid_ext4_features &= + kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX); } #endif From ffa8c11f0bbf47e1b7a3a62f97bc1da591c6734a Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Oct 2012 17:49:07 -0300 Subject: [PATCH 101/291] i386: kvm: filter CPUID leaf 7 based on GET_SUPPORTED_CPUID, too Now that CPUID leaf 7 features can be enabled/disabled on the command-line, we need to filter them properly using GET_SUPPORTED_CPUID, at the same place where other features are filtered out. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index be16898e37..22d91ed074 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1384,6 +1384,8 @@ static void filter_features_for_kvm(X86CPU *cpu) kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX); env->cpuid_svm_features &= kvm_arch_get_supported_cpuid(s, 0x8000000A, 0, R_EDX); + env->cpuid_7_0_ebx_features &= + kvm_arch_get_supported_cpuid(s, 7, 0, R_EBX); env->cpuid_kvm_features &= kvm_arch_get_supported_cpuid(s, KVM_CPUID_FEATURES, 0, R_EAX); env->cpuid_ext4_features &= From 811a8ae09e179d0a4d8cde13ba9f72e7c782c9ff Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Tue, 9 Oct 2012 11:03:59 -0300 Subject: [PATCH 102/291] i386: cpu: add missing CPUID[EAX=7,ECX=0] flag names This makes QEMU recognize the following CPU flag names: Flags | Corresponding KVM kernel commit -----------------+---------------------------------------- FSGSBASE | 176f61da82435eae09cc96f70b530d1ba0746b8b AVX2, BMI1, BMI2 | fb215366b3c7320ac25dca766a0152df16534932 HLE, RTM | 83c529151ab0d4a813e3f6a3e293fff75d468519 INVPCID | ad756a1603c5fac207758faaac7f01c34c9d0b7b ERMS | a01c8f9b4e266df1d7166d23216f2060648f862d Reviewed-by: Don Slutz Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/cpu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 22d91ed074..7c726fc0b1 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -106,8 +106,8 @@ static const char *svm_feature_name[] = { }; static const char *cpuid_7_0_ebx_feature_name[] = { - NULL, NULL, NULL, NULL, NULL, NULL, NULL, "smep", - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep", + "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "smap", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, }; From c3d3980794124508e0bd4eaa406d7fa0e832a221 Mon Sep 17 00:00:00 2001 From: Don Slutz Date: Fri, 12 Oct 2012 15:43:23 -0400 Subject: [PATCH 103/291] target-i386: Add missing kvm cpuid feature name Currently "-cpu host,-kvmclock,-kvm_nopiodelay,-kvm_mmu" does not turn off all bits in CPUID 0x40000001 EAX. The missing ones is KVM_FEATURE_STEAL_TIME. This adds the name kvm_steal_time. Signed-off-by: Don Slutz Signed-off-by: Marcelo Tosatti --- target-i386/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 7c726fc0b1..4417d6abed 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -88,10 +88,14 @@ static const char *ext3_feature_name[] = { }; static const char *kvm_feature_name[] = { - "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL, "kvm_pv_eoi", NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, - NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", + "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, }; static const char *svm_feature_name[] = { From 19403a68fb8eaefb2e1245b6a8384d3a3ffa7ca0 Mon Sep 17 00:00:00 2001 From: Marcelo Tosatti Date: Fri, 5 Oct 2012 14:51:39 -0300 Subject: [PATCH 104/291] cirrus_vga: allow configurable vram size Allow RAM size to be configurable for cirrus, to allow migration compatibility from qemu-kvm. Acked-by: Gerd Hoffmann Signed-off-by: Marcelo Tosatti --- hw/cirrus_vga.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c index e4af2e9ded..9bef96e6d7 100644 --- a/hw/cirrus_vga.c +++ b/hw/cirrus_vga.c @@ -42,8 +42,6 @@ //#define DEBUG_CIRRUS //#define DEBUG_BITBLT -#define VGA_RAM_SIZE (8192 * 1024) - /*************************************** * * definitions @@ -2856,7 +2854,8 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci, /* I/O handler for LFB */ memory_region_init_io(&s->cirrus_linear_io, &cirrus_linear_io_ops, s, - "cirrus-linear-io", VGA_RAM_SIZE); + "cirrus-linear-io", s->vga.vram_size_mb + * 1024 * 1024); memory_region_set_flush_coalesced(&s->cirrus_linear_io); /* I/O handler for LFB */ @@ -2899,7 +2898,6 @@ static int vga_initfn(ISADevice *dev) ISACirrusVGAState *d = DO_UPCAST(ISACirrusVGAState, dev, dev); VGACommonState *s = &d->cirrus_vga.vga; - s->vram_size_mb = VGA_RAM_SIZE >> 20; vga_common_init(s); cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0, isa_address_space(dev)); @@ -2912,6 +2910,12 @@ static int vga_initfn(ISADevice *dev) return 0; } +static Property isa_vga_cirrus_properties[] = { + DEFINE_PROP_UINT32("vgamem_mb", struct ISACirrusVGAState, + cirrus_vga.vga.vram_size_mb, 8), + DEFINE_PROP_END_OF_LIST(), +}; + static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data) { ISADeviceClass *k = ISA_DEVICE_CLASS(klass); @@ -2919,6 +2923,7 @@ static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data) dc->vmsd = &vmstate_cirrus_vga; k->init = vga_initfn; + dc->props = isa_vga_cirrus_properties; } static TypeInfo isa_cirrus_vga_info = { @@ -2942,7 +2947,6 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev) int16_t device_id = pc->device_id; /* setup VGA */ - s->vga.vram_size_mb = VGA_RAM_SIZE >> 20; vga_common_init(&s->vga); cirrus_init_common(s, device_id, 1, pci_address_space(dev)); s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate, @@ -2969,6 +2973,12 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev) return 0; } +static Property pci_vga_cirrus_properties[] = { + DEFINE_PROP_UINT32("vgamem_mb", struct PCICirrusVGAState, + cirrus_vga.vga.vram_size_mb, 8), + DEFINE_PROP_END_OF_LIST(), +}; + static void cirrus_vga_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); @@ -2982,6 +2992,7 @@ static void cirrus_vga_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_DISPLAY_VGA; dc->desc = "Cirrus CLGD 54xx VGA"; dc->vmsd = &vmstate_pci_cirrus_vga; + dc->props = pci_vga_cirrus_properties; } static TypeInfo cirrus_vga_info = { From e43d594ee55038442d59d301eb34fdf0c378d3a4 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Fri, 5 Oct 2012 14:51:40 -0300 Subject: [PATCH 105/291] Use machine options to emulate -no-kvm-irqchip Releases of qemu-kvm will be interrupted at qemu 1.3.0. Users should switch to plain qemu releases. To avoid breaking scenarios which are setup with command line options specific to qemu-kvm, port these switches from qemu-kvm to qemu.git. Port -no-kvm-irqchip option. Signed-off-by: Marcelo Tosatti --- qemu-options.hx | 3 +++ vl.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index a67a2551e5..d813755ccb 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -2888,6 +2888,9 @@ STEXI Enable FIPS 140-2 compliance mode. ETEXI +HXCOMM Deprecated by -machine kernel_irqchip=on|off property +DEF("no-kvm-irqchip", HAS_ARG, QEMU_OPTION_no_kvm_irqchip, "", QEMU_ARCH_I386) + HXCOMM This is the last statement. Insert new options before this line! STEXI @end table diff --git a/vl.c b/vl.c index 5a3d316980..7d0708afcd 100644 --- a/vl.c +++ b/vl.c @@ -2574,6 +2574,11 @@ int main(int argc, char **argv, char **envp) case QEMU_OPTION_M: machine = machine_parse(optarg); break; + case QEMU_OPTION_no_kvm_irqchip: { + olist = qemu_find_opts("machine"); + qemu_opts_parse(olist, "kernel_irqchip=off", 0); + break; + } case QEMU_OPTION_cpu: /* hw initialization will check this */ cpu_model = optarg; From 4086bde8c08746913d7ca6dcbc5e18a49a627cdc Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Fri, 5 Oct 2012 14:51:41 -0300 Subject: [PATCH 106/291] Issue warning when deprecated -no-kvm-pit is used Releases of qemu-kvm will be interrupted at qemu 1.3.0. Users should switch to plain qemu releases. To avoid breaking scenarios which are setup with command line options specific to qemu-kvm, port these switches from qemu-kvm to qemu.git. Port -no-kvm-pit option. Signed-off-by: Marcelo Tosatti --- qemu-options.hx | 3 +++ vl.c | 5 +++++ 2 files changed, 8 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index d813755ccb..42e642c65b 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -2888,6 +2888,9 @@ STEXI Enable FIPS 140-2 compliance mode. ETEXI +HXCOMM Deprecated (ignored) +DEF("no-kvm-pit", HAS_ARG, QEMU_OPTION_no_kvm_pit, "", QEMU_ARCH_I386) + HXCOMM Deprecated by -machine kernel_irqchip=on|off property DEF("no-kvm-irqchip", HAS_ARG, QEMU_OPTION_no_kvm_irqchip, "", QEMU_ARCH_I386) diff --git a/vl.c b/vl.c index 7d0708afcd..37717b4559 100644 --- a/vl.c +++ b/vl.c @@ -3171,6 +3171,11 @@ int main(int argc, char **argv, char **envp) machine = machine_parse(optarg); } break; + case QEMU_OPTION_no_kvm_pit: { + fprintf(stderr, "Warning: KVM PIT can no longer be disabled " + "separately.\n"); + break; + } case QEMU_OPTION_usb: machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); if (machine_opts) { From c21fb4f8b802108697f9353a8f807079507b586c Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Fri, 5 Oct 2012 14:51:42 -0300 Subject: [PATCH 107/291] Use global properties to emulate -no-kvm-pit-reinjection Releases of qemu-kvm will be interrupted at qemu 1.3.0. Users should switch to plain qemu releases. To avoid breaking scenarios which are setup with command line options specific to qemu-kvm, port these switches from qemu-kvm to qemu.git. Port -no-kvm-pit-reinjection. Signed-off-by: Marcelo Tosatti --- qemu-options.hx | 4 ++++ vl.c | 15 +++++++++++++++ 2 files changed, 19 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index 42e642c65b..4403c9c718 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -2888,6 +2888,10 @@ STEXI Enable FIPS 140-2 compliance mode. ETEXI +HXCOMM Deprecated by kvm-pit driver properties +DEF("no-kvm-pit-reinjection", HAS_ARG, QEMU_OPTION_no_kvm_pit_reinjection, + "", QEMU_ARCH_I386) + HXCOMM Deprecated (ignored) DEF("no-kvm-pit", HAS_ARG, QEMU_OPTION_no_kvm_pit, "", QEMU_ARCH_I386) diff --git a/vl.c b/vl.c index 37717b4559..3068b4bc59 100644 --- a/vl.c +++ b/vl.c @@ -3176,6 +3176,21 @@ int main(int argc, char **argv, char **envp) "separately.\n"); break; } + case QEMU_OPTION_no_kvm_pit_reinjection: { + static GlobalProperty kvm_pit_lost_tick_policy[] = { + { + .driver = "kvm-pit", + .property = "lost_tick_policy", + .value = "discard", + }, + { /* end of list */ } + }; + + fprintf(stderr, "Warning: option deprecated, use " + "lost_tick_policy property of kvm-pit instead.\n"); + qdev_prop_register_global_list(kvm_pit_lost_tick_policy); + break; + } case QEMU_OPTION_usb: machine_opts = qemu_opts_find(qemu_find_opts("machine"), 0); if (machine_opts) { From 0d92d17a6d0d65af8cb905bdd5f9e04e210564ff Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Fri, 5 Oct 2012 14:51:43 -0300 Subject: [PATCH 108/291] Issue warning when deprecated drive parameter boot=on|off is used Releases of qemu-kvm will be interrupted at qemu 1.3.0. Users should switch to plain qemu releases. To avoid breaking scenarios which are setup with command line options specific to qemu-kvm, port these switches from qemu-kvm to qemu.git. Port drive boot option. From the qemu-kvm original commit message: We do not want to maintain this option forever. It will be removed after a grace period of a few releases. So warn the user that this option has no effect and will become invalid soon. Signed-off-by: Marcelo Tosatti --- blockdev.c | 6 ++++++ qemu-config.c | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/blockdev.c b/blockdev.c index a068a4b669..e73fd6e388 100644 --- a/blockdev.c +++ b/blockdev.c @@ -433,6 +433,12 @@ DriveInfo *drive_init(QemuOpts *opts, int default_to_scsi) return NULL; } + if (qemu_opt_get(opts, "boot") != NULL) { + fprintf(stderr, "qemu-kvm: boot=on|off is deprecated and will be " + "ignored. Future versions will reject this parameter. Please " + "update your scripts.\n"); + } + on_write_error = BLOCKDEV_ON_ERROR_ENOSPC; if ((buf = qemu_opt_get(opts, "werror")) != NULL) { if (type != IF_IDE && type != IF_SCSI && type != IF_VIRTIO && type != IF_NONE) { diff --git a/qemu-config.c b/qemu-config.c index e854fffe19..3154cac10f 100644 --- a/qemu-config.c +++ b/qemu-config.c @@ -114,6 +114,10 @@ static QemuOptsList qemu_drive_opts = { .name = "copy-on-read", .type = QEMU_OPT_BOOL, .help = "copy read data from backing file into image file", + },{ + .name = "boot", + .type = QEMU_OPT_BOOL, + .help = "(deprecated, ignored)", }, { /* end of list */ } }, From 88eed34a6b3eba46397de5aaf24ed66ea290794b Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Fri, 5 Oct 2012 14:51:44 -0300 Subject: [PATCH 109/291] Issue warning when deprecated -tdf option is used Releases of qemu-kvm will be interrupted at qemu 1.3.0. Users should switch to plain qemu releases. To avoid breaking scenarios which are setup with command line options specific to qemu-kvm, port these switches from qemu-kvm to qemu.git. Port -tdf option. Signed-off-by: Marcelo Tosatti --- qemu-options.hx | 3 +++ vl.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index 4403c9c718..628bd44591 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -2898,6 +2898,9 @@ DEF("no-kvm-pit", HAS_ARG, QEMU_OPTION_no_kvm_pit, "", QEMU_ARCH_I386) HXCOMM Deprecated by -machine kernel_irqchip=on|off property DEF("no-kvm-irqchip", HAS_ARG, QEMU_OPTION_no_kvm_irqchip, "", QEMU_ARCH_I386) +HXCOMM Deprecated (ignored) +DEF("tdf", 0, QEMU_OPTION_tdf,"", QEMU_ARCH_ALL) + HXCOMM This is the last statement. Insert new options before this line! STEXI @end table diff --git a/vl.c b/vl.c index 3068b4bc59..cd7c0fbd52 100644 --- a/vl.c +++ b/vl.c @@ -3280,6 +3280,10 @@ int main(int argc, char **argv, char **envp) case QEMU_OPTION_semihosting: semihosting_enabled = 1; break; + case QEMU_OPTION_tdf: + fprintf(stderr, "Warning: user space PIT time drift fix " + "is no longer supported.\n"); + break; case QEMU_OPTION_name: qemu_name = g_strdup(optarg); { From a0dac021fa4b8b87160192c1f60ee26fc6c5ce2e Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Fri, 5 Oct 2012 14:51:45 -0300 Subject: [PATCH 110/291] Emulate qemu-kvms -no-kvm option Releases of qemu-kvm will be interrupted at qemu 1.3.0. Users should switch to plain qemu releases. To avoid breaking scenarios which are setup with command line options specific to qemu-kvm, port these switches from qemu-kvm to qemu.git. Port -no-kvm option. Signed-off-by: Marcelo Tosatti --- qemu-options.hx | 3 +++ vl.c | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/qemu-options.hx b/qemu-options.hx index 628bd44591..fe8f15c541 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -2888,6 +2888,9 @@ STEXI Enable FIPS 140-2 compliance mode. ETEXI +HXCOMM Deprecated by -machine accel=tcg property +DEF("no-kvm", HAS_ARG, QEMU_OPTION_no_kvm, "", QEMU_ARCH_I386) + HXCOMM Deprecated by kvm-pit driver properties DEF("no-kvm-pit-reinjection", HAS_ARG, QEMU_OPTION_no_kvm_pit_reinjection, "", QEMU_ARCH_I386) diff --git a/vl.c b/vl.c index cd7c0fbd52..b39f22ed35 100644 --- a/vl.c +++ b/vl.c @@ -3171,6 +3171,10 @@ int main(int argc, char **argv, char **envp) machine = machine_parse(optarg); } break; + case QEMU_OPTION_no_kvm: + olist = qemu_find_opts("machine"); + qemu_opts_parse(olist, "accel=tcg", 0); + break; case QEMU_OPTION_no_kvm_pit: { fprintf(stderr, "Warning: KVM PIT can no longer be disabled " "separately.\n"); From 1aefc6b8cbe66e5adb3e6b160f6790171e0a7785 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Wed, 24 Oct 2012 19:44:05 -0200 Subject: [PATCH 111/291] target-i386: make cpu_x86_fill_host() void The return value of that function is always 0, and is always ignored. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/cpu.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 4417d6abed..6575834885 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -766,7 +766,7 @@ static int cpu_x86_fill_model_id(char *str) return 0; } -static int cpu_x86_fill_host(x86_def_t *x86_cpu_def) +static void cpu_x86_fill_host(x86_def_t *x86_cpu_def) { uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; @@ -819,8 +819,6 @@ static int cpu_x86_fill_host(x86_def_t *x86_cpu_def) * unsupported ones later. */ x86_cpu_def->svm_features = -1; - - return 0; } static int unavailable_host_feature(struct model_features_t *f, uint32_t mask) From 6e746f30558cb1331598575918c2a8808be2a75b Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Wed, 24 Oct 2012 19:44:06 -0200 Subject: [PATCH 112/291] target-i386: cpu: make -cpu host/check/enforce code KVM-specific Rationale: * "-cpu host" is available only when using KVM * The current implementation of -cpu check/enforce (check_features_against_host()) makes sense only when using KVM. So this makes the functions check_features_against_host() and cpu_x86_fill_host() KVM-specific, document them as such, and rename them to kvm_check_features_against_host() and kvm_cpu_fill_host(). Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/cpu.c | 25 ++++++++++++++++++------- 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 6575834885..390ed4771d 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -766,10 +766,17 @@ static int cpu_x86_fill_model_id(char *str) return 0; } -static void cpu_x86_fill_host(x86_def_t *x86_cpu_def) +/* Fill a x86_def_t struct with information about the host CPU, and + * the CPU features supported by the host hardware + host kernel + * + * This function may be called only if KVM is enabled. + */ +static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def) { uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; + assert(kvm_enabled()); + x86_cpu_def->name = "host"; host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); x86_cpu_def->level = eax; @@ -784,7 +791,7 @@ static void cpu_x86_fill_host(x86_def_t *x86_cpu_def) x86_cpu_def->ext_features = ecx; x86_cpu_def->features = edx; - if (kvm_enabled() && x86_cpu_def->level >= 7) { + if (x86_cpu_def->level >= 7) { x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX); } else { x86_cpu_def->cpuid_7_0_ebx_features = 0; @@ -839,8 +846,10 @@ static int unavailable_host_feature(struct model_features_t *f, uint32_t mask) /* best effort attempt to inform user requested cpu flags aren't making * their way to the guest. Note: ft[].check_feat ideally should be * specified via a guest_def field to suppress report of extraneous flags. + * + * This function may be called only if KVM is enabled. */ -static int check_features_against_host(x86_def_t *guest_def) +static int kvm_check_features_against_host(x86_def_t *guest_def) { x86_def_t host_def; uint32_t mask; @@ -855,7 +864,9 @@ static int check_features_against_host(x86_def_t *guest_def) {&guest_def->ext3_features, &host_def.ext3_features, ~CPUID_EXT3_SVM, ext3_feature_name, 0x80000001}}; - cpu_x86_fill_host(&host_def); + assert(kvm_enabled()); + + kvm_cpu_fill_host(&host_def); for (rv = 0, i = 0; i < ARRAY_SIZE(ft); ++i) for (mask = 1; mask; mask <<= 1) if (ft[i].check_feat & mask && *ft[i].guest_feat & mask && @@ -1142,7 +1153,7 @@ static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model) if (name && !strcmp(name, def->name)) break; if (kvm_enabled() && name && strcmp(name, "host") == 0) { - cpu_x86_fill_host(x86_cpu_def); + kvm_cpu_fill_host(x86_cpu_def); } else if (!def) { goto error; } else { @@ -1280,8 +1291,8 @@ static int cpu_x86_find_by_name(x86_def_t *x86_cpu_def, const char *cpu_model) x86_cpu_def->kvm_features &= ~minus_kvm_features; x86_cpu_def->svm_features &= ~minus_svm_features; x86_cpu_def->cpuid_7_0_ebx_features &= ~minus_7_0_ebx_features; - if (check_cpuid) { - if (check_features_against_host(x86_cpu_def) && enforce_cpuid) + if (check_cpuid && kvm_enabled()) { + if (kvm_check_features_against_host(x86_cpu_def) && enforce_cpuid) goto error; } if (x86_cpu_def->cpuid_7_0_ebx_features && x86_cpu_def->level < 7) { From 12869995ea4f436ab76af5059fd2e9ae83c6cf9d Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Wed, 24 Oct 2012 19:44:07 -0200 Subject: [PATCH 113/291] target-i386: kvm_cpu_fill_host: use GET_SUPPORTED_CPUID Change the kvm_cpu_fill_host() function to use kvm_arch_get_supported_cpuid() instead of running the CPUID instruction directly, when checking for supported CPUID features. This should solve two problems at the same time: * "-cpu host" was not enabling features that don't need support on the host CPU (e.g. x2apic); * "check" and "enforce" options were not detecting problems when the host CPU did support a feature, but the KVM kernel code didn't support it. Signed-off-by: Eduardo Habkost Signed-off-by: Marcelo Tosatti --- target-i386/cpu.c | 25 +++++++++++++++---------- 1 file changed, 15 insertions(+), 10 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 390ed4771d..4c84e9fbc4 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -773,13 +773,13 @@ static int cpu_x86_fill_model_id(char *str) */ static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def) { + KVMState *s = kvm_state; uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; assert(kvm_enabled()); x86_cpu_def->name = "host"; host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx); - x86_cpu_def->level = eax; x86_cpu_def->vendor1 = ebx; x86_cpu_def->vendor2 = edx; x86_cpu_def->vendor3 = ecx; @@ -788,21 +788,24 @@ static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def) x86_cpu_def->family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF); x86_cpu_def->model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12); x86_cpu_def->stepping = eax & 0x0F; - x86_cpu_def->ext_features = ecx; - x86_cpu_def->features = edx; + + x86_cpu_def->level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX); + x86_cpu_def->features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_EDX); + x86_cpu_def->ext_features = kvm_arch_get_supported_cpuid(s, 0x1, 0, R_ECX); if (x86_cpu_def->level >= 7) { - x86_cpu_def->cpuid_7_0_ebx_features = kvm_arch_get_supported_cpuid(kvm_state, 0x7, 0, R_EBX); + x86_cpu_def->cpuid_7_0_ebx_features = + kvm_arch_get_supported_cpuid(s, 0x7, 0, R_EBX); } else { x86_cpu_def->cpuid_7_0_ebx_features = 0; } - host_cpuid(0x80000000, 0, &eax, &ebx, &ecx, &edx); - x86_cpu_def->xlevel = eax; + x86_cpu_def->xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX); + x86_cpu_def->ext2_features = + kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_EDX); + x86_cpu_def->ext3_features = + kvm_arch_get_supported_cpuid(s, 0x80000001, 0, R_ECX); - host_cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx); - x86_cpu_def->ext2_features = edx; - x86_cpu_def->ext3_features = ecx; cpu_x86_fill_model_id(x86_cpu_def->model_id); x86_cpu_def->vendor_override = 0; @@ -811,11 +814,13 @@ static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def) x86_cpu_def->vendor2 == CPUID_VENDOR_VIA_2 && x86_cpu_def->vendor3 == CPUID_VENDOR_VIA_3) { host_cpuid(0xC0000000, 0, &eax, &ebx, &ecx, &edx); + eax = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX); if (eax >= 0xC0000001) { /* Support VIA max extended level */ x86_cpu_def->xlevel2 = eax; host_cpuid(0xC0000001, 0, &eax, &ebx, &ecx, &edx); - x86_cpu_def->ext4_features = edx; + x86_cpu_def->ext4_features = + kvm_arch_get_supported_cpuid(s, 0xC0000001, 0, R_EDX); } } From b55f546eefe79cb6e6b15ebb23f352a736bafc39 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 22 Oct 2012 12:54:39 +0100 Subject: [PATCH 114/291] update-linux-headers.sh: Handle new kernel uapi/ directories Recent kernels have moved to keeping the userspace headers in uapi/ subdirectories. This breaks the detection of whether an architecture has KVM support in the kernel because kvm.h has moved in the kernel source tree. Update the check to support both the old and new locations. Signed-off-by: Peter Maydell Signed-off-by: Marcelo Tosatti --- scripts/update-linux-headers.sh | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/scripts/update-linux-headers.sh b/scripts/update-linux-headers.sh index 67be2efecd..4c7b566fdf 100755 --- a/scripts/update-linux-headers.sh +++ b/scripts/update-linux-headers.sh @@ -34,7 +34,8 @@ ARCHLIST=$(cd "$linux/arch" && echo *) for arch in $ARCHLIST; do # Discard anything which isn't a KVM-supporting architecture - if ! [ -e "$linux/arch/$arch/include/asm/kvm.h" ]; then + if ! [ -e "$linux/arch/$arch/include/asm/kvm.h" ] && + ! [ -e "$linux/arch/$arch/include/uapi/asm/kvm.h" ] ; then continue fi From 3993c6bddf6da21977349ba1b14b86294ef4f7ff Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 06:43:49 +0200 Subject: [PATCH 115/291] cpus: Pass CPUState to [qemu_]cpu_has_work() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit For target-mips also change the return type to bool. Make include paths for cpu-qom.h consistent for alpha and unicore32. Signed-off-by: Andreas Färber [AF: Updated new target-openrisc function accordingly] Acked-by: Richard Henderson (for alpha) --- cpu-all.h | 2 -- cpu-exec.c | 8 +++----- cpus.c | 2 +- hw/spapr_hcall.c | 2 +- hw/xtensa_pic.c | 2 +- include/qemu/cpu.h | 10 ++++++++++ target-alpha/cpu.c | 2 +- target-alpha/cpu.h | 4 +++- target-arm/cpu.h | 4 +++- target-cris/cpu.h | 4 +++- target-i386/cpu.h | 4 +++- target-lm32/cpu.h | 4 +++- target-m68k/cpu.h | 4 +++- target-microblaze/cpu.h | 4 +++- target-mips/cpu.h | 11 ++++++----- target-openrisc/cpu.h | 4 +++- target-ppc/cpu.h | 4 +++- target-s390x/cpu.h | 4 +++- target-sh4/cpu.h | 4 +++- target-sparc/cpu.h | 4 +++- target-unicore32/cpu.c | 2 +- target-unicore32/cpu.h | 4 +++- target-xtensa/cpu.h | 4 +++- 23 files changed, 66 insertions(+), 31 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index d19ec127e1..0356684e2f 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -438,8 +438,6 @@ void cpu_reset_interrupt(CPUArchState *env, int mask); void cpu_exit(CPUArchState *s); -bool qemu_cpu_has_work(CPUArchState *env); - /* Breakpoint/watchpoint flags */ #define BP_MEM_READ 0x01 #define BP_MEM_WRITE 0x02 diff --git a/cpu-exec.c b/cpu-exec.c index 252da86882..904ee73c7b 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -27,9 +27,9 @@ int tb_invalidated_flag; //#define CONFIG_DEBUG_EXEC -bool qemu_cpu_has_work(CPUArchState *env) +bool qemu_cpu_has_work(CPUState *cpu) { - return cpu_has_work(env); + return cpu_has_work(cpu); } void cpu_loop_exit(CPUArchState *env) @@ -181,16 +181,14 @@ volatile sig_atomic_t exit_request; int cpu_exec(CPUArchState *env) { -#ifdef TARGET_PPC CPUState *cpu = ENV_GET_CPU(env); -#endif int ret, interrupt_request; TranslationBlock *tb; uint8_t *tc_ptr; tcg_target_ulong next_tb; if (env->halted) { - if (!cpu_has_work(env)) { + if (!cpu_has_work(cpu)) { return EXCP_HALTED; } diff --git a/cpus.c b/cpus.c index 6baf2bcb35..76f32fc050 100644 --- a/cpus.c +++ b/cpus.c @@ -72,7 +72,7 @@ static bool cpu_thread_is_idle(CPUArchState *env) if (cpu->stopped || !runstate_is_running()) { return true; } - if (!env->halted || qemu_cpu_has_work(env) || + if (!env->halted || qemu_cpu_has_work(cpu) || kvm_async_interrupts_enabled()) { return false; } diff --git a/hw/spapr_hcall.c b/hw/spapr_hcall.c index c6d55da7a6..63cadb8d92 100644 --- a/hw/spapr_hcall.c +++ b/hw/spapr_hcall.c @@ -516,7 +516,7 @@ static target_ulong h_cede(PowerPCCPU *cpu, sPAPREnvironment *spapr, env->msr |= (1ULL << MSR_EE); hreg_compute_hflags(env); - if (!cpu_has_work(env)) { + if (!cpu_has_work(CPU(cpu))) { env->halted = 1; env->exception_index = EXCP_HLT; env->exit_request = 1; diff --git a/hw/xtensa_pic.c b/hw/xtensa_pic.c index 8b9c0510f9..1ec70cd969 100644 --- a/hw/xtensa_pic.c +++ b/hw/xtensa_pic.c @@ -131,7 +131,7 @@ static void xtensa_ccompare_cb(void *opaque) if (env->halted) { env->halt_clock = qemu_get_clock_ns(vm_clock); xtensa_advance_ccount(env, env->wake_ccount - env->sregs[CCOUNT]); - if (!cpu_has_work(env)) { + if (!cpu_has_work(CPU(cpu))) { env->sregs[CCOUNT] = env->wake_ccount + 1; xtensa_rearm_ccompare_timer(env); } diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index eea6175cb9..f04da6ec4f 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -86,6 +86,16 @@ struct CPUState { */ void cpu_reset(CPUState *cpu); +/** + * qemu_cpu_has_work: + * @cpu: The vCPU to check. + * + * Checks whether the CPU has work to do. + * + * Returns: %true if the CPU has work, %false otherwise. + */ +bool qemu_cpu_has_work(CPUState *cpu); + /** * qemu_cpu_is_self: * @cpu: The vCPU to check against. diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index 62d2a669a9..11a19ebc87 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -19,7 +19,7 @@ * */ -#include "cpu-qom.h" +#include "cpu.h" #include "qemu-common.h" diff --git a/target-alpha/cpu.h b/target-alpha/cpu.h index 8f131b7325..34221fb184 100644 --- a/target-alpha/cpu.h +++ b/target-alpha/cpu.h @@ -510,8 +510,10 @@ static inline void cpu_set_tls(CPUAlphaState *env, target_ulong newtls) } #endif -static inline bool cpu_has_work(CPUAlphaState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUAlphaState *env = &ALPHA_CPU(cpu)->env; + /* Here we are checking to see if the CPU should wake up from HALT. We will have gotten into this state only for WTINT from PALmode. */ /* ??? I'm not sure how the IPL state works with WTINT to keep a CPU diff --git a/target-arm/cpu.h b/target-arm/cpu.h index ff4de10f12..e4ff918fa4 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -718,8 +718,10 @@ static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, } } -static inline bool cpu_has_work(CPUARMState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUARMState *env = &ARM_CPU(cpu)->env; + return env->interrupt_request & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); } diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 4f4df6d9b5..2c27506d0d 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -285,8 +285,10 @@ static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *pc, #define cpu_list cris_cpu_list void cris_cpu_list(FILE *f, fprintf_function cpu_fprintf); -static inline bool cpu_has_work(CPUCRISState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUCRISState *env = &CRIS_CPU(cpu)->env; + return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target-i386/cpu.h b/target-i386/cpu.h index d840914ebf..2d7b4c3b56 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1100,8 +1100,10 @@ static inline void cpu_clone_regs(CPUX86State *env, target_ulong newsp) #include "hw/apic.h" #endif -static inline bool cpu_has_work(CPUX86State *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUX86State *env = &X86_CPU(cpu)->env; + return ((env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_POLL)) && (env->eflags & IF_MASK)) || diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index da80469f51..7243b4f7c7 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -253,8 +253,10 @@ static inline void cpu_get_tb_cpu_state(CPULM32State *env, target_ulong *pc, *flags = 0; } -static inline bool cpu_has_work(CPULM32State *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPULM32State *env = &LM32_CPU(cpu)->env; + return env->interrupt_request & CPU_INTERRUPT_HARD; } diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index 5e6ee50969..780e2c94e7 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -257,8 +257,10 @@ static inline void cpu_get_tb_cpu_state(CPUM68KState *env, target_ulong *pc, | ((env->macsr >> 4) & 0xf); /* Bits 0-3 */ } -static inline bool cpu_has_work(CPUM68KState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUM68KState *env = &M68K_CPU(cpu)->env; + return env->interrupt_request & CPU_INTERRUPT_HARD; } diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index 37bbdf1591..585bbd6dbc 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -374,8 +374,10 @@ void cpu_unassigned_access(CPUMBState *env1, hwaddr addr, int is_write, int is_exec, int is_asi, int size); #endif -static inline bool cpu_has_work(CPUMBState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUMBState *env = &MICROBLAZE_CPU(cpu)->env; + return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } diff --git a/target-mips/cpu.h b/target-mips/cpu.h index c4ca2855df..38943dec10 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -706,16 +706,17 @@ static inline int mips_vpe_active(CPUMIPSState *env) return active; } -static inline int cpu_has_work(CPUMIPSState *env) +static inline bool cpu_has_work(CPUState *cpu) { - int has_work = 0; + CPUMIPSState *env = &MIPS_CPU(cpu)->env; + bool has_work = false; /* It is implementation dependent if non-enabled interrupts wake-up the CPU, however most of the implementations only check for interrupts that can be taken. */ if ((env->interrupt_request & CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { - has_work = 1; + has_work = true; } /* MIPS-MT has the ability to halt the CPU. */ @@ -723,11 +724,11 @@ static inline int cpu_has_work(CPUMIPSState *env) /* The QEMU model will issue an _WAKE request whenever the CPUs should be woken up. */ if (env->interrupt_request & CPU_INTERRUPT_WAKE) { - has_work = 1; + has_work = true; } if (!mips_vpe_active(env)) { - has_work = 0; + has_work = false; } } return has_work; diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index a701d364a5..d42ffb09b6 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -437,8 +437,10 @@ static inline int cpu_mmu_index(CPUOpenRISCState *env) } #define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0 -static inline bool cpu_has_work(CPUOpenRISCState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUOpenRISCState *env = &OPENRISC_CPU(cpu)->env; + return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER); } diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 5574042a87..ed491d2ed2 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -2222,8 +2222,10 @@ static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr) extern void (*cpu_ppc_hypercall)(PowerPCCPU *); -static inline bool cpu_has_work(CPUPPCState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUPPCState *env = &POWERPC_CPU(cpu)->env; + return msr_ee && (env->interrupt_request & CPU_INTERRUPT_HARD); } diff --git a/target-s390x/cpu.h b/target-s390x/cpu.h index 5be6e83528..0f9a1f7340 100644 --- a/target-s390x/cpu.h +++ b/target-s390x/cpu.h @@ -977,8 +977,10 @@ static inline void cpu_inject_ext(CPUS390XState *env, uint32_t code, uint32_t pa cpu_interrupt(env, CPU_INTERRUPT_HARD); } -static inline bool cpu_has_work(CPUS390XState *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUS390XState *env = &S390_CPU(cpu)->env; + return (env->interrupt_request & CPU_INTERRUPT_HARD) && (env->psw.mask & PSW_MASK_EXT); } diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index 782159e8ba..9a0e72b1fb 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -371,8 +371,10 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc, | (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */ } -static inline bool cpu_has_work(CPUSH4State *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUSH4State *env = &SUPERH_CPU(cpu)->env; + return env->interrupt_request & CPU_INTERRUPT_HARD; } diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index a55fe08d36..6aa82b371a 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -764,8 +764,10 @@ static inline bool tb_am_enabled(int tb_flags) #endif } -static inline bool cpu_has_work(CPUSPARCState *env1) +static inline bool cpu_has_work(CPUState *cpu) { + CPUSPARCState *env1 = &SPARC_CPU(cpu)->env; + return (env1->interrupt_request & CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(env1); } diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index 3425bbeac9..884c101010 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -12,7 +12,7 @@ * or (at your option) any later version. */ -#include "cpu-qom.h" +#include "cpu.h" #include "qemu-common.h" static inline void set_feature(CPUUniCore32State *env, int feature) diff --git a/target-unicore32/cpu.h b/target-unicore32/cpu.h index 06508a1278..676c5d9d99 100644 --- a/target-unicore32/cpu.h +++ b/target-unicore32/cpu.h @@ -181,8 +181,10 @@ void uc32_translate_init(void); void do_interrupt(CPUUniCore32State *); void switch_mode(CPUUniCore32State *, int); -static inline bool cpu_has_work(CPUUniCore32State *env) +static inline bool cpu_has_work(CPUState *cpu) { + CPUUniCore32State *env = &UNICORE32_CPU(cpu)->env; + return env->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB); } diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 7348277edc..74e98883bf 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -501,8 +501,10 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, #include "cpu-all.h" #include "exec-all.h" -static inline int cpu_has_work(CPUXtensaState *env) +static inline int cpu_has_work(CPUState *cpu) { + CPUXtensaState *env = &XTENSA_CPU(cpu)->env; + return env->pending_irq_level; } From bee615d4b945e6d88dc37a39e40be9f105622f8d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 15:13:58 +0200 Subject: [PATCH 116/291] target-i386: Pass X86CPU to kvm_mce_inject() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for changing cpu_x86_inject_mce() argument to X86CPU. Signed-off-by: Andreas Färber [AF: Rebased onto hwaddr] --- target-i386/kvm.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index a3491a4fa1..5bf2f89c13 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -229,8 +229,9 @@ static int kvm_get_mce_cap_supported(KVMState *s, uint64_t *mce_cap, return -ENOSYS; } -static void kvm_mce_inject(CPUX86State *env, hwaddr paddr, int code) +static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) { + CPUX86State *env = &cpu->env; uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN | MCI_STATUS_MISCV | MCI_STATUS_ADDRV | MCI_STATUS_S; uint64_t mcg_status = MCG_STATUS_MCIP; @@ -256,6 +257,7 @@ static void hardware_memory_error(void) int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr) { + X86CPU *cpu = x86_env_get_cpu(env); ram_addr_t ram_addr; hwaddr paddr; @@ -273,7 +275,7 @@ int kvm_arch_on_sigbus_vcpu(CPUX86State *env, int code, void *addr) } } kvm_hwpoison_page_add(ram_addr); - kvm_mce_inject(env, paddr, code); + kvm_mce_inject(cpu, paddr, code); } else { if (code == BUS_MCEERR_AO) { return 0; @@ -301,7 +303,7 @@ int kvm_arch_on_sigbus(int code, void *addr) return 0; } kvm_hwpoison_page_add(ram_addr); - kvm_mce_inject(first_cpu, paddr, code); + kvm_mce_inject(x86_env_get_cpu(first_cpu), paddr, code); } else { if (code == BUS_MCEERR_AO) { return 0; From 8c5cf3b6219d5d5fb61a9d6e59022fc72dab8f85 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 15:22:54 +0200 Subject: [PATCH 117/291] target-i386: Pass X86CPU to cpu_x86_inject_mce() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for changing run_on_cpu() argument to CPUState. Signed-off-by: Andreas Färber --- monitor.c | 6 ++++-- target-i386/cpu.h | 2 +- target-i386/helper.c | 3 ++- target-i386/kvm.c | 2 +- 4 files changed, 8 insertions(+), 5 deletions(-) diff --git a/monitor.c b/monitor.c index eeef32e38b..c0e32d60c3 100644 --- a/monitor.c +++ b/monitor.c @@ -1988,7 +1988,8 @@ static void do_acl_remove(Monitor *mon, const QDict *qdict) #if defined(TARGET_I386) static void do_inject_mce(Monitor *mon, const QDict *qdict) { - CPUArchState *cenv; + X86CPU *cpu; + CPUX86State *cenv; int cpu_index = qdict_get_int(qdict, "cpu_index"); int bank = qdict_get_int(qdict, "bank"); uint64_t status = qdict_get_int(qdict, "status"); @@ -2001,8 +2002,9 @@ static void do_inject_mce(Monitor *mon, const QDict *qdict) flags |= MCE_INJECT_BROADCAST; } for (cenv = first_cpu; cenv != NULL; cenv = cenv->next_cpu) { + cpu = x86_env_get_cpu(cenv); if (cenv->cpu_index == cpu_index) { - cpu_x86_inject_mce(mon, cenv, bank, status, mcg_status, addr, misc, + cpu_x86_inject_mce(mon, cpu, bank, status, mcg_status, addr, misc, flags); break; } diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2d7b4c3b56..cdc59dc0ca 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1135,7 +1135,7 @@ void do_cpu_sipi(X86CPU *cpu); #define MCE_INJECT_BROADCAST 1 #define MCE_INJECT_UNCOND_AO 2 -void cpu_x86_inject_mce(Monitor *mon, CPUX86State *cenv, int bank, +void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, uint64_t status, uint64_t mcg_status, uint64_t addr, uint64_t misc, int flags); diff --git a/target-i386/helper.c b/target-i386/helper.c index 0424ccf6fb..45f4bed57f 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1141,10 +1141,11 @@ static void do_inject_x86_mce(void *data) } } -void cpu_x86_inject_mce(Monitor *mon, CPUX86State *cenv, int bank, +void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, uint64_t status, uint64_t mcg_status, uint64_t addr, uint64_t misc, int flags) { + CPUX86State *cenv = &cpu->env; MCEInjectionParams params = { .mon = mon, .env = cenv, diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 5bf2f89c13..64b837b570 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -243,7 +243,7 @@ static void kvm_mce_inject(X86CPU *cpu, hwaddr paddr, int code) status |= 0xc0; mcg_status |= MCG_STATUS_RIPV; } - cpu_x86_inject_mce(NULL, env, 9, status, mcg_status, paddr, + cpu_x86_inject_mce(NULL, cpu, 9, status, mcg_status, paddr, (MCM_ADDR_PHYS << 6) | 0xc, cpu_x86_support_mca_broadcast(env) ? MCE_INJECT_BROADCAST : 0); From f100f0b38fe43c683f437a8fa3e449d6752f6a58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 14:58:47 +0200 Subject: [PATCH 118/291] cpus: Pass CPUState to run_on_cpu() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit CPUArchState is no longer needed. Move the declaration to include/qemu/cpu.h and add documentation. Signed-off-by: Andreas Färber --- cpu-all.h | 1 - cpus.c | 3 +-- hw/kvm/apic.c | 2 +- hw/kvmvapic.c | 6 ++++-- hw/ppce500_spin.c | 2 +- include/qemu/cpu.h | 10 ++++++++++ kvm-all.c | 7 +++++-- target-i386/helper.c | 4 ++-- 8 files changed, 24 insertions(+), 11 deletions(-) diff --git a/cpu-all.h b/cpu-all.h index 0356684e2f..c9c51b83ac 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -464,7 +464,6 @@ void cpu_watchpoint_remove_all(CPUArchState *env, int mask); #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ void cpu_single_step(CPUArchState *env, int enabled); -void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data); #if !defined(CONFIG_USER_ONLY) diff --git a/cpus.c b/cpus.c index 76f32fc050..bee09b996f 100644 --- a/cpus.c +++ b/cpus.c @@ -640,9 +640,8 @@ void qemu_init_cpu_loop(void) qemu_thread_get_self(&io_thread); } -void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data) +void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data) { - CPUState *cpu = ENV_GET_CPU(env); struct qemu_work_item wi; if (qemu_cpu_is_self(cpu)) { diff --git a/hw/kvm/apic.c b/hw/kvm/apic.c index e4a7307ca5..8b65d513db 100644 --- a/hw/kvm/apic.c +++ b/hw/kvm/apic.c @@ -143,7 +143,7 @@ static void do_inject_external_nmi(void *data) static void kvm_apic_external_nmi(APICCommonState *s) { - run_on_cpu(&s->cpu->env, do_inject_external_nmi, s); + run_on_cpu(CPU(s->cpu), do_inject_external_nmi, s); } static uint64_t kvm_apic_mem_read(void *opaque, hwaddr addr, diff --git a/hw/kvmvapic.c b/hw/kvmvapic.c index 5e0a7c9384..dc111ee8e6 100644 --- a/hw/kvmvapic.c +++ b/hw/kvmvapic.c @@ -475,11 +475,13 @@ static void vapic_enable_tpr_reporting(bool enable) VAPICEnableTPRReporting info = { .enable = enable, }; + X86CPU *cpu; CPUX86State *env; for (env = first_cpu; env != NULL; env = env->next_cpu) { + cpu = x86_env_get_cpu(env); info.apic = env->apic_state; - run_on_cpu(env, vapic_do_enable_tpr_reporting, &info); + run_on_cpu(CPU(cpu), vapic_do_enable_tpr_reporting, &info); } } @@ -717,7 +719,7 @@ static int vapic_post_load(void *opaque, int version_id) } if (s->state == VAPIC_ACTIVE) { if (smp_cpus == 1) { - run_on_cpu(first_cpu, do_vapic_enable, s); + run_on_cpu(ENV_GET_CPU(first_cpu), do_vapic_enable, s); } else { zero = g_malloc0(s->rom_state.vapic_size); cpu_physical_memory_rw(s->vapic_paddr, zero, diff --git a/hw/ppce500_spin.c b/hw/ppce500_spin.c index 7f8c8428b6..c1a155bd31 100644 --- a/hw/ppce500_spin.c +++ b/hw/ppce500_spin.c @@ -163,7 +163,7 @@ static void spin_write(void *opaque, hwaddr addr, uint64_t value, .spin = curspin, }; - run_on_cpu(env, spin_kick, &kick); + run_on_cpu(CPU(kick.cpu), spin_kick, &kick); } } diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index f04da6ec4f..33f01d9a6f 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -125,5 +125,15 @@ void qemu_cpu_kick(CPUState *cpu); */ bool cpu_is_stopped(CPUState *cpu); +/** + * run_on_cpu: + * @cpu: The vCPU to run on. + * @func: The function to be executed. + * @data: Data to pass to the function. + * + * Schedules the function @func for execution on the vCPU @cpu. + */ +void run_on_cpu(CPUState *cpu, void (*func)(void *data), void *data); + #endif diff --git a/kvm-all.c b/kvm-all.c index e41e1c9531..b6d0483576 100644 --- a/kvm-all.c +++ b/kvm-all.c @@ -1500,8 +1500,10 @@ static void do_kvm_cpu_synchronize_state(void *_env) void kvm_cpu_synchronize_state(CPUArchState *env) { + CPUState *cpu = ENV_GET_CPU(env); + if (!env->kvm_vcpu_dirty) { - run_on_cpu(env, do_kvm_cpu_synchronize_state, env); + run_on_cpu(cpu, do_kvm_cpu_synchronize_state, env); } } @@ -1787,6 +1789,7 @@ static void kvm_invoke_set_guest_debug(void *data) int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap) { + CPUState *cpu = ENV_GET_CPU(env); struct kvm_set_guest_debug_data data; data.dbg.control = reinject_trap; @@ -1797,7 +1800,7 @@ int kvm_update_guest_debug(CPUArchState *env, unsigned long reinject_trap) kvm_arch_update_guest_debug(env, &data.dbg); data.env = env; - run_on_cpu(env, kvm_invoke_set_guest_debug, &data); + run_on_cpu(cpu, kvm_invoke_set_guest_debug, &data); return data.err; } diff --git a/target-i386/helper.c b/target-i386/helper.c index 45f4bed57f..bf206cfa97 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1177,7 +1177,7 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, return; } - run_on_cpu(cenv, do_inject_x86_mce, ¶ms); + run_on_cpu(CPU(cpu), do_inject_x86_mce, ¶ms); if (flags & MCE_INJECT_BROADCAST) { params.bank = 1; params.status = MCI_STATUS_VAL | MCI_STATUS_UC; @@ -1189,7 +1189,7 @@ void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank, continue; } params.env = env; - run_on_cpu(cenv, do_inject_x86_mce, ¶ms); + run_on_cpu(CPU(cpu), do_inject_x86_mce, ¶ms); } } } From 9f09e18a6df39ab11cd80e203c5736af1823f3b3 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 06:59:07 +0200 Subject: [PATCH 119/291] cpu: Move thread_id to CPUState MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Andreas Färber --- cpu-defs.h | 1 - cpus.c | 11 ++++++----- exec.c | 5 ++++- include/qemu/cpu.h | 1 + 4 files changed, 11 insertions(+), 7 deletions(-) diff --git a/cpu-defs.h b/cpu-defs.h index b30a8e91bb..3669241faf 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -201,7 +201,6 @@ typedef struct CPUWatchpoint { int nr_cores; /* number of cores within this CPU package */ \ int nr_threads;/* number of threads within this CPU */ \ int running; /* Nonzero if cpu is currently running(usermode). */ \ - int thread_id; \ /* user data */ \ void *opaque; \ \ diff --git a/cpus.c b/cpus.c index bee09b996f..d9c332fcb8 100644 --- a/cpus.c +++ b/cpus.c @@ -737,7 +737,7 @@ static void *qemu_kvm_cpu_thread_fn(void *arg) qemu_mutex_lock(&qemu_global_mutex); qemu_thread_get_self(cpu->thread); - env->thread_id = qemu_get_thread_id(); + cpu->thread_id = qemu_get_thread_id(); cpu_single_env = env; r = kvm_init_vcpu(env); @@ -778,7 +778,7 @@ static void *qemu_dummy_cpu_thread_fn(void *arg) qemu_mutex_lock_iothread(); qemu_thread_get_self(cpu->thread); - env->thread_id = qemu_get_thread_id(); + cpu->thread_id = qemu_get_thread_id(); sigemptyset(&waitset); sigaddset(&waitset, SIG_IPI); @@ -822,7 +822,7 @@ static void *qemu_tcg_cpu_thread_fn(void *arg) qemu_mutex_lock(&qemu_global_mutex); for (env = first_cpu; env != NULL; env = env->next_cpu) { cpu = ENV_GET_CPU(env); - env->thread_id = qemu_get_thread_id(); + cpu->thread_id = qemu_get_thread_id(); cpu->created = true; } qemu_cond_signal(&qemu_cpu_cond); @@ -1205,7 +1205,8 @@ CpuInfoList *qmp_query_cpus(Error **errp) CpuInfoList *head = NULL, *cur_item = NULL; CPUArchState *env; - for(env = first_cpu; env != NULL; env = env->next_cpu) { + for (env = first_cpu; env != NULL; env = env->next_cpu) { + CPUState *cpu = ENV_GET_CPU(env); CpuInfoList *info; cpu_synchronize_state(env); @@ -1215,7 +1216,7 @@ CpuInfoList *qmp_query_cpus(Error **errp) info->value->CPU = env->cpu_index; info->value->current = (env == first_cpu); info->value->halted = env->halted; - info->value->thread_id = env->thread_id; + info->value->thread_id = cpu->thread_id; #if defined(TARGET_I386) info->value->has_pc = true; info->value->pc = env->eip + env->segs[R_CS].base; diff --git a/exec.c b/exec.c index 038e40d09b..df6793812f 100644 --- a/exec.c +++ b/exec.c @@ -689,6 +689,9 @@ CPUArchState *qemu_get_cpu(int cpu) void cpu_exec_init(CPUArchState *env) { +#ifndef CONFIG_USER_ONLY + CPUState *cpu = ENV_GET_CPU(env); +#endif CPUArchState **penv; int cpu_index; @@ -707,7 +710,7 @@ void cpu_exec_init(CPUArchState *env) QTAILQ_INIT(&env->breakpoints); QTAILQ_INIT(&env->watchpoints); #ifndef CONFIG_USER_ONLY - env->thread_id = qemu_get_thread_id(); + cpu->thread_id = qemu_get_thread_id(); #endif *penv = env; #if defined(CONFIG_USER_ONLY) diff --git a/include/qemu/cpu.h b/include/qemu/cpu.h index 33f01d9a6f..61b76982f1 100644 --- a/include/qemu/cpu.h +++ b/include/qemu/cpu.h @@ -69,6 +69,7 @@ struct CPUState { #ifdef _WIN32 HANDLE hThread; #endif + int thread_id; struct QemuCond *halt_cond; struct qemu_work_item *queued_work_first, *queued_work_last; bool thread_kicked; From 23d02d9b4bbe362a5b9cfc3ce1e5cc106eff5664 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 16:56:46 +0200 Subject: [PATCH 120/291] target-i386: Pass X86CPU to kvm_get_mp_state() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for moving halted field to CPUState. Signed-off-by: Andreas Färber --- target-i386/kvm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 64b837b570..7da816f484 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1367,8 +1367,9 @@ static int kvm_put_mp_state(CPUX86State *env) return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state); } -static int kvm_get_mp_state(CPUX86State *env) +static int kvm_get_mp_state(X86CPU *cpu) { + CPUX86State *env = &cpu->env; struct kvm_mp_state mp_state; int ret; @@ -1612,10 +1613,10 @@ int kvm_arch_put_registers(CPUX86State *env, int level) int kvm_arch_get_registers(CPUX86State *env) { - CPUState *cpu = ENV_GET_CPU(env); + X86CPU *cpu = x86_env_get_cpu(env); int ret; - assert(cpu_is_stopped(cpu) || qemu_cpu_is_self(cpu)); + assert(cpu_is_stopped(CPU(cpu)) || qemu_cpu_is_self(CPU(cpu))); ret = kvm_getput_regs(env, 0); if (ret < 0) { @@ -1637,7 +1638,7 @@ int kvm_arch_get_registers(CPUX86State *env) if (ret < 0) { return ret; } - ret = kvm_get_mp_state(env); + ret = kvm_get_mp_state(cpu); if (ret < 0) { return ret; } From 839b5630cd4f49ce10618a7bf0b705b76f3a01ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Andreas=20F=C3=A4rber?= Date: Thu, 3 May 2012 17:00:31 +0200 Subject: [PATCH 121/291] target-i386: Pass X86CPU to kvm_handle_halt() MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Needed for moving interrupt_request and halted fields to CPUState. Signed-off-by: Andreas Färber --- target-i386/kvm.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 7da816f484..9ccbcb5be5 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1786,8 +1786,10 @@ int kvm_arch_process_async_events(CPUX86State *env) return env->halted; } -static int kvm_handle_halt(CPUX86State *env) +static int kvm_handle_halt(X86CPU *cpu) { + CPUX86State *env = &cpu->env; + if (!((env->interrupt_request & CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) && !(env->interrupt_request & CPU_INTERRUPT_NMI)) { @@ -2001,13 +2003,14 @@ static bool host_supports_vmx(void) int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run) { + X86CPU *cpu = x86_env_get_cpu(env); uint64_t code; int ret; switch (run->exit_reason) { case KVM_EXIT_HLT: DPRINTF("handle_hlt\n"); - ret = kvm_handle_halt(env); + ret = kvm_handle_halt(cpu); break; case KVM_EXIT_SET_TPR: ret = 0; From 38b14db34e16bb0ae1f28b7ddccb6aa11a2a96a1 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Mon, 8 Aug 2011 14:36:41 +0200 Subject: [PATCH 122/291] qemu-thread: add QemuSemaphore The new thread pool will use semaphores instead of condition variables, because QemuCond does not have qemu_cond_timedwait. (I also like it more this way). Signed-off-by: Paolo Bonzini --- qemu-thread-posix.c | 80 +++++++++++++++++++++++++++++++++++++++++++++ qemu-thread-posix.h | 5 +++ qemu-thread-win32.c | 35 ++++++++++++++++++++ qemu-thread-win32.h | 4 +++ qemu-thread.h | 7 ++++ 5 files changed, 131 insertions(+) diff --git a/qemu-thread-posix.c b/qemu-thread-posix.c index 8fbabdac36..6a3d3a12a8 100644 --- a/qemu-thread-posix.c +++ b/qemu-thread-posix.c @@ -17,6 +17,9 @@ #include #include #include +#include +#include +#include #include "qemu-thread.h" static void error_exit(int err, const char *msg) @@ -115,6 +118,83 @@ void qemu_cond_wait(QemuCond *cond, QemuMutex *mutex) error_exit(err, __func__); } +void qemu_sem_init(QemuSemaphore *sem, int init) +{ + int rc; + + rc = sem_init(&sem->sem, 0, init); + if (rc < 0) { + error_exit(errno, __func__); + } +} + +void qemu_sem_destroy(QemuSemaphore *sem) +{ + int rc; + + rc = sem_destroy(&sem->sem); + if (rc < 0) { + error_exit(errno, __func__); + } +} + +void qemu_sem_post(QemuSemaphore *sem) +{ + int rc; + + rc = sem_post(&sem->sem); + if (rc < 0) { + error_exit(errno, __func__); + } +} + +int qemu_sem_timedwait(QemuSemaphore *sem, int ms) +{ + int rc; + + if (ms <= 0) { + /* This is cheaper than sem_timedwait. */ + do { + rc = sem_trywait(&sem->sem); + } while (rc == -1 && errno == EINTR); + if (rc == -1 && errno == EAGAIN) { + return -1; + } + } else { + struct timeval tv; + struct timespec ts; + gettimeofday(&tv, NULL); + ts.tv_nsec = tv.tv_usec * 1000 + (ms % 1000) * 1000000; + ts.tv_sec = tv.tv_sec + ms / 1000; + if (ts.tv_nsec >= 1000000000) { + ts.tv_sec++; + ts.tv_nsec -= 1000000000; + } + do { + rc = sem_timedwait(&sem->sem, &ts); + } while (rc == -1 && errno == EINTR); + if (rc == -1 && errno == ETIMEDOUT) { + return -1; + } + } + if (rc < 0) { + error_exit(errno, __func__); + } + return 0; +} + +void qemu_sem_wait(QemuSemaphore *sem) +{ + int rc; + + do { + rc = sem_wait(&sem->sem); + } while (rc == -1 && errno == EINTR); + if (rc < 0) { + error_exit(errno, __func__); + } +} + void qemu_thread_create(QemuThread *thread, void *(*start_routine)(void*), void *arg, int mode) diff --git a/qemu-thread-posix.h b/qemu-thread-posix.h index ee4618e620..2542c15200 100644 --- a/qemu-thread-posix.h +++ b/qemu-thread-posix.h @@ -1,6 +1,7 @@ #ifndef __QEMU_THREAD_POSIX_H #define __QEMU_THREAD_POSIX_H 1 #include "pthread.h" +#include struct QemuMutex { pthread_mutex_t lock; @@ -10,6 +11,10 @@ struct QemuCond { pthread_cond_t cond; }; +struct QemuSemaphore { + sem_t sem; +}; + struct QemuThread { pthread_t thread; }; diff --git a/qemu-thread-win32.c b/qemu-thread-win32.c index 177b398cc4..4b3db60f5c 100644 --- a/qemu-thread-win32.c +++ b/qemu-thread-win32.c @@ -192,6 +192,41 @@ void qemu_cond_wait(QemuCond *cond, QemuMutex *mutex) qemu_mutex_lock(mutex); } +void qemu_sem_init(QemuSemaphore *sem, int init) +{ + /* Manual reset. */ + sem->sema = CreateSemaphore(NULL, init, LONG_MAX, NULL); +} + +void qemu_sem_destroy(QemuSemaphore *sem) +{ + CloseHandle(sem->sema); +} + +void qemu_sem_post(QemuSemaphore *sem) +{ + ReleaseSemaphore(sem->sema, 1, NULL); +} + +int qemu_sem_timedwait(QemuSemaphore *sem, int ms) +{ + int rc = WaitForSingleObject(sem->sema, ms); + if (rc == WAIT_OBJECT_0) { + return 0; + } + if (rc != WAIT_TIMEOUT) { + error_exit(GetLastError(), __func__); + } + return -1; +} + +void qemu_sem_wait(QemuSemaphore *sem) +{ + if (WaitForSingleObject(sem->sema, INFINITE) != WAIT_OBJECT_0) { + error_exit(GetLastError(), __func__); + } +} + struct QemuThreadData { /* Passed to win32_start_routine. */ void *(*start_routine)(void *); diff --git a/qemu-thread-win32.h b/qemu-thread-win32.h index b9d1be8478..13adb958f0 100644 --- a/qemu-thread-win32.h +++ b/qemu-thread-win32.h @@ -13,6 +13,10 @@ struct QemuCond { HANDLE continue_event; }; +struct QemuSemaphore { + HANDLE sema; +}; + typedef struct QemuThreadData QemuThreadData; struct QemuThread { QemuThreadData *data; diff --git a/qemu-thread.h b/qemu-thread.h index 05fdaaf50e..3ee2f6b1f9 100644 --- a/qemu-thread.h +++ b/qemu-thread.h @@ -6,6 +6,7 @@ typedef struct QemuMutex QemuMutex; typedef struct QemuCond QemuCond; +typedef struct QemuSemaphore QemuSemaphore; typedef struct QemuThread QemuThread; #ifdef _WIN32 @@ -38,6 +39,12 @@ void qemu_cond_signal(QemuCond *cond); void qemu_cond_broadcast(QemuCond *cond); void qemu_cond_wait(QemuCond *cond, QemuMutex *mutex); +void qemu_sem_init(QemuSemaphore *sem, int init); +void qemu_sem_post(QemuSemaphore *sem); +void qemu_sem_wait(QemuSemaphore *sem); +int qemu_sem_timedwait(QemuSemaphore *sem, int ms); +void qemu_sem_destroy(QemuSemaphore *sem); + void qemu_thread_create(QemuThread *thread, void *(*start_routine)(void *), void *arg, int mode); From d354c7eccf5466ec2715a03d3f33dbfd6680dcc5 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 23 Feb 2012 13:23:34 +0100 Subject: [PATCH 123/291] aio: add generic thread-pool facility Add a generic thread-pool. The code is roughly based on posix-aio-compat.c, with some changes, especially the following: - use QemuSemaphore instead of QemuCond; - separate the state of the thread from the return code of the worker function. The return code is totally opaque for the thread pool; - do not busy wait when doing cancellation. A more generic threadpool (but still specific to I/O so that in the future it can use special scheduling classes or PI mutexes) can have many uses: it allows more flexibility in raw-posix.c and can more easily be extended to Win32, and it will also be used to do an msync of the persistent bitmap. Signed-off-by: Paolo Bonzini --- Makefile.objs | 2 +- thread-pool.c | 282 ++++++++++++++++++++++++++++++++++++++++++++++++++ thread-pool.h | 34 ++++++ trace-events | 5 + 4 files changed, 322 insertions(+), 1 deletion(-) create mode 100644 thread-pool.c create mode 100644 thread-pool.h diff --git a/Makefile.objs b/Makefile.objs index a8ade04c02..f8ae0316b8 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -43,7 +43,7 @@ coroutine-obj-$(CONFIG_WIN32) += coroutine-win32.o block-obj-y = iov.o cache-utils.o qemu-option.o module.o async.o block-obj-y += nbd.o block.o blockjob.o aes.o qemu-config.o -block-obj-y += qemu-progress.o qemu-sockets.o uri.o notify.o +block-obj-y += thread-pool.o qemu-progress.o qemu-sockets.o uri.o notify.o block-obj-y += $(coroutine-obj-y) $(qobject-obj-y) $(version-obj-y) block-obj-$(CONFIG_POSIX) += posix-aio-compat.o block-obj-$(CONFIG_POSIX) += event_notifier-posix.o aio-posix.o diff --git a/thread-pool.c b/thread-pool.c new file mode 100644 index 0000000000..80749b77e0 --- /dev/null +++ b/thread-pool.c @@ -0,0 +1,282 @@ +/* + * QEMU block layer thread pool + * + * Copyright IBM, Corp. 2008 + * Copyright Red Hat, Inc. 2012 + * + * Authors: + * Anthony Liguori + * Paolo Bonzini + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ +#include "qemu-common.h" +#include "qemu-queue.h" +#include "qemu-thread.h" +#include "osdep.h" +#include "qemu-coroutine.h" +#include "trace.h" +#include "block_int.h" +#include "event_notifier.h" +#include "thread-pool.h" + +static void do_spawn_thread(void); + +typedef struct ThreadPoolElement ThreadPoolElement; + +enum ThreadState { + THREAD_QUEUED, + THREAD_ACTIVE, + THREAD_DONE, + THREAD_CANCELED, +}; + +struct ThreadPoolElement { + BlockDriverAIOCB common; + ThreadPoolFunc *func; + void *arg; + enum ThreadState state; + int ret; + + /* Access to this list is protected by lock. */ + QTAILQ_ENTRY(ThreadPoolElement) reqs; + + /* Access to this list is protected by the global mutex. */ + QLIST_ENTRY(ThreadPoolElement) all; +}; + +static EventNotifier notifier; +static QemuMutex lock; +static QemuCond check_cancel; +static QemuSemaphore sem; +static int max_threads = 64; +static QEMUBH *new_thread_bh; + +/* The following variables are protected by the global mutex. */ +static QLIST_HEAD(, ThreadPoolElement) head; + +/* The following variables are protected by lock. */ +static QTAILQ_HEAD(, ThreadPoolElement) request_list; +static int cur_threads; +static int idle_threads; +static int new_threads; /* backlog of threads we need to create */ +static int pending_threads; /* threads created but not running yet */ +static int pending_cancellations; /* whether we need a cond_broadcast */ + +static void *worker_thread(void *unused) +{ + qemu_mutex_lock(&lock); + pending_threads--; + do_spawn_thread(); + + while (1) { + ThreadPoolElement *req; + int ret; + + do { + idle_threads++; + qemu_mutex_unlock(&lock); + ret = qemu_sem_timedwait(&sem, 10000); + qemu_mutex_lock(&lock); + idle_threads--; + } while (ret == -1 && !QTAILQ_EMPTY(&request_list)); + if (ret == -1) { + break; + } + + req = QTAILQ_FIRST(&request_list); + QTAILQ_REMOVE(&request_list, req, reqs); + req->state = THREAD_ACTIVE; + qemu_mutex_unlock(&lock); + + ret = req->func(req->arg); + + qemu_mutex_lock(&lock); + req->state = THREAD_DONE; + req->ret = ret; + if (pending_cancellations) { + qemu_cond_broadcast(&check_cancel); + } + + event_notifier_set(¬ifier); + } + + cur_threads--; + qemu_mutex_unlock(&lock); + return NULL; +} + +static void do_spawn_thread(void) +{ + QemuThread t; + + /* Runs with lock taken. */ + if (!new_threads) { + return; + } + + new_threads--; + pending_threads++; + + qemu_thread_create(&t, worker_thread, NULL, QEMU_THREAD_DETACHED); +} + +static void spawn_thread_bh_fn(void *opaque) +{ + qemu_mutex_lock(&lock); + do_spawn_thread(); + qemu_mutex_unlock(&lock); +} + +static void spawn_thread(void) +{ + cur_threads++; + new_threads++; + /* If there are threads being created, they will spawn new workers, so + * we don't spend time creating many threads in a loop holding a mutex or + * starving the current vcpu. + * + * If there are no idle threads, ask the main thread to create one, so we + * inherit the correct affinity instead of the vcpu affinity. + */ + if (!pending_threads) { + qemu_bh_schedule(new_thread_bh); + } +} + +static void event_notifier_ready(EventNotifier *notifier) +{ + ThreadPoolElement *elem, *next; + + event_notifier_test_and_clear(notifier); +restart: + QLIST_FOREACH_SAFE(elem, &head, all, next) { + if (elem->state != THREAD_CANCELED && elem->state != THREAD_DONE) { + continue; + } + if (elem->state == THREAD_DONE) { + trace_thread_pool_complete(elem, elem->common.opaque, elem->ret); + } + if (elem->state == THREAD_DONE && elem->common.cb) { + qemu_mutex_lock(&lock); + int ret = elem->ret; + qemu_mutex_unlock(&lock); + QLIST_REMOVE(elem, all); + elem->common.cb(elem->common.opaque, ret); + qemu_aio_release(elem); + goto restart; + } else { + /* remove the request */ + QLIST_REMOVE(elem, all); + qemu_aio_release(elem); + } + } +} + +static int thread_pool_active(EventNotifier *notifier) +{ + return !QLIST_EMPTY(&head); +} + +static void thread_pool_cancel(BlockDriverAIOCB *acb) +{ + ThreadPoolElement *elem = (ThreadPoolElement *)acb; + + trace_thread_pool_cancel(elem, elem->common.opaque); + + qemu_mutex_lock(&lock); + if (elem->state == THREAD_QUEUED && + /* No thread has yet started working on elem. we can try to "steal" + * the item from the worker if we can get a signal from the + * semaphore. Because this is non-blocking, we can do it with + * the lock taken and ensure that elem will remain THREAD_QUEUED. + */ + qemu_sem_timedwait(&sem, 0) == 0) { + QTAILQ_REMOVE(&request_list, elem, reqs); + elem->state = THREAD_CANCELED; + event_notifier_set(¬ifier); + } else { + pending_cancellations++; + while (elem->state != THREAD_CANCELED && elem->state != THREAD_DONE) { + qemu_cond_wait(&check_cancel, &lock); + } + pending_cancellations--; + } + qemu_mutex_unlock(&lock); +} + +static AIOPool thread_pool_cb_pool = { + .aiocb_size = sizeof(ThreadPoolElement), + .cancel = thread_pool_cancel, +}; + +BlockDriverAIOCB *thread_pool_submit_aio(ThreadPoolFunc *func, void *arg, + BlockDriverCompletionFunc *cb, void *opaque) +{ + ThreadPoolElement *req; + + req = qemu_aio_get(&thread_pool_cb_pool, NULL, cb, opaque); + req->func = func; + req->arg = arg; + req->state = THREAD_QUEUED; + + QLIST_INSERT_HEAD(&head, req, all); + + trace_thread_pool_submit(req, arg); + + qemu_mutex_lock(&lock); + if (idle_threads == 0 && cur_threads < max_threads) { + spawn_thread(); + } + QTAILQ_INSERT_TAIL(&request_list, req, reqs); + qemu_mutex_unlock(&lock); + qemu_sem_post(&sem); + return &req->common; +} + +typedef struct ThreadPoolCo { + Coroutine *co; + int ret; +} ThreadPoolCo; + +static void thread_pool_co_cb(void *opaque, int ret) +{ + ThreadPoolCo *co = opaque; + + co->ret = ret; + qemu_coroutine_enter(co->co, NULL); +} + +int coroutine_fn thread_pool_submit_co(ThreadPoolFunc *func, void *arg) +{ + ThreadPoolCo tpc = { .co = qemu_coroutine_self(), .ret = -EINPROGRESS }; + assert(qemu_in_coroutine()); + thread_pool_submit_aio(func, arg, thread_pool_co_cb, &tpc); + qemu_coroutine_yield(); + return tpc.ret; +} + +void thread_pool_submit(ThreadPoolFunc *func, void *arg) +{ + thread_pool_submit_aio(func, arg, NULL, NULL); +} + +static void thread_pool_init(void) +{ + QLIST_INIT(&head); + event_notifier_init(¬ifier, false); + qemu_mutex_init(&lock); + qemu_cond_init(&check_cancel); + qemu_sem_init(&sem, 0); + qemu_aio_set_event_notifier(¬ifier, event_notifier_ready, + thread_pool_active); + + QTAILQ_INIT(&request_list); + new_thread_bh = qemu_bh_new(spawn_thread_bh_fn, NULL); +} + +block_init(thread_pool_init) diff --git a/thread-pool.h b/thread-pool.h new file mode 100644 index 0000000000..378a4ac9f9 --- /dev/null +++ b/thread-pool.h @@ -0,0 +1,34 @@ +/* + * QEMU block layer thread pool + * + * Copyright IBM, Corp. 2008 + * Copyright Red Hat, Inc. 2012 + * + * Authors: + * Anthony Liguori + * Paolo Bonzini + * + * This work is licensed under the terms of the GNU GPL, version 2. See + * the COPYING file in the top-level directory. + * + * Contributions after 2012-01-13 are licensed under the terms of the + * GNU GPL, version 2 or (at your option) any later version. + */ + +#ifndef QEMU_THREAD_POOL_H +#define QEMU_THREAD_POOL_H 1 + +#include "qemu-common.h" +#include "qemu-queue.h" +#include "qemu-thread.h" +#include "qemu-coroutine.h" +#include "block_int.h" + +typedef int ThreadPoolFunc(void *opaque); + +BlockDriverAIOCB *thread_pool_submit_aio(ThreadPoolFunc *func, void *arg, + BlockDriverCompletionFunc *cb, void *opaque); +int coroutine_fn thread_pool_submit_co(ThreadPoolFunc *func, void *arg); +void thread_pool_submit(ThreadPoolFunc *func, void *arg); + +#endif diff --git a/trace-events b/trace-events index e2d4580d4c..58c18ebb6c 100644 --- a/trace-events +++ b/trace-events @@ -90,6 +90,11 @@ virtio_blk_rw_complete(void *req, int ret) "req %p ret %d" virtio_blk_handle_write(void *req, uint64_t sector, size_t nsectors) "req %p sector %"PRIu64" nsectors %zu" virtio_blk_handle_read(void *req, uint64_t sector, size_t nsectors) "req %p sector %"PRIu64" nsectors %zu" +# thread-pool.c +thread_pool_submit(void *req, void *opaque) "req %p opaque %p" +thread_pool_complete(void *req, void *opaque, int ret) "req %p opaque %p ret %d" +thread_pool_cancel(void *req, void *opaque) "req %p opaque %p" + # posix-aio-compat.c paio_submit(void *acb, void *opaque, int64_t sector_num, int nb_sectors, int type) "acb %p opaque %p sector_num %"PRId64" nb_sectors %d type %d" paio_complete(void *acb, void *opaque, int ret) "acb %p opaque %p ret %d" From 19d092cf9ba3c01b0e22ef65c499ae7ddc28d0e8 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 31 Oct 2012 10:09:11 +0100 Subject: [PATCH 124/291] threadpool: do not take lock in event_notifier_ready The ordering is: worker thread consumer thread ------------------------------------------------------------------- write ret event_notifier_test_and_clear wmb() read state write state rmb() event_notifier_set read ret Signed-off-by: Paolo Bonzini --- thread-pool.c | 19 +++++++++++++------ 1 file changed, 13 insertions(+), 6 deletions(-) diff --git a/thread-pool.c b/thread-pool.c index 80749b77e0..651b32419b 100644 --- a/thread-pool.c +++ b/thread-pool.c @@ -39,6 +39,11 @@ struct ThreadPoolElement { BlockDriverAIOCB common; ThreadPoolFunc *func; void *arg; + + /* Moving state out of THREAD_QUEUED is protected by lock. After + * that, only the worker thread can write to it. Reads and writes + * of state and ret are ordered with memory barriers. + */ enum ThreadState state; int ret; @@ -95,9 +100,12 @@ static void *worker_thread(void *unused) ret = req->func(req->arg); - qemu_mutex_lock(&lock); - req->state = THREAD_DONE; req->ret = ret; + /* Write ret before state. */ + smp_wmb(); + req->state = THREAD_DONE; + + qemu_mutex_lock(&lock); if (pending_cancellations) { qemu_cond_broadcast(&check_cancel); } @@ -162,11 +170,10 @@ restart: trace_thread_pool_complete(elem, elem->common.opaque, elem->ret); } if (elem->state == THREAD_DONE && elem->common.cb) { - qemu_mutex_lock(&lock); - int ret = elem->ret; - qemu_mutex_unlock(&lock); QLIST_REMOVE(elem, all); - elem->common.cb(elem->common.opaque, ret); + /* Read state before ret. */ + smp_rmb(); + elem->common.cb(elem->common.opaque, elem->ret); qemu_aio_release(elem); goto restart; } else { From 47e6b251a5e9a47c406f2f2c0b01bb88854c98ec Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 24 May 2012 18:03:13 +0200 Subject: [PATCH 125/291] block: switch posix-aio-compat to threadpool This is not meant for portability, but to remove code duplication. Signed-off-by: Paolo Bonzini --- block/raw-posix-aio.h | 1 - block/raw-posix.c | 12 +- posix-aio-compat.c | 425 ++++-------------------------------------- 3 files changed, 40 insertions(+), 398 deletions(-) diff --git a/block/raw-posix-aio.h b/block/raw-posix-aio.h index ba118f616b..6725135dd4 100644 --- a/block/raw-posix-aio.h +++ b/block/raw-posix-aio.h @@ -28,7 +28,6 @@ /* posix-aio-compat.c - thread pool based implementation */ -int paio_init(void); BlockDriverAIOCB *paio_submit(BlockDriverState *bs, int fd, int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, BlockDriverCompletionFunc *cb, void *opaque, int type); diff --git a/block/raw-posix.c b/block/raw-posix.c index 28d439fa81..9ae2c505a8 100644 --- a/block/raw-posix.c +++ b/block/raw-posix.c @@ -266,14 +266,10 @@ static int raw_open_common(BlockDriverState *bs, const char *filename, } s->fd = fd; - /* We're falling back to POSIX AIO in some cases so init always */ - if (paio_init() < 0) { - goto out_close; - } - #ifdef CONFIG_LINUX_AIO if (raw_set_aio(&s->aio_ctx, &s->use_aio, bdrv_flags)) { - goto out_close; + qemu_close(fd); + return -errno; } #endif @@ -284,10 +280,6 @@ static int raw_open_common(BlockDriverState *bs, const char *filename, #endif return 0; - -out_close: - qemu_close(fd); - return -errno; } static int raw_open(BlockDriverState *bs, const char *filename, int flags) diff --git a/posix-aio-compat.c b/posix-aio-compat.c index 96e4daf505..4a1e3d3662 100644 --- a/posix-aio-compat.c +++ b/posix-aio-compat.c @@ -28,13 +28,12 @@ #include "sysemu.h" #include "qemu-common.h" #include "trace.h" +#include "thread-pool.h" #include "block_int.h" #include "iov.h" #include "block/raw-posix-aio.h" -static void do_spawn_thread(void); - struct qemu_paiocb { BlockDriverAIOCB common; int aio_fildes; @@ -46,82 +45,15 @@ struct qemu_paiocb { size_t aio_nbytes; #define aio_ioctl_cmd aio_nbytes /* for QEMU_AIO_IOCTL */ off_t aio_offset; - - QTAILQ_ENTRY(qemu_paiocb) node; int aio_type; - ssize_t ret; - int active; - struct qemu_paiocb *next; }; -typedef struct PosixAioState { - int rfd, wfd; - struct qemu_paiocb *first_aio; -} PosixAioState; - - -static pthread_mutex_t lock = PTHREAD_MUTEX_INITIALIZER; -static pthread_cond_t cond = PTHREAD_COND_INITIALIZER; -static pthread_t thread_id; -static pthread_attr_t attr; -static int max_threads = 64; -static int cur_threads = 0; -static int idle_threads = 0; -static int new_threads = 0; /* backlog of threads we need to create */ -static int pending_threads = 0; /* threads created but not running yet */ -static QEMUBH *new_thread_bh; -static QTAILQ_HEAD(, qemu_paiocb) request_list; - #ifdef CONFIG_PREADV static int preadv_present = 1; #else static int preadv_present = 0; #endif -static void die2(int err, const char *what) -{ - fprintf(stderr, "%s failed: %s\n", what, strerror(err)); - abort(); -} - -static void die(const char *what) -{ - die2(errno, what); -} - -static void mutex_lock(pthread_mutex_t *mutex) -{ - int ret = pthread_mutex_lock(mutex); - if (ret) die2(ret, "pthread_mutex_lock"); -} - -static void mutex_unlock(pthread_mutex_t *mutex) -{ - int ret = pthread_mutex_unlock(mutex); - if (ret) die2(ret, "pthread_mutex_unlock"); -} - -static int cond_timedwait(pthread_cond_t *cond, pthread_mutex_t *mutex, - struct timespec *ts) -{ - int ret = pthread_cond_timedwait(cond, mutex, ts); - if (ret && ret != ETIMEDOUT) die2(ret, "pthread_cond_timedwait"); - return ret; -} - -static void cond_signal(pthread_cond_t *cond) -{ - int ret = pthread_cond_signal(cond); - if (ret) die2(ret, "pthread_cond_signal"); -} - -static void thread_create(pthread_t *thread, pthread_attr_t *attr, - void *(*start_routine)(void*), void *arg) -{ - int ret = pthread_create(thread, attr, start_routine, arg); - if (ret) die2(ret, "pthread_create"); -} - static ssize_t handle_aiocb_ioctl(struct qemu_paiocb *aiocb) { int ret; @@ -310,286 +242,54 @@ static ssize_t handle_aiocb_rw(struct qemu_paiocb *aiocb) return nbytes; } -static void posix_aio_notify_event(void); - -static void *aio_thread(void *unused) +static int aio_worker(void *arg) { - mutex_lock(&lock); - pending_threads--; - mutex_unlock(&lock); - do_spawn_thread(); + struct qemu_paiocb *aiocb = arg; + ssize_t ret = 0; - while (1) { - struct qemu_paiocb *aiocb; - ssize_t ret = 0; - qemu_timeval tv; - struct timespec ts; + switch (aiocb->aio_type & QEMU_AIO_TYPE_MASK) { + case QEMU_AIO_READ: + ret = handle_aiocb_rw(aiocb); + if (ret >= 0 && ret < aiocb->aio_nbytes && aiocb->common.bs->growable) { + /* A short read means that we have reached EOF. Pad the buffer + * with zeros for bytes after EOF. */ + iov_memset(aiocb->aio_iov, aiocb->aio_niov, ret, + 0, aiocb->aio_nbytes - ret); - qemu_gettimeofday(&tv); - ts.tv_sec = tv.tv_sec + 10; - ts.tv_nsec = 0; - - mutex_lock(&lock); - - while (QTAILQ_EMPTY(&request_list) && - !(ret == ETIMEDOUT)) { - idle_threads++; - ret = cond_timedwait(&cond, &lock, &ts); - idle_threads--; + ret = aiocb->aio_nbytes; } - - if (QTAILQ_EMPTY(&request_list)) - break; - - aiocb = QTAILQ_FIRST(&request_list); - QTAILQ_REMOVE(&request_list, aiocb, node); - aiocb->active = 1; - mutex_unlock(&lock); - - switch (aiocb->aio_type & QEMU_AIO_TYPE_MASK) { - case QEMU_AIO_READ: - ret = handle_aiocb_rw(aiocb); - if (ret >= 0 && ret < aiocb->aio_nbytes && aiocb->common.bs->growable) { - /* A short read means that we have reached EOF. Pad the buffer - * with zeros for bytes after EOF. */ - iov_memset(aiocb->aio_iov, aiocb->aio_niov, ret, - 0, aiocb->aio_nbytes - ret); - - ret = aiocb->aio_nbytes; - } - break; - case QEMU_AIO_WRITE: - ret = handle_aiocb_rw(aiocb); - break; - case QEMU_AIO_FLUSH: - ret = handle_aiocb_flush(aiocb); - break; - case QEMU_AIO_IOCTL: - ret = handle_aiocb_ioctl(aiocb); - break; - default: - fprintf(stderr, "invalid aio request (0x%x)\n", aiocb->aio_type); + if (ret == aiocb->aio_nbytes) { + ret = 0; + } else if (ret >= 0 && ret < aiocb->aio_nbytes) { ret = -EINVAL; - break; } - - mutex_lock(&lock); - aiocb->ret = ret; - mutex_unlock(&lock); - - posix_aio_notify_event(); - } - - cur_threads--; - mutex_unlock(&lock); - - return NULL; -} - -static void do_spawn_thread(void) -{ - sigset_t set, oldset; - - mutex_lock(&lock); - if (!new_threads) { - mutex_unlock(&lock); - return; - } - - new_threads--; - pending_threads++; - - mutex_unlock(&lock); - - /* block all signals */ - if (sigfillset(&set)) die("sigfillset"); - if (sigprocmask(SIG_SETMASK, &set, &oldset)) die("sigprocmask"); - - thread_create(&thread_id, &attr, aio_thread, NULL); - - if (sigprocmask(SIG_SETMASK, &oldset, NULL)) die("sigprocmask restore"); -} - -static void spawn_thread_bh_fn(void *opaque) -{ - do_spawn_thread(); -} - -static void spawn_thread(void) -{ - cur_threads++; - new_threads++; - /* If there are threads being created, they will spawn new workers, so - * we don't spend time creating many threads in a loop holding a mutex or - * starving the current vcpu. - * - * If there are no idle threads, ask the main thread to create one, so we - * inherit the correct affinity instead of the vcpu affinity. - */ - if (!pending_threads) { - qemu_bh_schedule(new_thread_bh); - } -} - -static void qemu_paio_submit(struct qemu_paiocb *aiocb) -{ - aiocb->ret = -EINPROGRESS; - aiocb->active = 0; - mutex_lock(&lock); - if (idle_threads == 0 && cur_threads < max_threads) - spawn_thread(); - QTAILQ_INSERT_TAIL(&request_list, aiocb, node); - mutex_unlock(&lock); - cond_signal(&cond); -} - -static ssize_t qemu_paio_return(struct qemu_paiocb *aiocb) -{ - ssize_t ret; - - mutex_lock(&lock); - ret = aiocb->ret; - mutex_unlock(&lock); - - return ret; -} - -static int qemu_paio_error(struct qemu_paiocb *aiocb) -{ - ssize_t ret = qemu_paio_return(aiocb); - - if (ret < 0) - ret = -ret; - else - ret = 0; - - return ret; -} - -static void posix_aio_read(void *opaque) -{ - PosixAioState *s = opaque; - struct qemu_paiocb *acb, **pacb; - int ret; - ssize_t len; - - /* read all bytes from signal pipe */ - for (;;) { - char bytes[16]; - - len = read(s->rfd, bytes, sizeof(bytes)); - if (len == -1 && errno == EINTR) - continue; /* try again */ - if (len == sizeof(bytes)) - continue; /* more to read */ + break; + case QEMU_AIO_WRITE: + ret = handle_aiocb_rw(aiocb); + if (ret == aiocb->aio_nbytes) { + ret = 0; + } else if (ret >= 0 && ret < aiocb->aio_nbytes) { + ret = -EINVAL; + } + break; + case QEMU_AIO_FLUSH: + ret = handle_aiocb_flush(aiocb); + break; + case QEMU_AIO_IOCTL: + ret = handle_aiocb_ioctl(aiocb); + break; + default: + fprintf(stderr, "invalid aio request (0x%x)\n", aiocb->aio_type); + ret = -EINVAL; break; } - for(;;) { - pacb = &s->first_aio; - for(;;) { - acb = *pacb; - if (!acb) - return; - - ret = qemu_paio_error(acb); - if (ret == ECANCELED) { - /* remove the request */ - *pacb = acb->next; - qemu_aio_release(acb); - } else if (ret != EINPROGRESS) { - /* end of aio */ - if (ret == 0) { - ret = qemu_paio_return(acb); - if (ret == acb->aio_nbytes) - ret = 0; - else - ret = -EINVAL; - } else { - ret = -ret; - } - - trace_paio_complete(acb, acb->common.opaque, ret); - - /* remove the request */ - *pacb = acb->next; - /* call the callback */ - acb->common.cb(acb->common.opaque, ret); - qemu_aio_release(acb); - break; - } else { - pacb = &acb->next; - } - } - } -} - -static int posix_aio_flush(void *opaque) -{ - PosixAioState *s = opaque; - return !!s->first_aio; -} - -static PosixAioState *posix_aio_state; - -static void posix_aio_notify_event(void) -{ - char byte = 0; - ssize_t ret; - - ret = write(posix_aio_state->wfd, &byte, sizeof(byte)); - if (ret < 0 && errno != EAGAIN) - die("write()"); -} - -static void paio_remove(struct qemu_paiocb *acb) -{ - struct qemu_paiocb **pacb; - - /* remove the callback from the queue */ - pacb = &posix_aio_state->first_aio; - for(;;) { - if (*pacb == NULL) { - fprintf(stderr, "paio_remove: aio request not found!\n"); - break; - } else if (*pacb == acb) { - *pacb = acb->next; - qemu_aio_release(acb); - break; - } - pacb = &(*pacb)->next; - } -} - -static void paio_cancel(BlockDriverAIOCB *blockacb) -{ - struct qemu_paiocb *acb = (struct qemu_paiocb *)blockacb; - int active = 0; - - trace_paio_cancel(acb, acb->common.opaque); - - mutex_lock(&lock); - if (!acb->active) { - QTAILQ_REMOVE(&request_list, acb, node); - acb->ret = -ECANCELED; - } else if (acb->ret == -EINPROGRESS) { - active = 1; - } - mutex_unlock(&lock); - - if (active) { - /* fail safe: if the aio could not be canceled, we wait for - it */ - while (qemu_paio_error(acb) == EINPROGRESS) - ; - } - - paio_remove(acb); + qemu_aio_release(aiocb); + return ret; } static AIOPool raw_aio_pool = { .aiocb_size = sizeof(struct qemu_paiocb), - .cancel = paio_cancel, }; BlockDriverAIOCB *paio_submit(BlockDriverState *bs, int fd, @@ -609,12 +309,8 @@ BlockDriverAIOCB *paio_submit(BlockDriverState *bs, int fd, acb->aio_nbytes = nb_sectors * 512; acb->aio_offset = sector_num * 512; - acb->next = posix_aio_state->first_aio; - posix_aio_state->first_aio = acb; - trace_paio_submit(acb, opaque, sector_num, nb_sectors, type); - qemu_paio_submit(acb); - return &acb->common; + return thread_pool_submit_aio(aio_worker, acb, cb, opaque); } BlockDriverAIOCB *paio_ioctl(BlockDriverState *bs, int fd, @@ -630,50 +326,5 @@ BlockDriverAIOCB *paio_ioctl(BlockDriverState *bs, int fd, acb->aio_ioctl_buf = buf; acb->aio_ioctl_cmd = req; - acb->next = posix_aio_state->first_aio; - posix_aio_state->first_aio = acb; - - qemu_paio_submit(acb); - return &acb->common; -} - -int paio_init(void) -{ - PosixAioState *s; - int fds[2]; - int ret; - - if (posix_aio_state) - return 0; - - s = g_malloc(sizeof(PosixAioState)); - - s->first_aio = NULL; - if (qemu_pipe(fds) == -1) { - fprintf(stderr, "failed to create pipe\n"); - g_free(s); - return -1; - } - - s->rfd = fds[0]; - s->wfd = fds[1]; - - fcntl(s->rfd, F_SETFL, O_NONBLOCK); - fcntl(s->wfd, F_SETFL, O_NONBLOCK); - - qemu_aio_set_fd_handler(s->rfd, posix_aio_read, NULL, posix_aio_flush, s); - - ret = pthread_attr_init(&attr); - if (ret) - die2(ret, "pthread_attr_init"); - - ret = pthread_attr_setdetachstate(&attr, PTHREAD_CREATE_DETACHED); - if (ret) - die2(ret, "pthread_attr_setdetachstate"); - - QTAILQ_INIT(&request_list); - new_thread_bh = qemu_bh_new(spawn_thread_bh_fn, NULL); - - posix_aio_state = s; - return 0; + return thread_pool_submit_aio(aio_worker, acb, cb, opaque); } From de81a169366c2e3e0c47d0be637cc450b71aac67 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 25 May 2012 11:46:27 +0200 Subject: [PATCH 126/291] raw: merge posix-aio-compat.c into block/raw-posix.c Making the qemu_paiocb specific to raw devices will let us access members of the BDRVRawState arbitrarily. Signed-off-by: Paolo Bonzini --- Makefile.objs | 1 - block/raw-posix-aio.h | 8 - block/raw-posix.c | 294 +++++++++++++++++++++++++++++++++++++ posix-aio-compat.c | 330 ------------------------------------------ 4 files changed, 294 insertions(+), 339 deletions(-) delete mode 100644 posix-aio-compat.c diff --git a/Makefile.objs b/Makefile.objs index f8ae0316b8..35c2355e82 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -45,7 +45,6 @@ block-obj-y = iov.o cache-utils.o qemu-option.o module.o async.o block-obj-y += nbd.o block.o blockjob.o aes.o qemu-config.o block-obj-y += thread-pool.o qemu-progress.o qemu-sockets.o uri.o notify.o block-obj-y += $(coroutine-obj-y) $(qobject-obj-y) $(version-obj-y) -block-obj-$(CONFIG_POSIX) += posix-aio-compat.o block-obj-$(CONFIG_POSIX) += event_notifier-posix.o aio-posix.o block-obj-$(CONFIG_WIN32) += event_notifier-win32.o aio-win32.o block-obj-$(CONFIG_LINUX_AIO) += linux-aio.o diff --git a/block/raw-posix-aio.h b/block/raw-posix-aio.h index 6725135dd4..c714367401 100644 --- a/block/raw-posix-aio.h +++ b/block/raw-posix-aio.h @@ -27,14 +27,6 @@ #define QEMU_AIO_MISALIGNED 0x1000 -/* posix-aio-compat.c - thread pool based implementation */ -BlockDriverAIOCB *paio_submit(BlockDriverState *bs, int fd, - int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, - BlockDriverCompletionFunc *cb, void *opaque, int type); -BlockDriverAIOCB *paio_ioctl(BlockDriverState *bs, int fd, - unsigned long int req, void *buf, - BlockDriverCompletionFunc *cb, void *opaque); - /* linux-aio.c - Linux native implementation */ void *laio_init(void); BlockDriverAIOCB *laio_submit(BlockDriverState *bs, void *aio_ctx, int fd, diff --git a/block/raw-posix.c b/block/raw-posix.c index 9ae2c505a8..4d6d5df5bc 100644 --- a/block/raw-posix.c +++ b/block/raw-posix.c @@ -27,6 +27,9 @@ #include "qemu-log.h" #include "block_int.h" #include "module.h" +#include "trace.h" +#include "thread-pool.h" +#include "iov.h" #include "block/raw-posix-aio.h" #if defined(__APPLE__) && (__MACH__) @@ -149,6 +152,20 @@ typedef struct BDRVRawReopenState { static int fd_open(BlockDriverState *bs); static int64_t raw_getlength(BlockDriverState *bs); +typedef struct RawPosixAIOData { + BlockDriverState *bs; + int aio_fildes; + union { + struct iovec *aio_iov; + void *aio_ioctl_buf; + }; + int aio_niov; + size_t aio_nbytes; +#define aio_ioctl_cmd aio_nbytes /* for QEMU_AIO_IOCTL */ + off_t aio_offset; + int aio_type; +} RawPosixAIOData; + #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__) static int cdrom_reopen(BlockDriverState *bs); #endif @@ -426,6 +443,283 @@ static int qiov_is_aligned(BlockDriverState *bs, QEMUIOVector *qiov) return 1; } +static ssize_t handle_aiocb_ioctl(RawPosixAIOData *aiocb) +{ + int ret; + + ret = ioctl(aiocb->aio_fildes, aiocb->aio_ioctl_cmd, aiocb->aio_ioctl_buf); + if (ret == -1) { + return -errno; + } + + /* + * This looks weird, but the aio code only considers a request + * successful if it has written the full number of bytes. + * + * Now we overload aio_nbytes as aio_ioctl_cmd for the ioctl command, + * so in fact we return the ioctl command here to make posix_aio_read() + * happy.. + */ + return aiocb->aio_nbytes; +} + +static ssize_t handle_aiocb_flush(RawPosixAIOData *aiocb) +{ + int ret; + + ret = qemu_fdatasync(aiocb->aio_fildes); + if (ret == -1) { + return -errno; + } + return 0; +} + +#ifdef CONFIG_PREADV + +static bool preadv_present = true; + +static ssize_t +qemu_preadv(int fd, const struct iovec *iov, int nr_iov, off_t offset) +{ + return preadv(fd, iov, nr_iov, offset); +} + +static ssize_t +qemu_pwritev(int fd, const struct iovec *iov, int nr_iov, off_t offset) +{ + return pwritev(fd, iov, nr_iov, offset); +} + +#else + +static bool preadv_present = false; + +static ssize_t +qemu_preadv(int fd, const struct iovec *iov, int nr_iov, off_t offset) +{ + return -ENOSYS; +} + +static ssize_t +qemu_pwritev(int fd, const struct iovec *iov, int nr_iov, off_t offset) +{ + return -ENOSYS; +} + +#endif + +static ssize_t handle_aiocb_rw_vector(RawPosixAIOData *aiocb) +{ + ssize_t len; + + do { + if (aiocb->aio_type & QEMU_AIO_WRITE) + len = qemu_pwritev(aiocb->aio_fildes, + aiocb->aio_iov, + aiocb->aio_niov, + aiocb->aio_offset); + else + len = qemu_preadv(aiocb->aio_fildes, + aiocb->aio_iov, + aiocb->aio_niov, + aiocb->aio_offset); + } while (len == -1 && errno == EINTR); + + if (len == -1) { + return -errno; + } + return len; +} + +/* + * Read/writes the data to/from a given linear buffer. + * + * Returns the number of bytes handles or -errno in case of an error. Short + * reads are only returned if the end of the file is reached. + */ +static ssize_t handle_aiocb_rw_linear(RawPosixAIOData *aiocb, char *buf) +{ + ssize_t offset = 0; + ssize_t len; + + while (offset < aiocb->aio_nbytes) { + if (aiocb->aio_type & QEMU_AIO_WRITE) { + len = pwrite(aiocb->aio_fildes, + (const char *)buf + offset, + aiocb->aio_nbytes - offset, + aiocb->aio_offset + offset); + } else { + len = pread(aiocb->aio_fildes, + buf + offset, + aiocb->aio_nbytes - offset, + aiocb->aio_offset + offset); + } + if (len == -1 && errno == EINTR) { + continue; + } else if (len == -1) { + offset = -errno; + break; + } else if (len == 0) { + break; + } + offset += len; + } + + return offset; +} + +static ssize_t handle_aiocb_rw(RawPosixAIOData *aiocb) +{ + ssize_t nbytes; + char *buf; + + if (!(aiocb->aio_type & QEMU_AIO_MISALIGNED)) { + /* + * If there is just a single buffer, and it is properly aligned + * we can just use plain pread/pwrite without any problems. + */ + if (aiocb->aio_niov == 1) { + return handle_aiocb_rw_linear(aiocb, aiocb->aio_iov->iov_base); + } + /* + * We have more than one iovec, and all are properly aligned. + * + * Try preadv/pwritev first and fall back to linearizing the + * buffer if it's not supported. + */ + if (preadv_present) { + nbytes = handle_aiocb_rw_vector(aiocb); + if (nbytes == aiocb->aio_nbytes || + (nbytes < 0 && nbytes != -ENOSYS)) { + return nbytes; + } + preadv_present = false; + } + + /* + * XXX(hch): short read/write. no easy way to handle the reminder + * using these interfaces. For now retry using plain + * pread/pwrite? + */ + } + + /* + * Ok, we have to do it the hard way, copy all segments into + * a single aligned buffer. + */ + buf = qemu_blockalign(aiocb->bs, aiocb->aio_nbytes); + if (aiocb->aio_type & QEMU_AIO_WRITE) { + char *p = buf; + int i; + + for (i = 0; i < aiocb->aio_niov; ++i) { + memcpy(p, aiocb->aio_iov[i].iov_base, aiocb->aio_iov[i].iov_len); + p += aiocb->aio_iov[i].iov_len; + } + } + + nbytes = handle_aiocb_rw_linear(aiocb, buf); + if (!(aiocb->aio_type & QEMU_AIO_WRITE)) { + char *p = buf; + size_t count = aiocb->aio_nbytes, copy; + int i; + + for (i = 0; i < aiocb->aio_niov && count; ++i) { + copy = count; + if (copy > aiocb->aio_iov[i].iov_len) { + copy = aiocb->aio_iov[i].iov_len; + } + memcpy(aiocb->aio_iov[i].iov_base, p, copy); + p += copy; + count -= copy; + } + } + qemu_vfree(buf); + + return nbytes; +} + +static int aio_worker(void *arg) +{ + RawPosixAIOData *aiocb = arg; + ssize_t ret = 0; + + switch (aiocb->aio_type & QEMU_AIO_TYPE_MASK) { + case QEMU_AIO_READ: + ret = handle_aiocb_rw(aiocb); + if (ret >= 0 && ret < aiocb->aio_nbytes && aiocb->bs->growable) { + iov_memset(aiocb->aio_iov, aiocb->aio_niov, ret, + 0, aiocb->aio_nbytes - ret); + + ret = aiocb->aio_nbytes; + } + if (ret == aiocb->aio_nbytes) { + ret = 0; + } else if (ret >= 0 && ret < aiocb->aio_nbytes) { + ret = -EINVAL; + } + break; + case QEMU_AIO_WRITE: + ret = handle_aiocb_rw(aiocb); + if (ret == aiocb->aio_nbytes) { + ret = 0; + } else if (ret >= 0 && ret < aiocb->aio_nbytes) { + ret = -EINVAL; + } + break; + case QEMU_AIO_FLUSH: + ret = handle_aiocb_flush(aiocb); + break; + case QEMU_AIO_IOCTL: + ret = handle_aiocb_ioctl(aiocb); + break; + default: + fprintf(stderr, "invalid aio request (0x%x)\n", aiocb->aio_type); + ret = -EINVAL; + break; + } + + g_slice_free(RawPosixAIOData, aiocb); + return ret; +} + +static BlockDriverAIOCB *paio_submit(BlockDriverState *bs, int fd, + int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, + BlockDriverCompletionFunc *cb, void *opaque, int type) +{ + RawPosixAIOData *acb = g_slice_new(RawPosixAIOData); + + acb->bs = bs; + acb->aio_type = type; + acb->aio_fildes = fd; + + if (qiov) { + acb->aio_iov = qiov->iov; + acb->aio_niov = qiov->niov; + } + acb->aio_nbytes = nb_sectors * 512; + acb->aio_offset = sector_num * 512; + + trace_paio_submit(acb, opaque, sector_num, nb_sectors, type); + return thread_pool_submit_aio(aio_worker, acb, cb, opaque); +} + +static BlockDriverAIOCB *paio_ioctl(BlockDriverState *bs, int fd, + unsigned long int req, void *buf, + BlockDriverCompletionFunc *cb, void *opaque) +{ + RawPosixAIOData *acb = g_slice_new(RawPosixAIOData); + + acb->bs = bs; + acb->aio_type = QEMU_AIO_IOCTL; + acb->aio_fildes = fd; + acb->aio_offset = 0; + acb->aio_ioctl_buf = buf; + acb->aio_ioctl_cmd = req; + + return thread_pool_submit_aio(aio_worker, acb, cb, opaque); +} + static BlockDriverAIOCB *raw_aio_submit(BlockDriverState *bs, int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, BlockDriverCompletionFunc *cb, void *opaque, int type) diff --git a/posix-aio-compat.c b/posix-aio-compat.c deleted file mode 100644 index 4a1e3d3662..0000000000 --- a/posix-aio-compat.c +++ /dev/null @@ -1,330 +0,0 @@ -/* - * QEMU posix-aio emulation - * - * Copyright IBM, Corp. 2008 - * - * Authors: - * Anthony Liguori - * - * This work is licensed under the terms of the GNU GPL, version 2. See - * the COPYING file in the top-level directory. - * - * Contributions after 2012-01-13 are licensed under the terms of the - * GNU GPL, version 2 or (at your option) any later version. - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "qemu-queue.h" -#include "osdep.h" -#include "sysemu.h" -#include "qemu-common.h" -#include "trace.h" -#include "thread-pool.h" -#include "block_int.h" -#include "iov.h" - -#include "block/raw-posix-aio.h" - -struct qemu_paiocb { - BlockDriverAIOCB common; - int aio_fildes; - union { - struct iovec *aio_iov; - void *aio_ioctl_buf; - }; - int aio_niov; - size_t aio_nbytes; -#define aio_ioctl_cmd aio_nbytes /* for QEMU_AIO_IOCTL */ - off_t aio_offset; - int aio_type; -}; - -#ifdef CONFIG_PREADV -static int preadv_present = 1; -#else -static int preadv_present = 0; -#endif - -static ssize_t handle_aiocb_ioctl(struct qemu_paiocb *aiocb) -{ - int ret; - - ret = ioctl(aiocb->aio_fildes, aiocb->aio_ioctl_cmd, aiocb->aio_ioctl_buf); - if (ret == -1) - return -errno; - - /* - * This looks weird, but the aio code only considers a request - * successful if it has written the full number of bytes. - * - * Now we overload aio_nbytes as aio_ioctl_cmd for the ioctl command, - * so in fact we return the ioctl command here to make posix_aio_read() - * happy.. - */ - return aiocb->aio_nbytes; -} - -static ssize_t handle_aiocb_flush(struct qemu_paiocb *aiocb) -{ - int ret; - - ret = qemu_fdatasync(aiocb->aio_fildes); - if (ret == -1) - return -errno; - return 0; -} - -#ifdef CONFIG_PREADV - -static ssize_t -qemu_preadv(int fd, const struct iovec *iov, int nr_iov, off_t offset) -{ - return preadv(fd, iov, nr_iov, offset); -} - -static ssize_t -qemu_pwritev(int fd, const struct iovec *iov, int nr_iov, off_t offset) -{ - return pwritev(fd, iov, nr_iov, offset); -} - -#else - -static ssize_t -qemu_preadv(int fd, const struct iovec *iov, int nr_iov, off_t offset) -{ - return -ENOSYS; -} - -static ssize_t -qemu_pwritev(int fd, const struct iovec *iov, int nr_iov, off_t offset) -{ - return -ENOSYS; -} - -#endif - -static ssize_t handle_aiocb_rw_vector(struct qemu_paiocb *aiocb) -{ - ssize_t len; - - do { - if (aiocb->aio_type & QEMU_AIO_WRITE) - len = qemu_pwritev(aiocb->aio_fildes, - aiocb->aio_iov, - aiocb->aio_niov, - aiocb->aio_offset); - else - len = qemu_preadv(aiocb->aio_fildes, - aiocb->aio_iov, - aiocb->aio_niov, - aiocb->aio_offset); - } while (len == -1 && errno == EINTR); - - if (len == -1) - return -errno; - return len; -} - -/* - * Read/writes the data to/from a given linear buffer. - * - * Returns the number of bytes handles or -errno in case of an error. Short - * reads are only returned if the end of the file is reached. - */ -static ssize_t handle_aiocb_rw_linear(struct qemu_paiocb *aiocb, char *buf) -{ - ssize_t offset = 0; - ssize_t len; - - while (offset < aiocb->aio_nbytes) { - if (aiocb->aio_type & QEMU_AIO_WRITE) - len = pwrite(aiocb->aio_fildes, - (const char *)buf + offset, - aiocb->aio_nbytes - offset, - aiocb->aio_offset + offset); - else - len = pread(aiocb->aio_fildes, - buf + offset, - aiocb->aio_nbytes - offset, - aiocb->aio_offset + offset); - - if (len == -1 && errno == EINTR) - continue; - else if (len == -1) { - offset = -errno; - break; - } else if (len == 0) - break; - - offset += len; - } - - return offset; -} - -static ssize_t handle_aiocb_rw(struct qemu_paiocb *aiocb) -{ - ssize_t nbytes; - char *buf; - - if (!(aiocb->aio_type & QEMU_AIO_MISALIGNED)) { - /* - * If there is just a single buffer, and it is properly aligned - * we can just use plain pread/pwrite without any problems. - */ - if (aiocb->aio_niov == 1) - return handle_aiocb_rw_linear(aiocb, aiocb->aio_iov->iov_base); - - /* - * We have more than one iovec, and all are properly aligned. - * - * Try preadv/pwritev first and fall back to linearizing the - * buffer if it's not supported. - */ - if (preadv_present) { - nbytes = handle_aiocb_rw_vector(aiocb); - if (nbytes == aiocb->aio_nbytes) - return nbytes; - if (nbytes < 0 && nbytes != -ENOSYS) - return nbytes; - preadv_present = 0; - } - - /* - * XXX(hch): short read/write. no easy way to handle the reminder - * using these interfaces. For now retry using plain - * pread/pwrite? - */ - } - - /* - * Ok, we have to do it the hard way, copy all segments into - * a single aligned buffer. - */ - buf = qemu_blockalign(aiocb->common.bs, aiocb->aio_nbytes); - if (aiocb->aio_type & QEMU_AIO_WRITE) { - char *p = buf; - int i; - - for (i = 0; i < aiocb->aio_niov; ++i) { - memcpy(p, aiocb->aio_iov[i].iov_base, aiocb->aio_iov[i].iov_len); - p += aiocb->aio_iov[i].iov_len; - } - } - - nbytes = handle_aiocb_rw_linear(aiocb, buf); - if (!(aiocb->aio_type & QEMU_AIO_WRITE)) { - char *p = buf; - size_t count = aiocb->aio_nbytes, copy; - int i; - - for (i = 0; i < aiocb->aio_niov && count; ++i) { - copy = count; - if (copy > aiocb->aio_iov[i].iov_len) - copy = aiocb->aio_iov[i].iov_len; - memcpy(aiocb->aio_iov[i].iov_base, p, copy); - p += copy; - count -= copy; - } - } - qemu_vfree(buf); - - return nbytes; -} - -static int aio_worker(void *arg) -{ - struct qemu_paiocb *aiocb = arg; - ssize_t ret = 0; - - switch (aiocb->aio_type & QEMU_AIO_TYPE_MASK) { - case QEMU_AIO_READ: - ret = handle_aiocb_rw(aiocb); - if (ret >= 0 && ret < aiocb->aio_nbytes && aiocb->common.bs->growable) { - /* A short read means that we have reached EOF. Pad the buffer - * with zeros for bytes after EOF. */ - iov_memset(aiocb->aio_iov, aiocb->aio_niov, ret, - 0, aiocb->aio_nbytes - ret); - - ret = aiocb->aio_nbytes; - } - if (ret == aiocb->aio_nbytes) { - ret = 0; - } else if (ret >= 0 && ret < aiocb->aio_nbytes) { - ret = -EINVAL; - } - break; - case QEMU_AIO_WRITE: - ret = handle_aiocb_rw(aiocb); - if (ret == aiocb->aio_nbytes) { - ret = 0; - } else if (ret >= 0 && ret < aiocb->aio_nbytes) { - ret = -EINVAL; - } - break; - case QEMU_AIO_FLUSH: - ret = handle_aiocb_flush(aiocb); - break; - case QEMU_AIO_IOCTL: - ret = handle_aiocb_ioctl(aiocb); - break; - default: - fprintf(stderr, "invalid aio request (0x%x)\n", aiocb->aio_type); - ret = -EINVAL; - break; - } - - qemu_aio_release(aiocb); - return ret; -} - -static AIOPool raw_aio_pool = { - .aiocb_size = sizeof(struct qemu_paiocb), -}; - -BlockDriverAIOCB *paio_submit(BlockDriverState *bs, int fd, - int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, - BlockDriverCompletionFunc *cb, void *opaque, int type) -{ - struct qemu_paiocb *acb; - - acb = qemu_aio_get(&raw_aio_pool, bs, cb, opaque); - acb->aio_type = type; - acb->aio_fildes = fd; - - if (qiov) { - acb->aio_iov = qiov->iov; - acb->aio_niov = qiov->niov; - } - acb->aio_nbytes = nb_sectors * 512; - acb->aio_offset = sector_num * 512; - - trace_paio_submit(acb, opaque, sector_num, nb_sectors, type); - return thread_pool_submit_aio(aio_worker, acb, cb, opaque); -} - -BlockDriverAIOCB *paio_ioctl(BlockDriverState *bs, int fd, - unsigned long int req, void *buf, - BlockDriverCompletionFunc *cb, void *opaque) -{ - struct qemu_paiocb *acb; - - acb = qemu_aio_get(&raw_aio_pool, bs, cb, opaque); - acb->aio_type = QEMU_AIO_IOCTL; - acb->aio_fildes = fd; - acb->aio_offset = 0; - acb->aio_ioctl_buf = buf; - acb->aio_ioctl_cmd = req; - - return thread_pool_submit_aio(aio_worker, acb, cb, opaque); -} From 9f8540ecef6fc5ededa825d766c8bcd1987884dd Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Sat, 9 Jun 2012 10:57:37 +0200 Subject: [PATCH 127/291] raw-posix: rename raw-posix-aio.h, hide unavailable prototypes Signed-off-by: Paolo Bonzini --- block/{raw-posix-aio.h => raw-aio.h} | 10 ++++++---- block/raw-posix.c | 2 +- linux-aio.c | 2 +- 3 files changed, 8 insertions(+), 6 deletions(-) rename block/{raw-posix-aio.h => raw-aio.h} (86%) diff --git a/block/raw-posix-aio.h b/block/raw-aio.h similarity index 86% rename from block/raw-posix-aio.h rename to block/raw-aio.h index c714367401..b3bb07377e 100644 --- a/block/raw-posix-aio.h +++ b/block/raw-aio.h @@ -1,5 +1,5 @@ /* - * QEMU Posix block I/O backend AIO support + * Declarations for AIO in the raw protocol * * Copyright IBM, Corp. 2008 * @@ -12,8 +12,8 @@ * Contributions after 2012-01-13 are licensed under the terms of the * GNU GPL, version 2 or (at your option) any later version. */ -#ifndef QEMU_RAW_POSIX_AIO_H -#define QEMU_RAW_POSIX_AIO_H +#ifndef QEMU_RAW_AIO_H +#define QEMU_RAW_AIO_H /* AIO request types */ #define QEMU_AIO_READ 0x0001 @@ -28,9 +28,11 @@ /* linux-aio.c - Linux native implementation */ +#ifdef CONFIG_LINUX_AIO void *laio_init(void); BlockDriverAIOCB *laio_submit(BlockDriverState *bs, void *aio_ctx, int fd, int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, BlockDriverCompletionFunc *cb, void *opaque, int type); +#endif -#endif /* QEMU_RAW_POSIX_AIO_H */ +#endif /* QEMU_RAW_AIO_H */ diff --git a/block/raw-posix.c b/block/raw-posix.c index 4d6d5df5bc..f2f0404f6f 100644 --- a/block/raw-posix.c +++ b/block/raw-posix.c @@ -30,7 +30,7 @@ #include "trace.h" #include "thread-pool.h" #include "iov.h" -#include "block/raw-posix-aio.h" +#include "raw-aio.h" #if defined(__APPLE__) && (__MACH__) #include diff --git a/linux-aio.c b/linux-aio.c index d1afb460c2..6ca984dbe8 100644 --- a/linux-aio.c +++ b/linux-aio.c @@ -10,7 +10,7 @@ #include "qemu-common.h" #include "qemu-aio.h" #include "qemu-queue.h" -#include "block/raw-posix-aio.h" +#include "block/raw-aio.h" #include "event_notifier.h" #include From fc4edb84bfc49e4ed6c1a54c8ac037e9a7479fc8 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Sat, 9 Jun 2012 04:48:28 +0200 Subject: [PATCH 128/291] raw-win32: add emulated AIO support Signed-off-by: Paolo Bonzini --- block/raw-win32.c | 187 ++++++++++++++++++++++++++++++++++------------ 1 file changed, 138 insertions(+), 49 deletions(-) diff --git a/block/raw-win32.c b/block/raw-win32.c index 78c830648b..ffd86e3f38 100644 --- a/block/raw-win32.c +++ b/block/raw-win32.c @@ -25,6 +25,10 @@ #include "qemu-timer.h" #include "block_int.h" #include "module.h" +#include "raw-aio.h" +#include "trace.h" +#include "thread-pool.h" +#include "iov.h" #include #include @@ -32,12 +36,127 @@ #define FTYPE_CD 1 #define FTYPE_HARDDISK 2 +typedef struct RawWin32AIOData { + BlockDriverState *bs; + HANDLE hfile; + struct iovec *aio_iov; + int aio_niov; + size_t aio_nbytes; + off64_t aio_offset; + int aio_type; +} RawWin32AIOData; + typedef struct BDRVRawState { HANDLE hfile; int type; char drive_path[16]; /* format: "d:\" */ } BDRVRawState; +/* + * Read/writes the data to/from a given linear buffer. + * + * Returns the number of bytes handles or -errno in case of an error. Short + * reads are only returned if the end of the file is reached. + */ +static size_t handle_aiocb_rw(RawWin32AIOData *aiocb) +{ + size_t offset = 0; + int i; + + for (i = 0; i < aiocb->aio_niov; i++) { + OVERLAPPED ov; + DWORD ret, ret_count, len; + + memset(&ov, 0, sizeof(ov)); + ov.Offset = (aiocb->aio_offset + offset); + ov.OffsetHigh = (aiocb->aio_offset + offset) >> 32; + len = aiocb->aio_iov[i].iov_len; + if (aiocb->aio_type & QEMU_AIO_WRITE) { + ret = WriteFile(aiocb->hfile, aiocb->aio_iov[i].iov_base, + len, &ret_count, &ov); + } else { + ret = ReadFile(aiocb->hfile, aiocb->aio_iov[i].iov_base, + len, &ret_count, &ov); + } + if (!ret) { + ret_count = 0; + } + if (ret_count != len) { + break; + } + offset += len; + } + + return offset; +} + +static int aio_worker(void *arg) +{ + RawWin32AIOData *aiocb = arg; + ssize_t ret = 0; + size_t count; + + switch (aiocb->aio_type & QEMU_AIO_TYPE_MASK) { + case QEMU_AIO_READ: + count = handle_aiocb_rw(aiocb); + if (count < aiocb->aio_nbytes && aiocb->bs->growable) { + /* A short read means that we have reached EOF. Pad the buffer + * with zeros for bytes after EOF. */ + iov_memset(aiocb->aio_iov, aiocb->aio_niov, count, + 0, aiocb->aio_nbytes - count); + + count = aiocb->aio_nbytes; + } + if (count == aiocb->aio_nbytes) { + ret = 0; + } else { + ret = -EINVAL; + } + break; + case QEMU_AIO_WRITE: + count = handle_aiocb_rw(aiocb); + if (count == aiocb->aio_nbytes) { + count = 0; + } else { + count = -EINVAL; + } + break; + case QEMU_AIO_FLUSH: + if (!FlushFileBuffers(aiocb->hfile)) { + return -EIO; + } + break; + default: + fprintf(stderr, "invalid aio request (0x%x)\n", aiocb->aio_type); + ret = -EINVAL; + break; + } + + g_slice_free(RawWin32AIOData, aiocb); + return ret; +} + +static BlockDriverAIOCB *paio_submit(BlockDriverState *bs, HANDLE hfile, + int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, + BlockDriverCompletionFunc *cb, void *opaque, int type) +{ + RawWin32AIOData *acb = g_slice_new(RawWin32AIOData); + + acb->bs = bs; + acb->hfile = hfile; + acb->aio_type = type; + + if (qiov) { + acb->aio_iov = qiov->iov; + acb->aio_niov = qiov->niov; + } + acb->aio_nbytes = nb_sectors * 512; + acb->aio_offset = sector_num * 512; + + trace_paio_submit(acb, opaque, sector_num, nb_sectors, type); + return thread_pool_submit_aio(aio_worker, acb, cb, opaque); +} + int qemu_ftruncate64(int fd, int64_t length) { LARGE_INTEGER li; @@ -117,59 +236,29 @@ static int raw_open(BlockDriverState *bs, const char *filename, int flags) return 0; } -static int raw_read(BlockDriverState *bs, int64_t sector_num, - uint8_t *buf, int nb_sectors) +static BlockDriverAIOCB *raw_aio_readv(BlockDriverState *bs, + int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, + BlockDriverCompletionFunc *cb, void *opaque) { BDRVRawState *s = bs->opaque; - OVERLAPPED ov; - DWORD ret_count; - int ret; - int64_t offset = sector_num * 512; - int count = nb_sectors * 512; - - memset(&ov, 0, sizeof(ov)); - ov.Offset = offset; - ov.OffsetHigh = offset >> 32; - ret = ReadFile(s->hfile, buf, count, &ret_count, &ov); - if (!ret) - return ret_count; - if (ret_count == count) - ret_count = 0; - return ret_count; + return paio_submit(bs, s->hfile, sector_num, qiov, nb_sectors, + cb, opaque, QEMU_AIO_READ); } -static int raw_write(BlockDriverState *bs, int64_t sector_num, - const uint8_t *buf, int nb_sectors) +static BlockDriverAIOCB *raw_aio_writev(BlockDriverState *bs, + int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, + BlockDriverCompletionFunc *cb, void *opaque) { BDRVRawState *s = bs->opaque; - OVERLAPPED ov; - DWORD ret_count; - int ret; - int64_t offset = sector_num * 512; - int count = nb_sectors * 512; - - memset(&ov, 0, sizeof(ov)); - ov.Offset = offset; - ov.OffsetHigh = offset >> 32; - ret = WriteFile(s->hfile, buf, count, &ret_count, &ov); - if (!ret) - return ret_count; - if (ret_count == count) - ret_count = 0; - return ret_count; + return paio_submit(bs, s->hfile, sector_num, qiov, nb_sectors, + cb, opaque, QEMU_AIO_WRITE); } -static int raw_flush(BlockDriverState *bs) +static BlockDriverAIOCB *raw_aio_flush(BlockDriverState *bs, + BlockDriverCompletionFunc *cb, void *opaque) { BDRVRawState *s = bs->opaque; - int ret; - - ret = FlushFileBuffers(s->hfile); - if (ret == 0) { - return -EIO; - } - - return 0; + return paio_submit(bs, s->hfile, 0, NULL, 0, cb, opaque, QEMU_AIO_FLUSH); } static void raw_close(BlockDriverState *bs) @@ -290,9 +379,9 @@ static BlockDriver bdrv_file = { .bdrv_close = raw_close, .bdrv_create = raw_create, - .bdrv_read = raw_read, - .bdrv_write = raw_write, - .bdrv_co_flush_to_disk = raw_flush, + .bdrv_aio_readv = raw_aio_readv, + .bdrv_aio_writev = raw_aio_writev, + .bdrv_aio_flush = raw_aio_flush, .bdrv_truncate = raw_truncate, .bdrv_getlength = raw_getlength, @@ -413,9 +502,9 @@ static BlockDriver bdrv_host_device = { .bdrv_close = raw_close, .bdrv_has_zero_init = hdev_has_zero_init, - .bdrv_read = raw_read, - .bdrv_write = raw_write, - .bdrv_co_flush_to_disk = raw_flush, + .bdrv_aio_readv = raw_aio_readv, + .bdrv_aio_writev = raw_aio_writev, + .bdrv_aio_flush = raw_aio_flush, .bdrv_getlength = raw_getlength, .bdrv_get_allocated_file_size From 10fb6e06825743bd517d4b5bb0e7b9e05e0fe92c Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 26 Oct 2012 11:27:45 +0200 Subject: [PATCH 129/291] raw-posix: move linux-aio.c to block/ Signed-off-by: Paolo Bonzini --- Makefile.objs | 1 - block/Makefile.objs | 1 + linux-aio.c => block/linux-aio.c | 0 3 files changed, 1 insertion(+), 1 deletion(-) rename linux-aio.c => block/linux-aio.c (100%) diff --git a/Makefile.objs b/Makefile.objs index 35c2355e82..2b5427ee5f 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -47,7 +47,6 @@ block-obj-y += thread-pool.o qemu-progress.o qemu-sockets.o uri.o notify.o block-obj-y += $(coroutine-obj-y) $(qobject-obj-y) $(version-obj-y) block-obj-$(CONFIG_POSIX) += event_notifier-posix.o aio-posix.o block-obj-$(CONFIG_WIN32) += event_notifier-win32.o aio-win32.o -block-obj-$(CONFIG_LINUX_AIO) += linux-aio.o block-obj-y += block/ block-obj-y += $(qapi-obj-y) qapi-types.o qapi-visit.o diff --git a/block/Makefile.objs b/block/Makefile.objs index 684765bf63..771d3414d9 100644 --- a/block/Makefile.objs +++ b/block/Makefile.objs @@ -5,6 +5,7 @@ block-obj-y += qed-check.o block-obj-y += parallels.o blkdebug.o blkverify.o block-obj-$(CONFIG_WIN32) += raw-win32.o block-obj-$(CONFIG_POSIX) += raw-posix.o +block-obj-$(CONFIG_LINUX_AIO) += linux-aio.o ifeq ($(CONFIG_POSIX),y) block-obj-y += nbd.o sheepdog.o diff --git a/linux-aio.c b/block/linux-aio.c similarity index 100% rename from linux-aio.c rename to block/linux-aio.c From a27365265cc2fed1178bf25a205e8ee02a9c0caf Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 26 Oct 2012 11:43:58 +0200 Subject: [PATCH 130/291] raw-win32: implement native asynchronous I/O With the new support for EventNotifiers in the AIO event loop, we can hook a completion port to every opened file and use asynchronous I/O on them. Wine's support is extremely inefficient, also because it really does the I/O synchronously on regular files. (!) But it works, and it is good to keep the Win32 and POSIX ports as similar as possible. Signed-off-by: Paolo Bonzini --- block/Makefile.objs | 2 +- block/raw-aio.h | 10 ++ block/raw-win32.c | 42 +++++++- block/win32-aio.c | 226 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 274 insertions(+), 6 deletions(-) create mode 100644 block/win32-aio.c diff --git a/block/Makefile.objs b/block/Makefile.objs index 771d3414d9..30ef6aec03 100644 --- a/block/Makefile.objs +++ b/block/Makefile.objs @@ -3,7 +3,7 @@ block-obj-y += qcow2.o qcow2-refcount.o qcow2-cluster.o qcow2-snapshot.o qcow2-c block-obj-y += qed.o qed-gencb.o qed-l2-cache.o qed-table.o qed-cluster.o block-obj-y += qed-check.o block-obj-y += parallels.o blkdebug.o blkverify.o -block-obj-$(CONFIG_WIN32) += raw-win32.o +block-obj-$(CONFIG_WIN32) += raw-win32.o win32-aio.o block-obj-$(CONFIG_POSIX) += raw-posix.o block-obj-$(CONFIG_LINUX_AIO) += linux-aio.o diff --git a/block/raw-aio.h b/block/raw-aio.h index b3bb07377e..e77f361148 100644 --- a/block/raw-aio.h +++ b/block/raw-aio.h @@ -35,4 +35,14 @@ BlockDriverAIOCB *laio_submit(BlockDriverState *bs, void *aio_ctx, int fd, BlockDriverCompletionFunc *cb, void *opaque, int type); #endif +#ifdef _WIN32 +typedef struct QEMUWin32AIOState QEMUWin32AIOState; +QEMUWin32AIOState *win32_aio_init(void); +int win32_aio_attach(QEMUWin32AIOState *aio, HANDLE hfile); +BlockDriverAIOCB *win32_aio_submit(BlockDriverState *bs, + QEMUWin32AIOState *aio, HANDLE hfile, + int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, + BlockDriverCompletionFunc *cb, void *opaque, int type); +#endif + #endif /* QEMU_RAW_AIO_H */ diff --git a/block/raw-win32.c b/block/raw-win32.c index ffd86e3f38..0c05c58c5a 100644 --- a/block/raw-win32.c +++ b/block/raw-win32.c @@ -36,6 +36,8 @@ #define FTYPE_CD 1 #define FTYPE_HARDDISK 2 +static QEMUWin32AIOState *aio; + typedef struct RawWin32AIOData { BlockDriverState *bs; HANDLE hfile; @@ -50,6 +52,7 @@ typedef struct BDRVRawState { HANDLE hfile; int type; char drive_path[16]; /* format: "d:\" */ + QEMUWin32AIOState *aio; } BDRVRawState; /* @@ -208,6 +211,9 @@ static void raw_parse_flags(int flags, int *access_flags, DWORD *overlapped) } *overlapped = FILE_ATTRIBUTE_NORMAL; + if (flags & BDRV_O_NATIVE_AIO) { + *overlapped |= FILE_FLAG_OVERLAPPED; + } if (flags & BDRV_O_NOCACHE) { *overlapped |= FILE_FLAG_NO_BUFFERING; } @@ -222,6 +228,13 @@ static int raw_open(BlockDriverState *bs, const char *filename, int flags) s->type = FTYPE_FILE; raw_parse_flags(flags, &access_flags, &overlapped); + + if ((flags & BDRV_O_NATIVE_AIO) && aio == NULL) { + aio = win32_aio_init(); + if (aio == NULL) { + return -EINVAL; + } + } s->hfile = CreateFile(filename, access_flags, FILE_SHARE_READ, NULL, @@ -231,7 +244,16 @@ static int raw_open(BlockDriverState *bs, const char *filename, int flags) if (err == ERROR_ACCESS_DENIED) return -EACCES; - return -1; + return -EINVAL; + } + + if (flags & BDRV_O_NATIVE_AIO) { + int ret = win32_aio_attach(aio, s->hfile); + if (ret < 0) { + CloseHandle(s->hfile); + return ret; + } + s->aio = aio; } return 0; } @@ -241,8 +263,13 @@ static BlockDriverAIOCB *raw_aio_readv(BlockDriverState *bs, BlockDriverCompletionFunc *cb, void *opaque) { BDRVRawState *s = bs->opaque; - return paio_submit(bs, s->hfile, sector_num, qiov, nb_sectors, - cb, opaque, QEMU_AIO_READ); + if (s->aio) { + return win32_aio_submit(bs, s->aio, s->hfile, sector_num, qiov, + nb_sectors, cb, opaque, QEMU_AIO_READ); + } else { + return paio_submit(bs, s->hfile, sector_num, qiov, nb_sectors, + cb, opaque, QEMU_AIO_READ); + } } static BlockDriverAIOCB *raw_aio_writev(BlockDriverState *bs, @@ -250,8 +277,13 @@ static BlockDriverAIOCB *raw_aio_writev(BlockDriverState *bs, BlockDriverCompletionFunc *cb, void *opaque) { BDRVRawState *s = bs->opaque; - return paio_submit(bs, s->hfile, sector_num, qiov, nb_sectors, - cb, opaque, QEMU_AIO_WRITE); + if (s->aio) { + return win32_aio_submit(bs, s->aio, s->hfile, sector_num, qiov, + nb_sectors, cb, opaque, QEMU_AIO_WRITE); + } else { + return paio_submit(bs, s->hfile, sector_num, qiov, nb_sectors, + cb, opaque, QEMU_AIO_WRITE); + } } static BlockDriverAIOCB *raw_aio_flush(BlockDriverState *bs, diff --git a/block/win32-aio.c b/block/win32-aio.c new file mode 100644 index 0000000000..c34dc73b6c --- /dev/null +++ b/block/win32-aio.c @@ -0,0 +1,226 @@ +/* + * Block driver for RAW files (win32) + * + * Copyright (c) 2006 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#include "qemu-common.h" +#include "qemu-timer.h" +#include "block_int.h" +#include "module.h" +#include "qemu-common.h" +#include "qemu-aio.h" +#include "raw-aio.h" +#include "event_notifier.h" +#include +#include + +#define FTYPE_FILE 0 +#define FTYPE_CD 1 +#define FTYPE_HARDDISK 2 + +struct QEMUWin32AIOState { + HANDLE hIOCP; + EventNotifier e; + int count; +}; + +typedef struct QEMUWin32AIOCB { + BlockDriverAIOCB common; + struct QEMUWin32AIOState *ctx; + int nbytes; + OVERLAPPED ov; + QEMUIOVector *qiov; + void *buf; + bool is_read; + bool is_linear; +} QEMUWin32AIOCB; + +/* + * Completes an AIO request (calls the callback and frees the ACB). + */ +static void win32_aio_process_completion(QEMUWin32AIOState *s, + QEMUWin32AIOCB *waiocb, DWORD count) +{ + int ret; + s->count--; + + if (waiocb->ov.Internal != 0) { + ret = -EIO; + } else { + ret = 0; + if (count < waiocb->nbytes) { + /* Short reads mean EOF, pad with zeros. */ + if (waiocb->is_read) { + qemu_iovec_memset(waiocb->qiov, count, 0, + waiocb->qiov->size - count); + } else { + ret = -EINVAL; + } + } + } + + if (!waiocb->is_linear) { + if (ret == 0 && waiocb->is_read) { + QEMUIOVector *qiov = waiocb->qiov; + char *p = waiocb->buf; + int i; + + for (i = 0; i < qiov->niov; ++i) { + memcpy(p, qiov->iov[i].iov_base, qiov->iov[i].iov_len); + p += qiov->iov[i].iov_len; + } + g_free(waiocb->buf); + } + } + + + waiocb->common.cb(waiocb->common.opaque, ret); + qemu_aio_release(waiocb); +} + +static void win32_aio_completion_cb(EventNotifier *e) +{ + QEMUWin32AIOState *s = container_of(e, QEMUWin32AIOState, e); + DWORD count; + ULONG_PTR key; + OVERLAPPED *ov; + + event_notifier_test_and_clear(&s->e); + while (GetQueuedCompletionStatus(s->hIOCP, &count, &key, &ov, 0)) { + QEMUWin32AIOCB *waiocb = container_of(ov, QEMUWin32AIOCB, ov); + + win32_aio_process_completion(s, waiocb, count); + } +} + +static int win32_aio_flush_cb(EventNotifier *e) +{ + QEMUWin32AIOState *s = container_of(e, QEMUWin32AIOState, e); + + return (s->count > 0) ? 1 : 0; +} + +static void win32_aio_cancel(BlockDriverAIOCB *blockacb) +{ + QEMUWin32AIOCB *waiocb = (QEMUWin32AIOCB *)blockacb; + + /* + * CancelIoEx is only supported in Vista and newer. For now, just + * wait for completion. + */ + while (!HasOverlappedIoCompleted(&waiocb->ov)) { + qemu_aio_wait(); + } +} + +static AIOPool win32_aio_pool = { + .aiocb_size = sizeof(QEMUWin32AIOCB), + .cancel = win32_aio_cancel, +}; + +BlockDriverAIOCB *win32_aio_submit(BlockDriverState *bs, + QEMUWin32AIOState *aio, HANDLE hfile, + int64_t sector_num, QEMUIOVector *qiov, int nb_sectors, + BlockDriverCompletionFunc *cb, void *opaque, int type) +{ + struct QEMUWin32AIOCB *waiocb; + uint64_t offset = sector_num * 512; + DWORD rc; + + waiocb = qemu_aio_get(&win32_aio_pool, bs, cb, opaque); + waiocb->nbytes = nb_sectors * 512; + waiocb->qiov = qiov; + waiocb->is_read = (type == QEMU_AIO_READ); + + if (qiov->niov > 1) { + waiocb->buf = qemu_blockalign(bs, qiov->size); + if (type & QEMU_AIO_WRITE) { + char *p = waiocb->buf; + int i; + + for (i = 0; i < qiov->niov; ++i) { + memcpy(p, qiov->iov[i].iov_base, qiov->iov[i].iov_len); + p += qiov->iov[i].iov_len; + } + } + waiocb->is_linear = false; + } else { + waiocb->buf = qiov->iov[0].iov_base; + waiocb->is_linear = true; + } + + waiocb->ov = (OVERLAPPED) { + .Offset = (DWORD) offset, + .OffsetHigh = (DWORD) (offset >> 32), + .hEvent = event_notifier_get_handle(&aio->e) + }; + aio->count++; + + if (type & QEMU_AIO_READ) { + rc = ReadFile(hfile, waiocb->buf, waiocb->nbytes, NULL, &waiocb->ov); + } else { + rc = WriteFile(hfile, waiocb->buf, waiocb->nbytes, NULL, &waiocb->ov); + } + if(rc == 0 && GetLastError() != ERROR_IO_PENDING) { + goto out_dec_count; + } + return &waiocb->common; + +out_dec_count: + aio->count--; + qemu_aio_release(waiocb); + return NULL; +} + +int win32_aio_attach(QEMUWin32AIOState *aio, HANDLE hfile) +{ + if (CreateIoCompletionPort(hfile, aio->hIOCP, (ULONG_PTR) 0, 0) == NULL) { + return -EINVAL; + } else { + return 0; + } +} + +QEMUWin32AIOState *win32_aio_init(void) +{ + QEMUWin32AIOState *s; + + s = g_malloc0(sizeof(*s)); + if (event_notifier_init(&s->e, false) < 0) { + goto out_free_state; + } + + s->hIOCP = CreateIoCompletionPort(INVALID_HANDLE_VALUE, NULL, 0, 0); + if (s->hIOCP == NULL) { + goto out_close_efd; + } + + qemu_aio_set_event_notifier(&s->e, win32_aio_completion_cb, + win32_aio_flush_cb); + + return s; + +out_close_efd: + event_notifier_cleanup(&s->e); +out_free_state: + g_free(s); + return NULL; +} From 235eb0158cfb31bb8a7cad7296e2327d7f7349fc Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:01 +0800 Subject: [PATCH 131/291] target-mips: Add ASE DSP internal functions Add internal functions using by MIPS ASE DSP instructions. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/Makefile.objs | 2 +- target-mips/dsp_helper.c | 1063 +++++++++++++++++++++++++++++++++++++ 2 files changed, 1064 insertions(+), 1 deletion(-) create mode 100644 target-mips/dsp_helper.c diff --git a/target-mips/Makefile.objs b/target-mips/Makefile.objs index 3eeeeac8b8..119c816518 100644 --- a/target-mips/Makefile.objs +++ b/target-mips/Makefile.objs @@ -1,2 +1,2 @@ -obj-y += translate.o op_helper.o lmi_helper.o helper.o cpu.o +obj-y += translate.o dsp_helper.o op_helper.o lmi_helper.o helper.o cpu.o obj-$(CONFIG_SOFTMMU) += machine.o diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c new file mode 100644 index 0000000000..55ea9236fa --- /dev/null +++ b/target-mips/dsp_helper.c @@ -0,0 +1,1063 @@ +/* + * MIPS ASE DSP Instruction emulation helpers for QEMU. + * + * Copyright (c) 2012 Jia Liu + * Dongxue Zhang + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ + +#include "cpu.h" +#include "helper.h" + +/*** MIPS DSP internal functions begin ***/ +#define MIPSDSP_ABS(x) (((x) >= 0) ? x : -x) +#define MIPSDSP_OVERFLOW(a, b, c, d) (!(!((a ^ b ^ -1) & (a ^ c) & d))) + +static inline void set_DSPControl_overflow_flag(uint32_t flag, int position, + CPUMIPSState *env) +{ + env->active_tc.DSPControl |= (target_ulong)flag << position; +} + +static inline void set_DSPControl_carryflag(uint32_t flag, CPUMIPSState *env) +{ + env->active_tc.DSPControl |= (target_ulong)flag << 13; +} + +static inline uint32_t get_DSPControl_carryflag(CPUMIPSState *env) +{ + return (env->active_tc.DSPControl >> 13) & 0x01; +} + +static inline void set_DSPControl_24(uint32_t flag, int len, CPUMIPSState *env) +{ + uint32_t filter; + + filter = ((0x01 << len) - 1) << 24; + filter = ~filter; + + env->active_tc.DSPControl &= filter; + env->active_tc.DSPControl |= (target_ulong)flag << 24; +} + +static inline uint32_t get_DSPControl_24(int len, CPUMIPSState *env) +{ + uint32_t filter; + + filter = (0x01 << len) - 1; + + return (env->active_tc.DSPControl >> 24) & filter; +} + +static inline void set_DSPControl_pos(uint32_t pos, CPUMIPSState *env) +{ + target_ulong dspc; + + dspc = env->active_tc.DSPControl; +#ifndef TARGET_MIPS64 + dspc = dspc & 0xFFFFFFC0; + dspc |= pos; +#else + dspc = dspc & 0xFFFFFF80; + dspc |= pos; +#endif + env->active_tc.DSPControl = dspc; +} + +static inline uint32_t get_DSPControl_pos(CPUMIPSState *env) +{ + target_ulong dspc; + uint32_t pos; + + dspc = env->active_tc.DSPControl; + +#ifndef TARGET_MIPS64 + pos = dspc & 0x3F; +#else + pos = dspc & 0x7F; +#endif + + return pos; +} + +static inline void set_DSPControl_efi(uint32_t flag, CPUMIPSState *env) +{ + env->active_tc.DSPControl &= 0xFFFFBFFF; + env->active_tc.DSPControl |= (target_ulong)flag << 14; +} + +#define DO_MIPS_SAT_ABS(size) \ +static inline int##size##_t mipsdsp_sat_abs##size(int##size##_t a, \ + CPUMIPSState *env) \ +{ \ + if (a == INT##size##_MIN) { \ + set_DSPControl_overflow_flag(1, 20, env); \ + return INT##size##_MAX; \ + } else { \ + return MIPSDSP_ABS(a); \ + } \ +} +DO_MIPS_SAT_ABS(8) +DO_MIPS_SAT_ABS(16) +DO_MIPS_SAT_ABS(32) +#undef DO_MIPS_SAT_ABS + +/* get sum value */ +static inline int16_t mipsdsp_add_i16(int16_t a, int16_t b, CPUMIPSState *env) +{ + int16_t tempI; + + tempI = a + b; + + if (MIPSDSP_OVERFLOW(a, b, tempI, 0x8000)) { + set_DSPControl_overflow_flag(1, 20, env); + } + + return tempI; +} + +static inline int16_t mipsdsp_sat_add_i16(int16_t a, int16_t b, + CPUMIPSState *env) +{ + int16_t tempS; + + tempS = a + b; + + if (MIPSDSP_OVERFLOW(a, b, tempS, 0x8000)) { + if (a > 0) { + tempS = 0x7FFF; + } else { + tempS = 0x8000; + } + set_DSPControl_overflow_flag(1, 20, env); + } + + return tempS; +} + +static inline int32_t mipsdsp_sat_add_i32(int32_t a, int32_t b, + CPUMIPSState *env) +{ + int32_t tempI; + + tempI = a + b; + + if (MIPSDSP_OVERFLOW(a, b, tempI, 0x80000000)) { + if (a > 0) { + tempI = 0x7FFFFFFF; + } else { + tempI = 0x80000000; + } + set_DSPControl_overflow_flag(1, 20, env); + } + + return tempI; +} + +static inline uint8_t mipsdsp_add_u8(uint8_t a, uint8_t b, CPUMIPSState *env) +{ + uint16_t temp; + + temp = (uint16_t)a + (uint16_t)b; + + if (temp & 0x0100) { + set_DSPControl_overflow_flag(1, 20, env); + } + + return temp & 0xFF; +} + +static inline uint16_t mipsdsp_add_u16(uint16_t a, uint16_t b, + CPUMIPSState *env) +{ + uint32_t temp; + + temp = (uint32_t)a + (uint32_t)b; + + if (temp & 0x00010000) { + set_DSPControl_overflow_flag(1, 20, env); + } + + return temp & 0xFFFF; +} + +static inline uint8_t mipsdsp_sat_add_u8(uint8_t a, uint8_t b, + CPUMIPSState *env) +{ + uint8_t result; + uint16_t temp; + + temp = (uint16_t)a + (uint16_t)b; + result = temp & 0xFF; + + if (0x0100 & temp) { + result = 0xFF; + set_DSPControl_overflow_flag(1, 20, env); + } + + return result; +} + +static inline uint16_t mipsdsp_sat_add_u16(uint16_t a, uint16_t b, + CPUMIPSState *env) +{ + uint16_t result; + uint32_t temp; + + temp = (uint32_t)a + (uint32_t)b; + result = temp & 0xFFFF; + + if (0x00010000 & temp) { + result = 0xFFFF; + set_DSPControl_overflow_flag(1, 20, env); + } + + return result; +} + +static inline int32_t mipsdsp_sat32_acc_q31(int32_t acc, int32_t a, + CPUMIPSState *env) +{ + int64_t temp; + int32_t temp32, temp31, result; + int64_t temp_sum; + +#ifndef TARGET_MIPS64 + temp = ((uint64_t)env->active_tc.HI[acc] << 32) | + (uint64_t)env->active_tc.LO[acc]; +#else + temp = (uint64_t)env->active_tc.LO[acc]; +#endif + + temp_sum = (int64_t)a + temp; + + temp32 = (temp_sum >> 32) & 0x01; + temp31 = (temp_sum >> 31) & 0x01; + result = temp_sum & 0xFFFFFFFF; + + /* FIXME + This sat function may wrong, because user manual wrote: + temp127..0 ← temp + ( (signA) || a31..0 + if ( temp32 ≠ temp31 ) then + if ( temp32 = 0 ) then + temp31..0 ← 0x80000000 + else + temp31..0 ← 0x7FFFFFFF + endif + DSPControlouflag:16+acc ← 1 + endif + */ + if (temp32 != temp31) { + if (temp32 == 0) { + result = 0x7FFFFFFF; + } else { + result = 0x80000000; + } + set_DSPControl_overflow_flag(1, 16 + acc, env); + } + + return result; +} + +/* a[0] is LO, a[1] is HI. */ +static inline void mipsdsp_sat64_acc_add_q63(int64_t *ret, + int32_t ac, + int64_t *a, + CPUMIPSState *env) +{ + bool temp64; + + ret[0] = env->active_tc.LO[ac] + a[0]; + ret[1] = env->active_tc.HI[ac] + a[1]; + + if (((uint64_t)ret[0] < (uint64_t)env->active_tc.LO[ac]) && + ((uint64_t)ret[0] < (uint64_t)a[0])) { + ret[1] += 1; + } + temp64 = ret[1] & 1; + if (temp64 != ((ret[0] >> 63) & 0x01)) { + if (temp64) { + ret[0] = (0x01ull << 63); + ret[1] = ~0ull; + } else { + ret[0] = (0x01ull << 63) - 1; + ret[1] = 0x00; + } + set_DSPControl_overflow_flag(1, 16 + ac, env); + } +} + +static inline void mipsdsp_sat64_acc_sub_q63(int64_t *ret, + int32_t ac, + int64_t *a, + CPUMIPSState *env) +{ + bool temp64; + + ret[0] = env->active_tc.LO[ac] - a[0]; + ret[1] = env->active_tc.HI[ac] - a[1]; + + if ((uint64_t)ret[0] > (uint64_t)env->active_tc.LO[ac]) { + ret[1] -= 1; + } + temp64 = ret[1] & 1; + if (temp64 != ((ret[0] >> 63) & 0x01)) { + if (temp64) { + ret[0] = (0x01ull << 63); + ret[1] = ~0ull; + } else { + ret[0] = (0x01ull << 63) - 1; + ret[1] = 0x00; + } + set_DSPControl_overflow_flag(1, 16 + ac, env); + } +} + +static inline int32_t mipsdsp_mul_i16_i16(int16_t a, int16_t b, + CPUMIPSState *env) +{ + int32_t temp; + + temp = (int32_t)a * (int32_t)b; + + if ((temp > (int)0x7FFF) || (temp < (int)0xFFFF8000)) { + set_DSPControl_overflow_flag(1, 21, env); + } + temp &= 0x0000FFFF; + + return temp; +} + +static inline int32_t mipsdsp_mul_u16_u16(int32_t a, int32_t b) +{ + return a * b; +} + +static inline int32_t mipsdsp_mul_i32_i32(int32_t a, int32_t b) +{ + return a * b; +} + +static inline int32_t mipsdsp_sat16_mul_i16_i16(int16_t a, int16_t b, + CPUMIPSState *env) +{ + int32_t temp; + + temp = (int32_t)a * (int32_t)b; + + if (temp > (int)0x7FFF) { + temp = 0x00007FFF; + set_DSPControl_overflow_flag(1, 21, env); + } else if (temp < (int)0xffff8000) { + temp = 0xFFFF8000; + set_DSPControl_overflow_flag(1, 21, env); + } + temp &= 0x0000FFFF; + + return temp; +} + +static inline int32_t mipsdsp_mul_q15_q15_overflowflag21(uint16_t a, uint16_t b, + CPUMIPSState *env) +{ + int32_t temp; + + if ((a == 0x8000) && (b == 0x8000)) { + temp = 0x7FFFFFFF; + set_DSPControl_overflow_flag(1, 21, env); + } else { + temp = ((int32_t)(int16_t)a * (int32_t)(int16_t)b) << 1; + } + + return temp; +} + +/* right shift */ +static inline uint8_t mipsdsp_rshift_u8(uint8_t a, target_ulong mov) +{ + return a >> mov; +} + +static inline uint16_t mipsdsp_rshift_u16(uint16_t a, target_ulong mov) +{ + return a >> mov; +} + +static inline int8_t mipsdsp_rashift8(int8_t a, target_ulong mov) +{ + return a >> mov; +} + +static inline int16_t mipsdsp_rashift16(int16_t a, target_ulong mov) +{ + return a >> mov; +} + +static inline int32_t mipsdsp_rashift32(int32_t a, target_ulong mov) +{ + return a >> mov; +} + +static inline int16_t mipsdsp_rshift1_add_q16(int16_t a, int16_t b) +{ + int32_t temp; + + temp = (int32_t)a + (int32_t)b; + + return (temp >> 1) & 0xFFFF; +} + +/* round right shift */ +static inline int16_t mipsdsp_rrshift1_add_q16(int16_t a, int16_t b) +{ + int32_t temp; + + temp = (int32_t)a + (int32_t)b; + temp += 1; + + return (temp >> 1) & 0xFFFF; +} + +static inline int32_t mipsdsp_rshift1_add_q32(int32_t a, int32_t b) +{ + int64_t temp; + + temp = (int64_t)a + (int64_t)b; + + return (temp >> 1) & 0xFFFFFFFF; +} + +static inline int32_t mipsdsp_rrshift1_add_q32(int32_t a, int32_t b) +{ + int64_t temp; + + temp = (int64_t)a + (int64_t)b; + temp += 1; + + return (temp >> 1) & 0xFFFFFFFF; +} + +static inline uint8_t mipsdsp_rshift1_add_u8(uint8_t a, uint8_t b) +{ + uint16_t temp; + + temp = (uint16_t)a + (uint16_t)b; + + return (temp >> 1) & 0x00FF; +} + +static inline uint8_t mipsdsp_rrshift1_add_u8(uint8_t a, uint8_t b) +{ + uint16_t temp; + + temp = (uint16_t)a + (uint16_t)b + 1; + + return (temp >> 1) & 0x00FF; +} + +static inline uint8_t mipsdsp_rshift1_sub_u8(uint8_t a, uint8_t b) +{ + uint16_t temp; + + temp = (uint16_t)a - (uint16_t)b; + + return (temp >> 1) & 0x00FF; +} + +static inline uint8_t mipsdsp_rrshift1_sub_u8(uint8_t a, uint8_t b) +{ + uint16_t temp; + + temp = (uint16_t)a - (uint16_t)b + 1; + + return (temp >> 1) & 0x00FF; +} + +static inline int64_t mipsdsp_rashift_short_acc(int32_t ac, + int32_t shift, + CPUMIPSState *env) +{ + int32_t sign, temp31; + int64_t temp, acc; + + sign = (env->active_tc.HI[ac] >> 31) & 0x01; + acc = ((int64_t)env->active_tc.HI[ac] << 32) | + ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF); + if (shift == 0) { + temp = acc; + } else { + if (sign == 0) { + temp = (((int64_t)0x01 << (32 - shift + 1)) - 1) & (acc >> shift); + } else { + temp = ((((int64_t)0x01 << (shift + 1)) - 1) << (32 - shift)) | + (acc >> shift); + } + } + + temp31 = (temp >> 31) & 0x01; + if (sign != temp31) { + set_DSPControl_overflow_flag(1, 23, env); + } + + return temp; +} + +/* 128 bits long. p[0] is LO, p[1] is HI. */ +static inline void mipsdsp_rndrashift_short_acc(int64_t *p, + int32_t ac, + int32_t shift, + CPUMIPSState *env) +{ + int64_t acc; + + acc = ((int64_t)env->active_tc.HI[ac] << 32) | + ((int64_t)env->active_tc.LO[ac] & 0xFFFFFFFF); + if (shift == 0) { + p[0] = acc << 1; + p[1] = (acc >> 63) & 0x01; + } else { + p[0] = acc >> (shift - 1); + p[1] = 0; + } +} + +/* 128 bits long. p[0] is LO, p[1] is HI */ +static inline void mipsdsp_rashift_acc(uint64_t *p, + uint32_t ac, + uint32_t shift, + CPUMIPSState *env) +{ + uint64_t tempB, tempA; + + tempB = env->active_tc.HI[ac]; + tempA = env->active_tc.LO[ac]; + shift = shift & 0x1F; + + if (shift == 0) { + p[1] = tempB; + p[0] = tempA; + } else { + p[0] = (tempB << (64 - shift)) | (tempA >> shift); + p[1] = (int64_t)tempB >> shift; + } +} + +/* 128 bits long. p[0] is LO, p[1] is HI , p[2] is sign of HI.*/ +static inline void mipsdsp_rndrashift_acc(uint64_t *p, + uint32_t ac, + uint32_t shift, + CPUMIPSState *env) +{ + int64_t tempB, tempA; + + tempB = env->active_tc.HI[ac]; + tempA = env->active_tc.LO[ac]; + shift = shift & 0x3F; + + if (shift == 0) { + p[2] = tempB >> 63; + p[1] = (tempB << 1) | (tempA >> 63); + p[0] = tempA << 1; + } else { + p[0] = (tempB << (65 - shift)) | (tempA >> (shift - 1)); + p[1] = (int64_t)tempB >> (shift - 1); + if (tempB >= 0) { + p[2] = 0x0; + } else { + p[2] = ~0ull; + } + } +} + +static inline int32_t mipsdsp_mul_q15_q15(int32_t ac, uint16_t a, uint16_t b, + CPUMIPSState *env) +{ + int32_t temp; + + if ((a == 0x8000) && (b == 0x8000)) { + temp = 0x7FFFFFFF; + set_DSPControl_overflow_flag(1, 16 + ac, env); + } else { + temp = ((uint32_t)a * (uint32_t)b) << 1; + } + + return temp; +} + +static inline int64_t mipsdsp_mul_q31_q31(int32_t ac, uint32_t a, uint32_t b, + CPUMIPSState *env) +{ + uint64_t temp; + + if ((a == 0x80000000) && (b == 0x80000000)) { + temp = (0x01ull << 63) - 1; + set_DSPControl_overflow_flag(1, 16 + ac, env); + } else { + temp = ((uint64_t)a * (uint64_t)b) << 1; + } + + return temp; +} + +static inline uint16_t mipsdsp_mul_u8_u8(uint8_t a, uint8_t b) +{ + return (uint16_t)a * (uint16_t)b; +} + +static inline uint16_t mipsdsp_mul_u8_u16(uint8_t a, uint16_t b, + CPUMIPSState *env) +{ + uint32_t tempI; + + tempI = (uint32_t)a * (uint32_t)b; + if (tempI > 0x0000FFFF) { + tempI = 0x0000FFFF; + set_DSPControl_overflow_flag(1, 21, env); + } + + return tempI & 0x0000FFFF; +} + +static inline uint64_t mipsdsp_mul_u32_u32(uint32_t a, uint32_t b) +{ + return (uint64_t)a * (uint64_t)b; +} + +static inline int16_t mipsdsp_rndq15_mul_q15_q15(uint16_t a, uint16_t b, + CPUMIPSState *env) +{ + uint32_t temp; + + if ((a == 0x8000) && (b == 0x8000)) { + temp = 0x7FFF0000; + set_DSPControl_overflow_flag(1, 21, env); + } else { + temp = (a * b) << 1; + temp = temp + 0x00008000; + } + + return (temp & 0xFFFF0000) >> 16; +} + +static inline int32_t mipsdsp_sat16_mul_q15_q15(uint16_t a, uint16_t b, + CPUMIPSState *env) +{ + int32_t temp; + + if ((a == 0x8000) && (b == 0x8000)) { + temp = 0x7FFF0000; + set_DSPControl_overflow_flag(1, 21, env); + } else { + temp = ((uint32_t)a * (uint32_t)b); + temp = temp << 1; + } + + return (temp >> 16) & 0x0000FFFF; +} + +static inline uint16_t mipsdsp_trunc16_sat16_round(int32_t a, + CPUMIPSState *env) +{ + int64_t temp; + + temp = (int32_t)a + 0x00008000; + + if (a > (int)0x7fff8000) { + temp = 0x7FFFFFFF; + set_DSPControl_overflow_flag(1, 22, env); + } + + return (temp >> 16) & 0xFFFF; +} + +static inline uint8_t mipsdsp_sat8_reduce_precision(uint16_t a, + CPUMIPSState *env) +{ + uint16_t mag; + uint32_t sign; + + sign = (a >> 15) & 0x01; + mag = a & 0x7FFF; + + if (sign == 0) { + if (mag > 0x7F80) { + set_DSPControl_overflow_flag(1, 22, env); + return 0xFF; + } else { + return (mag >> 7) & 0xFFFF; + } + } else { + set_DSPControl_overflow_flag(1, 22, env); + return 0x00; + } +} + +static inline uint8_t mipsdsp_lshift8(uint8_t a, uint8_t s, CPUMIPSState *env) +{ + uint8_t sign; + uint8_t discard; + + if (s == 0) { + return a; + } else { + sign = (a >> 7) & 0x01; + if (sign != 0) { + discard = (((0x01 << (8 - s)) - 1) << s) | + ((a >> (6 - (s - 1))) & ((0x01 << s) - 1)); + } else { + discard = a >> (6 - (s - 1)); + } + + if (discard != 0x00) { + set_DSPControl_overflow_flag(1, 22, env); + } + return a << s; + } +} + +static inline uint16_t mipsdsp_lshift16(uint16_t a, uint8_t s, + CPUMIPSState *env) +{ + uint8_t sign; + uint16_t discard; + + if (s == 0) { + return a; + } else { + sign = (a >> 15) & 0x01; + if (sign != 0) { + discard = (((0x01 << (16 - s)) - 1) << s) | + ((a >> (14 - (s - 1))) & ((0x01 << s) - 1)); + } else { + discard = a >> (14 - (s - 1)); + } + + if ((discard != 0x0000) && (discard != 0xFFFF)) { + set_DSPControl_overflow_flag(1, 22, env); + } + return a << s; + } +} + + +static inline uint32_t mipsdsp_lshift32(uint32_t a, uint8_t s, + CPUMIPSState *env) +{ + uint32_t discard; + + if (s == 0) { + return a; + } else { + discard = (int32_t)a >> (31 - (s - 1)); + + if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) { + set_DSPControl_overflow_flag(1, 22, env); + } + return a << s; + } +} + +static inline uint16_t mipsdsp_sat16_lshift(uint16_t a, uint8_t s, + CPUMIPSState *env) +{ + uint8_t sign; + uint16_t discard; + + if (s == 0) { + return a; + } else { + sign = (a >> 15) & 0x01; + if (sign != 0) { + discard = (((0x01 << (16 - s)) - 1) << s) | + ((a >> (14 - (s - 1))) & ((0x01 << s) - 1)); + } else { + discard = a >> (14 - (s - 1)); + } + + if ((discard != 0x0000) && (discard != 0xFFFF)) { + set_DSPControl_overflow_flag(1, 22, env); + return (sign == 0) ? 0x7FFF : 0x8000; + } else { + return a << s; + } + } +} + +static inline uint32_t mipsdsp_sat32_lshift(uint32_t a, uint8_t s, + CPUMIPSState *env) +{ + uint8_t sign; + uint32_t discard; + + if (s == 0) { + return a; + } else { + sign = (a >> 31) & 0x01; + if (sign != 0) { + discard = (((0x01 << (32 - s)) - 1) << s) | + ((a >> (30 - (s - 1))) & ((0x01 << s) - 1)); + } else { + discard = a >> (30 - (s - 1)); + } + + if ((discard != 0x00000000) && (discard != 0xFFFFFFFF)) { + set_DSPControl_overflow_flag(1, 22, env); + return (sign == 0) ? 0x7FFFFFFF : 0x80000000; + } else { + return a << s; + } + } +} + +static inline uint8_t mipsdsp_rnd8_rashift(uint8_t a, uint8_t s) +{ + uint32_t temp; + + if (s == 0) { + temp = (uint32_t)a << 1; + } else { + temp = (int32_t)(int8_t)a >> (s - 1); + } + + return (temp + 1) >> 1; +} + +static inline uint16_t mipsdsp_rnd16_rashift(uint16_t a, uint8_t s) +{ + uint32_t temp; + + if (s == 0) { + temp = (uint32_t)a << 1; + } else { + temp = (int32_t)(int16_t)a >> (s - 1); + } + + return (temp + 1) >> 1; +} + +static inline uint32_t mipsdsp_rnd32_rashift(uint32_t a, uint8_t s) +{ + int64_t temp; + + if (s == 0) { + temp = (uint64_t)a << 1; + } else { + temp = (int64_t)(int32_t)a >> (s - 1); + } + temp += 1; + + return (temp >> 1) & 0xFFFFFFFFull; +} + +static inline uint16_t mipsdsp_sub_i16(int16_t a, int16_t b, CPUMIPSState *env) +{ + int16_t temp; + + temp = a - b; + if (MIPSDSP_OVERFLOW(a, -b, temp, 0x8000)) { + set_DSPControl_overflow_flag(1, 20, env); + } + + return temp; +} + +static inline uint16_t mipsdsp_sat16_sub(int16_t a, int16_t b, + CPUMIPSState *env) +{ + int16_t temp; + + temp = a - b; + if (MIPSDSP_OVERFLOW(a, -b, temp, 0x8000)) { + if (a > 0) { + temp = 0x7FFF; + } else { + temp = 0x8000; + } + set_DSPControl_overflow_flag(1, 20, env); + } + + return temp; +} + +static inline uint32_t mipsdsp_sat32_sub(int32_t a, int32_t b, + CPUMIPSState *env) +{ + int32_t temp; + + temp = a - b; + if (MIPSDSP_OVERFLOW(a, -b, temp, 0x80000000)) { + if (a > 0) { + temp = 0x7FFFFFFF; + } else { + temp = 0x80000000; + } + set_DSPControl_overflow_flag(1, 20, env); + } + + return temp & 0xFFFFFFFFull; +} + +static inline uint16_t mipsdsp_rshift1_sub_q16(int16_t a, int16_t b) +{ + int32_t temp; + + temp = (int32_t)a - (int32_t)b; + + return (temp >> 1) & 0x0000FFFF; +} + +static inline uint16_t mipsdsp_rrshift1_sub_q16(int16_t a, int16_t b) +{ + int32_t temp; + + temp = (int32_t)a - (int32_t)b; + temp += 1; + + return (temp >> 1) & 0x0000FFFF; +} + +static inline uint32_t mipsdsp_rshift1_sub_q32(int32_t a, int32_t b) +{ + int64_t temp; + + temp = (int64_t)a - (int64_t)b; + + return (temp >> 1) & 0xFFFFFFFFull; +} + +static inline uint32_t mipsdsp_rrshift1_sub_q32(int32_t a, int32_t b) +{ + int64_t temp; + + temp = (int64_t)a - (int64_t)b; + temp += 1; + + return (temp >> 1) & 0xFFFFFFFFull; +} + +static inline uint16_t mipsdsp_sub_u16_u16(uint16_t a, uint16_t b, + CPUMIPSState *env) +{ + uint8_t temp16; + uint32_t temp; + + temp = (uint32_t)a - (uint32_t)b; + temp16 = (temp >> 16) & 0x01; + if (temp16 == 1) { + set_DSPControl_overflow_flag(1, 20, env); + } + return temp & 0x0000FFFF; +} + +static inline uint16_t mipsdsp_satu16_sub_u16_u16(uint16_t a, uint16_t b, + CPUMIPSState *env) +{ + uint8_t temp16; + uint32_t temp; + + temp = (uint32_t)a - (uint32_t)b; + temp16 = (temp >> 16) & 0x01; + + if (temp16 == 1) { + temp = 0x0000; + set_DSPControl_overflow_flag(1, 20, env); + } + + return temp & 0x0000FFFF; +} + +static inline uint8_t mipsdsp_sub_u8(uint8_t a, uint8_t b, CPUMIPSState *env) +{ + uint8_t temp8; + uint16_t temp; + + temp = (uint16_t)a - (uint16_t)b; + temp8 = (temp >> 8) & 0x01; + if (temp8 == 1) { + set_DSPControl_overflow_flag(1, 20, env); + } + + return temp & 0x00FF; +} + +static inline uint8_t mipsdsp_satu8_sub(uint8_t a, uint8_t b, CPUMIPSState *env) +{ + uint8_t temp8; + uint16_t temp; + + temp = (uint16_t)a - (uint16_t)b; + temp8 = (temp >> 8) & 0x01; + if (temp8 == 1) { + temp = 0x00; + set_DSPControl_overflow_flag(1, 20, env); + } + + return temp & 0x00FF; +} + +static inline uint32_t mipsdsp_sub32(int32_t a, int32_t b, CPUMIPSState *env) +{ + int32_t temp; + + temp = a - b; + if (MIPSDSP_OVERFLOW(a, -b, temp, 0x80000000)) { + set_DSPControl_overflow_flag(1, 20, env); + } + + return temp; +} + +static inline int32_t mipsdsp_add_i32(int32_t a, int32_t b, CPUMIPSState *env) +{ + int32_t temp; + + temp = a + b; + + if (MIPSDSP_OVERFLOW(a, b, temp, 0x80000000)) { + set_DSPControl_overflow_flag(1, 20, env); + } + + return temp; +} + +static inline int32_t mipsdsp_cmp_eq(int32_t a, int32_t b) +{ + return a == b; +} + +static inline int32_t mipsdsp_cmp_le(int32_t a, int32_t b) +{ + return a <= b; +} + +static inline int32_t mipsdsp_cmp_lt(int32_t a, int32_t b) +{ + return a < b; +} + +static inline int32_t mipsdsp_cmpu_eq(uint32_t a, uint32_t b) +{ + return a == b; +} + +static inline int32_t mipsdsp_cmpu_le(uint32_t a, uint32_t b) +{ + return a <= b; +} + +static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) +{ + return a < b; +} +/*** MIPS DSP internal functions end ***/ From 853c3240c0753735b82fe80a86123e09234f5448 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:02 +0800 Subject: [PATCH 132/291] target-mips: Add ASE DSP resources access check Add MIPS ASE DSP resources access check. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- linux-user/main.c | 6 ++++++ target-mips/cpu.h | 23 +++++++++++++++++++++-- target-mips/helper.c | 3 +++ target-mips/translate.c | 23 +++++++++++++++++++++++ 4 files changed, 53 insertions(+), 2 deletions(-) diff --git a/linux-user/main.c b/linux-user/main.c index 5d20abd3e5..25e35cd3dc 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -2286,6 +2286,12 @@ done_syscall: queue_signal(env, info.si_signo, &info); } break; + case EXCP_DSPDIS: + info.si_signo = TARGET_SIGILL; + info.si_errno = 0; + info.si_code = TARGET_ILL_ILLOPC; + queue_signal(env, info.si_signo, &info); + break; default: // error: fprintf(stderr, "qemu: unhandled CPU exception 0x%x - aborting\n", diff --git a/target-mips/cpu.h b/target-mips/cpu.h index c4ca2855df..4c012d503f 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -415,7 +415,7 @@ struct CPUMIPSState { int error_code; uint32_t hflags; /* CPU State */ /* TMASK defines different execution modes */ -#define MIPS_HFLAG_TMASK 0x007FF +#define MIPS_HFLAG_TMASK 0xC07FF #define MIPS_HFLAG_MODE 0x00007 /* execution modes */ /* The KSU flags must be the lowest bits in hflags. The flag order must be the same as defined for CP0 Status. This allows to use @@ -453,6 +453,9 @@ struct CPUMIPSState { #define MIPS_HFLAG_BDS32 0x10000 /* branch requires 32-bit delay slot */ #define MIPS_HFLAG_BX 0x20000 /* branch exchanges execution mode */ #define MIPS_HFLAG_BMASK (MIPS_HFLAG_BMASK_BASE | MIPS_HFLAG_BMASK_EXT) + /* MIPS DSP resources access. */ +#define MIPS_HFLAG_DSP 0x40000 /* Enable access to MIPS DSP resources. */ +#define MIPS_HFLAG_DSPR2 0x80000 /* Enable access to MIPS DSPR2 resources. */ target_ulong btarget; /* Jump / branch target */ target_ulong bcond; /* Branch condition (if needed) */ @@ -610,8 +613,9 @@ enum { EXCP_MDMX, EXCP_C2E, EXCP_CACHE, /* 32 */ + EXCP_DSPDIS, - EXCP_LAST = EXCP_CACHE, + EXCP_LAST = EXCP_DSPDIS, }; /* Dummy exception for conditional stores. */ #define EXCP_SC 0x100 @@ -772,6 +776,21 @@ static inline void compute_hflags(CPUMIPSState *env) if (env->CP0_Status & (1 << CP0St_FR)) { env->hflags |= MIPS_HFLAG_F64; } + if (env->insn_flags & ASE_DSPR2) { + /* Enables access MIPS DSP resources, now our cpu is DSP ASER2, + so enable to access DSPR2 resources. */ + if (env->CP0_Status & (1 << CP0St_MX)) { + env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; + } + + } else if (env->insn_flags & ASE_DSP) { + /* Enables access MIPS DSP resources, now our cpu is DSP ASE, + so enable to access DSP resources. */ + if (env->CP0_Status & (1 << CP0St_MX)) { + env->hflags |= MIPS_HFLAG_DSP; + } + + } if (env->insn_flags & ISA_MIPS32R2) { if (env->active_fpu.fcr0 & (1 << FCR0_F64)) { env->hflags |= MIPS_HFLAG_COP1X; diff --git a/target-mips/helper.c b/target-mips/helper.c index 3b8c696a9e..e877b8db78 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -592,6 +592,9 @@ void do_interrupt (CPUMIPSState *env) case EXCP_THREAD: cause = 25; goto set_EPC; + case EXCP_DSPDIS: + cause = 26; + goto set_EPC; case EXCP_CACHE: cause = 30; if (env->CP0_Status & (1 << CP0St_BEV)) { diff --git a/target-mips/translate.c b/target-mips/translate.c index ed55e260ac..586f564e27 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -948,6 +948,24 @@ static inline void check_cp1_registers(DisasContext *ctx, int regs) generate_exception(ctx, EXCP_RI); } +/* Verify that the processor is running with DSP instructions enabled. + This is enabled by CP0 Status register MX(24) bit. + */ + +static inline void check_dsp(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { + generate_exception(ctx, EXCP_DSPDIS); + } +} + +static inline void check_dspr2(DisasContext *ctx) +{ + if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) { + generate_exception(ctx, EXCP_DSPDIS); + } +} + /* This code generates a "reserved instruction" exception if the CPU does not support the instruction set corresponding to flags. */ static inline void check_insn(CPUMIPSState *env, DisasContext *ctx, int flags) @@ -13209,6 +13227,11 @@ void cpu_state_reset(CPUMIPSState *env) if (env->CP0_Config1 & (1 << CP0C1_FP)) { env->CP0_Status |= (1 << CP0St_CU1); } + if (env->cpu_model->insn_flags & ASE_DSPR2) { + env->hflags |= MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2; + } else if (env->cpu_model->insn_flags & ASE_DSP) { + env->hflags |= MIPS_HFLAG_DSP; + } #else if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, From 4133498f8e532f9a32dae2153ef5e14433626e9f Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:03 +0800 Subject: [PATCH 133/291] Use correct acc value to index cpu_HI/cpu_LO rather than using a fix number Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 122 +++++++++++++++++++++++++++++++--------- 1 file changed, 95 insertions(+), 27 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 586f564e27..134d06f9f0 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -5,6 +5,7 @@ * Copyright (c) 2006 Marius Groeger (FPU operations) * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * Copyright (c) 2012 Jia Liu & Dongxue Zhang (MIPS ASE DSP support) * * This library is free software; you can redistribute it and/or * modify it under the terms of the GNU Lesser General Public @@ -2119,33 +2120,75 @@ static void gen_shift (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, static void gen_HILO (DisasContext *ctx, uint32_t opc, int reg) { const char *opn = "hilo"; + unsigned int acc; if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { /* Treat as NOP. */ MIPS_DEBUG("NOP"); return; } + + if (opc == OPC_MFHI || opc == OPC_MFLO) { + acc = ((ctx->opcode) >> 21) & 0x03; + } else { + acc = ((ctx->opcode) >> 11) & 0x03; + } + + if (acc != 0) { + check_dsp(ctx); + } + switch (opc) { case OPC_MFHI: - tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[0]); +#if defined(TARGET_MIPS64) + if (acc != 0) { + tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_HI[acc]); + } else +#endif + { + tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]); + } opn = "mfhi"; break; case OPC_MFLO: - tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[0]); +#if defined(TARGET_MIPS64) + if (acc != 0) { + tcg_gen_ext32s_tl(cpu_gpr[reg], cpu_LO[acc]); + } else +#endif + { + tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]); + } opn = "mflo"; break; case OPC_MTHI: - if (reg != 0) - tcg_gen_mov_tl(cpu_HI[0], cpu_gpr[reg]); - else - tcg_gen_movi_tl(cpu_HI[0], 0); + if (reg != 0) { +#if defined(TARGET_MIPS64) + if (acc != 0) { + tcg_gen_ext32s_tl(cpu_HI[acc], cpu_gpr[reg]); + } else +#endif + { + tcg_gen_mov_tl(cpu_HI[acc], cpu_gpr[reg]); + } + } else { + tcg_gen_movi_tl(cpu_HI[acc], 0); + } opn = "mthi"; break; case OPC_MTLO: - if (reg != 0) - tcg_gen_mov_tl(cpu_LO[0], cpu_gpr[reg]); - else - tcg_gen_movi_tl(cpu_LO[0], 0); + if (reg != 0) { +#if defined(TARGET_MIPS64) + if (acc != 0) { + tcg_gen_ext32s_tl(cpu_LO[acc], cpu_gpr[reg]); + } else +#endif + { + tcg_gen_mov_tl(cpu_LO[acc], cpu_gpr[reg]); + } + } else { + tcg_gen_movi_tl(cpu_LO[acc], 0); + } opn = "mtlo"; break; } @@ -2158,6 +2201,7 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { const char *opn = "mul/div"; TCGv t0, t1; + unsigned int acc; switch (opc) { case OPC_DIV: @@ -2220,6 +2264,10 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = ((ctx->opcode) >> 11) & 0x03; + if (acc != 0) { + check_dsp(ctx); + } tcg_gen_ext_tl_i64(t2, t0); tcg_gen_ext_tl_i64(t3, t1); @@ -2229,8 +2277,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "mult"; break; @@ -2238,6 +2286,10 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = ((ctx->opcode) >> 11) & 0x03; + if (acc != 0) { + check_dsp(ctx); + } tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); @@ -2249,8 +2301,8 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "multu"; break; @@ -2297,41 +2349,49 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = ((ctx->opcode) >> 11) & 0x03; + if (acc != 0) { + check_dsp(ctx); + } tcg_gen_ext_tl_i64(t2, t0); tcg_gen_ext_tl_i64(t3, t1); tcg_gen_mul_i64(t2, t2, t3); - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); tcg_temp_free_i64(t3); tcg_gen_trunc_i64_tl(t0, t2); tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "madd"; break; case OPC_MADDU: - { + { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = ((ctx->opcode) >> 11) & 0x03; + if (acc != 0) { + check_dsp(ctx); + } tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); tcg_gen_extu_tl_i64(t2, t0); tcg_gen_extu_tl_i64(t3, t1); tcg_gen_mul_i64(t2, t2, t3); - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); tcg_temp_free_i64(t3); tcg_gen_trunc_i64_tl(t0, t2); tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "maddu"; break; @@ -2339,19 +2399,23 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = ((ctx->opcode) >> 11) & 0x03; + if (acc != 0) { + check_dsp(ctx); + } tcg_gen_ext_tl_i64(t2, t0); tcg_gen_ext_tl_i64(t3, t1); tcg_gen_mul_i64(t2, t2, t3); - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); tcg_temp_free_i64(t3); tcg_gen_trunc_i64_tl(t0, t2); tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "msub"; break; @@ -2359,21 +2423,25 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, { TCGv_i64 t2 = tcg_temp_new_i64(); TCGv_i64 t3 = tcg_temp_new_i64(); + acc = ((ctx->opcode) >> 11) & 0x03; + if (acc != 0) { + check_dsp(ctx); + } tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); tcg_gen_extu_tl_i64(t2, t0); tcg_gen_extu_tl_i64(t3, t1); tcg_gen_mul_i64(t2, t2, t3); - tcg_gen_concat_tl_i64(t3, cpu_LO[0], cpu_HI[0]); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); tcg_temp_free_i64(t3); tcg_gen_trunc_i64_tl(t0, t2); tcg_gen_shri_i64(t2, t2, 32); tcg_gen_trunc_i64_tl(t1, t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[0], t0); - tcg_gen_ext32s_tl(cpu_HI[0], t1); + tcg_gen_ext32s_tl(cpu_LO[acc], t0); + tcg_gen_ext32s_tl(cpu_HI[acc], t1); } opn = "msubu"; break; From e45a93e2590051e77a3d944a0feb3360a1ff1841 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:04 +0800 Subject: [PATCH 134/291] target-mips: Add ASE DSP branch instructions Add MIPS ASE DSP Branch instructions. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 134d06f9f0..6677d2b531 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -332,6 +332,14 @@ enum { OPC_DSHD = (0x05 << 6) | OPC_DBSHFL, }; +/* MIPS DSP REGIMM opcodes */ +enum { + OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, +#if defined(TARGET_MIPS64) + OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, +#endif +}; + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -3230,6 +3238,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, } btgt = ctx->pc + insn_bytes + offset; break; + case OPC_BPOSGE32: +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x7F); +#else + tcg_gen_andi_tl(t0, cpu_dspctrl, 0x3F); +#endif + bcond_compute = 1; + btgt = ctx->pc + insn_bytes + offset; + break; case OPC_J: case OPC_JAL: case OPC_JALX: @@ -3418,6 +3436,16 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt); goto likely; + case OPC_BPOSGE32: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); + MIPS_DEBUG("bposge32 " TARGET_FMT_lx, btgt); + goto not_likely; +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: + tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); + MIPS_DEBUG("bposge64 " TARGET_FMT_lx, btgt); + goto not_likely; +#endif case OPC_BLTZALS: case OPC_BLTZAL: ctx->hflags |= (opc == OPC_BLTZALS @@ -12589,6 +12617,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, ISA_MIPS32R2); /* Treat as NOP. */ break; + case OPC_BPOSGE32: /* MIPS DSP branch */ +#if defined(TARGET_MIPS64) + case OPC_BPOSGE64: +#endif + check_dsp(ctx); + gen_compute_branch(ctx, op1, 4, -1, -2, (int32_t)imm << 2); + *is_branch = 1; + break; default: /* Invalid */ MIPS_INVAL("regimm"); generate_exception(ctx, EXCP_RI); From 9b1a1d68d0411cf67502b2adb3daae2eb157b704 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:05 +0800 Subject: [PATCH 135/291] target-mips: Add ASE DSP load instructions Add MIPS ASE DSP Load instructions. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 88 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 6677d2b531..fdff3273ad 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -313,6 +313,9 @@ enum { OPC_MODU_G_2E = 0x23 | OPC_SPECIAL3, OPC_DMOD_G_2E = 0x26 | OPC_SPECIAL3, OPC_DMODU_G_2E = 0x27 | OPC_SPECIAL3, + + /* MIPS DSP Load */ + OPC_LX_DSP = 0x0A | OPC_SPECIAL3, }; /* BSHFL opcodes */ @@ -340,6 +343,17 @@ enum { #endif }; +#define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +/* MIPS DSP Load */ +enum { + OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, + OPC_LHX = (0x04 << 6) | OPC_LX_DSP, + OPC_LWX = (0x00 << 6) | OPC_LX_DSP, +#if defined(TARGET_MIPS64) + OPC_LDX = (0x08 << 6) | OPC_LX_DSP, +#endif +}; + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -12219,6 +12233,63 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx, int *is_b #endif +/* MIPSDSP functions. */ +static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, + int rd, int base, int offset) +{ + const char *opn = "ldx"; + TCGv t0; + + if (rd == 0) { + MIPS_DEBUG("NOP"); + return; + } + + check_dsp(ctx); + t0 = tcg_temp_new(); + + if (base == 0) { + gen_load_gpr(t0, offset); + } else if (offset == 0) { + gen_load_gpr(t0, base); + } else { + gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); + } + + save_cpu_state(ctx, 0); + switch (opc) { + case OPC_LBUX: + op_ld_lbu(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lbux"; + break; + case OPC_LHX: + op_ld_lh(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lhx"; + break; + case OPC_LWX: + op_ld_lw(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "lwx"; + break; +#if defined(TARGET_MIPS64) + case OPC_LDX: + op_ld_ld(t0, t0, ctx); + gen_store_gpr(t0, rd); + opn = "ldx"; + break; +#endif + } + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s %s, %s(%s)", opn, + regnames[rd], regnames[offset], regnames[base]); + tcg_temp_free(t0); +} + + +/* End MIPSDSP functions. */ + static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) { int32_t offset; @@ -12575,6 +12646,23 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, INSN_LOONGSON2E); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + case OPC_LX_DSP: + op2 = MASK_LX(ctx->opcode); + switch (op2) { +#if defined(TARGET_MIPS64) + case OPC_LDX: +#endif + case OPC_LBUX: + case OPC_LHX: + case OPC_LWX: + gen_mipsdsp_ld(env, ctx, op2, rd, rs, rt); + break; + default: /* Invalid */ + MIPS_INVAL("MASK LX"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: From 461c08df75d8564a3ef8582bfcda398e9b09c0ff Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:06 +0800 Subject: [PATCH 136/291] target-mips: Add ASE DSP arithmetic instructions Add MIPS ASE DSP Arithmetic instructions. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 894 +++++++++++++++++++++++++++++++++++++++ target-mips/helper.h | 126 ++++++ target-mips/translate.c | 795 +++++++++++++++++++++++++++++++++- 3 files changed, 1812 insertions(+), 3 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 55ea9236fa..7ddad34d10 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -1061,3 +1061,897 @@ static inline int32_t mipsdsp_cmpu_lt(uint32_t a, uint32_t b) return a < b; } /*** MIPS DSP internal functions end ***/ + +#define MIPSDSP_LHI 0xFFFFFFFF00000000ull +#define MIPSDSP_LLO 0x00000000FFFFFFFFull +#define MIPSDSP_HI 0xFFFF0000 +#define MIPSDSP_LO 0x0000FFFF +#define MIPSDSP_Q3 0xFF000000 +#define MIPSDSP_Q2 0x00FF0000 +#define MIPSDSP_Q1 0x0000FF00 +#define MIPSDSP_Q0 0x000000FF + +#define MIPSDSP_SPLIT32_8(num, a, b, c, d) \ + do { \ + a = (num >> 24) & MIPSDSP_Q0; \ + b = (num >> 16) & MIPSDSP_Q0; \ + c = (num >> 8) & MIPSDSP_Q0; \ + d = num & MIPSDSP_Q0; \ + } while (0) + +#define MIPSDSP_SPLIT32_16(num, a, b) \ + do { \ + a = (num >> 16) & MIPSDSP_LO; \ + b = num & MIPSDSP_LO; \ + } while (0) + +#define MIPSDSP_RETURN32(a) ((target_long)(int32_t)a) +#define MIPSDSP_RETURN32_8(a, b, c, d) ((target_long)(int32_t) \ + (((uint32_t)a << 24) | \ + (((uint32_t)b << 16) | \ + (((uint32_t)c << 8) | \ + ((uint32_t)d & 0xFF))))) +#define MIPSDSP_RETURN32_16(a, b) ((target_long)(int32_t) \ + (((uint32_t)a << 16) | \ + ((uint32_t)b & 0xFFFF))) + +#ifdef TARGET_MIPS64 +#define MIPSDSP_SPLIT64_16(num, a, b, c, d) \ + do { \ + a = (num >> 48) & MIPSDSP_LO; \ + b = (num >> 32) & MIPSDSP_LO; \ + c = (num >> 16) & MIPSDSP_LO; \ + d = num & MIPSDSP_LO; \ + } while (0) + +#define MIPSDSP_SPLIT64_32(num, a, b) \ + do { \ + a = (num >> 32) & MIPSDSP_LLO; \ + b = num & MIPSDSP_LLO; \ + } while (0) + +#define MIPSDSP_RETURN64_16(a, b, c, d) (((uint64_t)a << 48) | \ + ((uint64_t)b << 32) | \ + ((uint64_t)c << 16) | \ + (uint64_t)d) +#define MIPSDSP_RETURN64_32(a, b) (((uint64_t)a << 32) | (uint64_t)b) +#endif + +/** DSP Arithmetic Sub-class insns **/ +#define ARITH_PH(name, func) \ +target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt) \ +{ \ + uint16_t rsh, rsl, rth, rtl, temph, templ; \ + \ + MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ + MIPSDSP_SPLIT32_16(rt, rth, rtl); \ + \ + temph = mipsdsp_##func(rsh, rth); \ + templ = mipsdsp_##func(rsl, rtl); \ + \ + return MIPSDSP_RETURN32_16(temph, templ); \ +} + +#define ARITH_PH_ENV(name, func) \ +target_ulong helper_##name##_ph(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint16_t rsh, rsl, rth, rtl, temph, templ; \ + \ + MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ + MIPSDSP_SPLIT32_16(rt, rth, rtl); \ + \ + temph = mipsdsp_##func(rsh, rth, env); \ + templ = mipsdsp_##func(rsl, rtl, env); \ + \ + return MIPSDSP_RETURN32_16(temph, templ); \ +} + + +ARITH_PH_ENV(addq, add_i16); +ARITH_PH_ENV(addq_s, sat_add_i16); +ARITH_PH_ENV(addu, add_u16); +ARITH_PH_ENV(addu_s, sat_add_u16); + +ARITH_PH(addqh, rshift1_add_q16); +ARITH_PH(addqh_r, rrshift1_add_q16); + +ARITH_PH_ENV(subq, sub_i16); +ARITH_PH_ENV(subq_s, sat16_sub); +ARITH_PH_ENV(subu, sub_u16_u16); +ARITH_PH_ENV(subu_s, satu16_sub_u16_u16); + +ARITH_PH(subqh, rshift1_sub_q16); +ARITH_PH(subqh_r, rrshift1_sub_q16); + +#undef ARITH_PH +#undef ARITH_PH_ENV + +#ifdef TARGET_MIPS64 +#define ARITH_QH_ENV(name, func) \ +target_ulong helper_##name##_qh(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint16_t rs3, rs2, rs1, rs0; \ + uint16_t rt3, rt2, rt1, rt0; \ + uint16_t tempD, tempC, tempB, tempA; \ + \ + MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \ + MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ + \ + tempD = mipsdsp_##func(rs3, rt3, env); \ + tempC = mipsdsp_##func(rs2, rt2, env); \ + tempB = mipsdsp_##func(rs1, rt1, env); \ + tempA = mipsdsp_##func(rs0, rt0, env); \ + \ + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \ +} + +ARITH_QH_ENV(addq, add_i16); +ARITH_QH_ENV(addq_s, sat_add_i16); +ARITH_QH_ENV(addu, add_u16); +ARITH_QH_ENV(addu_s, sat_add_u16); + +ARITH_QH_ENV(subq, sub_i16); +ARITH_QH_ENV(subq_s, sat16_sub); +ARITH_QH_ENV(subu, sub_u16_u16); +ARITH_QH_ENV(subu_s, satu16_sub_u16_u16); + +#undef ARITH_QH_ENV + +#endif + +#define ARITH_W(name, func) \ +target_ulong helper_##name##_w(target_ulong rs, target_ulong rt) \ +{ \ + uint32_t rd; \ + rd = mipsdsp_##func(rs, rt); \ + return MIPSDSP_RETURN32(rd); \ +} + +#define ARITH_W_ENV(name, func) \ +target_ulong helper_##name##_w(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint32_t rd; \ + rd = mipsdsp_##func(rs, rt, env); \ + return MIPSDSP_RETURN32(rd); \ +} + +ARITH_W_ENV(addq_s, sat_add_i32); + +ARITH_W(addqh, rshift1_add_q32); +ARITH_W(addqh_r, rrshift1_add_q32); + +ARITH_W_ENV(subq_s, sat32_sub); + +ARITH_W(subqh, rshift1_sub_q32); +ARITH_W(subqh_r, rrshift1_sub_q32); + +#undef ARITH_W +#undef ARITH_W_ENV + +target_ulong helper_absq_s_w(target_ulong rt, CPUMIPSState *env) +{ + uint32_t rd; + + rd = mipsdsp_sat_abs32(rt, env); + + return (target_ulong)rd; +} + + +#if defined(TARGET_MIPS64) + +#define ARITH_PW_ENV(name, func) \ +target_ulong helper_##name##_pw(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint32_t rs1, rs0; \ + uint32_t rt1, rt0; \ + uint32_t tempB, tempA; \ + \ + MIPSDSP_SPLIT64_32(rs, rs1, rs0); \ + MIPSDSP_SPLIT64_32(rt, rt1, rt0); \ + \ + tempB = mipsdsp_##func(rs1, rt1, env); \ + tempA = mipsdsp_##func(rs0, rt0, env); \ + \ + return MIPSDSP_RETURN64_32(tempB, tempA); \ +} + +ARITH_PW_ENV(addq, add_i32); +ARITH_PW_ENV(addq_s, sat_add_i32); +ARITH_PW_ENV(subq, sub32); +ARITH_PW_ENV(subq_s, sat32_sub); + +#undef ARITH_PW_ENV + +#endif + +#define ARITH_QB(name, func) \ +target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \ +{ \ + uint8_t rs0, rs1, rs2, rs3; \ + uint8_t rt0, rt1, rt2, rt3; \ + uint8_t temp0, temp1, temp2, temp3; \ + \ + MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \ + MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ + \ + temp0 = mipsdsp_##func(rs0, rt0); \ + temp1 = mipsdsp_##func(rs1, rt1); \ + temp2 = mipsdsp_##func(rs2, rt2); \ + temp3 = mipsdsp_##func(rs3, rt3); \ + \ + return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \ +} + +#define ARITH_QB_ENV(name, func) \ +target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint8_t rs0, rs1, rs2, rs3; \ + uint8_t rt0, rt1, rt2, rt3; \ + uint8_t temp0, temp1, temp2, temp3; \ + \ + MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \ + MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ + \ + temp0 = mipsdsp_##func(rs0, rt0, env); \ + temp1 = mipsdsp_##func(rs1, rt1, env); \ + temp2 = mipsdsp_##func(rs2, rt2, env); \ + temp3 = mipsdsp_##func(rs3, rt3, env); \ + \ + return MIPSDSP_RETURN32_8(temp3, temp2, temp1, temp0); \ +} + +ARITH_QB(adduh, rshift1_add_u8); +ARITH_QB(adduh_r, rrshift1_add_u8); + +ARITH_QB_ENV(addu, add_u8); +ARITH_QB_ENV(addu_s, sat_add_u8); + +#undef ADDU_QB +#undef ADDU_QB_ENV + +#if defined(TARGET_MIPS64) +#define ARITH_OB(name, func) \ +target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt) \ +{ \ + int i; \ + uint8_t rs_t[8], rt_t[8]; \ + uint8_t temp[8]; \ + uint64_t result; \ + \ + result = 0; \ + \ + for (i = 0; i < 8; i++) { \ + rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \ + rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \ + temp[i] = mipsdsp_##func(rs_t[i], rt_t[i]); \ + result |= (uint64_t)temp[i] << (8 * i); \ + } \ + \ + return result; \ +} + +#define ARITH_OB_ENV(name, func) \ +target_ulong helper_##name##_ob(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int i; \ + uint8_t rs_t[8], rt_t[8]; \ + uint8_t temp[8]; \ + uint64_t result; \ + \ + result = 0; \ + \ + for (i = 0; i < 8; i++) { \ + rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; \ + rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \ + temp[i] = mipsdsp_##func(rs_t[i], rt_t[i], env); \ + result |= (uint64_t)temp[i] << (8 * i); \ + } \ + \ + return result; \ +} + +ARITH_OB_ENV(addu, add_u8); +ARITH_OB_ENV(addu_s, sat_add_u8); + +ARITH_OB(adduh, rshift1_add_u8); +ARITH_OB(adduh_r, rrshift1_add_u8); + +ARITH_OB_ENV(subu, sub_u8); +ARITH_OB_ENV(subu_s, satu8_sub); + +ARITH_OB(subuh, rshift1_sub_u8); +ARITH_OB(subuh_r, rrshift1_sub_u8); + +#undef ARITH_OB +#undef ARITH_OB_ENV + +#endif + +#define SUBU_QB(name, func) \ +target_ulong helper_##name##_qb(target_ulong rs, \ + target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint8_t rs3, rs2, rs1, rs0; \ + uint8_t rt3, rt2, rt1, rt0; \ + uint8_t tempD, tempC, tempB, tempA; \ + \ + MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \ + MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ + \ + tempD = mipsdsp_##func(rs3, rt3, env); \ + tempC = mipsdsp_##func(rs2, rt2, env); \ + tempB = mipsdsp_##func(rs1, rt1, env); \ + tempA = mipsdsp_##func(rs0, rt0, env); \ + \ + return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \ +} + +SUBU_QB(subu, sub_u8); +SUBU_QB(subu_s, satu8_sub); + +#undef SUBU_QB + +#define SUBUH_QB(name, var) \ +target_ulong helper_##name##_qb(target_ulong rs, target_ulong rt) \ +{ \ + uint8_t rs3, rs2, rs1, rs0; \ + uint8_t rt3, rt2, rt1, rt0; \ + uint8_t tempD, tempC, tempB, tempA; \ + \ + MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); \ + MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ + \ + tempD = ((uint16_t)rs3 - (uint16_t)rt3 + var) >> 1; \ + tempC = ((uint16_t)rs2 - (uint16_t)rt2 + var) >> 1; \ + tempB = ((uint16_t)rs1 - (uint16_t)rt1 + var) >> 1; \ + tempA = ((uint16_t)rs0 - (uint16_t)rt0 + var) >> 1; \ + \ + return ((uint32_t)tempD << 24) | ((uint32_t)tempC << 16) | \ + ((uint32_t)tempB << 8) | ((uint32_t)tempA); \ +} + +SUBUH_QB(subuh, 0); +SUBUH_QB(subuh_r, 1); + +#undef SUBUH_QB + +target_ulong helper_addsc(target_ulong rs, target_ulong rt, CPUMIPSState *env) +{ + uint64_t temp, tempRs, tempRt; + int32_t flag; + + tempRs = (uint64_t)rs & MIPSDSP_LLO; + tempRt = (uint64_t)rt & MIPSDSP_LLO; + + temp = tempRs + tempRt; + flag = (temp & 0x0100000000ull) >> 32; + set_DSPControl_carryflag(flag, env); + + return (target_long)(int32_t)(temp & MIPSDSP_LLO); +} + +target_ulong helper_addwc(target_ulong rs, target_ulong rt, CPUMIPSState *env) +{ + uint32_t rd; + int32_t temp32, temp31; + int64_t tempL; + + tempL = (int64_t)(int32_t)rs + (int64_t)(int32_t)rt + + get_DSPControl_carryflag(env); + temp31 = (tempL >> 31) & 0x01; + temp32 = (tempL >> 32) & 0x01; + + if (temp31 != temp32) { + set_DSPControl_overflow_flag(1, 20, env); + } + + rd = tempL & MIPSDSP_LLO; + + return (target_long)(int32_t)rd; +} + +target_ulong helper_modsub(target_ulong rs, target_ulong rt) +{ + int32_t decr; + uint16_t lastindex; + target_ulong rd; + + decr = rt & MIPSDSP_Q0; + lastindex = (rt >> 8) & MIPSDSP_LO; + + if ((rs & MIPSDSP_LLO) == 0x00000000) { + rd = (target_ulong)lastindex; + } else { + rd = rs - decr; + } + + return rd; +} + +target_ulong helper_raddu_w_qb(target_ulong rs) +{ + uint8_t rs3, rs2, rs1, rs0; + uint16_t temp; + + MIPSDSP_SPLIT32_8(rs, rs3, rs2, rs1, rs0); + + temp = (uint16_t)rs3 + (uint16_t)rs2 + (uint16_t)rs1 + (uint16_t)rs0; + + return (target_ulong)temp; +} + +#if defined(TARGET_MIPS64) +target_ulong helper_raddu_l_ob(target_ulong rs) +{ + int i; + uint16_t rs_t[8]; + uint64_t temp; + + temp = 0; + + for (i = 0; i < 8; i++) { + rs_t[i] = (rs >> (8 * i)) & MIPSDSP_Q0; + temp += (uint64_t)rs_t[i]; + } + + return temp; +} +#endif + +target_ulong helper_absq_s_qb(target_ulong rt, CPUMIPSState *env) +{ + uint8_t tempD, tempC, tempB, tempA; + + MIPSDSP_SPLIT32_8(rt, tempD, tempC, tempB, tempA); + + tempD = mipsdsp_sat_abs8(tempD, env); + tempC = mipsdsp_sat_abs8(tempC, env); + tempB = mipsdsp_sat_abs8(tempB, env); + tempA = mipsdsp_sat_abs8(tempA, env); + + return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); +} + +target_ulong helper_absq_s_ph(target_ulong rt, CPUMIPSState *env) +{ + uint16_t tempB, tempA; + + MIPSDSP_SPLIT32_16(rt, tempB, tempA); + + tempB = mipsdsp_sat_abs16 (tempB, env); + tempA = mipsdsp_sat_abs16 (tempA, env); + + return MIPSDSP_RETURN32_16(tempB, tempA); +} + +#if defined(TARGET_MIPS64) +target_ulong helper_absq_s_ob(target_ulong rt, CPUMIPSState *env) +{ + int i; + int8_t temp[8]; + uint64_t result; + + for (i = 0; i < 8; i++) { + temp[i] = (rt >> (8 * i)) & MIPSDSP_Q0; + temp[i] = mipsdsp_sat_abs8(temp[i], env); + } + + for (i = 0; i < 8; i++) { + result = (uint64_t)(uint8_t)temp[i] << (8 * i); + } + + return result; +} + +target_ulong helper_absq_s_qh(target_ulong rt, CPUMIPSState *env) +{ + int16_t tempD, tempC, tempB, tempA; + + MIPSDSP_SPLIT64_16(rt, tempD, tempC, tempB, tempA); + + tempD = mipsdsp_sat_abs16(tempD, env); + tempC = mipsdsp_sat_abs16(tempC, env); + tempB = mipsdsp_sat_abs16(tempB, env); + tempA = mipsdsp_sat_abs16(tempA, env); + + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); +} + +target_ulong helper_absq_s_pw(target_ulong rt, CPUMIPSState *env) +{ + int32_t tempB, tempA; + + MIPSDSP_SPLIT64_32(rt, tempB, tempA); + + tempB = mipsdsp_sat_abs32(tempB, env); + tempA = mipsdsp_sat_abs32(tempA, env); + + return MIPSDSP_RETURN64_32(tempB, tempA); +} +#endif + +#define PRECR_QB_PH(name, a, b)\ +target_ulong helper_##name##_qb_ph(target_ulong rs, target_ulong rt) \ +{ \ + uint8_t tempD, tempC, tempB, tempA; \ + \ + tempD = (rs >> a) & MIPSDSP_Q0; \ + tempC = (rs >> b) & MIPSDSP_Q0; \ + tempB = (rt >> a) & MIPSDSP_Q0; \ + tempA = (rt >> b) & MIPSDSP_Q0; \ + \ + return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); \ +} + +PRECR_QB_PH(precr, 16, 0); +PRECR_QB_PH(precrq, 24, 8); + +#undef PRECR_QB_OH + +target_ulong helper_precr_sra_ph_w(uint32_t sa, target_ulong rs, + target_ulong rt) +{ + uint16_t tempB, tempA; + + tempB = ((int32_t)rt >> sa) & MIPSDSP_LO; + tempA = ((int32_t)rs >> sa) & MIPSDSP_LO; + + return MIPSDSP_RETURN32_16(tempB, tempA); +} + +target_ulong helper_precr_sra_r_ph_w(uint32_t sa, + target_ulong rs, target_ulong rt) +{ + uint64_t tempB, tempA; + + /* If sa = 0, then (sa - 1) = -1 will case shift error, so we need else. */ + if (sa == 0) { + tempB = (rt & MIPSDSP_LO) << 1; + tempA = (rs & MIPSDSP_LO) << 1; + } else { + tempB = ((int32_t)rt >> (sa - 1)) + 1; + tempA = ((int32_t)rs >> (sa - 1)) + 1; + } + rt = (((tempB >> 1) & MIPSDSP_LO) << 16) | ((tempA >> 1) & MIPSDSP_LO); + + return (target_long)(int32_t)rt; +} + +target_ulong helper_precrq_ph_w(target_ulong rs, target_ulong rt) +{ + uint16_t tempB, tempA; + + tempB = (rs & MIPSDSP_HI) >> 16; + tempA = (rt & MIPSDSP_HI) >> 16; + + return MIPSDSP_RETURN32_16(tempB, tempA); +} + +target_ulong helper_precrq_rs_ph_w(target_ulong rs, target_ulong rt, + CPUMIPSState *env) +{ + uint16_t tempB, tempA; + + tempB = mipsdsp_trunc16_sat16_round(rs, env); + tempA = mipsdsp_trunc16_sat16_round(rt, env); + + return MIPSDSP_RETURN32_16(tempB, tempA); +} + +#if defined(TARGET_MIPS64) +target_ulong helper_precr_ob_qh(target_ulong rs, target_ulong rt) +{ + uint8_t rs6, rs4, rs2, rs0; + uint8_t rt6, rt4, rt2, rt0; + uint64_t temp; + + rs6 = (rs >> 48) & MIPSDSP_Q0; + rs4 = (rs >> 32) & MIPSDSP_Q0; + rs2 = (rs >> 16) & MIPSDSP_Q0; + rs0 = rs & MIPSDSP_Q0; + rt6 = (rt >> 48) & MIPSDSP_Q0; + rt4 = (rt >> 32) & MIPSDSP_Q0; + rt2 = (rt >> 16) & MIPSDSP_Q0; + rt0 = rt & MIPSDSP_Q0; + + temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) | + ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) | + ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) | + ((uint64_t)rt2 << 8) | (uint64_t)rt0; + + return temp; +} + +#define PRECR_QH_PW(name, var) \ +target_ulong helper_precr_##name##_qh_pw(target_ulong rs, target_ulong rt, \ + uint32_t sa) \ +{ \ + uint16_t rs3, rs2, rs1, rs0; \ + uint16_t rt3, rt2, rt1, rt0; \ + uint16_t tempD, tempC, tempB, tempA; \ + \ + MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \ + MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ + \ + /* When sa = 0, we use rt2, rt0, rs2, rs0; \ + * when sa != 0, we use rt3, rt1, rs3, rs1. */ \ + if (sa == 0) { \ + tempD = rt2 << var; \ + tempC = rt0 << var; \ + tempB = rs2 << var; \ + tempA = rs0 << var; \ + } else { \ + tempD = (((int16_t)rt3 >> sa) + var) >> var; \ + tempC = (((int16_t)rt1 >> sa) + var) >> var; \ + tempB = (((int16_t)rs3 >> sa) + var) >> var; \ + tempA = (((int16_t)rs1 >> sa) + var) >> var; \ + } \ + \ + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \ +} + +PRECR_QH_PW(sra, 0); +PRECR_QH_PW(sra_r, 1); + +#undef PRECR_QH_PW + +target_ulong helper_precrq_ob_qh(target_ulong rs, target_ulong rt) +{ + uint8_t rs6, rs4, rs2, rs0; + uint8_t rt6, rt4, rt2, rt0; + uint64_t temp; + + rs6 = (rs >> 56) & MIPSDSP_Q0; + rs4 = (rs >> 40) & MIPSDSP_Q0; + rs2 = (rs >> 24) & MIPSDSP_Q0; + rs0 = (rs >> 8) & MIPSDSP_Q0; + rt6 = (rt >> 56) & MIPSDSP_Q0; + rt4 = (rt >> 40) & MIPSDSP_Q0; + rt2 = (rt >> 24) & MIPSDSP_Q0; + rt0 = (rt >> 8) & MIPSDSP_Q0; + + temp = ((uint64_t)rs6 << 56) | ((uint64_t)rs4 << 48) | + ((uint64_t)rs2 << 40) | ((uint64_t)rs0 << 32) | + ((uint64_t)rt6 << 24) | ((uint64_t)rt4 << 16) | + ((uint64_t)rt2 << 8) | (uint64_t)rt0; + + return temp; +} + +target_ulong helper_precrq_qh_pw(target_ulong rs, target_ulong rt) +{ + uint16_t tempD, tempC, tempB, tempA; + + tempD = (rs >> 48) & MIPSDSP_LO; + tempC = (rs >> 16) & MIPSDSP_LO; + tempB = (rt >> 48) & MIPSDSP_LO; + tempA = (rt >> 16) & MIPSDSP_LO; + + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); +} + +target_ulong helper_precrq_rs_qh_pw(target_ulong rs, target_ulong rt, + CPUMIPSState *env) +{ + uint32_t rs2, rs0; + uint32_t rt2, rt0; + uint16_t tempD, tempC, tempB, tempA; + + rs2 = (rs >> 32) & MIPSDSP_LLO; + rs0 = rs & MIPSDSP_LLO; + rt2 = (rt >> 32) & MIPSDSP_LLO; + rt0 = rt & MIPSDSP_LLO; + + tempD = mipsdsp_trunc16_sat16_round(rs2, env); + tempC = mipsdsp_trunc16_sat16_round(rs0, env); + tempB = mipsdsp_trunc16_sat16_round(rt2, env); + tempA = mipsdsp_trunc16_sat16_round(rt0, env); + + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); +} + +target_ulong helper_precrq_pw_l(target_ulong rs, target_ulong rt) +{ + uint32_t tempB, tempA; + + tempB = (rs >> 32) & MIPSDSP_LLO; + tempA = (rt >> 32) & MIPSDSP_LLO; + + return MIPSDSP_RETURN64_32(tempB, tempA); +} +#endif + +target_ulong helper_precrqu_s_qb_ph(target_ulong rs, target_ulong rt, + CPUMIPSState *env) +{ + uint8_t tempD, tempC, tempB, tempA; + uint16_t rsh, rsl, rth, rtl; + + rsh = (rs & MIPSDSP_HI) >> 16; + rsl = rs & MIPSDSP_LO; + rth = (rt & MIPSDSP_HI) >> 16; + rtl = rt & MIPSDSP_LO; + + tempD = mipsdsp_sat8_reduce_precision(rsh, env); + tempC = mipsdsp_sat8_reduce_precision(rsl, env); + tempB = mipsdsp_sat8_reduce_precision(rth, env); + tempA = mipsdsp_sat8_reduce_precision(rtl, env); + + return MIPSDSP_RETURN32_8(tempD, tempC, tempB, tempA); +} + +#if defined(TARGET_MIPS64) +target_ulong helper_precrqu_s_ob_qh(target_ulong rs, target_ulong rt, + CPUMIPSState *env) +{ + int i; + uint16_t rs3, rs2, rs1, rs0; + uint16_t rt3, rt2, rt1, rt0; + uint8_t temp[8]; + uint64_t result; + + result = 0; + + MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); + MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); + + temp[7] = mipsdsp_sat8_reduce_precision(rs3, env); + temp[6] = mipsdsp_sat8_reduce_precision(rs2, env); + temp[5] = mipsdsp_sat8_reduce_precision(rs1, env); + temp[4] = mipsdsp_sat8_reduce_precision(rs0, env); + temp[3] = mipsdsp_sat8_reduce_precision(rt3, env); + temp[2] = mipsdsp_sat8_reduce_precision(rt2, env); + temp[1] = mipsdsp_sat8_reduce_precision(rt1, env); + temp[0] = mipsdsp_sat8_reduce_precision(rt0, env); + + for (i = 0; i < 8; i++) { + result |= (uint64_t)temp[i] << (8 * i); + } + + return result; +} + +#define PRECEQ_PW(name, a, b) \ +target_ulong helper_preceq_pw_##name(target_ulong rt) \ +{ \ + uint16_t tempB, tempA; \ + uint32_t tempBI, tempAI; \ + \ + tempB = (rt >> a) & MIPSDSP_LO; \ + tempA = (rt >> b) & MIPSDSP_LO; \ + \ + tempBI = (uint32_t)tempB << 16; \ + tempAI = (uint32_t)tempA << 16; \ + \ + return MIPSDSP_RETURN64_32(tempBI, tempAI); \ +} + +PRECEQ_PW(qhl, 48, 32); +PRECEQ_PW(qhr, 16, 0); +PRECEQ_PW(qhla, 48, 16); +PRECEQ_PW(qhra, 32, 0); + +#undef PRECEQ_PW + +#endif + +#define PRECEQU_PH(name, a, b) \ +target_ulong helper_precequ_ph_##name(target_ulong rt) \ +{ \ + uint16_t tempB, tempA; \ + \ + tempB = (rt >> a) & MIPSDSP_Q0; \ + tempA = (rt >> b) & MIPSDSP_Q0; \ + \ + tempB = tempB << 7; \ + tempA = tempA << 7; \ + \ + return MIPSDSP_RETURN32_16(tempB, tempA); \ +} + +PRECEQU_PH(qbl, 24, 16); +PRECEQU_PH(qbr, 8, 0); +PRECEQU_PH(qbla, 24, 8); +PRECEQU_PH(qbra, 16, 0); + +#undef PRECEQU_PH + +#if defined(TARGET_MIPS64) +#define PRECEQU_QH(name, a, b, c, d) \ +target_ulong helper_precequ_qh_##name(target_ulong rt) \ +{ \ + uint16_t tempD, tempC, tempB, tempA; \ + \ + tempD = (rt >> a) & MIPSDSP_Q0; \ + tempC = (rt >> b) & MIPSDSP_Q0; \ + tempB = (rt >> c) & MIPSDSP_Q0; \ + tempA = (rt >> d) & MIPSDSP_Q0; \ + \ + tempD = tempD << 7; \ + tempC = tempC << 7; \ + tempB = tempB << 7; \ + tempA = tempA << 7; \ + \ + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \ +} + +PRECEQU_QH(obl, 56, 48, 40, 32); +PRECEQU_QH(obr, 24, 16, 8, 0); +PRECEQU_QH(obla, 56, 40, 24, 8); +PRECEQU_QH(obra, 48, 32, 16, 0); + +#undef PRECEQU_QH + +#endif + +#define PRECEU_PH(name, a, b) \ +target_ulong helper_preceu_ph_##name(target_ulong rt) \ +{ \ + uint16_t tempB, tempA; \ + \ + tempB = (rt >> a) & MIPSDSP_Q0; \ + tempA = (rt >> b) & MIPSDSP_Q0; \ + \ + return MIPSDSP_RETURN32_16(tempB, tempA); \ +} + +PRECEU_PH(qbl, 24, 16); +PRECEU_PH(qbr, 8, 0); +PRECEU_PH(qbla, 24, 8); +PRECEU_PH(qbra, 16, 0); + +#undef PRECEU_PH + +#if defined(TARGET_MIPS64) +#define PRECEU_QH(name, a, b, c, d) \ +target_ulong helper_preceu_qh_##name(target_ulong rt) \ +{ \ + uint16_t tempD, tempC, tempB, tempA; \ + \ + tempD = (rt >> a) & MIPSDSP_Q0; \ + tempC = (rt >> b) & MIPSDSP_Q0; \ + tempB = (rt >> c) & MIPSDSP_Q0; \ + tempA = (rt >> d) & MIPSDSP_Q0; \ + \ + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \ +} + +PRECEU_QH(obl, 56, 48, 40, 32); +PRECEU_QH(obr, 24, 16, 8, 0); +PRECEU_QH(obla, 56, 40, 24, 8); +PRECEU_QH(obra, 48, 32, 16, 0); + +#undef PRECEU_QH + +#endif + +#undef MIPSDSP_LHI +#undef MIPSDSP_LLO +#undef MIPSDSP_HI +#undef MIPSDSP_LO +#undef MIPSDSP_Q3 +#undef MIPSDSP_Q2 +#undef MIPSDSP_Q1 +#undef MIPSDSP_Q0 + +#undef MIPSDSP_SPLIT32_8 +#undef MIPSDSP_SPLIT32_16 + +#undef MIPSDSP_RETURN32 +#undef MIPSDSP_RETURN32_8 +#undef MIPSDSP_RETURN32_16 + +#ifdef TARGET_MIPS64 +#undef MIPSDSP_SPLIT64_16 +#undef MIPSDSP_SPLIT64_32 +#undef MIPSDSP_RETURN64_16 +#undef MIPSDSP_RETURN64_32 +#endif diff --git a/target-mips/helper.h b/target-mips/helper.h index 43ac39ff41..3325ed6164 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -362,4 +362,130 @@ DEF_HELPER_FLAGS_2(pasubub, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_1(biadd, TCG_CALL_NO_RWG_SE, i64, i64) DEF_HELPER_FLAGS_1(pmovmskb, TCG_CALL_NO_RWG_SE, i64, i64) +/*** MIPS DSP ***/ +/* DSP Arithmetic Sub-class insns */ +DEF_HELPER_FLAGS_3(addq_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addq_s_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(addq_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addq_s_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(addq_s_w, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(addq_pw, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addq_s_pw, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(addu_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addu_s_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(adduh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(adduh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(addu_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addu_s_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(addqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(addqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(addqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(addqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(addu_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addu_s_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(adduh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(adduh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(addu_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addu_s_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(subq_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subq_s_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(subq_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subq_s_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(subq_s_w, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(subq_pw, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subq_s_pw, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(subu_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subu_s_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(subuh_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(subuh_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(subu_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subu_s_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(subqh_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(subqh_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(subqh_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(subqh_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(subu_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subu_s_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(subuh_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(subuh_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(subu_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(subu_s_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(addsc, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(addwc, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(modsub, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_1(raddu_w_qb, TCG_CALL_NO_RWG_SE, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_1(raddu_l_ob, TCG_CALL_NO_RWG_SE, tl, tl) +#endif +DEF_HELPER_FLAGS_2(absq_s_qb, 0, tl, tl, env) +DEF_HELPER_FLAGS_2(absq_s_ph, 0, tl, tl, env) +DEF_HELPER_FLAGS_2(absq_s_w, 0, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(absq_s_ob, 0, tl, tl, env) +DEF_HELPER_FLAGS_2(absq_s_qh, 0, tl, tl, env) +DEF_HELPER_FLAGS_2(absq_s_pw, 0, tl, tl, env) +#endif +DEF_HELPER_FLAGS_2(precr_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(precrq_qb_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(precr_sra_ph_w, TCG_CALL_NO_RWG_SE, + tl, i32, tl, tl) +DEF_HELPER_FLAGS_3(precr_sra_r_ph_w, TCG_CALL_NO_RWG_SE, + tl, i32, tl, tl) +DEF_HELPER_FLAGS_2(precrq_ph_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(precrq_rs_ph_w, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(precr_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(precr_sra_qh_pw, + TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +DEF_HELPER_FLAGS_3(precr_sra_r_qh_pw, + TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +DEF_HELPER_FLAGS_2(precrq_ob_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(precrq_qh_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(precrq_rs_qh_pw, + TCG_CALL_NO_RWG_SE, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(precrq_pw_l, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif +DEF_HELPER_FLAGS_3(precrqu_s_qb_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(precrqu_s_ob_qh, + TCG_CALL_NO_RWG_SE, tl, tl, tl, env) + +DEF_HELPER_FLAGS_1(preceq_pw_qhl, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceq_pw_qhr, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceq_pw_qhla, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceq_pw_qhra, TCG_CALL_NO_RWG_SE, tl, tl) +#endif +DEF_HELPER_FLAGS_1(precequ_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_1(precequ_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(precequ_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl) +#endif +DEF_HELPER_FLAGS_1(preceu_ph_qbl, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_ph_qbr, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_ph_qbla, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_ph_qbra, TCG_CALL_NO_RWG_SE, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_1(preceu_qh_obl, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_qh_obr, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_1(preceu_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl) +#endif + #include "def-helper.h" diff --git a/target-mips/translate.c b/target-mips/translate.c index fdff3273ad..b1fd02b806 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -316,6 +316,21 @@ enum { /* MIPS DSP Load */ OPC_LX_DSP = 0x0A | OPC_SPECIAL3, + /* MIPS DSP Arithmetic */ + OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3, +#if defined(TARGET_MIPS64) + OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3, +#endif + OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3, +#if defined(TARGET_MIPS64) + OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3, +#endif + /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */ + /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */ + OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3, +#if defined(TARGET_MIPS64) + OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3, +#endif }; /* BSHFL opcodes */ @@ -354,6 +369,144 @@ enum { #endif }; +#define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Arithmetic Sub-class */ + OPC_ADDQ_PH = (0x0A << 6) | OPC_ADDU_QB_DSP, + OPC_ADDQ_S_PH = (0x0E << 6) | OPC_ADDU_QB_DSP, + OPC_ADDQ_S_W = (0x16 << 6) | OPC_ADDU_QB_DSP, + OPC_ADDU_QB = (0x00 << 6) | OPC_ADDU_QB_DSP, + OPC_ADDU_S_QB = (0x04 << 6) | OPC_ADDU_QB_DSP, + OPC_ADDU_PH = (0x08 << 6) | OPC_ADDU_QB_DSP, + OPC_ADDU_S_PH = (0x0C << 6) | OPC_ADDU_QB_DSP, + OPC_SUBQ_PH = (0x0B << 6) | OPC_ADDU_QB_DSP, + OPC_SUBQ_S_PH = (0x0F << 6) | OPC_ADDU_QB_DSP, + OPC_SUBQ_S_W = (0x17 << 6) | OPC_ADDU_QB_DSP, + OPC_SUBU_QB = (0x01 << 6) | OPC_ADDU_QB_DSP, + OPC_SUBU_S_QB = (0x05 << 6) | OPC_ADDU_QB_DSP, + OPC_SUBU_PH = (0x09 << 6) | OPC_ADDU_QB_DSP, + OPC_SUBU_S_PH = (0x0D << 6) | OPC_ADDU_QB_DSP, + OPC_ADDSC = (0x10 << 6) | OPC_ADDU_QB_DSP, + OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP, + OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP, + OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP, +}; + +#define OPC_ADDUH_QB_DSP OPC_MULT_G_2E +#define MASK_ADDUH_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Arithmetic Sub-class */ + OPC_ADDUH_QB = (0x00 << 6) | OPC_ADDUH_QB_DSP, + OPC_ADDUH_R_QB = (0x02 << 6) | OPC_ADDUH_QB_DSP, + OPC_ADDQH_PH = (0x08 << 6) | OPC_ADDUH_QB_DSP, + OPC_ADDQH_R_PH = (0x0A << 6) | OPC_ADDUH_QB_DSP, + OPC_ADDQH_W = (0x10 << 6) | OPC_ADDUH_QB_DSP, + OPC_ADDQH_R_W = (0x12 << 6) | OPC_ADDUH_QB_DSP, + OPC_SUBUH_QB = (0x01 << 6) | OPC_ADDUH_QB_DSP, + OPC_SUBUH_R_QB = (0x03 << 6) | OPC_ADDUH_QB_DSP, + OPC_SUBQH_PH = (0x09 << 6) | OPC_ADDUH_QB_DSP, + OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP, + OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP, + OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP, +}; + +#define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Arithmetic Sub-class */ + OPC_ABSQ_S_QB = (0x01 << 6) | OPC_ABSQ_S_PH_DSP, + OPC_ABSQ_S_PH = (0x09 << 6) | OPC_ABSQ_S_PH_DSP, + OPC_ABSQ_S_W = (0x11 << 6) | OPC_ABSQ_S_PH_DSP, + OPC_PRECEQ_W_PHL = (0x0C << 6) | OPC_ABSQ_S_PH_DSP, + OPC_PRECEQ_W_PHR = (0x0D << 6) | OPC_ABSQ_S_PH_DSP, + OPC_PRECEQU_PH_QBL = (0x04 << 6) | OPC_ABSQ_S_PH_DSP, + OPC_PRECEQU_PH_QBR = (0x05 << 6) | OPC_ABSQ_S_PH_DSP, + OPC_PRECEQU_PH_QBLA = (0x06 << 6) | OPC_ABSQ_S_PH_DSP, + OPC_PRECEQU_PH_QBRA = (0x07 << 6) | OPC_ABSQ_S_PH_DSP, + OPC_PRECEU_PH_QBL = (0x1C << 6) | OPC_ABSQ_S_PH_DSP, + OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP, + OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP, + OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP, +}; + +#define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Arithmetic Sub-class */ + OPC_PRECR_QB_PH = (0x0D << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PRECRQ_QB_PH = (0x0C << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PRECR_SRA_PH_W = (0x1E << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PRECR_SRA_R_PH_W = (0x1F << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP, +}; + +#if defined(TARGET_MIPS64) +#define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Arithmetic Sub-class */ + OPC_PRECEQ_L_PWL = (0x14 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEQ_L_PWR = (0x15 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEQ_PW_QHL = (0x0C << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEQ_PW_QHR = (0x0D << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEQ_PW_QHLA = (0x0E << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEQ_PW_QHRA = (0x0F << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEQU_QH_OBL = (0x04 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEQU_QH_OBR = (0x05 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEQU_QH_OBLA = (0x06 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEQU_QH_OBRA = (0x07 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEU_QH_OBL = (0x1C << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEU_QH_OBR = (0x1D << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEU_QH_OBLA = (0x1E << 6) | OPC_ABSQ_S_QH_DSP, + OPC_PRECEU_QH_OBRA = (0x1F << 6) | OPC_ABSQ_S_QH_DSP, + OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP, +}; +#endif + +#if defined(TARGET_MIPS64) +#define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Arithmetic Sub-class */ + OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP, + OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP, + OPC_SUBQ_S_PW = (0x17 << 6) | OPC_ADDU_OB_DSP, + OPC_SUBQ_QH = (0x0B << 6) | OPC_ADDU_OB_DSP, + OPC_SUBQ_S_QH = (0x0F << 6) | OPC_ADDU_OB_DSP, + OPC_SUBU_OB = (0x01 << 6) | OPC_ADDU_OB_DSP, + OPC_SUBU_S_OB = (0x05 << 6) | OPC_ADDU_OB_DSP, + OPC_SUBU_QH = (0x09 << 6) | OPC_ADDU_OB_DSP, + OPC_SUBU_S_QH = (0x0D << 6) | OPC_ADDU_OB_DSP, + OPC_SUBUH_OB = (0x19 << 6) | OPC_ADDU_OB_DSP, + OPC_SUBUH_R_OB = (0x1B << 6) | OPC_ADDU_OB_DSP, + OPC_ADDQ_PW = (0x12 << 6) | OPC_ADDU_OB_DSP, + OPC_ADDQ_S_PW = (0x16 << 6) | OPC_ADDU_OB_DSP, + OPC_ADDQ_QH = (0x0A << 6) | OPC_ADDU_OB_DSP, + OPC_ADDQ_S_QH = (0x0E << 6) | OPC_ADDU_OB_DSP, + OPC_ADDU_OB = (0x00 << 6) | OPC_ADDU_OB_DSP, + OPC_ADDU_S_OB = (0x04 << 6) | OPC_ADDU_OB_DSP, + OPC_ADDU_QH = (0x08 << 6) | OPC_ADDU_OB_DSP, + OPC_ADDU_S_QH = (0x0C << 6) | OPC_ADDU_OB_DSP, + OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP, + OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP, +}; +#endif + +#if defined(TARGET_MIPS64) +#define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Arithmetic Sub-class */ + OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PRECR_SRA_R_QH_PW = (0x1F << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PRECRQ_OB_QH = (0x0C << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PRECRQ_PW_L = (0x1C << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PRECRQ_QH_PW = (0x14 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP, +}; +#endif + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -12287,6 +12440,459 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, tcg_temp_free(t0); } +static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, + int ret, int v1, int v2) +{ + const char *opn = "mipsdsp arith"; + TCGv v1_t; + TCGv v2_t; + + if (ret == 0) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + v1_t = tcg_temp_new(); + v2_t = tcg_temp_new(); + + gen_load_gpr(v1_t, v1); + gen_load_gpr(v2_t, v2); + + switch (op1) { + /* OPC_MULT_G_2E is equal OPC_ADDUH_QB_DSP */ + case OPC_MULT_G_2E: + check_dspr2(ctx); + switch (op2) { + case OPC_ADDUH_QB: + gen_helper_adduh_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_ADDUH_R_QB: + gen_helper_adduh_r_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_ADDQH_PH: + gen_helper_addqh_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_ADDQH_R_PH: + gen_helper_addqh_r_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_ADDQH_W: + gen_helper_addqh_w(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_ADDQH_R_W: + gen_helper_addqh_r_w(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SUBUH_QB: + gen_helper_subuh_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SUBUH_R_QB: + gen_helper_subuh_r_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SUBQH_PH: + gen_helper_subqh_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SUBQH_R_PH: + gen_helper_subqh_r_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SUBQH_W: + gen_helper_subqh_w(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SUBQH_R_W: + gen_helper_subqh_r_w(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; + case OPC_ABSQ_S_PH_DSP: + switch (op2) { + case OPC_ABSQ_S_QB: + check_dspr2(ctx); + gen_helper_absq_s_qb(cpu_gpr[ret], v2_t, cpu_env); + break; + case OPC_ABSQ_S_PH: + check_dsp(ctx); + gen_helper_absq_s_ph(cpu_gpr[ret], v2_t, cpu_env); + break; + case OPC_ABSQ_S_W: + check_dsp(ctx); + gen_helper_absq_s_w(cpu_gpr[ret], v2_t, cpu_env); + break; + case OPC_PRECEQ_W_PHL: + check_dsp(ctx); + tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFF0000); + tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); + break; + case OPC_PRECEQ_W_PHR: + check_dsp(ctx); + tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0x0000FFFF); + tcg_gen_shli_tl(cpu_gpr[ret], cpu_gpr[ret], 16); + tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); + break; + case OPC_PRECEQU_PH_QBL: + check_dsp(ctx); + gen_helper_precequ_ph_qbl(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEQU_PH_QBR: + check_dsp(ctx); + gen_helper_precequ_ph_qbr(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEQU_PH_QBLA: + check_dsp(ctx); + gen_helper_precequ_ph_qbla(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEQU_PH_QBRA: + check_dsp(ctx); + gen_helper_precequ_ph_qbra(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEU_PH_QBL: + check_dsp(ctx); + gen_helper_preceu_ph_qbl(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEU_PH_QBR: + check_dsp(ctx); + gen_helper_preceu_ph_qbr(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEU_PH_QBLA: + check_dsp(ctx); + gen_helper_preceu_ph_qbla(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEU_PH_QBRA: + check_dsp(ctx); + gen_helper_preceu_ph_qbra(cpu_gpr[ret], v2_t); + break; + } + break; + case OPC_ADDU_QB_DSP: + switch (op2) { + case OPC_ADDQ_PH: + check_dsp(ctx); + gen_helper_addq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDQ_S_PH: + check_dsp(ctx); + gen_helper_addq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDQ_S_W: + check_dsp(ctx); + gen_helper_addq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDU_QB: + check_dsp(ctx); + gen_helper_addu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDU_S_QB: + check_dsp(ctx); + gen_helper_addu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDU_PH: + check_dspr2(ctx); + gen_helper_addu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDU_S_PH: + check_dspr2(ctx); + gen_helper_addu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBQ_PH: + check_dsp(ctx); + gen_helper_subq_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBQ_S_PH: + check_dsp(ctx); + gen_helper_subq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBQ_S_W: + check_dsp(ctx); + gen_helper_subq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBU_QB: + check_dsp(ctx); + gen_helper_subu_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBU_S_QB: + check_dsp(ctx); + gen_helper_subu_s_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBU_PH: + check_dspr2(ctx); + gen_helper_subu_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBU_S_PH: + check_dspr2(ctx); + gen_helper_subu_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDSC: + check_dsp(ctx); + gen_helper_addsc(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDWC: + check_dsp(ctx); + gen_helper_addwc(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MODSUB: + check_dsp(ctx); + gen_helper_modsub(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_RADDU_W_QB: + check_dsp(ctx); + gen_helper_raddu_w_qb(cpu_gpr[ret], v1_t); + break; + } + break; + case OPC_CMPU_EQ_QB_DSP: + switch (op2) { + case OPC_PRECR_QB_PH: + check_dspr2(ctx); + gen_helper_precr_qb_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PRECRQ_QB_PH: + check_dsp(ctx); + gen_helper_precrq_qb_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PRECR_SRA_PH_W: + check_dspr2(ctx); + { + TCGv_i32 sa_t = tcg_const_i32(v2); + gen_helper_precr_sra_ph_w(cpu_gpr[ret], sa_t, v1_t, + cpu_gpr[ret]); + tcg_temp_free_i32(sa_t); + break; + } + case OPC_PRECR_SRA_R_PH_W: + check_dspr2(ctx); + { + TCGv_i32 sa_t = tcg_const_i32(v2); + gen_helper_precr_sra_r_ph_w(cpu_gpr[ret], sa_t, v1_t, + cpu_gpr[ret]); + tcg_temp_free_i32(sa_t); + break; + } + case OPC_PRECRQ_PH_W: + check_dsp(ctx); + gen_helper_precrq_ph_w(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PRECRQ_RS_PH_W: + check_dsp(ctx); + gen_helper_precrq_rs_ph_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_PRECRQU_S_QB_PH: + check_dsp(ctx); + gen_helper_precrqu_s_qb_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; +#ifdef TARGET_MIPS64 + case OPC_ABSQ_S_QH_DSP: + switch (op2) { + case OPC_PRECEQ_L_PWL: + check_dsp(ctx); + tcg_gen_andi_tl(cpu_gpr[ret], v2_t, 0xFFFFFFFF00000000ull); + break; + case OPC_PRECEQ_L_PWR: + check_dsp(ctx); + tcg_gen_shli_tl(cpu_gpr[ret], v2_t, 32); + break; + case OPC_PRECEQ_PW_QHL: + check_dsp(ctx); + gen_helper_preceq_pw_qhl(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEQ_PW_QHR: + check_dsp(ctx); + gen_helper_preceq_pw_qhr(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEQ_PW_QHLA: + check_dsp(ctx); + gen_helper_preceq_pw_qhla(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEQ_PW_QHRA: + check_dsp(ctx); + gen_helper_preceq_pw_qhra(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEQU_QH_OBL: + check_dsp(ctx); + gen_helper_precequ_qh_obl(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEQU_QH_OBR: + check_dsp(ctx); + gen_helper_precequ_qh_obr(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEQU_QH_OBLA: + check_dsp(ctx); + gen_helper_precequ_qh_obla(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEQU_QH_OBRA: + check_dsp(ctx); + gen_helper_precequ_qh_obra(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEU_QH_OBL: + check_dsp(ctx); + gen_helper_preceu_qh_obl(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEU_QH_OBR: + check_dsp(ctx); + gen_helper_preceu_qh_obr(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEU_QH_OBLA: + check_dsp(ctx); + gen_helper_preceu_qh_obla(cpu_gpr[ret], v2_t); + break; + case OPC_PRECEU_QH_OBRA: + check_dsp(ctx); + gen_helper_preceu_qh_obra(cpu_gpr[ret], v2_t); + break; + case OPC_ABSQ_S_OB: + check_dspr2(ctx); + gen_helper_absq_s_ob(cpu_gpr[ret], v2_t, cpu_env); + break; + case OPC_ABSQ_S_PW: + check_dsp(ctx); + gen_helper_absq_s_pw(cpu_gpr[ret], v2_t, cpu_env); + break; + case OPC_ABSQ_S_QH: + check_dsp(ctx); + gen_helper_absq_s_qh(cpu_gpr[ret], v2_t, cpu_env); + break; + } + break; + case OPC_ADDU_OB_DSP: + switch (op2) { + case OPC_RADDU_L_OB: + check_dsp(ctx); + gen_helper_raddu_l_ob(cpu_gpr[ret], v1_t); + break; + case OPC_SUBQ_PW: + check_dsp(ctx); + gen_helper_subq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBQ_S_PW: + check_dsp(ctx); + gen_helper_subq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBQ_QH: + check_dsp(ctx); + gen_helper_subq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBQ_S_QH: + check_dsp(ctx); + gen_helper_subq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBU_OB: + check_dsp(ctx); + gen_helper_subu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBU_S_OB: + check_dsp(ctx); + gen_helper_subu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBU_QH: + check_dspr2(ctx); + gen_helper_subu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBU_S_QH: + check_dspr2(ctx); + gen_helper_subu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SUBUH_OB: + check_dspr2(ctx); + gen_helper_subuh_ob(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SUBUH_R_OB: + check_dspr2(ctx); + gen_helper_subuh_r_ob(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_ADDQ_PW: + check_dsp(ctx); + gen_helper_addq_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDQ_S_PW: + check_dsp(ctx); + gen_helper_addq_s_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDQ_QH: + check_dsp(ctx); + gen_helper_addq_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDQ_S_QH: + check_dsp(ctx); + gen_helper_addq_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDU_OB: + check_dsp(ctx); + gen_helper_addu_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDU_S_OB: + check_dsp(ctx); + gen_helper_addu_s_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDU_QH: + check_dspr2(ctx); + gen_helper_addu_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDU_S_QH: + check_dspr2(ctx); + gen_helper_addu_s_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_ADDUH_OB: + check_dspr2(ctx); + gen_helper_adduh_ob(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_ADDUH_R_OB: + check_dspr2(ctx); + gen_helper_adduh_r_ob(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; + case OPC_CMPU_EQ_OB_DSP: + switch (op2) { + case OPC_PRECR_OB_QH: + check_dspr2(ctx); + gen_helper_precr_ob_qh(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PRECR_SRA_QH_PW: + check_dspr2(ctx); + { + TCGv_i32 ret_t = tcg_const_i32(ret); + gen_helper_precr_sra_qh_pw(v2_t, v1_t, v2_t, ret_t); + tcg_temp_free_i32(ret_t); + break; + } + case OPC_PRECR_SRA_R_QH_PW: + check_dspr2(ctx); + { + TCGv_i32 sa_v = tcg_const_i32(ret); + gen_helper_precr_sra_r_qh_pw(v2_t, v1_t, v2_t, sa_v); + tcg_temp_free_i32(sa_v); + break; + } + case OPC_PRECRQ_OB_QH: + check_dsp(ctx); + gen_helper_precrq_ob_qh(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PRECRQ_PW_L: + check_dsp(ctx); + gen_helper_precrq_pw_l(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PRECRQ_QH_PW: + check_dsp(ctx); + gen_helper_precrq_qh_pw(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PRECRQ_RS_QH_PW: + check_dsp(ctx); + gen_helper_precrq_rs_qh_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_PRECRQU_S_OB_QH: + check_dsp(ctx); + gen_helper_precrqu_s_ob_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; +#endif + } + + tcg_temp_free(v1_t); + tcg_temp_free(v2_t); + + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s", opn); +} /* End MIPSDSP functions. */ @@ -12641,10 +13247,37 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) } break; case OPC_DIV_G_2E ... OPC_DIVU_G_2E: - case OPC_MULT_G_2E ... OPC_MULTU_G_2E: case OPC_MOD_G_2E ... OPC_MODU_G_2E: - check_insn(env, ctx, INSN_LOONGSON2E); - gen_loongson_integer(ctx, op1, rd, rs, rt); + case OPC_MULT_G_2E ... OPC_MULTU_G_2E: + /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have + * the same mask and op1. */ + if ((env->insn_flags & ASE_DSPR2) && (op1 == OPC_MULT_G_2E)) { + op2 = MASK_ADDUH_QB(ctx->opcode); + switch (op2) { + case OPC_ADDUH_QB: + case OPC_ADDUH_R_QB: + case OPC_ADDQH_PH: + case OPC_ADDQH_R_PH: + case OPC_ADDQH_W: + case OPC_ADDQH_R_W: + case OPC_SUBUH_QB: + case OPC_SUBUH_R_QB: + case OPC_SUBQH_PH: + case OPC_SUBQH_R_PH: + case OPC_SUBQH_W: + case OPC_SUBQH_R_W: + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); + break; + default: + MIPS_INVAL("MASK ADDUH.QB"); + generate_exception(ctx, EXCP_RI); + break; + } + } else if (env->insn_flags & INSN_LOONGSON2E) { + gen_loongson_integer(ctx, op1, rd, rs, rt); + } else { + generate_exception(ctx, EXCP_RI); + } break; case OPC_LX_DSP: op2 = MASK_LX(ctx->opcode); @@ -12663,6 +13296,80 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; } break; + case OPC_ABSQ_S_PH_DSP: + op2 = MASK_ABSQ_S_PH(ctx->opcode); + switch (op2) { + case OPC_ABSQ_S_QB: + case OPC_ABSQ_S_PH: + case OPC_ABSQ_S_W: + case OPC_PRECEQ_W_PHL: + case OPC_PRECEQ_W_PHR: + case OPC_PRECEQU_PH_QBL: + case OPC_PRECEQU_PH_QBR: + case OPC_PRECEQU_PH_QBLA: + case OPC_PRECEQU_PH_QBRA: + case OPC_PRECEU_PH_QBL: + case OPC_PRECEU_PH_QBR: + case OPC_PRECEU_PH_QBLA: + case OPC_PRECEU_PH_QBRA: + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); + break; + default: + MIPS_INVAL("MASK ABSQ_S.PH"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_ADDU_QB_DSP: + op2 = MASK_ADDU_QB(ctx->opcode); + switch (op2) { + case OPC_ADDQ_PH: + case OPC_ADDQ_S_PH: + case OPC_ADDQ_S_W: + case OPC_ADDU_QB: + case OPC_ADDU_S_QB: + case OPC_ADDU_PH: + case OPC_ADDU_S_PH: + case OPC_SUBQ_PH: + case OPC_SUBQ_S_PH: + case OPC_SUBQ_S_W: + case OPC_SUBU_QB: + case OPC_SUBU_S_QB: + case OPC_SUBU_PH: + case OPC_SUBU_S_PH: + case OPC_ADDSC: + case OPC_ADDWC: + case OPC_MODSUB: + case OPC_RADDU_W_QB: + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); + break; + default: /* Invalid */ + MIPS_INVAL("MASK ADDU.QB"); + generate_exception(ctx, EXCP_RI); + break; + + } + break; + case OPC_CMPU_EQ_QB_DSP: + op2 = MASK_CMPU_EQ_QB(ctx->opcode); + switch (op2) { + case OPC_PRECR_SRA_PH_W: + case OPC_PRECR_SRA_R_PH_W: + gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd); + break; + case OPC_PRECR_QB_PH: + case OPC_PRECRQ_QB_PH: + case OPC_PRECRQ_PH_W: + case OPC_PRECRQ_RS_PH_W: + case OPC_PRECRQU_S_QB_PH: + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); + break; + default: /* Invalid */ + MIPS_INVAL("MASK CMPU.EQ.QB"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: @@ -12682,6 +13389,88 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) check_insn(env, ctx, INSN_LOONGSON2E); gen_loongson_integer(ctx, op1, rd, rs, rt); break; + case OPC_ABSQ_S_QH_DSP: + op2 = MASK_ABSQ_S_QH(ctx->opcode); + switch (op2) { + case OPC_PRECEQ_L_PWL: + case OPC_PRECEQ_L_PWR: + case OPC_PRECEQ_PW_QHL: + case OPC_PRECEQ_PW_QHR: + case OPC_PRECEQ_PW_QHLA: + case OPC_PRECEQ_PW_QHRA: + case OPC_PRECEQU_QH_OBL: + case OPC_PRECEQU_QH_OBR: + case OPC_PRECEQU_QH_OBLA: + case OPC_PRECEQU_QH_OBRA: + case OPC_PRECEU_QH_OBL: + case OPC_PRECEU_QH_OBR: + case OPC_PRECEU_QH_OBLA: + case OPC_PRECEU_QH_OBRA: + case OPC_ABSQ_S_OB: + case OPC_ABSQ_S_PW: + case OPC_ABSQ_S_QH: + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); + break; + default: /* Invalid */ + MIPS_INVAL("MASK ABSQ_S.QH"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_ADDU_OB_DSP: + op2 = MASK_ADDU_OB(ctx->opcode); + switch (op2) { + case OPC_RADDU_L_OB: + case OPC_SUBQ_PW: + case OPC_SUBQ_S_PW: + case OPC_SUBQ_QH: + case OPC_SUBQ_S_QH: + case OPC_SUBU_OB: + case OPC_SUBU_S_OB: + case OPC_SUBU_QH: + case OPC_SUBU_S_QH: + case OPC_SUBUH_OB: + case OPC_SUBUH_R_OB: + case OPC_ADDQ_PW: + case OPC_ADDQ_S_PW: + case OPC_ADDQ_QH: + case OPC_ADDQ_S_QH: + case OPC_ADDU_OB: + case OPC_ADDU_S_OB: + case OPC_ADDU_QH: + case OPC_ADDU_S_QH: + case OPC_ADDUH_OB: + case OPC_ADDUH_R_OB: + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); + break; + default: /* Invalid */ + MIPS_INVAL("MASK ADDU.OB"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_CMPU_EQ_OB_DSP: + op2 = MASK_CMPU_EQ_OB(ctx->opcode); + switch (op2) { + case OPC_PRECR_SRA_QH_PW: + case OPC_PRECR_SRA_R_QH_PW: + /* Return value is rt. */ + gen_mipsdsp_arith(ctx, op1, op2, rt, rs, rd); + break; + case OPC_PRECR_OB_QH: + case OPC_PRECRQ_OB_QH: + case OPC_PRECRQ_PW_L: + case OPC_PRECRQ_QH_PW: + case OPC_PRECRQ_RS_QH_PW: + case OPC_PRECRQU_S_OB_QH: + gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); + break; + default: /* Invalid */ + MIPS_INVAL("MASK CMPU_EQ.OB"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #endif default: /* Invalid */ MIPS_INVAL("special3"); From 77c5fa8b55adbd277dfa272752b4e99836ee4702 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:07 +0800 Subject: [PATCH 137/291] target-mips: Add ASE DSP GPR-based shift instructions Add MIPS ASE DSP GPR-Based Shift instructions. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 256 +++++++++++++++++++++++++++++++ target-mips/helper.h | 38 +++++ target-mips/translate.c | 324 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 618 insertions(+) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 7ddad34d10..3c79ceb1a7 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -1933,6 +1933,262 @@ PRECEU_QH(obra, 48, 32, 16, 0); #endif +/** DSP GPR-Based Shift Sub-class insns **/ +#define SHIFT_QB(name, func) \ +target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt) \ +{ \ + uint8_t rt3, rt2, rt1, rt0; \ + \ + sa = sa & 0x07; \ + \ + MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ + \ + rt3 = mipsdsp_##func(rt3, sa); \ + rt2 = mipsdsp_##func(rt2, sa); \ + rt1 = mipsdsp_##func(rt1, sa); \ + rt0 = mipsdsp_##func(rt0, sa); \ + \ + return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \ +} + +#define SHIFT_QB_ENV(name, func) \ +target_ulong helper_##name##_qb(target_ulong sa, target_ulong rt,\ + CPUMIPSState *env) \ +{ \ + uint8_t rt3, rt2, rt1, rt0; \ + \ + sa = sa & 0x07; \ + \ + MIPSDSP_SPLIT32_8(rt, rt3, rt2, rt1, rt0); \ + \ + rt3 = mipsdsp_##func(rt3, sa, env); \ + rt2 = mipsdsp_##func(rt2, sa, env); \ + rt1 = mipsdsp_##func(rt1, sa, env); \ + rt0 = mipsdsp_##func(rt0, sa, env); \ + \ + return MIPSDSP_RETURN32_8(rt3, rt2, rt1, rt0); \ +} + +SHIFT_QB_ENV(shll, lshift8); +SHIFT_QB(shrl, rshift_u8); + +SHIFT_QB(shra, rashift8); +SHIFT_QB(shra_r, rnd8_rashift); + +#undef SHIFT_QB +#undef SHIFT_QB_ENV + +#if defined(TARGET_MIPS64) +#define SHIFT_OB(name, func) \ +target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa) \ +{ \ + int i; \ + uint8_t rt_t[8]; \ + uint64_t temp; \ + \ + sa = sa & 0x07; \ + temp = 0; \ + \ + for (i = 0; i < 8; i++) { \ + rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \ + rt_t[i] = mipsdsp_##func(rt_t[i], sa); \ + temp |= (uint64_t)rt_t[i] << (8 * i); \ + } \ + \ + return temp; \ +} + +#define SHIFT_OB_ENV(name, func) \ +target_ulong helper_##name##_ob(target_ulong rt, target_ulong sa, \ + CPUMIPSState *env) \ +{ \ + int i; \ + uint8_t rt_t[8]; \ + uint64_t temp; \ + \ + sa = sa & 0x07; \ + temp = 0; \ + \ + for (i = 0; i < 8; i++) { \ + rt_t[i] = (rt >> (8 * i)) & MIPSDSP_Q0; \ + rt_t[i] = mipsdsp_##func(rt_t[i], sa, env); \ + temp |= (uint64_t)rt_t[i] << (8 * i); \ + } \ + \ + return temp; \ +} + +SHIFT_OB_ENV(shll, lshift8); +SHIFT_OB(shrl, rshift_u8); + +SHIFT_OB(shra, rashift8); +SHIFT_OB(shra_r, rnd8_rashift); + +#undef SHIFT_OB +#undef SHIFT_OB_ENV + +#endif + +#define SHIFT_PH(name, func) \ +target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint16_t rth, rtl; \ + \ + sa = sa & 0x0F; \ + \ + MIPSDSP_SPLIT32_16(rt, rth, rtl); \ + \ + rth = mipsdsp_##func(rth, sa, env); \ + rtl = mipsdsp_##func(rtl, sa, env); \ + \ + return MIPSDSP_RETURN32_16(rth, rtl); \ +} + +SHIFT_PH(shll, lshift16); +SHIFT_PH(shll_s, sat16_lshift); + +#undef SHIFT_PH + +#if defined(TARGET_MIPS64) +#define SHIFT_QH(name, func) \ +target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa) \ +{ \ + uint16_t rt3, rt2, rt1, rt0; \ + \ + sa = sa & 0x0F; \ + \ + MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ + \ + rt3 = mipsdsp_##func(rt3, sa); \ + rt2 = mipsdsp_##func(rt2, sa); \ + rt1 = mipsdsp_##func(rt1, sa); \ + rt0 = mipsdsp_##func(rt0, sa); \ + \ + return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \ +} + +#define SHIFT_QH_ENV(name, func) \ +target_ulong helper_##name##_qh(target_ulong rt, target_ulong sa, \ + CPUMIPSState *env) \ +{ \ + uint16_t rt3, rt2, rt1, rt0; \ + \ + sa = sa & 0x0F; \ + \ + MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ + \ + rt3 = mipsdsp_##func(rt3, sa, env); \ + rt2 = mipsdsp_##func(rt2, sa, env); \ + rt1 = mipsdsp_##func(rt1, sa, env); \ + rt0 = mipsdsp_##func(rt0, sa, env); \ + \ + return MIPSDSP_RETURN64_16(rt3, rt2, rt1, rt0); \ +} + +SHIFT_QH_ENV(shll, lshift16); +SHIFT_QH_ENV(shll_s, sat16_lshift); + +SHIFT_QH(shrl, rshift_u16); +SHIFT_QH(shra, rashift16); +SHIFT_QH(shra_r, rnd16_rashift); + +#undef SHIFT_QH +#undef SHIFT_QH_ENV + +#endif + +#define SHIFT_W(name, func) \ +target_ulong helper_##name##_w(target_ulong sa, target_ulong rt) \ +{ \ + uint32_t temp; \ + \ + sa = sa & 0x1F; \ + temp = mipsdsp_##func(rt, sa); \ + \ + return (target_long)(int32_t)temp; \ +} + +#define SHIFT_W_ENV(name, func) \ +target_ulong helper_##name##_w(target_ulong sa, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint32_t temp; \ + \ + sa = sa & 0x1F; \ + temp = mipsdsp_##func(rt, sa, env); \ + \ + return (target_long)(int32_t)temp; \ +} + +SHIFT_W_ENV(shll_s, sat32_lshift); +SHIFT_W(shra_r, rnd32_rashift); + +#undef SHIFT_W +#undef SHIFT_W_ENV + +#if defined(TARGET_MIPS64) +#define SHIFT_PW(name, func) \ +target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa) \ +{ \ + uint32_t rt1, rt0; \ + \ + sa = sa & 0x1F; \ + MIPSDSP_SPLIT64_32(rt, rt1, rt0); \ + \ + rt1 = mipsdsp_##func(rt1, sa); \ + rt0 = mipsdsp_##func(rt0, sa); \ + \ + return MIPSDSP_RETURN64_32(rt1, rt0); \ +} + +#define SHIFT_PW_ENV(name, func) \ +target_ulong helper_##name##_pw(target_ulong rt, target_ulong sa, \ + CPUMIPSState *env) \ +{ \ + uint32_t rt1, rt0; \ + \ + sa = sa & 0x1F; \ + MIPSDSP_SPLIT64_32(rt, rt1, rt0); \ + \ + rt1 = mipsdsp_##func(rt1, sa, env); \ + rt0 = mipsdsp_##func(rt0, sa, env); \ + \ + return MIPSDSP_RETURN64_32(rt1, rt0); \ +} + +SHIFT_PW_ENV(shll, lshift32); +SHIFT_PW_ENV(shll_s, sat32_lshift); + +SHIFT_PW(shra, rashift32); +SHIFT_PW(shra_r, rnd32_rashift); + +#undef SHIFT_PW +#undef SHIFT_PW_ENV + +#endif + +#define SHIFT_PH(name, func) \ +target_ulong helper_##name##_ph(target_ulong sa, target_ulong rt) \ +{ \ + uint16_t rth, rtl; \ + \ + sa = sa & 0x0F; \ + \ + MIPSDSP_SPLIT32_16(rt, rth, rtl); \ + \ + rth = mipsdsp_##func(rth, sa); \ + rtl = mipsdsp_##func(rtl, sa); \ + \ + return MIPSDSP_RETURN32_16(rth, rtl); \ +} + +SHIFT_PH(shrl, rshift_u16); +SHIFT_PH(shra, rashift16); +SHIFT_PH(shra_r, rnd16_rashift); + +#undef SHIFT_PH + #undef MIPSDSP_LHI #undef MIPSDSP_LLO #undef MIPSDSP_HI diff --git a/target-mips/helper.h b/target-mips/helper.h index 3325ed6164..c1a0fead5b 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -488,4 +488,42 @@ DEF_HELPER_FLAGS_1(preceu_qh_obla, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_1(preceu_qh_obra, TCG_CALL_NO_RWG_SE, tl, tl) #endif +/* DSP GPR-Based Shift Sub-class insns */ +DEF_HELPER_FLAGS_3(shll_qb, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(shll_ob, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(shll_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(shll_s_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(shll_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(shll_s_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(shll_s_w, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(shll_pw, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(shll_s_pw, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_2(shrl_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(shrl_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shrl_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif +DEF_HELPER_FLAGS_2(shra_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(shra_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif +DEF_HELPER_FLAGS_2(shra_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_w, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(shra_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_qh, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(shra_r_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif + #include "def-helper.h" diff --git a/target-mips/translate.c b/target-mips/translate.c index b1fd02b806..044fde95aa 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -330,6 +330,18 @@ enum { OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3, #if defined(TARGET_MIPS64) OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3, +#endif + /* MIPS DSP GPR-Based Shift Sub-class */ + OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3, +#if defined(TARGET_MIPS64) + OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3, +#endif + /* MIPS DSP Multiply Sub-class insns */ + /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */ + /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */ + OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3, +#if defined(TARGET_MIPS64) + OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3, #endif }; @@ -439,6 +451,32 @@ enum { OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP, OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP, }; +#define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP GPR-Based Shift Sub-class */ + OPC_SHLL_QB = (0x00 << 6) | OPC_SHLL_QB_DSP, + OPC_SHLLV_QB = (0x02 << 6) | OPC_SHLL_QB_DSP, + OPC_SHLL_PH = (0x08 << 6) | OPC_SHLL_QB_DSP, + OPC_SHLLV_PH = (0x0A << 6) | OPC_SHLL_QB_DSP, + OPC_SHLL_S_PH = (0x0C << 6) | OPC_SHLL_QB_DSP, + OPC_SHLLV_S_PH = (0x0E << 6) | OPC_SHLL_QB_DSP, + OPC_SHLL_S_W = (0x14 << 6) | OPC_SHLL_QB_DSP, + OPC_SHLLV_S_W = (0x16 << 6) | OPC_SHLL_QB_DSP, + OPC_SHRL_QB = (0x01 << 6) | OPC_SHLL_QB_DSP, + OPC_SHRLV_QB = (0x03 << 6) | OPC_SHLL_QB_DSP, + OPC_SHRL_PH = (0x19 << 6) | OPC_SHLL_QB_DSP, + OPC_SHRLV_PH = (0x1B << 6) | OPC_SHLL_QB_DSP, + OPC_SHRA_QB = (0x04 << 6) | OPC_SHLL_QB_DSP, + OPC_SHRA_R_QB = (0x05 << 6) | OPC_SHLL_QB_DSP, + OPC_SHRAV_QB = (0x06 << 6) | OPC_SHLL_QB_DSP, + OPC_SHRAV_R_QB = (0x07 << 6) | OPC_SHLL_QB_DSP, + OPC_SHRA_PH = (0x09 << 6) | OPC_SHLL_QB_DSP, + OPC_SHRAV_PH = (0x0B << 6) | OPC_SHLL_QB_DSP, + OPC_SHRA_R_PH = (0x0D << 6) | OPC_SHLL_QB_DSP, + OPC_SHRAV_R_PH = (0x0F << 6) | OPC_SHLL_QB_DSP, + OPC_SHRA_R_W = (0x15 << 6) | OPC_SHLL_QB_DSP, + OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP, +}; #if defined(TARGET_MIPS64) #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) @@ -507,6 +545,39 @@ enum { }; #endif +#if defined(TARGET_MIPS64) +#define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP GPR-Based Shift Sub-class */ + OPC_SHLL_PW = (0x10 << 6) | OPC_SHLL_OB_DSP, + OPC_SHLL_S_PW = (0x14 << 6) | OPC_SHLL_OB_DSP, + OPC_SHLLV_OB = (0x02 << 6) | OPC_SHLL_OB_DSP, + OPC_SHLLV_PW = (0x12 << 6) | OPC_SHLL_OB_DSP, + OPC_SHLLV_S_PW = (0x16 << 6) | OPC_SHLL_OB_DSP, + OPC_SHLLV_QH = (0x0A << 6) | OPC_SHLL_OB_DSP, + OPC_SHLLV_S_QH = (0x0E << 6) | OPC_SHLL_OB_DSP, + OPC_SHRA_PW = (0x11 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRA_R_PW = (0x15 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRAV_OB = (0x06 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRAV_R_OB = (0x07 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRAV_PW = (0x13 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRAV_R_PW = (0x17 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRAV_QH = (0x0B << 6) | OPC_SHLL_OB_DSP, + OPC_SHRAV_R_QH = (0x0F << 6) | OPC_SHLL_OB_DSP, + OPC_SHRLV_OB = (0x03 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRLV_QH = (0x1B << 6) | OPC_SHLL_OB_DSP, + OPC_SHLL_OB = (0x00 << 6) | OPC_SHLL_OB_DSP, + OPC_SHLL_QH = (0x08 << 6) | OPC_SHLL_OB_DSP, + OPC_SHLL_S_QH = (0x0C << 6) | OPC_SHLL_OB_DSP, + OPC_SHRA_OB = (0x04 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRA_R_OB = (0x05 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRA_QH = (0x09 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRA_R_QH = (0x0D << 6) | OPC_SHLL_OB_DSP, + OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP, + OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP, +}; +#endif + /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) @@ -12894,6 +12965,253 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, MIPS_DEBUG("%s", opn); } +static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, + int ret, int v1, int v2) +{ + uint32_t op2; + const char *opn = "mipsdsp shift"; + TCGv t0; + TCGv v1_t; + TCGv v2_t; + + if (ret == 0) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + v1_t = tcg_temp_new(); + v2_t = tcg_temp_new(); + + tcg_gen_movi_tl(t0, v1); + gen_load_gpr(v1_t, v1); + gen_load_gpr(v2_t, v2); + + switch (opc) { + case OPC_SHLL_QB_DSP: + { + op2 = MASK_SHLL_QB(ctx->opcode); + switch (op2) { + case OPC_SHLL_QB: + check_dsp(ctx); + gen_helper_shll_qb(cpu_gpr[ret], t0, v2_t, cpu_env); + break; + case OPC_SHLLV_QB: + check_dsp(ctx); + gen_helper_shll_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SHLL_PH: + check_dsp(ctx); + gen_helper_shll_ph(cpu_gpr[ret], t0, v2_t, cpu_env); + break; + case OPC_SHLLV_PH: + check_dsp(ctx); + gen_helper_shll_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SHLL_S_PH: + check_dsp(ctx); + gen_helper_shll_s_ph(cpu_gpr[ret], t0, v2_t, cpu_env); + break; + case OPC_SHLLV_S_PH: + check_dsp(ctx); + gen_helper_shll_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SHLL_S_W: + check_dsp(ctx); + gen_helper_shll_s_w(cpu_gpr[ret], t0, v2_t, cpu_env); + break; + case OPC_SHLLV_S_W: + check_dsp(ctx); + gen_helper_shll_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_SHRL_QB: + check_dsp(ctx); + gen_helper_shrl_qb(cpu_gpr[ret], t0, v2_t); + break; + case OPC_SHRLV_QB: + check_dsp(ctx); + gen_helper_shrl_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SHRL_PH: + check_dspr2(ctx); + gen_helper_shrl_ph(cpu_gpr[ret], t0, v2_t); + break; + case OPC_SHRLV_PH: + check_dspr2(ctx); + gen_helper_shrl_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SHRA_QB: + check_dspr2(ctx); + gen_helper_shra_qb(cpu_gpr[ret], t0, v2_t); + break; + case OPC_SHRA_R_QB: + check_dspr2(ctx); + gen_helper_shra_r_qb(cpu_gpr[ret], t0, v2_t); + break; + case OPC_SHRAV_QB: + check_dspr2(ctx); + gen_helper_shra_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SHRAV_R_QB: + check_dspr2(ctx); + gen_helper_shra_r_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SHRA_PH: + check_dsp(ctx); + gen_helper_shra_ph(cpu_gpr[ret], t0, v2_t); + break; + case OPC_SHRA_R_PH: + check_dsp(ctx); + gen_helper_shra_r_ph(cpu_gpr[ret], t0, v2_t); + break; + case OPC_SHRAV_PH: + check_dsp(ctx); + gen_helper_shra_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SHRAV_R_PH: + check_dsp(ctx); + gen_helper_shra_r_ph(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_SHRA_R_W: + check_dsp(ctx); + gen_helper_shra_r_w(cpu_gpr[ret], t0, v2_t); + break; + case OPC_SHRAV_R_W: + check_dsp(ctx); + gen_helper_shra_r_w(cpu_gpr[ret], v1_t, v2_t); + break; + default: /* Invalid */ + MIPS_INVAL("MASK SHLL.QB"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + } +#ifdef TARGET_MIPS64 + case OPC_SHLL_OB_DSP: + op2 = MASK_SHLL_OB(ctx->opcode); + switch (op2) { + case OPC_SHLL_PW: + check_dsp(ctx); + gen_helper_shll_pw(cpu_gpr[ret], v2_t, t0, cpu_env); + break; + case OPC_SHLLV_PW: + check_dsp(ctx); + gen_helper_shll_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env); + break; + case OPC_SHLL_S_PW: + check_dsp(ctx); + gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, t0, cpu_env); + break; + case OPC_SHLLV_S_PW: + check_dsp(ctx); + gen_helper_shll_s_pw(cpu_gpr[ret], v2_t, v1_t, cpu_env); + break; + case OPC_SHLL_OB: + check_dsp(ctx); + gen_helper_shll_ob(cpu_gpr[ret], v2_t, t0, cpu_env); + break; + case OPC_SHLLV_OB: + check_dsp(ctx); + gen_helper_shll_ob(cpu_gpr[ret], v2_t, v1_t, cpu_env); + break; + case OPC_SHLL_QH: + check_dsp(ctx); + gen_helper_shll_qh(cpu_gpr[ret], v2_t, t0, cpu_env); + break; + case OPC_SHLLV_QH: + check_dsp(ctx); + gen_helper_shll_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env); + break; + case OPC_SHLL_S_QH: + check_dsp(ctx); + gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, t0, cpu_env); + break; + case OPC_SHLLV_S_QH: + check_dsp(ctx); + gen_helper_shll_s_qh(cpu_gpr[ret], v2_t, v1_t, cpu_env); + break; + case OPC_SHRA_OB: + check_dspr2(ctx); + gen_helper_shra_ob(cpu_gpr[ret], v2_t, t0); + break; + case OPC_SHRAV_OB: + check_dspr2(ctx); + gen_helper_shra_ob(cpu_gpr[ret], v2_t, v1_t); + break; + case OPC_SHRA_R_OB: + check_dspr2(ctx); + gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, t0); + break; + case OPC_SHRAV_R_OB: + check_dspr2(ctx); + gen_helper_shra_r_ob(cpu_gpr[ret], v2_t, v1_t); + break; + case OPC_SHRA_PW: + check_dsp(ctx); + gen_helper_shra_pw(cpu_gpr[ret], v2_t, t0); + break; + case OPC_SHRAV_PW: + check_dsp(ctx); + gen_helper_shra_pw(cpu_gpr[ret], v2_t, v1_t); + break; + case OPC_SHRA_R_PW: + check_dsp(ctx); + gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, t0); + break; + case OPC_SHRAV_R_PW: + check_dsp(ctx); + gen_helper_shra_r_pw(cpu_gpr[ret], v2_t, v1_t); + break; + case OPC_SHRA_QH: + check_dsp(ctx); + gen_helper_shra_qh(cpu_gpr[ret], v2_t, t0); + break; + case OPC_SHRAV_QH: + check_dsp(ctx); + gen_helper_shra_qh(cpu_gpr[ret], v2_t, v1_t); + break; + case OPC_SHRA_R_QH: + check_dsp(ctx); + gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, t0); + break; + case OPC_SHRAV_R_QH: + check_dsp(ctx); + gen_helper_shra_r_qh(cpu_gpr[ret], v2_t, v1_t); + break; + case OPC_SHRL_OB: + check_dsp(ctx); + gen_helper_shrl_ob(cpu_gpr[ret], v2_t, t0); + break; + case OPC_SHRLV_OB: + check_dsp(ctx); + gen_helper_shrl_ob(cpu_gpr[ret], v2_t, v1_t); + break; + case OPC_SHRL_QH: + check_dspr2(ctx); + gen_helper_shrl_qh(cpu_gpr[ret], v2_t, t0); + break; + case OPC_SHRLV_QH: + check_dspr2(ctx); + gen_helper_shrl_qh(cpu_gpr[ret], v2_t, v1_t); + break; + default: /* Invalid */ + MIPS_INVAL("MASK SHLL.OB"); + generate_exception(ctx, EXCP_RI); + break; + } + break; +#endif + } + + tcg_temp_free(t0); + tcg_temp_free(v1_t); + tcg_temp_free(v2_t); + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s", opn); +} + /* End MIPSDSP functions. */ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) @@ -13370,6 +13688,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; } break; + case OPC_SHLL_QB_DSP: + gen_mipsdsp_shift(ctx, op1, rd, rs, rt); + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: @@ -13471,6 +13792,9 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; } break; + case OPC_SHLL_OB_DSP: + gen_mipsdsp_shift(ctx, op1, rd, rs, rt); + break; #endif default: /* Invalid */ MIPS_INVAL("special3"); From a22260ae380fa6abb546479cfc2962ba4c40382d Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:08 +0800 Subject: [PATCH 138/291] target-mips: Add ASE DSP multiply instructions Add MIPS ASE DSP Multiply instructions. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 923 +++++++++++++++++++++++++++++++++++++++ target-mips/helper.h | 91 ++++ target-mips/translate.c | 485 ++++++++++++++++++++ 3 files changed, 1499 insertions(+) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 3c79ceb1a7..86c27ec0e8 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -2189,6 +2189,929 @@ SHIFT_PH(shra_r, rnd16_rashift); #undef SHIFT_PH +/** DSP Multiply Sub-class insns **/ +/* Return value made up by two 16bits value. + * FIXME give the macro a better name. + */ +#define MUL_RETURN32_16_PH(name, func, \ + rsmov1, rsmov2, rsfilter, \ + rtmov1, rtmov2, rtfilter) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint16_t rsB, rsA, rtB, rtA; \ + \ + rsB = (rs >> rsmov1) & rsfilter; \ + rsA = (rs >> rsmov2) & rsfilter; \ + rtB = (rt >> rtmov1) & rtfilter; \ + rtA = (rt >> rtmov2) & rtfilter; \ + \ + rsB = mipsdsp_##func(rsB, rtB, env); \ + rsA = mipsdsp_##func(rsA, rtA, env); \ + \ + return MIPSDSP_RETURN32_16(rsB, rsA); \ +} + +MUL_RETURN32_16_PH(muleu_s_ph_qbl, mul_u8_u16, \ + 24, 16, MIPSDSP_Q0, \ + 16, 0, MIPSDSP_LO); +MUL_RETURN32_16_PH(muleu_s_ph_qbr, mul_u8_u16, \ + 8, 0, MIPSDSP_Q0, \ + 16, 0, MIPSDSP_LO); +MUL_RETURN32_16_PH(mulq_rs_ph, rndq15_mul_q15_q15, \ + 16, 0, MIPSDSP_LO, \ + 16, 0, MIPSDSP_LO); +MUL_RETURN32_16_PH(mul_ph, mul_i16_i16, \ + 16, 0, MIPSDSP_LO, \ + 16, 0, MIPSDSP_LO); +MUL_RETURN32_16_PH(mul_s_ph, sat16_mul_i16_i16, \ + 16, 0, MIPSDSP_LO, \ + 16, 0, MIPSDSP_LO); +MUL_RETURN32_16_PH(mulq_s_ph, sat16_mul_q15_q15, \ + 16, 0, MIPSDSP_LO, \ + 16, 0, MIPSDSP_LO); + +#undef MUL_RETURN32_16_PH + +#define MUL_RETURN32_32_ph(name, func, movbits) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int16_t rsh, rth; \ + int32_t temp; \ + \ + rsh = (rs >> movbits) & MIPSDSP_LO; \ + rth = (rt >> movbits) & MIPSDSP_LO; \ + temp = mipsdsp_##func(rsh, rth, env); \ + \ + return (target_long)(int32_t)temp; \ +} + +MUL_RETURN32_32_ph(muleq_s_w_phl, mul_q15_q15_overflowflag21, 16); +MUL_RETURN32_32_ph(muleq_s_w_phr, mul_q15_q15_overflowflag21, 0); + +#undef MUL_RETURN32_32_ph + +#define MUL_VOID_PH(name, use_ac_env) \ +void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int16_t rsh, rsl, rth, rtl; \ + int32_t tempB, tempA; \ + int64_t acc, dotp; \ + \ + MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ + MIPSDSP_SPLIT32_16(rt, rth, rtl); \ + \ + if (use_ac_env == 1) { \ + tempB = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \ + tempA = mipsdsp_mul_q15_q15(ac, rsl, rtl, env); \ + } else { \ + tempB = mipsdsp_mul_u16_u16(rsh, rth); \ + tempA = mipsdsp_mul_u16_u16(rsl, rtl); \ + } \ + \ + dotp = (int64_t)tempB - (int64_t)tempA; \ + acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \ + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \ + dotp = dotp + acc; \ + env->active_tc.HI[ac] = (target_long)(int32_t) \ + ((dotp & MIPSDSP_LHI) >> 32); \ + env->active_tc.LO[ac] = (target_long)(int32_t)(dotp & MIPSDSP_LLO); \ +} + +MUL_VOID_PH(mulsaq_s_w_ph, 1); +MUL_VOID_PH(mulsa_w_ph, 0); + +#undef MUL_VOID_PH + +#if defined(TARGET_MIPS64) +#define MUL_RETURN64_16_QH(name, func, \ + rsmov1, rsmov2, rsmov3, rsmov4, rsfilter, \ + rtmov1, rtmov2, rtmov3, rtmov4, rtfilter) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint16_t rs3, rs2, rs1, rs0; \ + uint16_t rt3, rt2, rt1, rt0; \ + uint16_t tempD, tempC, tempB, tempA; \ + \ + rs3 = (rs >> rsmov1) & rsfilter; \ + rs2 = (rs >> rsmov2) & rsfilter; \ + rs1 = (rs >> rsmov3) & rsfilter; \ + rs0 = (rs >> rsmov4) & rsfilter; \ + rt3 = (rt >> rtmov1) & rtfilter; \ + rt2 = (rt >> rtmov2) & rtfilter; \ + rt1 = (rt >> rtmov3) & rtfilter; \ + rt0 = (rt >> rtmov4) & rtfilter; \ + \ + tempD = mipsdsp_##func(rs3, rt3, env); \ + tempC = mipsdsp_##func(rs2, rt2, env); \ + tempB = mipsdsp_##func(rs1, rt1, env); \ + tempA = mipsdsp_##func(rs0, rt0, env); \ + \ + return MIPSDSP_RETURN64_16(tempD, tempC, tempB, tempA); \ +} + +MUL_RETURN64_16_QH(muleu_s_qh_obl, mul_u8_u16, \ + 56, 48, 40, 32, MIPSDSP_Q0, \ + 48, 32, 16, 0, MIPSDSP_LO); +MUL_RETURN64_16_QH(muleu_s_qh_obr, mul_u8_u16, \ + 24, 16, 8, 0, MIPSDSP_Q0, \ + 48, 32, 16, 0, MIPSDSP_LO); +MUL_RETURN64_16_QH(mulq_rs_qh, rndq15_mul_q15_q15, \ + 48, 32, 16, 0, MIPSDSP_LO, \ + 48, 32, 16, 0, MIPSDSP_LO); + +#undef MUL_RETURN64_16_QH + +#define MUL_RETURN64_32_QH(name, \ + rsmov1, rsmov2, \ + rtmov1, rtmov2) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint16_t rsB, rsA; \ + uint16_t rtB, rtA; \ + uint32_t tempB, tempA; \ + \ + rsB = (rs >> rsmov1) & MIPSDSP_LO; \ + rsA = (rs >> rsmov2) & MIPSDSP_LO; \ + rtB = (rt >> rtmov1) & MIPSDSP_LO; \ + rtA = (rt >> rtmov2) & MIPSDSP_LO; \ + \ + tempB = mipsdsp_mul_q15_q15(5, rsB, rtB, env); \ + tempA = mipsdsp_mul_q15_q15(5, rsA, rtA, env); \ + \ + return ((uint64_t)tempB << 32) | (uint64_t)tempA; \ +} + +MUL_RETURN64_32_QH(muleq_s_pw_qhl, 48, 32, 48, 32); +MUL_RETURN64_32_QH(muleq_s_pw_qhr, 16, 0, 16, 0); + +#undef MUL_RETURN64_32_QH + +void helper_mulsaq_s_w_qh(target_ulong rs, target_ulong rt, uint32_t ac, + CPUMIPSState *env) +{ + int16_t rs3, rs2, rs1, rs0; + int16_t rt3, rt2, rt1, rt0; + int32_t tempD, tempC, tempB, tempA; + int64_t acc[2]; + int64_t temp[2]; + int64_t temp_sum; + + MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); + MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); + + tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env); + tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env); + tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env); + tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env); + + temp[0] = ((int32_t)tempD - (int32_t)tempC) + + ((int32_t)tempB - (int32_t)tempA); + temp[0] = (int64_t)(temp[0] << 30) >> 30; + if (((temp[0] >> 33) & 0x01) == 0) { + temp[1] = 0x00; + } else { + temp[1] = ~0ull; + } + + acc[0] = env->active_tc.LO[ac]; + acc[1] = env->active_tc.HI[ac]; + + temp_sum = acc[0] + temp[0]; + if (((uint64_t)temp_sum < (uint64_t)acc[0]) && + ((uint64_t)temp_sum < (uint64_t)temp[0])) { + acc[1] += 1; + } + acc[0] = temp_sum; + acc[1] += temp[1]; + + env->active_tc.HI[ac] = acc[1]; + env->active_tc.LO[ac] = acc[0]; +} +#endif + +#define DP_QB(name, func, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \ +void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint8_t rs3, rs2; \ + uint8_t rt3, rt2; \ + uint16_t tempB, tempA; \ + uint64_t tempC, dotp; \ + \ + rs3 = (rs >> rsmov1) & MIPSDSP_Q0; \ + rs2 = (rs >> rsmov2) & MIPSDSP_Q0; \ + rt3 = (rt >> rtmov1) & MIPSDSP_Q0; \ + rt2 = (rt >> rtmov2) & MIPSDSP_Q0; \ + tempB = mipsdsp_##func(rs3, rt3); \ + tempA = mipsdsp_##func(rs2, rt2); \ + dotp = (int64_t)tempB + (int64_t)tempA; \ + if (is_add) { \ + tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \ + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) \ + + dotp; \ + } else { \ + tempC = (((uint64_t)env->active_tc.HI[ac] << 32) | \ + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO)) \ + - dotp; \ + } \ + \ + env->active_tc.HI[ac] = (target_long)(int32_t) \ + ((tempC & MIPSDSP_LHI) >> 32); \ + env->active_tc.LO[ac] = (target_long)(int32_t)(tempC & MIPSDSP_LLO); \ +} + +DP_QB(dpau_h_qbl, mul_u8_u8, 1, 24, 16, 24, 16); +DP_QB(dpau_h_qbr, mul_u8_u8, 1, 8, 0, 8, 0); +DP_QB(dpsu_h_qbl, mul_u8_u8, 0, 24, 16, 24, 16); +DP_QB(dpsu_h_qbr, mul_u8_u8, 0, 8, 0, 8, 0); + +#undef DP_QB + +#if defined(TARGET_MIPS64) +#define DP_OB(name, add_sub, \ + rsmov1, rsmov2, rsmov3, rsmov4, \ + rtmov1, rtmov2, rtmov3, rtmov4) \ +void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \ + CPUMIPSState *env) \ +{ \ + uint8_t rsD, rsC, rsB, rsA; \ + uint8_t rtD, rtC, rtB, rtA; \ + uint16_t tempD, tempC, tempB, tempA; \ + uint64_t temp[2]; \ + uint64_t acc[2]; \ + uint64_t temp_sum; \ + \ + temp[0] = 0; \ + temp[1] = 0; \ + \ + rsD = (rs >> rsmov1) & MIPSDSP_Q0; \ + rsC = (rs >> rsmov2) & MIPSDSP_Q0; \ + rsB = (rs >> rsmov3) & MIPSDSP_Q0; \ + rsA = (rs >> rsmov4) & MIPSDSP_Q0; \ + rtD = (rt >> rtmov1) & MIPSDSP_Q0; \ + rtC = (rt >> rtmov2) & MIPSDSP_Q0; \ + rtB = (rt >> rtmov3) & MIPSDSP_Q0; \ + rtA = (rt >> rtmov4) & MIPSDSP_Q0; \ + \ + tempD = mipsdsp_mul_u8_u8(rsD, rtD); \ + tempC = mipsdsp_mul_u8_u8(rsC, rtC); \ + tempB = mipsdsp_mul_u8_u8(rsB, rtB); \ + tempA = mipsdsp_mul_u8_u8(rsA, rtA); \ + \ + temp[0] = (uint64_t)tempD + (uint64_t)tempC + \ + (uint64_t)tempB + (uint64_t)tempA; \ + \ + acc[0] = env->active_tc.LO[ac]; \ + acc[1] = env->active_tc.HI[ac]; \ + \ + if (add_sub) { \ + temp_sum = acc[0] + temp[0]; \ + if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \ + ((uint64_t)temp_sum < (uint64_t)temp[0])) { \ + acc[1] += 1; \ + } \ + temp[0] = temp_sum; \ + temp[1] = acc[1] + temp[1]; \ + } else { \ + temp_sum = acc[0] - temp[0]; \ + if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \ + acc[1] -= 1; \ + } \ + temp[0] = temp_sum; \ + temp[1] = acc[1] - temp[1]; \ + } \ + \ + env->active_tc.HI[ac] = temp[1]; \ + env->active_tc.LO[ac] = temp[0]; \ +} + +DP_OB(dpau_h_obl, 1, 56, 48, 40, 32, 56, 48, 40, 32); +DP_OB(dpau_h_obr, 1, 24, 16, 8, 0, 24, 16, 8, 0); +DP_OB(dpsu_h_obl, 0, 56, 48, 40, 32, 56, 48, 40, 32); +DP_OB(dpsu_h_obr, 0, 24, 16, 8, 0, 24, 16, 8, 0); + +#undef DP_OB +#endif + +#define DP_NOFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \ +void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint16_t rsB, rsA, rtB, rtA; \ + int32_t tempA, tempB; \ + int64_t acc; \ + \ + rsB = (rs >> rsmov1) & MIPSDSP_LO; \ + rsA = (rs >> rsmov2) & MIPSDSP_LO; \ + rtB = (rt >> rtmov1) & MIPSDSP_LO; \ + rtA = (rt >> rtmov2) & MIPSDSP_LO; \ + \ + tempB = (int32_t)rsB * (int32_t)rtB; \ + tempA = (int32_t)rsA * (int32_t)rtA; \ + \ + acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \ + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \ + \ + if (is_add) { \ + acc = acc + ((int64_t)tempB + (int64_t)tempA); \ + } else { \ + acc = acc - ((int64_t)tempB + (int64_t)tempA); \ + } \ + \ + env->active_tc.HI[ac] = (target_long)(int32_t)((acc & MIPSDSP_LHI) >> 32); \ + env->active_tc.LO[ac] = (target_long)(int32_t)(acc & MIPSDSP_LLO); \ +} + +DP_NOFUNC_PH(dpa_w_ph, 1, 16, 0, 16, 0); +DP_NOFUNC_PH(dpax_w_ph, 1, 16, 0, 0, 16); +DP_NOFUNC_PH(dps_w_ph, 0, 16, 0, 16, 0); +DP_NOFUNC_PH(dpsx_w_ph, 0, 16, 0, 0, 16); +#undef DP_NOFUNC_PH + +#define DP_HASFUNC_PH(name, is_add, rsmov1, rsmov2, rtmov1, rtmov2) \ +void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int16_t rsB, rsA, rtB, rtA; \ + int32_t tempB, tempA; \ + int64_t acc, dotp; \ + \ + rsB = (rs >> rsmov1) & MIPSDSP_LO; \ + rsA = (rs >> rsmov2) & MIPSDSP_LO; \ + rtB = (rt >> rtmov1) & MIPSDSP_LO; \ + rtA = (rt >> rtmov2) & MIPSDSP_LO; \ + \ + tempB = mipsdsp_mul_q15_q15(ac, rsB, rtB, env); \ + tempA = mipsdsp_mul_q15_q15(ac, rsA, rtA, env); \ + \ + dotp = (int64_t)tempB + (int64_t)tempA; \ + acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \ + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \ + \ + if (is_add) { \ + acc = acc + dotp; \ + } else { \ + acc = acc - dotp; \ + } \ + \ + env->active_tc.HI[ac] = (target_long)(int32_t) \ + ((acc & MIPSDSP_LHI) >> 32); \ + env->active_tc.LO[ac] = (target_long)(int32_t) \ + (acc & MIPSDSP_LLO); \ +} + +DP_HASFUNC_PH(dpaq_s_w_ph, 1, 16, 0, 16, 0); +DP_HASFUNC_PH(dpaqx_s_w_ph, 1, 16, 0, 0, 16); +DP_HASFUNC_PH(dpsq_s_w_ph, 0, 16, 0, 16, 0); +DP_HASFUNC_PH(dpsqx_s_w_ph, 0, 16, 0, 0, 16); + +#undef DP_HASFUNC_PH + +#define DP_128OPERATION_PH(name, is_add) \ +void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int16_t rsh, rsl, rth, rtl; \ + int32_t tempB, tempA, tempC62_31, tempC63; \ + int64_t acc, dotp, tempC; \ + \ + MIPSDSP_SPLIT32_16(rs, rsh, rsl); \ + MIPSDSP_SPLIT32_16(rt, rth, rtl); \ + \ + tempB = mipsdsp_mul_q15_q15(ac, rsh, rtl, env); \ + tempA = mipsdsp_mul_q15_q15(ac, rsl, rth, env); \ + \ + dotp = (int64_t)tempB + (int64_t)tempA; \ + acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \ + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \ + if (is_add) { \ + tempC = acc + dotp; \ + } else { \ + tempC = acc - dotp; \ + } \ + tempC63 = (tempC >> 63) & 0x01; \ + tempC62_31 = (tempC >> 31) & 0xFFFFFFFF; \ + \ + if ((tempC63 == 0) && (tempC62_31 != 0x00000000)) { \ + tempC = 0x7FFFFFFF; \ + set_DSPControl_overflow_flag(1, 16 + ac, env); \ + } \ + \ + if ((tempC63 == 1) && (tempC62_31 != 0xFFFFFFFF)) { \ + tempC = (int64_t)(int32_t)0x80000000; \ + set_DSPControl_overflow_flag(1, 16 + ac, env); \ + } \ + \ + env->active_tc.HI[ac] = (target_long)(int32_t) \ + ((tempC & MIPSDSP_LHI) >> 32); \ + env->active_tc.LO[ac] = (target_long)(int32_t) \ + (tempC & MIPSDSP_LLO); \ +} + +DP_128OPERATION_PH(dpaqx_sa_w_ph, 1); +DP_128OPERATION_PH(dpsqx_sa_w_ph, 0); + +#undef DP_128OPERATION_HP + +#if defined(TARGET_MIPS64) +#define DP_QH(name, is_add, use_ac_env) \ +void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \ + CPUMIPSState *env) \ +{ \ + int32_t rs3, rs2, rs1, rs0; \ + int32_t rt3, rt2, rt1, rt0; \ + int32_t tempD, tempC, tempB, tempA; \ + int64_t acc[2]; \ + int64_t temp[2]; \ + int64_t temp_sum; \ + \ + MIPSDSP_SPLIT64_16(rs, rs3, rs2, rs1, rs0); \ + MIPSDSP_SPLIT64_16(rt, rt3, rt2, rt1, rt0); \ + \ + if (use_ac_env) { \ + tempD = mipsdsp_mul_q15_q15(ac, rs3, rt3, env); \ + tempC = mipsdsp_mul_q15_q15(ac, rs2, rt2, env); \ + tempB = mipsdsp_mul_q15_q15(ac, rs1, rt1, env); \ + tempA = mipsdsp_mul_q15_q15(ac, rs0, rt0, env); \ + } else { \ + tempD = mipsdsp_mul_u16_u16(rs3, rt3); \ + tempC = mipsdsp_mul_u16_u16(rs2, rt2); \ + tempB = mipsdsp_mul_u16_u16(rs1, rt1); \ + tempA = mipsdsp_mul_u16_u16(rs0, rt0); \ + } \ + \ + temp[0] = (int64_t)tempD + (int64_t)tempC + \ + (int64_t)tempB + (int64_t)tempA; \ + \ + if (temp[0] >= 0) { \ + temp[1] = 0; \ + } else { \ + temp[1] = ~0ull; \ + } \ + \ + acc[1] = env->active_tc.HI[ac]; \ + acc[0] = env->active_tc.LO[ac]; \ + \ + if (is_add) { \ + temp_sum = acc[0] + temp[0]; \ + if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \ + ((uint64_t)temp_sum < (uint64_t)temp[0])) { \ + acc[1] = acc[1] + 1; \ + } \ + temp[0] = temp_sum; \ + temp[1] = acc[1] + temp[1]; \ + } else { \ + temp_sum = acc[0] - temp[0]; \ + if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \ + acc[1] = acc[1] - 1; \ + } \ + temp[0] = temp_sum; \ + temp[1] = acc[1] - temp[1]; \ + } \ + \ + env->active_tc.HI[ac] = temp[1]; \ + env->active_tc.LO[ac] = temp[0]; \ +} + +DP_QH(dpa_w_qh, 1, 0); +DP_QH(dpaq_s_w_qh, 1, 1); +DP_QH(dps_w_qh, 0, 0); +DP_QH(dpsq_s_w_qh, 0, 1); + +#undef DP_QH + +#endif + +#define DP_L_W(name, is_add) \ +void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int32_t temp63; \ + int64_t dotp, acc; \ + uint64_t temp; \ + \ + dotp = mipsdsp_mul_q31_q31(ac, rs, rt, env); \ + acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \ + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \ + if (!is_add) { \ + dotp = -dotp; \ + } \ + \ + temp = acc + dotp; \ + if (MIPSDSP_OVERFLOW((uint64_t)acc, (uint64_t)dotp, temp, \ + (0x01ull << 63))) { \ + temp63 = (temp >> 63) & 0x01; \ + if (temp63 == 1) { \ + temp = (0x01ull << 63) - 1; \ + } else { \ + temp = 0x01ull << 63; \ + } \ + \ + set_DSPControl_overflow_flag(1, 16 + ac, env); \ + } \ + \ + env->active_tc.HI[ac] = (target_long)(int32_t) \ + ((temp & MIPSDSP_LHI) >> 32); \ + env->active_tc.LO[ac] = (target_long)(int32_t) \ + (temp & MIPSDSP_LLO); \ +} + +DP_L_W(dpaq_sa_l_w, 1); +DP_L_W(dpsq_sa_l_w, 0); + +#undef DP_L_W + +#if defined(TARGET_MIPS64) +#define DP_L_PW(name, func) \ +void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \ + CPUMIPSState *env) \ +{ \ + int32_t rs1, rs0; \ + int32_t rt1, rt0; \ + int64_t tempB[2], tempA[2]; \ + int64_t temp[2]; \ + int64_t acc[2]; \ + int64_t temp_sum; \ + \ + temp[0] = 0; \ + temp[1] = 0; \ + \ + MIPSDSP_SPLIT64_32(rs, rs1, rs0); \ + MIPSDSP_SPLIT64_32(rt, rt1, rt0); \ + \ + tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env); \ + tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env); \ + \ + if (tempB[0] >= 0) { \ + tempB[1] = 0x00; \ + } else { \ + tempB[1] = ~0ull; \ + } \ + \ + if (tempA[0] >= 0) { \ + tempA[1] = 0x00; \ + } else { \ + tempA[1] = ~0ull; \ + } \ + \ + temp_sum = tempB[0] + tempA[0]; \ + if (((uint64_t)temp_sum < (uint64_t)tempB[0]) && \ + ((uint64_t)temp_sum < (uint64_t)tempA[0])) { \ + temp[1] += 1; \ + } \ + temp[0] = temp_sum; \ + temp[1] += tempB[1] + tempA[1]; \ + \ + mipsdsp_##func(acc, ac, temp, env); \ + \ + env->active_tc.HI[ac] = acc[1]; \ + env->active_tc.LO[ac] = acc[0]; \ +} + +DP_L_PW(dpaq_sa_l_pw, sat64_acc_add_q63); +DP_L_PW(dpsq_sa_l_pw, sat64_acc_sub_q63); + +#undef DP_L_PW + +void helper_mulsaq_s_l_pw(target_ulong rs, target_ulong rt, uint32_t ac, + CPUMIPSState *env) +{ + int32_t rs1, rs0; + int32_t rt1, rt0; + int64_t tempB[2], tempA[2]; + int64_t temp[2]; + int64_t acc[2]; + int64_t temp_sum; + + rs1 = (rs >> 32) & MIPSDSP_LLO; + rs0 = rs & MIPSDSP_LLO; + rt1 = (rt >> 32) & MIPSDSP_LLO; + rt0 = rt & MIPSDSP_LLO; + + tempB[0] = mipsdsp_mul_q31_q31(ac, rs1, rt1, env); + tempA[0] = mipsdsp_mul_q31_q31(ac, rs0, rt0, env); + + if (tempB[0] >= 0) { + tempB[1] = 0x00; + } else { + tempB[1] = ~0ull; + } + + if (tempA[0] >= 0) { + tempA[1] = 0x00; + } else { + tempA[1] = ~0ull; + } + + acc[0] = env->active_tc.LO[ac]; + acc[1] = env->active_tc.HI[ac]; + + temp_sum = tempB[0] - tempA[0]; + if ((uint64_t)temp_sum > (uint64_t)tempB[0]) { + tempB[1] -= 1; + } + temp[0] = temp_sum; + temp[1] = tempB[1] - tempA[1]; + + if ((temp[1] & 0x01) == 0) { + temp[1] = 0x00; + } else { + temp[1] = ~0ull; + } + + temp_sum = acc[0] + temp[0]; + if (((uint64_t)temp_sum < (uint64_t)acc[0]) && + ((uint64_t)temp_sum < (uint64_t)temp[0])) { + acc[1] += 1; + } + acc[0] = temp_sum; + acc[1] += temp[1]; + + env->active_tc.HI[ac] = acc[1]; + env->active_tc.LO[ac] = acc[0]; +} +#endif + +#define MAQ_S_W(name, mov) \ +void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int16_t rsh, rth; \ + int32_t tempA; \ + int64_t tempL, acc; \ + \ + rsh = (rs >> mov) & MIPSDSP_LO; \ + rth = (rt >> mov) & MIPSDSP_LO; \ + tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \ + acc = ((uint64_t)env->active_tc.HI[ac] << 32) | \ + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); \ + tempL = (int64_t)tempA + acc; \ + env->active_tc.HI[ac] = (target_long)(int32_t) \ + ((tempL & MIPSDSP_LHI) >> 32); \ + env->active_tc.LO[ac] = (target_long)(int32_t) \ + (tempL & MIPSDSP_LLO); \ +} + +MAQ_S_W(maq_s_w_phl, 16); +MAQ_S_W(maq_s_w_phr, 0); + +#undef MAQ_S_W + +#define MAQ_SA_W(name, mov) \ +void helper_##name(uint32_t ac, target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int16_t rsh, rth; \ + int32_t tempA; \ + \ + rsh = (rs >> mov) & MIPSDSP_LO; \ + rth = (rt >> mov) & MIPSDSP_LO; \ + tempA = mipsdsp_mul_q15_q15(ac, rsh, rth, env); \ + tempA = mipsdsp_sat32_acc_q31(ac, tempA, env); \ + \ + env->active_tc.HI[ac] = (target_long)(int32_t)(((int64_t)tempA & \ + MIPSDSP_LHI) >> 32); \ + env->active_tc.LO[ac] = (target_long)(int32_t)((int64_t)tempA & \ + MIPSDSP_LLO); \ +} + +MAQ_SA_W(maq_sa_w_phl, 16); +MAQ_SA_W(maq_sa_w_phr, 0); + +#undef MAQ_SA_W + +#define MULQ_W(name, addvar) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint32_t rs_t, rt_t; \ + int32_t tempI; \ + int64_t tempL; \ + \ + rs_t = rs & MIPSDSP_LLO; \ + rt_t = rt & MIPSDSP_LLO; \ + \ + if ((rs_t == 0x80000000) && (rt_t == 0x80000000)) { \ + tempL = 0x7FFFFFFF00000000ull; \ + set_DSPControl_overflow_flag(1, 21, env); \ + } else { \ + tempL = ((int64_t)rs_t * (int64_t)rt_t) << 1; \ + tempL += addvar; \ + } \ + tempI = (tempL & MIPSDSP_LHI) >> 32; \ + \ + return (target_long)(int32_t)tempI; \ +} + +MULQ_W(mulq_s_w, 0); +MULQ_W(mulq_rs_w, 0x80000000ull); + +#undef MULQ_W + +#if defined(TARGET_MIPS64) + +#define MAQ_S_W_QH(name, mov) \ +void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \ + CPUMIPSState *env) \ +{ \ + int16_t rs_t, rt_t; \ + int32_t temp_mul; \ + int64_t temp[2]; \ + int64_t acc[2]; \ + int64_t temp_sum; \ + \ + temp[0] = 0; \ + temp[1] = 0; \ + \ + rs_t = (rs >> mov) & MIPSDSP_LO; \ + rt_t = (rt >> mov) & MIPSDSP_LO; \ + temp_mul = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env); \ + \ + temp[0] = (int64_t)temp_mul; \ + if (temp[0] >= 0) { \ + temp[1] = 0x00; \ + } else { \ + temp[1] = ~0ull; \ + } \ + \ + acc[0] = env->active_tc.LO[ac]; \ + acc[1] = env->active_tc.HI[ac]; \ + \ + temp_sum = acc[0] + temp[0]; \ + if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \ + ((uint64_t)temp_sum < (uint64_t)temp[0])) { \ + acc[1] += 1; \ + } \ + acc[0] = temp_sum; \ + acc[1] += temp[1]; \ + \ + env->active_tc.HI[ac] = acc[1]; \ + env->active_tc.LO[ac] = acc[0]; \ +} + +MAQ_S_W_QH(maq_s_w_qhll, 48); +MAQ_S_W_QH(maq_s_w_qhlr, 32); +MAQ_S_W_QH(maq_s_w_qhrl, 16); +MAQ_S_W_QH(maq_s_w_qhrr, 0); + +#undef MAQ_S_W_QH + +#define MAQ_SA_W(name, mov) \ +void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \ + CPUMIPSState *env) \ +{ \ + int16_t rs_t, rt_t; \ + int32_t temp; \ + int64_t acc[2]; \ + \ + rs_t = (rs >> mov) & MIPSDSP_LO; \ + rt_t = (rt >> mov) & MIPSDSP_LO; \ + temp = mipsdsp_mul_q15_q15(ac, rs_t, rt_t, env); \ + temp = mipsdsp_sat32_acc_q31(ac, temp, env); \ + \ + acc[0] = (int64_t)(int32_t)temp; \ + if (acc[0] >= 0) { \ + acc[1] = 0x00; \ + } else { \ + acc[1] = ~0ull; \ + } \ + \ + env->active_tc.HI[ac] = acc[1]; \ + env->active_tc.LO[ac] = acc[0]; \ +} + +MAQ_SA_W(maq_sa_w_qhll, 48); +MAQ_SA_W(maq_sa_w_qhlr, 32); +MAQ_SA_W(maq_sa_w_qhrl, 16); +MAQ_SA_W(maq_sa_w_qhrr, 0); + +#undef MAQ_SA_W + +#define MAQ_S_L_PW(name, mov) \ +void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \ + CPUMIPSState *env) \ +{ \ + int32_t rs_t, rt_t; \ + int64_t temp[2]; \ + int64_t acc[2]; \ + int64_t temp_sum; \ + \ + temp[0] = 0; \ + temp[1] = 0; \ + \ + rs_t = (rs >> mov) & MIPSDSP_LLO; \ + rt_t = (rt >> mov) & MIPSDSP_LLO; \ + \ + temp[0] = mipsdsp_mul_q31_q31(ac, rs_t, rt_t, env); \ + if (temp[0] >= 0) { \ + temp[1] = 0x00; \ + } else { \ + temp[1] = ~0ull; \ + } \ + \ + acc[0] = env->active_tc.LO[ac]; \ + acc[1] = env->active_tc.HI[ac]; \ + \ + temp_sum = acc[0] + temp[0]; \ + if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \ + ((uint64_t)temp_sum < (uint64_t)temp[0])) { \ + acc[1] += 1; \ + } \ + acc[0] = temp_sum; \ + acc[1] += temp[1]; \ + \ + env->active_tc.HI[ac] = acc[1]; \ + env->active_tc.LO[ac] = acc[0]; \ +} + +MAQ_S_L_PW(maq_s_l_pwl, 32); +MAQ_S_L_PW(maq_s_l_pwr, 0); + +#undef MAQ_S_L_PW + +#define DM_OPERATE(name, func, is_add, sigext) \ +void helper_##name(target_ulong rs, target_ulong rt, uint32_t ac, \ + CPUMIPSState *env) \ +{ \ + int32_t rs1, rs0; \ + int32_t rt1, rt0; \ + int64_t tempBL[2], tempAL[2]; \ + int64_t acc[2]; \ + int64_t temp[2]; \ + int64_t temp_sum; \ + \ + temp[0] = 0x00; \ + temp[1] = 0x00; \ + \ + MIPSDSP_SPLIT64_32(rs, rs1, rs0); \ + MIPSDSP_SPLIT64_32(rt, rt1, rt0); \ + \ + if (sigext) { \ + tempBL[0] = (int64_t)mipsdsp_##func(rs1, rt1); \ + tempAL[0] = (int64_t)mipsdsp_##func(rs0, rt0); \ + \ + if (tempBL[0] >= 0) { \ + tempBL[1] = 0x0; \ + } else { \ + tempBL[1] = ~0ull; \ + } \ + \ + if (tempAL[0] >= 0) { \ + tempAL[1] = 0x0; \ + } else { \ + tempAL[1] = ~0ull; \ + } \ + } else { \ + tempBL[0] = mipsdsp_##func(rs1, rt1); \ + tempAL[0] = mipsdsp_##func(rs0, rt0); \ + tempBL[1] = 0; \ + tempAL[1] = 0; \ + } \ + \ + acc[1] = env->active_tc.HI[ac]; \ + acc[0] = env->active_tc.LO[ac]; \ + \ + temp_sum = tempBL[0] + tempAL[0]; \ + if (((uint64_t)temp_sum < (uint64_t)tempBL[0]) && \ + ((uint64_t)temp_sum < (uint64_t)tempAL[0])) { \ + temp[1] += 1; \ + } \ + temp[0] = temp_sum; \ + temp[1] += tempBL[1] + tempAL[1]; \ + \ + if (is_add) { \ + temp_sum = acc[0] + temp[0]; \ + if (((uint64_t)temp_sum < (uint64_t)acc[0]) && \ + ((uint64_t)temp_sum < (uint64_t)temp[0])) { \ + acc[1] += 1; \ + } \ + temp[0] = temp_sum; \ + temp[1] = acc[1] + temp[1]; \ + } else { \ + temp_sum = acc[0] - temp[0]; \ + if ((uint64_t)temp_sum > (uint64_t)acc[0]) { \ + acc[1] -= 1; \ + } \ + temp[0] = temp_sum; \ + temp[1] = acc[1] - temp[1]; \ + } \ + \ + env->active_tc.HI[ac] = temp[1]; \ + env->active_tc.LO[ac] = temp[0]; \ +} + +DM_OPERATE(dmadd, mul_i32_i32, 1, 1); +DM_OPERATE(dmaddu, mul_u32_u32, 1, 0); +DM_OPERATE(dmsub, mul_i32_i32, 0, 1); +DM_OPERATE(dmsubu, mul_u32_u32, 0, 0); +#undef DM_OPERATE +#endif + #undef MIPSDSP_LHI #undef MIPSDSP_LLO #undef MIPSDSP_HI diff --git a/target-mips/helper.h b/target-mips/helper.h index c1a0fead5b..139bb1e464 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -526,4 +526,95 @@ DEF_HELPER_FLAGS_2(shra_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(shra_r_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) #endif +/* DSP Multiply Sub-class insns */ +DEF_HELPER_FLAGS_3(muleu_s_ph_qbl, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(muleu_s_ph_qbr, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(muleu_s_qh_obl, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(muleu_s_qh_obr, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(mulq_rs_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(mulq_rs_qh, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(muleq_s_w_phl, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(muleq_s_w_phr, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(muleq_s_pw_qhl, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(muleq_s_pw_qhr, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_4(dpau_h_qbl, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpau_h_qbr, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpau_h_obl, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dpau_h_obr, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpsu_h_qbl, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpsu_h_qbr, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpsu_h_obl, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dpsu_h_obr, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpa_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpa_w_qh, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpax_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpaq_s_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpaq_s_w_qh, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpaqx_s_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpaqx_sa_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dps_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dps_w_qh, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpsx_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpsq_s_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpsq_s_w_qh, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpsqx_s_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(dpsqx_sa_w_ph, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(mulsaq_s_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(mulsaq_s_w_qh, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpaq_sa_l_w, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpaq_sa_l_pw, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(dpsq_sa_l_w, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(dpsq_sa_l_pw, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(mulsaq_s_l_pw, 0, void, tl, tl, i32, env) +#endif +DEF_HELPER_FLAGS_4(maq_s_w_phl, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(maq_s_w_phr, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(maq_sa_w_phl, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_4(maq_sa_w_phr, 0, void, i32, tl, tl, env) +DEF_HELPER_FLAGS_3(mul_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(mul_s_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(mulq_s_ph, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(mulq_s_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(mulq_rs_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_4(mulsa_w_ph, 0, void, i32, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_4(maq_s_w_qhll, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_s_w_qhlr, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_s_w_qhrl, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_s_w_qhrr, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_sa_w_qhll, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_sa_w_qhlr, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_sa_w_qhrl, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_sa_w_qhrr, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_s_l_pwl, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(maq_s_l_pwr, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dmadd, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dmaddu, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dmsub, 0, void, tl, tl, i32, env) +DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env) +#endif + #include "def-helper.h" diff --git a/target-mips/translate.c b/target-mips/translate.c index 044fde95aa..5d374c4c37 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -402,6 +402,13 @@ enum { OPC_ADDWC = (0x11 << 6) | OPC_ADDU_QB_DSP, OPC_MODSUB = (0x12 << 6) | OPC_ADDU_QB_DSP, OPC_RADDU_W_QB = (0x14 << 6) | OPC_ADDU_QB_DSP, + /* MIPS DSP Multiply Sub-class insns */ + OPC_MULEU_S_PH_QBL = (0x06 << 6) | OPC_ADDU_QB_DSP, + OPC_MULEU_S_PH_QBR = (0x07 << 6) | OPC_ADDU_QB_DSP, + OPC_MULQ_RS_PH = (0x1F << 6) | OPC_ADDU_QB_DSP, + OPC_MULEQ_S_W_PHL = (0x1C << 6) | OPC_ADDU_QB_DSP, + OPC_MULEQ_S_W_PHR = (0x1D << 6) | OPC_ADDU_QB_DSP, + OPC_MULQ_S_PH = (0x1E << 6) | OPC_ADDU_QB_DSP, }; #define OPC_ADDUH_QB_DSP OPC_MULT_G_2E @@ -420,6 +427,11 @@ enum { OPC_SUBQH_R_PH = (0x0B << 6) | OPC_ADDUH_QB_DSP, OPC_SUBQH_W = (0x11 << 6) | OPC_ADDUH_QB_DSP, OPC_SUBQH_R_W = (0x13 << 6) | OPC_ADDUH_QB_DSP, + /* MIPS DSP Multiply Sub-class insns */ + OPC_MUL_PH = (0x0C << 6) | OPC_ADDUH_QB_DSP, + OPC_MUL_S_PH = (0x0E << 6) | OPC_ADDUH_QB_DSP, + OPC_MULQ_S_W = (0x16 << 6) | OPC_ADDUH_QB_DSP, + OPC_MULQ_RS_W = (0x17 << 6) | OPC_ADDUH_QB_DSP, }; #define MASK_ABSQ_S_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) @@ -451,6 +463,7 @@ enum { OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP, OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP, }; + #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* MIPS DSP GPR-Based Shift Sub-class */ @@ -478,6 +491,33 @@ enum { OPC_SHRAV_R_W = (0x17 << 6) | OPC_SHLL_QB_DSP, }; +#define MASK_DPA_W_PH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Multiply Sub-class insns */ + OPC_DPAU_H_QBL = (0x03 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPAU_H_QBR = (0x07 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPSU_H_QBL = (0x0B << 6) | OPC_DPA_W_PH_DSP, + OPC_DPSU_H_QBR = (0x0F << 6) | OPC_DPA_W_PH_DSP, + OPC_DPA_W_PH = (0x00 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPAX_W_PH = (0x08 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPAQ_S_W_PH = (0x04 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPAQX_S_W_PH = (0x18 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPAQX_SA_W_PH = (0x1A << 6) | OPC_DPA_W_PH_DSP, + OPC_DPS_W_PH = (0x01 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPSX_W_PH = (0x09 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPSQ_S_W_PH = (0x05 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPSQX_S_W_PH = (0x19 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPSQX_SA_W_PH = (0x1B << 6) | OPC_DPA_W_PH_DSP, + OPC_MULSAQ_S_W_PH = (0x06 << 6) | OPC_DPA_W_PH_DSP, + OPC_DPAQ_SA_L_W = (0x0C << 6) | OPC_DPA_W_PH_DSP, + OPC_DPSQ_SA_L_W = (0x0D << 6) | OPC_DPA_W_PH_DSP, + OPC_MAQ_S_W_PHL = (0x14 << 6) | OPC_DPA_W_PH_DSP, + OPC_MAQ_S_W_PHR = (0x16 << 6) | OPC_DPA_W_PH_DSP, + OPC_MAQ_SA_W_PHL = (0x10 << 6) | OPC_DPA_W_PH_DSP, + OPC_MAQ_SA_W_PHR = (0x12 << 6) | OPC_DPA_W_PH_DSP, + OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP, +}; + #if defined(TARGET_MIPS64) #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { @@ -505,6 +545,12 @@ enum { #if defined(TARGET_MIPS64) #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { + /* MIPS DSP Multiply Sub-class insns */ + OPC_MULEQ_S_PW_QHL = (0x1C << 6) | OPC_ADDU_OB_DSP, + OPC_MULEQ_S_PW_QHR = (0x1D << 6) | OPC_ADDU_OB_DSP, + OPC_MULEU_S_QH_OBL = (0x06 << 6) | OPC_ADDU_OB_DSP, + OPC_MULEU_S_QH_OBR = (0x07 << 6) | OPC_ADDU_OB_DSP, + OPC_MULQ_RS_QH = (0x1F << 6) | OPC_ADDU_OB_DSP, /* MIPS DSP Arithmetic Sub-class */ OPC_RADDU_L_OB = (0x14 << 6) | OPC_ADDU_OB_DSP, OPC_SUBQ_PW = (0x13 << 6) | OPC_ADDU_OB_DSP, @@ -545,6 +591,39 @@ enum { }; #endif +#if defined(TARGET_MIPS64) +#define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Multiply Sub-class insns */ + OPC_DMADD = (0x19 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DMADDU = (0x1D << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DMSUB = (0x1B << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DMSUBU = (0x1F << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DPA_W_QH = (0x00 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DPAQ_S_W_QH = (0x04 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DPAQ_SA_L_PW = (0x0C << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DPAU_H_OBL = (0x03 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DPAU_H_OBR = (0x07 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DPS_W_QH = (0x01 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DPSQ_S_W_QH = (0x05 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DPSQ_SA_L_PW = (0x0D << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DPSU_H_OBL = (0x0B << 6) | OPC_DPAQ_W_QH_DSP, + OPC_DPSU_H_OBR = (0x0F << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MAQ_S_L_PWL = (0x1C << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MAQ_S_L_PWR = (0x1E << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MAQ_S_W_QHLL = (0x14 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MAQ_SA_W_QHLL = (0x10 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MAQ_S_W_QHLR = (0x15 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MAQ_SA_W_QHLR = (0x11 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MAQ_S_W_QHRL = (0x16 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MAQ_SA_W_QHRL = (0x12 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MAQ_S_W_QHRR = (0x17 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MAQ_SA_W_QHRR = (0x13 << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP, + OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP, +}; +#endif + #if defined(TARGET_MIPS64) #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { @@ -13212,6 +13291,319 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, MIPS_DEBUG("%s", opn); } +static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, + int ret, int v1, int v2, int check_ret) +{ + const char *opn = "mipsdsp multiply"; + TCGv_i32 t0; + TCGv v1_t; + TCGv v2_t; + + if ((ret == 0) && (check_ret == 1)) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new_i32(); + v1_t = tcg_temp_new(); + v2_t = tcg_temp_new(); + + tcg_gen_movi_i32(t0, ret); + gen_load_gpr(v1_t, v1); + gen_load_gpr(v2_t, v2); + + switch (op1) { + /* OPC_MULT_G_2E, OPC_ADDUH_QB_DSP, OPC_MUL_PH_DSP have + * the same mask and op1. */ + case OPC_MULT_G_2E: + switch (op2) { + case OPC_MUL_PH: + gen_helper_mul_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MUL_S_PH: + gen_helper_mul_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULQ_S_W: + gen_helper_mulq_s_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULQ_RS_W: + gen_helper_mulq_rs_w(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; + case OPC_DPA_W_PH_DSP: + switch (op2) { + case OPC_DPAU_H_QBL: + check_dsp(ctx); + gen_helper_dpau_h_qbl(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPAU_H_QBR: + check_dsp(ctx); + gen_helper_dpau_h_qbr(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPSU_H_QBL: + check_dsp(ctx); + gen_helper_dpsu_h_qbl(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPSU_H_QBR: + check_dsp(ctx); + gen_helper_dpsu_h_qbr(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPA_W_PH: + check_dspr2(ctx); + gen_helper_dpa_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPAX_W_PH: + check_dspr2(ctx); + gen_helper_dpax_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPAQ_S_W_PH: + check_dsp(ctx); + gen_helper_dpaq_s_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPAQX_S_W_PH: + check_dspr2(ctx); + gen_helper_dpaqx_s_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPAQX_SA_W_PH: + check_dspr2(ctx); + gen_helper_dpaqx_sa_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPS_W_PH: + check_dspr2(ctx); + gen_helper_dps_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPSX_W_PH: + check_dspr2(ctx); + gen_helper_dpsx_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPSQ_S_W_PH: + check_dsp(ctx); + gen_helper_dpsq_s_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPSQX_S_W_PH: + check_dspr2(ctx); + gen_helper_dpsqx_s_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPSQX_SA_W_PH: + check_dspr2(ctx); + gen_helper_dpsqx_sa_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_MULSAQ_S_W_PH: + check_dsp(ctx); + gen_helper_mulsaq_s_w_ph(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPAQ_SA_L_W: + check_dsp(ctx); + gen_helper_dpaq_sa_l_w(t0, v1_t, v2_t, cpu_env); + break; + case OPC_DPSQ_SA_L_W: + check_dsp(ctx); + gen_helper_dpsq_sa_l_w(t0, v1_t, v2_t, cpu_env); + break; + case OPC_MAQ_S_W_PHL: + check_dsp(ctx); + gen_helper_maq_s_w_phl(t0, v1_t, v2_t, cpu_env); + break; + case OPC_MAQ_S_W_PHR: + check_dsp(ctx); + gen_helper_maq_s_w_phr(t0, v1_t, v2_t, cpu_env); + break; + case OPC_MAQ_SA_W_PHL: + check_dsp(ctx); + gen_helper_maq_sa_w_phl(t0, v1_t, v2_t, cpu_env); + break; + case OPC_MAQ_SA_W_PHR: + check_dsp(ctx); + gen_helper_maq_sa_w_phr(t0, v1_t, v2_t, cpu_env); + break; + case OPC_MULSA_W_PH: + check_dspr2(ctx); + gen_helper_mulsa_w_ph(t0, v1_t, v2_t, cpu_env); + break; + } + break; +#ifdef TARGET_MIPS64 + case OPC_DPAQ_W_QH_DSP: + { + int ac = ret & 0x03; + tcg_gen_movi_i32(t0, ac); + + switch (op2) { + case OPC_DMADD: + check_dsp(ctx); + gen_helper_dmadd(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DMADDU: + check_dsp(ctx); + gen_helper_dmaddu(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DMSUB: + check_dsp(ctx); + gen_helper_dmsub(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DMSUBU: + check_dsp(ctx); + gen_helper_dmsubu(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DPA_W_QH: + check_dspr2(ctx); + gen_helper_dpa_w_qh(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DPAQ_S_W_QH: + check_dsp(ctx); + gen_helper_dpaq_s_w_qh(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DPAQ_SA_L_PW: + check_dsp(ctx); + gen_helper_dpaq_sa_l_pw(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DPAU_H_OBL: + check_dsp(ctx); + gen_helper_dpau_h_obl(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DPAU_H_OBR: + check_dsp(ctx); + gen_helper_dpau_h_obr(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DPS_W_QH: + check_dspr2(ctx); + gen_helper_dps_w_qh(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DPSQ_S_W_QH: + check_dsp(ctx); + gen_helper_dpsq_s_w_qh(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DPSQ_SA_L_PW: + check_dsp(ctx); + gen_helper_dpsq_sa_l_pw(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DPSU_H_OBL: + check_dsp(ctx); + gen_helper_dpsu_h_obl(v1_t, v2_t, t0, cpu_env); + break; + case OPC_DPSU_H_OBR: + check_dsp(ctx); + gen_helper_dpsu_h_obr(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MAQ_S_L_PWL: + check_dsp(ctx); + gen_helper_maq_s_l_pwl(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MAQ_S_L_PWR: + check_dsp(ctx); + gen_helper_maq_s_l_pwr(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MAQ_S_W_QHLL: + check_dsp(ctx); + gen_helper_maq_s_w_qhll(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MAQ_SA_W_QHLL: + check_dsp(ctx); + gen_helper_maq_sa_w_qhll(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MAQ_S_W_QHLR: + check_dsp(ctx); + gen_helper_maq_s_w_qhlr(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MAQ_SA_W_QHLR: + check_dsp(ctx); + gen_helper_maq_sa_w_qhlr(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MAQ_S_W_QHRL: + check_dsp(ctx); + gen_helper_maq_s_w_qhrl(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MAQ_SA_W_QHRL: + check_dsp(ctx); + gen_helper_maq_sa_w_qhrl(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MAQ_S_W_QHRR: + check_dsp(ctx); + gen_helper_maq_s_w_qhrr(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MAQ_SA_W_QHRR: + check_dsp(ctx); + gen_helper_maq_sa_w_qhrr(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MULSAQ_S_L_PW: + check_dsp(ctx); + gen_helper_mulsaq_s_l_pw(v1_t, v2_t, t0, cpu_env); + break; + case OPC_MULSAQ_S_W_QH: + check_dsp(ctx); + gen_helper_mulsaq_s_w_qh(v1_t, v2_t, t0, cpu_env); + break; + } + } + break; +#endif + case OPC_ADDU_QB_DSP: + switch (op2) { + case OPC_MULEU_S_PH_QBL: + check_dsp(ctx); + gen_helper_muleu_s_ph_qbl(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULEU_S_PH_QBR: + check_dsp(ctx); + gen_helper_muleu_s_ph_qbr(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULQ_RS_PH: + check_dsp(ctx); + gen_helper_mulq_rs_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULEQ_S_W_PHL: + check_dsp(ctx); + gen_helper_muleq_s_w_phl(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULEQ_S_W_PHR: + check_dsp(ctx); + gen_helper_muleq_s_w_phr(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULQ_S_PH: + check_dspr2(ctx); + gen_helper_mulq_s_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; +#ifdef TARGET_MIPS64 + case OPC_ADDU_OB_DSP: + switch (op2) { + case OPC_MULEQ_S_PW_QHL: + check_dsp(ctx); + gen_helper_muleq_s_pw_qhl(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULEQ_S_PW_QHR: + check_dsp(ctx); + gen_helper_muleq_s_pw_qhr(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULEU_S_QH_OBL: + check_dsp(ctx); + gen_helper_muleu_s_qh_obl(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULEU_S_QH_OBR: + check_dsp(ctx); + gen_helper_muleu_s_qh_obr(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_MULQ_RS_QH: + check_dsp(ctx); + gen_helper_mulq_rs_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; +#endif + } + + tcg_temp_free_i32(t0); + tcg_temp_free(v1_t); + tcg_temp_free(v2_t); + + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s", opn); + +} + /* End MIPSDSP functions. */ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) @@ -13586,6 +13978,12 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_SUBQH_R_W: gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); break; + case OPC_MUL_PH: + case OPC_MUL_S_PH: + case OPC_MULQ_S_W: + case OPC_MULQ_RS_W: + gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); + break; default: MIPS_INVAL("MASK ADDUH.QB"); generate_exception(ctx, EXCP_RI); @@ -13661,6 +14059,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_RADDU_W_QB: gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); break; + case OPC_MULEU_S_PH_QBL: + case OPC_MULEU_S_PH_QBR: + case OPC_MULQ_RS_PH: + case OPC_MULEQ_S_W_PHL: + case OPC_MULEQ_S_W_PHR: + case OPC_MULQ_S_PH: + gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); + break; default: /* Invalid */ MIPS_INVAL("MASK ADDU.QB"); generate_exception(ctx, EXCP_RI); @@ -13691,6 +14097,39 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_SHLL_QB_DSP: gen_mipsdsp_shift(ctx, op1, rd, rs, rt); break; + case OPC_DPA_W_PH_DSP: + op2 = MASK_DPA_W_PH(ctx->opcode); + switch (op2) { + case OPC_DPAU_H_QBL: + case OPC_DPAU_H_QBR: + case OPC_DPSU_H_QBL: + case OPC_DPSU_H_QBR: + case OPC_DPA_W_PH: + case OPC_DPAX_W_PH: + case OPC_DPAQ_S_W_PH: + case OPC_DPAQX_S_W_PH: + case OPC_DPAQX_SA_W_PH: + case OPC_DPS_W_PH: + case OPC_DPSX_W_PH: + case OPC_DPSQ_S_W_PH: + case OPC_DPSQX_S_W_PH: + case OPC_DPSQX_SA_W_PH: + case OPC_MULSAQ_S_W_PH: + case OPC_DPAQ_SA_L_W: + case OPC_DPSQ_SA_L_W: + case OPC_MAQ_S_W_PHL: + case OPC_MAQ_S_W_PHR: + case OPC_MAQ_SA_W_PHL: + case OPC_MAQ_SA_W_PHR: + case OPC_MULSA_W_PH: + gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); + break; + default: /* Invalid */ + MIPS_INVAL("MASK DPAW.PH"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: @@ -13764,6 +14203,13 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_ADDUH_R_OB: gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); break; + case OPC_MULEQ_S_PW_QHL: + case OPC_MULEQ_S_PW_QHR: + case OPC_MULEU_S_QH_OBL: + case OPC_MULEU_S_QH_OBR: + case OPC_MULQ_RS_QH: + gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 1); + break; default: /* Invalid */ MIPS_INVAL("MASK ADDU.OB"); generate_exception(ctx, EXCP_RI); @@ -13792,6 +14238,45 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; } break; + case OPC_DPAQ_W_QH_DSP: + op2 = MASK_DPAQ_W_QH(ctx->opcode); + switch (op2) { + case OPC_DPAU_H_OBL: + case OPC_DPAU_H_OBR: + case OPC_DPSU_H_OBL: + case OPC_DPSU_H_OBR: + case OPC_DPA_W_QH: + case OPC_DPAQ_S_W_QH: + case OPC_DPS_W_QH: + case OPC_DPSQ_S_W_QH: + case OPC_MULSAQ_S_W_QH: + case OPC_DPAQ_SA_L_PW: + case OPC_DPSQ_SA_L_PW: + case OPC_MULSAQ_S_L_PW: + gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); + break; + case OPC_MAQ_S_W_QHLL: + case OPC_MAQ_S_W_QHLR: + case OPC_MAQ_S_W_QHRL: + case OPC_MAQ_S_W_QHRR: + case OPC_MAQ_SA_W_QHLL: + case OPC_MAQ_SA_W_QHLR: + case OPC_MAQ_SA_W_QHRL: + case OPC_MAQ_SA_W_QHRR: + case OPC_MAQ_S_L_PWL: + case OPC_MAQ_S_L_PWR: + case OPC_DMADD: + case OPC_DMADDU: + case OPC_DMSUB: + case OPC_DMSUBU: + gen_mipsdsp_multiply(ctx, op1, op2, rd, rs, rt, 0); + break; + default: /* Invalid */ + MIPS_INVAL("MASK DPAQ.W.QH"); + generate_exception(ctx, EXCP_RI); + break; + } + break; case OPC_SHLL_OB_DSP: gen_mipsdsp_shift(ctx, op1, rd, rs, rt); break; From 1cb6686cf926e0efc2056405a0a76dd41eb65d89 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:09 +0800 Subject: [PATCH 139/291] target-mips: Add ASE DSP bit/manipulation instructions Add MIPS ASE DSP Bit/Manipulation instructions. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 55 +++++++++ target-mips/helper.h | 7 ++ target-mips/translate.c | 249 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 311 insertions(+) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 86c27ec0e8..919ff299f6 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3112,6 +3112,61 @@ DM_OPERATE(dmsubu, mul_u32_u32, 0, 0); #undef DM_OPERATE #endif +/** DSP Bit/Manipulation Sub-class insns **/ +target_ulong helper_bitrev(target_ulong rt) +{ + int32_t temp; + uint32_t rd; + int i; + + temp = rt & MIPSDSP_LO; + rd = 0; + for (i = 0; i < 16; i++) { + rd = (rd << 1) | (temp & 1); + temp = temp >> 1; + } + + return (target_ulong)rd; +} + +#define BIT_INSV(name, posfilter, sizefilter, ret_type) \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \ + target_ulong rt) \ +{ \ + uint32_t pos, size, msb, lsb; \ + target_ulong filter; \ + target_ulong temp, temprs, temprt; \ + target_ulong dspc; \ + \ + dspc = env->active_tc.DSPControl; \ + \ + pos = dspc & posfilter; \ + size = (dspc >> 7) & sizefilter; \ + \ + msb = pos + size - 1; \ + lsb = pos; \ + \ + if (lsb > msb || (msb > TARGET_LONG_BITS)) { \ + return rt; \ + } \ + \ + filter = ((int32_t)0x01 << size) - 1; \ + filter = filter << pos; \ + temprs = rs & filter; \ + temprt = rt & ~filter; \ + temp = temprs | temprt; \ + \ + return (target_long)(ret_type)temp; \ +} + +BIT_INSV(insv, 0x1F, 0x1F, int32_t); +#ifdef TARGET_MIPS64 +BIT_INSV(dinsv, 0x7F, 0x3F, target_long); +#endif + +#undef BIT_INSV + + #undef MIPSDSP_LHI #undef MIPSDSP_LLO #undef MIPSDSP_HI diff --git a/target-mips/helper.h b/target-mips/helper.h index 139bb1e464..5380adbdb6 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -617,4 +617,11 @@ DEF_HELPER_FLAGS_4(dmsub, 0, void, tl, tl, i32, env) DEF_HELPER_FLAGS_4(dmsubu, 0, void, tl, tl, i32, env) #endif +/* DSP Bit/Manipulation Sub-class insns */ +DEF_HELPER_FLAGS_1(bitrev, TCG_CALL_NO_RWG_SE, tl, tl) +DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl); +#endif + #include "def-helper.h" diff --git a/target-mips/translate.c b/target-mips/translate.c index 5d374c4c37..0947007c99 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -342,6 +342,11 @@ enum { OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3, #if defined(TARGET_MIPS64) OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3, +#endif + /* DSP Bit/Manipulation Sub-class */ + OPC_INSV_DSP = 0x0C | OPC_SPECIAL3, +#if defined(TARGET_MIPS64) + OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3, #endif }; @@ -450,6 +455,12 @@ enum { OPC_PRECEU_PH_QBR = (0x1D << 6) | OPC_ABSQ_S_PH_DSP, OPC_PRECEU_PH_QBLA = (0x1E << 6) | OPC_ABSQ_S_PH_DSP, OPC_PRECEU_PH_QBRA = (0x1F << 6) | OPC_ABSQ_S_PH_DSP, + /* DSP Bit/Manipulation Sub-class */ + OPC_BITREV = (0x1B << 6) | OPC_ABSQ_S_PH_DSP, + OPC_REPL_QB = (0x02 << 6) | OPC_ABSQ_S_PH_DSP, + OPC_REPLV_QB = (0x03 << 6) | OPC_ABSQ_S_PH_DSP, + OPC_REPL_PH = (0x0A << 6) | OPC_ABSQ_S_PH_DSP, + OPC_REPLV_PH = (0x0B << 6) | OPC_ABSQ_S_PH_DSP, }; #define MASK_CMPU_EQ_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) @@ -518,6 +529,12 @@ enum { OPC_MULSA_W_PH = (0x02 << 6) | OPC_DPA_W_PH_DSP, }; +#define MASK_INSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* DSP Bit/Manipulation Sub-class */ + OPC_INSV = (0x00 << 6) | OPC_INSV_DSP, +}; + #if defined(TARGET_MIPS64) #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { @@ -539,6 +556,13 @@ enum { OPC_ABSQ_S_OB = (0x01 << 6) | OPC_ABSQ_S_QH_DSP, OPC_ABSQ_S_PW = (0x11 << 6) | OPC_ABSQ_S_QH_DSP, OPC_ABSQ_S_QH = (0x09 << 6) | OPC_ABSQ_S_QH_DSP, + /* DSP Bit/Manipulation Sub-class */ + OPC_REPL_OB = (0x02 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_REPL_PW = (0x12 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_REPL_QH = (0x0A << 6) | OPC_ABSQ_S_QH_DSP, + OPC_REPLV_OB = (0x03 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP, + OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP, }; #endif @@ -591,6 +615,14 @@ enum { }; #endif +#if defined(TARGET_MIPS64) +#define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* DSP Bit/Manipulation Sub-class */ + OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP, +}; +#endif + #if defined(TARGET_MIPS64) #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { @@ -13604,6 +13636,149 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, } +static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx, + uint32_t op1, uint32_t op2, + int ret, int val) +{ + const char *opn = "mipsdsp Bit/ Manipulation"; + int16_t imm; + TCGv t0; + TCGv val_t; + + if (ret == 0) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + val_t = tcg_temp_new(); + gen_load_gpr(val_t, val); + + switch (op1) { + case OPC_ABSQ_S_PH_DSP: + switch (op2) { + case OPC_BITREV: + check_dsp(ctx); + gen_helper_bitrev(cpu_gpr[ret], val_t); + break; + case OPC_REPL_QB: + check_dsp(ctx); + { + target_long result; + imm = (ctx->opcode >> 16) & 0xFF; + result = (uint32_t)imm << 24 | + (uint32_t)imm << 16 | + (uint32_t)imm << 8 | + (uint32_t)imm; + result = (int32_t)result; + tcg_gen_movi_tl(cpu_gpr[ret], result); + } + break; + case OPC_REPLV_QB: + check_dsp(ctx); + tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); + break; + case OPC_REPL_PH: + check_dsp(ctx); + { + imm = (ctx->opcode >> 16) & 0x03FF; + tcg_gen_movi_tl(cpu_gpr[ret], \ + (target_long)((int32_t)imm << 16 | \ + (uint32_t)(uint16_t)imm)); + } + break; + case OPC_REPLV_PH: + check_dsp(ctx); + tcg_gen_ext16u_tl(cpu_gpr[ret], val_t); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + tcg_gen_ext32s_tl(cpu_gpr[ret], cpu_gpr[ret]); + break; + } + break; +#ifdef TARGET_MIPS64 + case OPC_ABSQ_S_QH_DSP: + switch (op2) { + case OPC_REPL_OB: + check_dsp(ctx); + { + target_long temp; + + imm = (ctx->opcode >> 16) & 0xFF; + temp = ((uint64_t)imm << 8) | (uint64_t)imm; + temp = (temp << 16) | temp; + temp = (temp << 32) | temp; + tcg_gen_movi_tl(cpu_gpr[ret], temp); + break; + } + case OPC_REPL_PW: + check_dsp(ctx); + { + target_long temp; + + imm = (ctx->opcode >> 16) & 0x03FF; + imm = (int16_t)(imm << 6) >> 6; + temp = ((target_long)imm << 32) \ + | ((target_long)imm & 0xFFFFFFFF); + tcg_gen_movi_tl(cpu_gpr[ret], temp); + break; + } + case OPC_REPL_QH: + check_dsp(ctx); + { + target_long temp; + + imm = (ctx->opcode >> 16) & 0x03FF; + imm = (int16_t)(imm << 6) >> 6; + + temp = ((uint64_t)(uint16_t)imm << 48) | + ((uint64_t)(uint16_t)imm << 32) | + ((uint64_t)(uint16_t)imm << 16) | + (uint64_t)(uint16_t)imm; + tcg_gen_movi_tl(cpu_gpr[ret], temp); + break; + } + case OPC_REPLV_OB: + check_dsp(ctx); + tcg_gen_ext8u_tl(cpu_gpr[ret], val_t); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 8); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + break; + case OPC_REPLV_PW: + check_dsp(ctx); + tcg_gen_ext32u_i64(cpu_gpr[ret], val_t); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + break; + case OPC_REPLV_QH: + check_dsp(ctx); + tcg_gen_ext16u_tl(cpu_gpr[ret], val_t); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 16); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + tcg_gen_shli_tl(t0, cpu_gpr[ret], 32); + tcg_gen_or_tl(cpu_gpr[ret], cpu_gpr[ret], t0); + break; + } + break; +#endif + } + tcg_temp_free(t0); + tcg_temp_free(val_t); + + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s", opn); +} + /* End MIPSDSP functions. */ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) @@ -14030,6 +14205,13 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_PRECEU_PH_QBRA: gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); break; + case OPC_BITREV: + case OPC_REPL_QB: + case OPC_REPLV_QB: + case OPC_REPL_PH: + case OPC_REPLV_PH: + gen_mipsdsp_bitinsn(env, ctx, op1, op2, rd, rt); + break; default: MIPS_INVAL("MASK ABSQ_S.PH"); generate_exception(ctx, EXCP_RI); @@ -14130,6 +14312,37 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; } break; + case OPC_INSV_DSP: + op2 = MASK_INSV(ctx->opcode); + switch (op2) { + case OPC_INSV: + check_dsp(ctx); + { + TCGv t0, t1; + + if (rt == 0) { + MIPS_DEBUG("NOP"); + break; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + + gen_helper_insv(cpu_gpr[rt], cpu_env, t1, t0); + + tcg_temp_free(t0); + tcg_temp_free(t1); + break; + } + default: /* Invalid */ + MIPS_INVAL("MASK INSV"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: @@ -14171,6 +14384,14 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_ABSQ_S_QH: gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); break; + case OPC_REPL_OB: + case OPC_REPL_PW: + case OPC_REPL_QH: + case OPC_REPLV_OB: + case OPC_REPLV_PW: + case OPC_REPLV_QH: + gen_mipsdsp_bitinsn(env, ctx, op1, op2, rd, rt); + break; default: /* Invalid */ MIPS_INVAL("MASK ABSQ_S.QH"); generate_exception(ctx, EXCP_RI); @@ -14277,6 +14498,34 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; } break; + case OPC_DINSV_DSP: + op2 = MASK_INSV(ctx->opcode); + switch (op2) { + case OPC_DINSV: + { + TCGv t0, t1; + + if (rt == 0) { + MIPS_DEBUG("NOP"); + break; + } + check_dsp(ctx); + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + gen_load_gpr(t0, rt); + gen_load_gpr(t1, rs); + + gen_helper_dinsv(cpu_gpr[rt], cpu_env, t1, t0); + break; + } + default: /* Invalid */ + MIPS_INVAL("MASK DINSV"); + generate_exception(ctx, EXCP_RI); + break; + } + break; case OPC_SHLL_OB_DSP: gen_mipsdsp_shift(ctx, op1, rd, rs, rt); break; From 266905602401e4aa849372bc50a71b2987157727 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:10 +0800 Subject: [PATCH 140/291] target-mips: Add ASE DSP compare-pick instructions Add MIPS ASE DSP Compare-Pick instructions. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 233 ++++++++++++++++++++++++++ target-mips/helper.h | 52 ++++++ target-mips/translate.c | 350 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 635 insertions(+) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index 919ff299f6..fcdc1bbcb9 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3167,6 +3167,239 @@ BIT_INSV(dinsv, 0x7F, 0x3F, target_long); #undef BIT_INSV +/** DSP Compare-Pick Sub-class insns **/ +#define CMP_HAS_RET(name, func, split_num, filter, bit_size) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt) \ +{ \ + uint32_t rs_t, rt_t; \ + uint8_t cc; \ + uint32_t temp = 0; \ + int i; \ + \ + for (i = 0; i < split_num; i++) { \ + rs_t = (rs >> (bit_size * i)) & filter; \ + rt_t = (rt >> (bit_size * i)) & filter; \ + cc = mipsdsp_##func(rs_t, rt_t); \ + temp |= cc << i; \ + } \ + \ + return (target_ulong)temp; \ +} + +CMP_HAS_RET(cmpgu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8); +CMP_HAS_RET(cmpgu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8); +CMP_HAS_RET(cmpgu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8); + +#ifdef TARGET_MIPS64 +CMP_HAS_RET(cmpgu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8); +CMP_HAS_RET(cmpgu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8); +CMP_HAS_RET(cmpgu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8); +#endif + +#undef CMP_HAS_RET + + +#define CMP_NO_RET(name, func, split_num, filter, bit_size) \ +void helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int##bit_size##_t rs_t, rt_t; \ + int##bit_size##_t flag = 0; \ + int##bit_size##_t cc; \ + int i; \ + \ + for (i = 0; i < split_num; i++) { \ + rs_t = (rs >> (bit_size * i)) & filter; \ + rt_t = (rt >> (bit_size * i)) & filter; \ + \ + cc = mipsdsp_##func((int32_t)rs_t, (int32_t)rt_t); \ + flag |= cc << i; \ + } \ + \ + set_DSPControl_24(flag, split_num, env); \ +} + +CMP_NO_RET(cmpu_eq_qb, cmpu_eq, 4, MIPSDSP_Q0, 8); +CMP_NO_RET(cmpu_lt_qb, cmpu_lt, 4, MIPSDSP_Q0, 8); +CMP_NO_RET(cmpu_le_qb, cmpu_le, 4, MIPSDSP_Q0, 8); + +CMP_NO_RET(cmp_eq_ph, cmp_eq, 2, MIPSDSP_LO, 16); +CMP_NO_RET(cmp_lt_ph, cmp_lt, 2, MIPSDSP_LO, 16); +CMP_NO_RET(cmp_le_ph, cmp_le, 2, MIPSDSP_LO, 16); + +#ifdef TARGET_MIPS64 +CMP_NO_RET(cmpu_eq_ob, cmpu_eq, 8, MIPSDSP_Q0, 8); +CMP_NO_RET(cmpu_lt_ob, cmpu_lt, 8, MIPSDSP_Q0, 8); +CMP_NO_RET(cmpu_le_ob, cmpu_le, 8, MIPSDSP_Q0, 8); + +CMP_NO_RET(cmp_eq_qh, cmp_eq, 4, MIPSDSP_LO, 16); +CMP_NO_RET(cmp_lt_qh, cmp_lt, 4, MIPSDSP_LO, 16); +CMP_NO_RET(cmp_le_qh, cmp_le, 4, MIPSDSP_LO, 16); + +CMP_NO_RET(cmp_eq_pw, cmp_eq, 2, MIPSDSP_LLO, 32); +CMP_NO_RET(cmp_lt_pw, cmp_lt, 2, MIPSDSP_LLO, 32); +CMP_NO_RET(cmp_le_pw, cmp_le, 2, MIPSDSP_LLO, 32); +#endif +#undef CMP_NO_RET + +#if defined(TARGET_MIPS64) + +#define CMPGDU_OB(name) \ +target_ulong helper_cmpgdu_##name##_ob(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + int i; \ + uint8_t rs_t, rt_t; \ + uint32_t cond; \ + \ + cond = 0; \ + \ + for (i = 0; i < 8; i++) { \ + rs_t = (rs >> (8 * i)) & MIPSDSP_Q0; \ + rt_t = (rt >> (8 * i)) & MIPSDSP_Q0; \ + \ + if (mipsdsp_cmpu_##name(rs_t, rt_t)) { \ + cond |= 0x01 << i; \ + } \ + } \ + \ + set_DSPControl_24(cond, 8, env); \ + \ + return (uint64_t)cond; \ +} + +CMPGDU_OB(eq) +CMPGDU_OB(lt) +CMPGDU_OB(le) +#undef CMPGDU_OB +#endif + +#define PICK_INSN(name, split_num, filter, bit_size, ret32bit) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + CPUMIPSState *env) \ +{ \ + uint32_t rs_t, rt_t; \ + uint32_t cc; \ + target_ulong dsp; \ + int i; \ + target_ulong result = 0; \ + \ + dsp = env->active_tc.DSPControl; \ + for (i = 0; i < split_num; i++) { \ + rs_t = (rs >> (bit_size * i)) & filter; \ + rt_t = (rt >> (bit_size * i)) & filter; \ + cc = (dsp >> (24 + i)) & 0x01; \ + cc = cc == 1 ? rs_t : rt_t; \ + \ + result |= (target_ulong)cc << (bit_size * i); \ + } \ + \ + if (ret32bit) { \ + result = (target_long)(int32_t)(result & MIPSDSP_LLO); \ + } \ + \ + return result; \ +} + +PICK_INSN(pick_qb, 4, MIPSDSP_Q0, 8, 1); +PICK_INSN(pick_ph, 2, MIPSDSP_LO, 16, 1); + +#ifdef TARGET_MIPS64 +PICK_INSN(pick_ob, 8, MIPSDSP_Q0, 8, 0); +PICK_INSN(pick_qh, 4, MIPSDSP_LO, 16, 0); +PICK_INSN(pick_pw, 2, MIPSDSP_LLO, 32, 0); +#endif +#undef PICK_INSN + +#define APPEND_INSN(name, ret_32) \ +target_ulong helper_##name(target_ulong rt, target_ulong rs, uint32_t sa) \ +{ \ + target_ulong temp; \ + \ + if (ret_32) { \ + temp = ((rt & MIPSDSP_LLO) << sa) | \ + ((rs & MIPSDSP_LLO) & ((0x01 << sa) - 1)); \ + temp = (target_long)(int32_t)(temp & MIPSDSP_LLO); \ + } else { \ + temp = (rt << sa) | (rs & ((0x01 << sa) - 1)); \ + } \ + \ + return temp; \ +} + +APPEND_INSN(append, 1); +#ifdef TARGET_MIPS64 +APPEND_INSN(dappend, 0); +#endif +#undef APPEND_INSN + +#define PREPEND_INSN(name, or_val, ret_32) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, \ + uint32_t sa) \ +{ \ + sa |= or_val; \ + \ + if (1) { \ + return (target_long)(int32_t)(uint32_t) \ + (((rs & MIPSDSP_LLO) << (32 - sa)) | \ + ((rt & MIPSDSP_LLO) >> sa)); \ + } else { \ + return (rs << (64 - sa)) | (rt >> sa); \ + } \ +} + +PREPEND_INSN(prepend, 0, 1); +#ifdef TARGET_MIPS64 +PREPEND_INSN(prependw, 0, 0); +PREPEND_INSN(prependd, 0x20, 0); +#endif +#undef PREPEND_INSN + +#define BALIGN_INSN(name, filter, ret32) \ +target_ulong helper_##name(target_ulong rs, target_ulong rt, uint32_t bp) \ +{ \ + bp = bp & 0x03; \ + \ + if ((bp & 1) == 0) { \ + return rt; \ + } else { \ + if (ret32) { \ + return (target_long)(int32_t)((rt << (8 * bp)) | \ + (rs >> (8 * (4 - bp)))); \ + } else { \ + return (rt << (8 * bp)) | (rs >> (8 * (8 - bp))); \ + } \ + } \ +} + +BALIGN_INSN(balign, 0x03, 1); +#if defined(TARGET_MIPS64) +BALIGN_INSN(dbalign, 0x07, 0); +#endif +#undef BALIGN_INSN + +target_ulong helper_packrl_ph(target_ulong rs, target_ulong rt) +{ + uint32_t rsl, rth; + + rsl = rs & MIPSDSP_LO; + rth = (rt & MIPSDSP_HI) >> 16; + + return (target_long)(int32_t)((rsl << 16) | rth); +} + +#if defined(TARGET_MIPS64) +target_ulong helper_packrl_pw(target_ulong rs, target_ulong rt) +{ + uint32_t rs0, rt1; + + rs0 = rs & MIPSDSP_LLO; + rt1 = (rt >> 32) & MIPSDSP_LLO; + + return ((uint64_t)rs0 << 32) | (uint64_t)rt1; +} +#endif + #undef MIPSDSP_LHI #undef MIPSDSP_LLO #undef MIPSDSP_HI diff --git a/target-mips/helper.h b/target-mips/helper.h index 5380adbdb6..a821326b26 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -624,4 +624,56 @@ DEF_HELPER_FLAGS_3(insv, 0, tl, env, tl, tl) DEF_HELPER_FLAGS_3(dinsv, 0, tl, env, tl, tl); #endif +/* DSP Compare-Pick Sub-class insns */ +DEF_HELPER_FLAGS_3(cmpu_eq_qb, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_lt_qb, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_le_qb, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_2(cmpgu_eq_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_lt_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_le_qb, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(cmp_eq_ph, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_lt_ph, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_le_ph, 0, void, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(cmpu_eq_ob, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_lt_ob, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpu_le_ob, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpgdu_eq_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpgdu_lt_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(cmpgdu_le_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_2(cmpgu_eq_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_lt_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_2(cmpgu_le_ob, TCG_CALL_NO_RWG_SE, tl, tl, tl) +DEF_HELPER_FLAGS_3(cmp_eq_qh, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_lt_qh, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_le_qh, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_eq_pw, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_lt_pw, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_3(cmp_le_pw, 0, void, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(pick_qb, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(pick_ph, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(pick_ob, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(pick_qh, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(pick_pw, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(append, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dappend, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +#endif +DEF_HELPER_FLAGS_3(prepend, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(prependd, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +DEF_HELPER_FLAGS_3(prependw, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +#endif +DEF_HELPER_FLAGS_3(balign, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dbalign, TCG_CALL_NO_RWG_SE, tl, tl, tl, i32) +#endif +DEF_HELPER_FLAGS_2(packrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_2(packrl_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) +#endif + #include "def-helper.h" diff --git a/target-mips/translate.c b/target-mips/translate.c index 0947007c99..69ef90a5aa 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -347,6 +347,11 @@ enum { OPC_INSV_DSP = 0x0C | OPC_SPECIAL3, #if defined(TARGET_MIPS64) OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3, +#endif + /* MIPS DSP Compare-Pick Sub-class */ + OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3, +#if defined(TARGET_MIPS64) + OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3, #endif }; @@ -473,6 +478,22 @@ enum { OPC_PRECRQ_PH_W = (0x14 << 6) | OPC_CMPU_EQ_QB_DSP, OPC_PRECRQ_RS_PH_W = (0x15 << 6) | OPC_CMPU_EQ_QB_DSP, OPC_PRECRQU_S_QB_PH = (0x0F << 6) | OPC_CMPU_EQ_QB_DSP, + /* DSP Compare-Pick Sub-class */ + OPC_CMPU_EQ_QB = (0x00 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPU_LT_QB = (0x01 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPU_LE_QB = (0x02 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGU_EQ_QB = (0x04 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGU_LT_QB = (0x05 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGU_LE_QB = (0x06 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGDU_EQ_QB = (0x18 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGDU_LT_QB = (0x19 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMPGDU_LE_QB = (0x1A << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMP_EQ_PH = (0x08 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMP_LT_PH = (0x09 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_CMP_LE_PH = (0x0A << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PICK_QB = (0x03 << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PICK_PH = (0x0B << 6) | OPC_CMPU_EQ_QB_DSP, + OPC_PACKRL_PH = (0x0E << 6) | OPC_CMPU_EQ_QB_DSP, }; #define MASK_SHLL_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) @@ -535,6 +556,14 @@ enum { OPC_INSV = (0x00 << 6) | OPC_INSV_DSP, }; +#define MASK_APPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Compare-Pick Sub-class */ + OPC_APPEND = (0x00 << 6) | OPC_APPEND_DSP, + OPC_PREPEND = (0x01 << 6) | OPC_APPEND_DSP, + OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP, +}; + #if defined(TARGET_MIPS64) #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { @@ -603,6 +632,26 @@ enum { #if defined(TARGET_MIPS64) #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { + /* DSP Compare-Pick Sub-class */ + OPC_CMP_EQ_PW = (0x10 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMP_LT_PW = (0x11 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMP_LE_PW = (0x12 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMP_EQ_QH = (0x08 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMP_LT_QH = (0x09 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMP_LE_QH = (0x0A << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGDU_EQ_OB = (0x18 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGDU_LT_OB = (0x19 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGDU_LE_OB = (0x1A << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGU_EQ_OB = (0x04 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGU_LT_OB = (0x05 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPGU_LE_OB = (0x06 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPU_EQ_OB = (0x00 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPU_LT_OB = (0x01 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_CMPU_LE_OB = (0x02 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PACKRL_PW = (0x0E << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PICK_OB = (0x03 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PICK_PW = (0x13 << 6) | OPC_CMPU_EQ_OB_DSP, + OPC_PICK_QH = (0x0B << 6) | OPC_CMPU_EQ_OB_DSP, /* MIPS DSP Arithmetic Sub-class */ OPC_PRECR_OB_QH = (0x0D << 6) | OPC_CMPU_EQ_OB_DSP, OPC_PRECR_SRA_QH_PW = (0x1E << 6) | OPC_CMPU_EQ_OB_DSP, @@ -615,6 +664,17 @@ enum { }; #endif +#if defined(TARGET_MIPS64) +#define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* DSP Compare-Pick Sub-class */ + OPC_DAPPEND = (0x00 << 6) | OPC_DAPPEND_DSP, + OPC_PREPENDD = (0x03 << 6) | OPC_DAPPEND_DSP, + OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP, + OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP, +}; +#endif + #if defined(TARGET_MIPS64) #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { @@ -13779,6 +13839,244 @@ static void gen_mipsdsp_bitinsn(CPUMIPSState *env, DisasContext *ctx, MIPS_DEBUG("%s", opn); } +static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, + uint32_t op1, uint32_t op2, + int ret, int v1, int v2, int check_ret) +{ + const char *opn = "mipsdsp add compare pick"; + TCGv_i32 t0; + TCGv t1; + TCGv v1_t; + TCGv v2_t; + + if ((ret == 0) && (check_ret == 1)) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new_i32(); + t1 = tcg_temp_new(); + v1_t = tcg_temp_new(); + v2_t = tcg_temp_new(); + + gen_load_gpr(v1_t, v1); + gen_load_gpr(v2_t, v2); + + switch (op1) { + case OPC_APPEND_DSP: + switch (op2) { + case OPC_APPEND: + tcg_gen_movi_i32(t0, v2); + gen_helper_append(cpu_gpr[ret], cpu_gpr[ret], v1_t, t0); + break; + case OPC_PREPEND: + tcg_gen_movi_i32(t0, v2); + gen_helper_prepend(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); + break; + case OPC_BALIGN: + tcg_gen_movi_i32(t0, v2); + gen_helper_balign(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); + break; + default: /* Invid */ + MIPS_INVAL("MASK APPEND"); + generate_exception(ctx, EXCP_RI); + break; + } + break; + case OPC_CMPU_EQ_QB_DSP: + switch (op2) { + case OPC_CMPU_EQ_QB: + check_dsp(ctx); + gen_helper_cmpu_eq_qb(v1_t, v2_t, cpu_env); + break; + case OPC_CMPU_LT_QB: + check_dsp(ctx); + gen_helper_cmpu_lt_qb(v1_t, v2_t, cpu_env); + break; + case OPC_CMPU_LE_QB: + check_dsp(ctx); + gen_helper_cmpu_le_qb(v1_t, v2_t, cpu_env); + break; + case OPC_CMPGU_EQ_QB: + check_dsp(ctx); + gen_helper_cmpgu_eq_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_CMPGU_LT_QB: + check_dsp(ctx); + gen_helper_cmpgu_lt_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_CMPGU_LE_QB: + check_dsp(ctx); + gen_helper_cmpgu_le_qb(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_CMPGDU_EQ_QB: + check_dspr2(ctx); + gen_helper_cmpgu_eq_qb(t1, v1_t, v2_t); + tcg_gen_mov_tl(cpu_gpr[ret], t1); + tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); + tcg_gen_shli_tl(t1, t1, 24); + tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); + break; + case OPC_CMPGDU_LT_QB: + check_dspr2(ctx); + gen_helper_cmpgu_lt_qb(t1, v1_t, v2_t); + tcg_gen_mov_tl(cpu_gpr[ret], t1); + tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); + tcg_gen_shli_tl(t1, t1, 24); + tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); + break; + case OPC_CMPGDU_LE_QB: + check_dspr2(ctx); + gen_helper_cmpgu_le_qb(t1, v1_t, v2_t); + tcg_gen_mov_tl(cpu_gpr[ret], t1); + tcg_gen_andi_tl(cpu_dspctrl, cpu_dspctrl, 0xF0FFFFFF); + tcg_gen_shli_tl(t1, t1, 24); + tcg_gen_or_tl(cpu_dspctrl, cpu_dspctrl, t1); + break; + case OPC_CMP_EQ_PH: + check_dsp(ctx); + gen_helper_cmp_eq_ph(v1_t, v2_t, cpu_env); + break; + case OPC_CMP_LT_PH: + check_dsp(ctx); + gen_helper_cmp_lt_ph(v1_t, v2_t, cpu_env); + break; + case OPC_CMP_LE_PH: + check_dsp(ctx); + gen_helper_cmp_le_ph(v1_t, v2_t, cpu_env); + break; + case OPC_PICK_QB: + check_dsp(ctx); + gen_helper_pick_qb(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_PICK_PH: + check_dsp(ctx); + gen_helper_pick_ph(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_PACKRL_PH: + check_dsp(ctx); + gen_helper_packrl_ph(cpu_gpr[ret], v1_t, v2_t); + break; + } + break; +#ifdef TARGET_MIPS64 + case OPC_CMPU_EQ_OB_DSP: + switch (op2) { + case OPC_CMP_EQ_PW: + check_dsp(ctx); + gen_helper_cmp_eq_pw(v1_t, v2_t, cpu_env); + break; + case OPC_CMP_LT_PW: + check_dsp(ctx); + gen_helper_cmp_lt_pw(v1_t, v2_t, cpu_env); + break; + case OPC_CMP_LE_PW: + check_dsp(ctx); + gen_helper_cmp_le_pw(v1_t, v2_t, cpu_env); + break; + case OPC_CMP_EQ_QH: + check_dsp(ctx); + gen_helper_cmp_eq_qh(v1_t, v2_t, cpu_env); + break; + case OPC_CMP_LT_QH: + check_dsp(ctx); + gen_helper_cmp_lt_qh(v1_t, v2_t, cpu_env); + break; + case OPC_CMP_LE_QH: + check_dsp(ctx); + gen_helper_cmp_le_qh(v1_t, v2_t, cpu_env); + break; + case OPC_CMPGDU_EQ_OB: + check_dspr2(ctx); + gen_helper_cmpgdu_eq_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_CMPGDU_LT_OB: + check_dspr2(ctx); + gen_helper_cmpgdu_lt_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_CMPGDU_LE_OB: + check_dspr2(ctx); + gen_helper_cmpgdu_le_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_CMPGU_EQ_OB: + check_dsp(ctx); + gen_helper_cmpgu_eq_ob(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_CMPGU_LT_OB: + check_dsp(ctx); + gen_helper_cmpgu_lt_ob(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_CMPGU_LE_OB: + check_dsp(ctx); + gen_helper_cmpgu_le_ob(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_CMPU_EQ_OB: + check_dsp(ctx); + gen_helper_cmpu_eq_ob(v1_t, v2_t, cpu_env); + break; + case OPC_CMPU_LT_OB: + check_dsp(ctx); + gen_helper_cmpu_lt_ob(v1_t, v2_t, cpu_env); + break; + case OPC_CMPU_LE_OB: + check_dsp(ctx); + gen_helper_cmpu_le_ob(v1_t, v2_t, cpu_env); + break; + case OPC_PACKRL_PW: + check_dsp(ctx); + gen_helper_packrl_pw(cpu_gpr[ret], v1_t, v2_t); + break; + case OPC_PICK_OB: + check_dsp(ctx); + gen_helper_pick_ob(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_PICK_PW: + check_dsp(ctx); + gen_helper_pick_pw(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + case OPC_PICK_QH: + check_dsp(ctx); + gen_helper_pick_qh(cpu_gpr[ret], v1_t, v2_t, cpu_env); + break; + } + break; + case OPC_DAPPEND_DSP: + switch (op2) { + case OPC_DAPPEND: + tcg_gen_movi_i32(t0, v2); + gen_helper_dappend(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); + break; + case OPC_PREPENDD: + tcg_gen_movi_i32(t0, v2); + gen_helper_prependd(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); + break; + case OPC_PREPENDW: + tcg_gen_movi_i32(t0, v2); + gen_helper_prependw(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); + break; + case OPC_DBALIGN: + tcg_gen_movi_i32(t0, v2); + gen_helper_dbalign(cpu_gpr[ret], v1_t, cpu_gpr[ret], t0); + break; + default: /* Invalid */ + MIPS_INVAL("MASK DAPPEND"); + generate_exception(ctx, EXCP_RI); + break; + } + break; +#endif + } + + tcg_temp_free_i32(t0); + tcg_temp_free(t1); + tcg_temp_free(v1_t); + tcg_temp_free(v2_t); + + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s", opn); +} + /* End MIPSDSP functions. */ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) @@ -14270,6 +14568,25 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_PRECRQU_S_QB_PH: gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); break; + case OPC_CMPU_EQ_QB: + case OPC_CMPU_LT_QB: + case OPC_CMPU_LE_QB: + case OPC_CMP_EQ_PH: + case OPC_CMP_LT_PH: + case OPC_CMP_LE_PH: + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); + break; + case OPC_CMPGU_EQ_QB: + case OPC_CMPGU_LT_QB: + case OPC_CMPGU_LE_QB: + case OPC_CMPGDU_EQ_QB: + case OPC_CMPGDU_LT_QB: + case OPC_CMPGDU_LE_QB: + case OPC_PICK_QB: + case OPC_PICK_PH: + case OPC_PACKRL_PH: + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); + break; default: /* Invalid */ MIPS_INVAL("MASK CMPU.EQ.QB"); generate_exception(ctx, EXCP_RI); @@ -14343,6 +14660,11 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) break; } break; + case OPC_APPEND_DSP: + check_dspr2(ctx); + op2 = MASK_APPEND(ctx->opcode); + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rt, rs, rd, 1); + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: @@ -14453,12 +14775,40 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) case OPC_PRECRQU_S_OB_QH: gen_mipsdsp_arith(ctx, op1, op2, rd, rs, rt); break; + case OPC_CMPU_EQ_OB: + case OPC_CMPU_LT_OB: + case OPC_CMPU_LE_OB: + case OPC_CMP_EQ_QH: + case OPC_CMP_LT_QH: + case OPC_CMP_LE_QH: + case OPC_CMP_EQ_PW: + case OPC_CMP_LT_PW: + case OPC_CMP_LE_PW: + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 0); + break; + case OPC_CMPGDU_EQ_OB: + case OPC_CMPGDU_LT_OB: + case OPC_CMPGDU_LE_OB: + case OPC_CMPGU_EQ_OB: + case OPC_CMPGU_LT_OB: + case OPC_CMPGU_LE_OB: + case OPC_PACKRL_PW: + case OPC_PICK_OB: + case OPC_PICK_PW: + case OPC_PICK_QH: + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rd, rs, rt, 1); + break; default: /* Invalid */ MIPS_INVAL("MASK CMPU_EQ.OB"); generate_exception(ctx, EXCP_RI); break; } break; + case OPC_DAPPEND_DSP: + check_dspr2(ctx); + op2 = MASK_DAPPEND(ctx->opcode); + gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rt, rs, rd, 1); + break; case OPC_DPAQ_W_QH_DSP: op2 = MASK_DPAQ_W_QH(ctx->opcode); switch (op2) { From b53371ed5d4b6a678bf524d381f80746739b7fc0 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:11 +0800 Subject: [PATCH 141/291] target-mips: Add ASE DSP accumulator instructions Add MIPS ASE DSP Accumulator and DSPControl Access instructions. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 609 +++++++++++++++++++++++++++++++++++++++ target-mips/helper.h | 35 +++ target-mips/translate.c | 351 ++++++++++++++++++++++ 3 files changed, 995 insertions(+) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index fcdc1bbcb9..b59133ea8f 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3400,6 +3400,615 @@ target_ulong helper_packrl_pw(target_ulong rs, target_ulong rt) } #endif +/** DSP Accumulator and DSPControl Access Sub-class insns **/ +target_ulong helper_extr_w(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + int32_t tempI; + int64_t tempDL[2]; + + shift = shift & 0x0F; + + mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env); + if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) && + (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) { + set_DSPControl_overflow_flag(1, 23, env); + } + + tempI = (tempDL[0] >> 1) & MIPSDSP_LLO; + + tempDL[0] += 1; + if (tempDL[0] == 0) { + tempDL[1] += 1; + } + + if ((!(tempDL[1] == 0 && (tempDL[0] & MIPSDSP_LHI) == 0x00)) && + (!(tempDL[1] == 1 && (tempDL[0] & MIPSDSP_LHI) == MIPSDSP_LHI))) { + set_DSPControl_overflow_flag(1, 23, env); + } + + return (target_long)tempI; +} + +target_ulong helper_extr_r_w(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + int64_t tempDL[2]; + + shift = shift & 0x0F; + + mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env); + if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) && + (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) { + set_DSPControl_overflow_flag(1, 23, env); + } + + tempDL[0] += 1; + if (tempDL[0] == 0) { + tempDL[1] += 1; + } + + if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) && + (tempDL[1] != 1 && (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) { + set_DSPControl_overflow_flag(1, 23, env); + } + + return (target_long)(int32_t)(tempDL[0] >> 1); +} + +target_ulong helper_extr_rs_w(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + int32_t tempI, temp64; + int64_t tempDL[2]; + + shift = shift & 0x0F; + + mipsdsp_rndrashift_short_acc(tempDL, ac, shift, env); + if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) && + (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) { + set_DSPControl_overflow_flag(1, 23, env); + } + tempDL[0] += 1; + if (tempDL[0] == 0) { + tempDL[1] += 1; + } + tempI = tempDL[0] >> 1; + + if ((tempDL[1] != 0 || (tempDL[0] & MIPSDSP_LHI) != 0) && + (tempDL[1] != 1 || (tempDL[0] & MIPSDSP_LHI) != MIPSDSP_LHI)) { + temp64 = tempDL[1]; + if (temp64 == 0) { + tempI = 0x7FFFFFFF; + } else { + tempI = 0x80000000; + } + set_DSPControl_overflow_flag(1, 23, env); + } + + return (target_long)tempI; +} + +#if defined(TARGET_MIPS64) +target_ulong helper_dextr_w(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + uint64_t temp[3]; + + shift = shift & 0x3F; + + mipsdsp_rndrashift_acc(temp, ac, shift, env); + + return (int64_t)(int32_t)(temp[0] >> 1); +} + +target_ulong helper_dextr_r_w(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + uint64_t temp[3]; + uint32_t temp128; + + shift = shift & 0x3F; + mipsdsp_rndrashift_acc(temp, ac, shift, env); + + temp[0] += 1; + if (temp[0] == 0) { + temp[1] += 1; + if (temp[1] == 0) { + temp[2] += 1; + } + } + + temp128 = temp[2] & 0x01; + + if ((temp128 != 0 || temp[1] != 0) && + (temp128 != 1 || temp[1] != ~0ull)) { + set_DSPControl_overflow_flag(1, 23, env); + } + + return (int64_t)(int32_t)(temp[0] >> 1); +} + +target_ulong helper_dextr_rs_w(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + uint64_t temp[3]; + uint32_t temp128; + + shift = shift & 0x3F; + mipsdsp_rndrashift_acc(temp, ac, shift, env); + + temp[0] += 1; + if (temp[0] == 0) { + temp[1] += 1; + if (temp[1] == 0) { + temp[2] += 1; + } + } + + temp128 = temp[2] & 0x01; + + if ((temp128 != 0 || temp[1] != 0) && + (temp128 != 1 || temp[1] != ~0ull)) { + if (temp128 == 0) { + temp[0] = 0x0FFFFFFFF; + } else { + temp[0] = 0x0100000000; + } + set_DSPControl_overflow_flag(1, 23, env); + } + + return (int64_t)(int32_t)(temp[0] >> 1); +} + +target_ulong helper_dextr_l(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + uint64_t temp[3]; + target_ulong result; + + shift = shift & 0x3F; + + mipsdsp_rndrashift_acc(temp, ac, shift, env); + result = (temp[1] << 63) | (temp[0] >> 1); + + return result; +} + +target_ulong helper_dextr_r_l(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + uint64_t temp[3]; + uint32_t temp128; + target_ulong result; + + shift = shift & 0x3F; + mipsdsp_rndrashift_acc(temp, ac, shift, env); + + temp[0] += 1; + if (temp[0] == 0) { + temp[1] += 1; + if (temp[1] == 0) { + temp[2] += 1; + } + } + + temp128 = temp[2] & 0x01; + + if ((temp128 != 0 || temp[1] != 0) && + (temp128 != 1 || temp[1] != ~0ull)) { + set_DSPControl_overflow_flag(1, 23, env); + } + + result = (temp[1] << 63) | (temp[0] >> 1); + + return result; +} + +target_ulong helper_dextr_rs_l(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + uint64_t temp[3]; + uint32_t temp128; + target_ulong result; + + shift = shift & 0x3F; + mipsdsp_rndrashift_acc(temp, ac, shift, env); + + temp[0] += 1; + if (temp[0] == 0) { + temp[1] += 1; + if (temp[1] == 0) { + temp[2] += 1; + } + } + + temp128 = temp[2] & 0x01; + + if ((temp128 != 0 || temp[1] != 0) && + (temp128 != 1 || temp[1] != ~0ull)) { + if (temp128 == 0) { + temp[1] &= ~0x00ull - 1; + temp[0] |= ~0x00ull - 1; + } else { + temp[1] |= 0x01; + temp[0] &= 0x01; + } + set_DSPControl_overflow_flag(1, 23, env); + } + result = (temp[1] << 63) | (temp[0] >> 1); + + return result; +} +#endif + +target_ulong helper_extr_s_h(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + int64_t temp; + + shift = shift & 0x0F; + + temp = mipsdsp_rashift_short_acc(ac, shift, env); + if (temp > (int64_t)0x7FFF) { + temp = 0x00007FFF; + set_DSPControl_overflow_flag(1, 23, env); + } else if (temp < (int64_t)0xFFFFFFFFFFFF8000) { + temp = 0xFFFF8000; + set_DSPControl_overflow_flag(1, 23, env); + } + + return (target_long)(int32_t)(temp & 0xFFFFFFFF); +} + + +#if defined(TARGET_MIPS64) +target_ulong helper_dextr_s_h(target_ulong ac, target_ulong shift, + CPUMIPSState *env) +{ + int64_t temp[2]; + uint32_t temp127; + + shift = shift & 0x1F; + + mipsdsp_rashift_acc((uint64_t *)temp, ac, shift, env); + + temp127 = (temp[1] >> 63) & 0x01; + + if ((temp127 == 0) && (temp[1] > 0 || temp[0] > 32767)) { + temp[0] &= 0xFFFF0000; + temp[0] |= 0x00007FFF; + set_DSPControl_overflow_flag(1, 23, env); + } else if ((temp127 == 1) && + (temp[1] < 0xFFFFFFFFFFFFFFFFll + || temp[0] < 0xFFFFFFFFFFFF1000ll)) { + temp[0] &= 0xFFFF0000; + temp[0] |= 0x00008000; + set_DSPControl_overflow_flag(1, 23, env); + } + + return (int64_t)(int16_t)(temp[0] & MIPSDSP_LO); +} + +#endif + +target_ulong helper_extp(target_ulong ac, target_ulong size, CPUMIPSState *env) +{ + int32_t start_pos; + int sub; + uint32_t temp; + uint64_t acc; + + size = size & 0x1F; + + temp = 0; + start_pos = get_DSPControl_pos(env); + sub = start_pos - (size + 1); + if (sub >= -1) { + acc = ((uint64_t)env->active_tc.HI[ac] << 32) | + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); + temp = (acc >> (start_pos - size)) & + (((uint32_t)0x01 << (size + 1)) - 1); + set_DSPControl_efi(0, env); + } else { + set_DSPControl_efi(1, env); + } + + return (target_ulong)temp; +} + +target_ulong helper_extpdp(target_ulong ac, target_ulong size, + CPUMIPSState *env) +{ + int32_t start_pos; + int sub; + uint32_t temp; + uint64_t acc; + + size = size & 0x1F; + temp = 0; + start_pos = get_DSPControl_pos(env); + sub = start_pos - (size + 1); + if (sub >= -1) { + acc = ((uint64_t)env->active_tc.HI[ac] << 32) | + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); + temp = (acc >> (start_pos - size)) & + (((uint32_t)0x01 << (size + 1)) - 1); + + set_DSPControl_pos(start_pos - (size + 1), env); + set_DSPControl_efi(0, env); + } else { + set_DSPControl_efi(1, env); + } + + return (target_ulong)temp; +} + + +#if defined(TARGET_MIPS64) +target_ulong helper_dextp(target_ulong ac, target_ulong size, CPUMIPSState *env) +{ + int start_pos; + int len; + int sub; + uint64_t tempB, tempA; + uint64_t temp; + + temp = 0; + + size = size & 0x3F; + start_pos = get_DSPControl_pos(env); + len = start_pos - size; + tempB = env->active_tc.HI[ac]; + tempA = env->active_tc.LO[ac]; + + sub = start_pos - (size + 1); + + if (sub >= -1) { + temp = (tempB << (64 - len)) | (tempA >> len); + temp = temp & ((0x01 << (size + 1)) - 1); + set_DSPControl_efi(0, env); + } else { + set_DSPControl_efi(1, env); + } + + return temp; +} + +target_ulong helper_dextpdp(target_ulong ac, target_ulong size, + CPUMIPSState *env) +{ + int start_pos; + int len; + int sub; + uint64_t tempB, tempA; + uint64_t temp; + + temp = 0; + size = size & 0x3F; + start_pos = get_DSPControl_pos(env); + len = start_pos - size; + tempB = env->active_tc.HI[ac]; + tempA = env->active_tc.LO[ac]; + + sub = start_pos - (size + 1); + + if (sub >= -1) { + temp = (tempB << (64 - len)) | (tempA >> len); + temp = temp & ((0x01 << (size + 1)) - 1); + set_DSPControl_pos(sub, env); + set_DSPControl_efi(0, env); + } else { + set_DSPControl_efi(1, env); + } + + return temp; +} + +#endif + +void helper_shilo(target_ulong ac, target_ulong rs, CPUMIPSState *env) +{ + int8_t rs5_0; + uint64_t temp, acc; + + rs5_0 = rs & 0x3F; + rs5_0 = (int8_t)(rs5_0 << 2) >> 2; + rs5_0 = MIPSDSP_ABS(rs5_0); + acc = (((uint64_t)env->active_tc.HI[ac] << 32) & MIPSDSP_LHI) | + ((uint64_t)env->active_tc.LO[ac] & MIPSDSP_LLO); + if (rs5_0 == 0) { + temp = acc; + } else { + if (rs5_0 > 0) { + temp = acc >> rs5_0; + } else { + temp = acc << rs5_0; + } + } + + env->active_tc.HI[ac] = (target_ulong)(int32_t)((temp & MIPSDSP_LHI) >> 32); + env->active_tc.LO[ac] = (target_ulong)(int32_t)(temp & MIPSDSP_LLO); +} + +#if defined(TARGET_MIPS64) +void helper_dshilo(target_ulong shift, target_ulong ac, CPUMIPSState *env) +{ + int8_t shift_t; + uint64_t tempB, tempA; + + shift_t = (int8_t)(shift << 1) >> 1; + + tempB = env->active_tc.HI[ac]; + tempA = env->active_tc.LO[ac]; + + if (shift_t != 0) { + if (shift_t >= 0) { + tempA = (tempB << (64 - shift_t)) | (tempA >> shift_t); + tempB = tempB >> shift_t; + } else { + shift_t = -shift_t; + tempB = (tempB << shift_t) | (tempA >> (64 - shift_t)); + tempA = tempA << shift_t; + } + } + + env->active_tc.HI[ac] = tempB; + env->active_tc.LO[ac] = tempA; +} + +#endif +void helper_mthlip(target_ulong ac, target_ulong rs, CPUMIPSState *env) +{ + int32_t tempA, tempB, pos; + + tempA = rs; + tempB = env->active_tc.LO[ac]; + env->active_tc.HI[ac] = (target_long)tempB; + env->active_tc.LO[ac] = (target_long)tempA; + pos = get_DSPControl_pos(env); + + if (pos > 32) { + return; + } else { + set_DSPControl_pos(pos + 32, env); + } +} + +#if defined(TARGET_MIPS64) +void helper_dmthlip(target_ulong rs, target_ulong ac, CPUMIPSState *env) +{ + uint8_t ac_t; + uint8_t pos; + uint64_t tempB, tempA; + + ac_t = ac & 0x3; + + tempA = rs; + tempB = env->active_tc.LO[ac_t]; + + env->active_tc.HI[ac_t] = tempB; + env->active_tc.LO[ac_t] = tempA; + + pos = get_DSPControl_pos(env); + + if (pos <= 64) { + pos = pos + 64; + set_DSPControl_pos(pos, env); + } +} +#endif + +void helper_wrdsp(target_ulong rs, target_ulong mask_num, CPUMIPSState *env) +{ + uint8_t mask[6]; + uint8_t i; + uint32_t newbits, overwrite; + target_ulong dsp; + + newbits = 0x00; + overwrite = 0xFFFFFFFF; + dsp = env->active_tc.DSPControl; + + for (i = 0; i < 6; i++) { + mask[i] = (mask_num >> i) & 0x01; + } + + if (mask[0] == 1) { +#if defined(TARGET_MIPS64) + overwrite &= 0xFFFFFF80; + newbits &= 0xFFFFFF80; + newbits |= 0x0000007F & rs; +#else + overwrite &= 0xFFFFFFC0; + newbits &= 0xFFFFFFC0; + newbits |= 0x0000003F & rs; +#endif + } + + if (mask[1] == 1) { + overwrite &= 0xFFFFE07F; + newbits &= 0xFFFFE07F; + newbits |= 0x00001F80 & rs; + } + + if (mask[2] == 1) { + overwrite &= 0xFFFFDFFF; + newbits &= 0xFFFFDFFF; + newbits |= 0x00002000 & rs; + } + + if (mask[3] == 1) { + overwrite &= 0xFF00FFFF; + newbits &= 0xFF00FFFF; + newbits |= 0x00FF0000 & rs; + } + + if (mask[4] == 1) { + overwrite &= 0x00FFFFFF; + newbits &= 0x00FFFFFF; + newbits |= 0xFF000000 & rs; + } + + if (mask[5] == 1) { + overwrite &= 0xFFFFBFFF; + newbits &= 0xFFFFBFFF; + newbits |= 0x00004000 & rs; + } + + dsp = dsp & overwrite; + dsp = dsp | newbits; + env->active_tc.DSPControl = dsp; +} + +target_ulong helper_rddsp(target_ulong masknum, CPUMIPSState *env) +{ + uint8_t mask[6]; + uint32_t ruler, i; + target_ulong temp; + target_ulong dsp; + + ruler = 0x01; + for (i = 0; i < 6; i++) { + mask[i] = (masknum & ruler) >> i ; + ruler = ruler << 1; + } + + temp = 0x00; + dsp = env->active_tc.DSPControl; + + if (mask[0] == 1) { +#if defined(TARGET_MIPS64) + temp |= dsp & 0x7F; +#else + temp |= dsp & 0x3F; +#endif + } + + if (mask[1] == 1) { + temp |= dsp & 0x1F80; + } + + if (mask[2] == 1) { + temp |= dsp & 0x2000; + } + + if (mask[3] == 1) { + temp |= dsp & 0x00FF0000; + } + + if (mask[4] == 1) { + temp |= dsp & 0xFF000000; + } + + if (mask[5] == 1) { + temp |= dsp & 0x4000; + } + + return temp; +} + + #undef MIPSDSP_LHI #undef MIPSDSP_LLO #undef MIPSDSP_HI diff --git a/target-mips/helper.h b/target-mips/helper.h index a821326b26..36a2e8da07 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -676,4 +676,39 @@ DEF_HELPER_FLAGS_2(packrl_ph, TCG_CALL_NO_RWG_SE, tl, tl, tl) DEF_HELPER_FLAGS_2(packrl_pw, TCG_CALL_NO_RWG_SE, tl, tl, tl) #endif +/* DSP Accumulator and DSPControl Access Sub-class insns */ +DEF_HELPER_FLAGS_3(extr_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(extr_r_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(extr_rs_w, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dextr_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextr_r_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextr_rs_w, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextr_l, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextr_r_l, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextr_rs_l, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(extr_s_h, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dextr_s_h, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(extp, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(extpdp, 0, tl, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dextp, 0, tl, tl, tl, env) +DEF_HELPER_FLAGS_3(dextpdp, 0, tl, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(shilo, 0, void, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dshilo, 0, void, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(mthlip, 0, void, tl, tl, env) +#if defined(TARGET_MIPS64) +DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) +#endif +DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) +DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) + + + #include "def-helper.h" diff --git a/target-mips/translate.c b/target-mips/translate.c index 69ef90a5aa..fea4113092 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -352,6 +352,11 @@ enum { OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3, #if defined(TARGET_MIPS64) OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3, +#endif + /* MIPS DSP Accumulator and DSPControl Access Sub-class */ + OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3, +#if defined(TARGET_MIPS64) + OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3, #endif }; @@ -564,6 +569,30 @@ enum { OPC_BALIGN = (0x10 << 6) | OPC_APPEND_DSP, }; +#define MASK_EXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Accumulator and DSPControl Access Sub-class */ + OPC_EXTR_W = (0x00 << 6) | OPC_EXTR_W_DSP, + OPC_EXTR_R_W = (0x04 << 6) | OPC_EXTR_W_DSP, + OPC_EXTR_RS_W = (0x06 << 6) | OPC_EXTR_W_DSP, + OPC_EXTR_S_H = (0x0E << 6) | OPC_EXTR_W_DSP, + OPC_EXTRV_S_H = (0x0F << 6) | OPC_EXTR_W_DSP, + OPC_EXTRV_W = (0x01 << 6) | OPC_EXTR_W_DSP, + OPC_EXTRV_R_W = (0x05 << 6) | OPC_EXTR_W_DSP, + OPC_EXTRV_RS_W = (0x07 << 6) | OPC_EXTR_W_DSP, + OPC_EXTP = (0x02 << 6) | OPC_EXTR_W_DSP, + OPC_EXTPV = (0x03 << 6) | OPC_EXTR_W_DSP, + OPC_EXTPDP = (0x0A << 6) | OPC_EXTR_W_DSP, + OPC_EXTPDPV = (0x0B << 6) | OPC_EXTR_W_DSP, + OPC_SHILO = (0x1A << 6) | OPC_EXTR_W_DSP, + OPC_SHILOV = (0x1B << 6) | OPC_EXTR_W_DSP, + OPC_MTHLIP = (0x1F << 6) | OPC_EXTR_W_DSP, + OPC_WRDSP = (0x13 << 6) | OPC_EXTR_W_DSP, + OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP, +}; + + + #if defined(TARGET_MIPS64) #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { @@ -676,6 +705,32 @@ enum { #endif #if defined(TARGET_MIPS64) +#define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) +enum { + /* MIPS DSP Accumulator and DSPControl Access Sub-class */ + OPC_DMTHLIP = (0x1F << 6) | OPC_DEXTR_W_DSP, + OPC_DSHILO = (0x1A << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTP = (0x02 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTPDP = (0x0A << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTPDPV = (0x0B << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTPV = (0x03 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTR_L = (0x10 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTR_R_L = (0x14 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTR_RS_L = (0x16 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTR_W = (0x00 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTR_R_W = (0x04 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTR_RS_W = (0x06 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTR_S_H = (0x0E << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTRV_L = (0x11 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTRV_R_L = (0x15 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTRV_RS_L = (0x17 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTRV_S_H = (0x0F << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTRV_W = (0x01 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTRV_R_W = (0x05 << 6) | OPC_DEXTR_W_DSP, + OPC_DEXTRV_RS_W = (0x07 << 6) | OPC_DEXTR_W_DSP, + OPC_DSHILOV = (0x1B << 6) | OPC_DEXTR_W_DSP, +}; + #define MASK_DINSV(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* DSP Bit/Manipulation Sub-class */ @@ -14077,6 +14132,236 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, MIPS_DEBUG("%s", opn); } +static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, + int ret, int v1, int v2, int check_ret) + +{ + const char *opn = "mipsdsp accumulator"; + TCGv t0; + TCGv t1; + TCGv v1_t; + TCGv v2_t; + int16_t imm; + + if ((ret == 0) && (check_ret == 1)) { + /* Treat as NOP. */ + MIPS_DEBUG("NOP"); + return; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + v1_t = tcg_temp_new(); + v2_t = tcg_temp_new(); + + gen_load_gpr(v1_t, v1); + gen_load_gpr(v2_t, v2); + + switch (op1) { + case OPC_EXTR_W_DSP: + check_dsp(ctx); + switch (op2) { + case OPC_EXTR_W: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_extr_w(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_EXTR_R_W: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_extr_r_w(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_EXTR_RS_W: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_extr_rs_w(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_EXTR_S_H: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_extr_s_h(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_EXTRV_S_H: + tcg_gen_movi_tl(t0, v2); + gen_helper_extr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_EXTRV_W: + tcg_gen_movi_tl(t0, v2); + gen_helper_extr_w(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_EXTRV_R_W: + tcg_gen_movi_tl(t0, v2); + gen_helper_extr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_EXTRV_RS_W: + tcg_gen_movi_tl(t0, v2); + gen_helper_extr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_EXTP: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_extp(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_EXTPV: + tcg_gen_movi_tl(t0, v2); + gen_helper_extp(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_EXTPDP: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_extpdp(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_EXTPDPV: + tcg_gen_movi_tl(t0, v2); + gen_helper_extpdp(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_SHILO: + imm = (ctx->opcode >> 20) & 0x3F; + tcg_gen_movi_tl(t0, ret); + tcg_gen_movi_tl(t1, imm); + gen_helper_shilo(t0, t1, cpu_env); + break; + case OPC_SHILOV: + tcg_gen_movi_tl(t0, ret); + gen_helper_shilo(t0, v1_t, cpu_env); + break; + case OPC_MTHLIP: + tcg_gen_movi_tl(t0, ret); + gen_helper_mthlip(t0, v1_t, cpu_env); + break; + case OPC_WRDSP: + imm = (ctx->opcode >> 11) & 0x3FF; + tcg_gen_movi_tl(t0, imm); + gen_helper_wrdsp(v1_t, t0, cpu_env); + break; + case OPC_RDDSP: + imm = (ctx->opcode >> 16) & 0x03FF; + tcg_gen_movi_tl(t0, imm); + gen_helper_rddsp(cpu_gpr[ret], t0, cpu_env); + break; + } + break; +#ifdef TARGET_MIPS64 + case OPC_DEXTR_W_DSP: + check_dsp(ctx); + switch (op2) { + case OPC_DMTHLIP: + tcg_gen_movi_tl(t0, ret); + gen_helper_dmthlip(v1_t, t0, cpu_env); + break; + case OPC_DSHILO: + { + int shift = (ctx->opcode >> 19) & 0x7F; + int ac = (ctx->opcode >> 11) & 0x03; + tcg_gen_movi_tl(t0, shift); + tcg_gen_movi_tl(t1, ac); + gen_helper_dshilo(t0, t1, cpu_env); + break; + } + case OPC_DSHILOV: + { + int ac = (ctx->opcode >> 11) & 0x03; + tcg_gen_movi_tl(t0, ac); + gen_helper_dshilo(v1_t, t0, cpu_env); + break; + } + case OPC_DEXTP: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + + gen_helper_dextp(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_DEXTPV: + tcg_gen_movi_tl(t0, v2); + gen_helper_dextp(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_DEXTPDP: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_dextpdp(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_DEXTPDPV: + tcg_gen_movi_tl(t0, v2); + gen_helper_dextpdp(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_DEXTR_L: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_dextr_l(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_DEXTR_R_L: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_dextr_r_l(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_DEXTR_RS_L: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_dextr_rs_l(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_DEXTR_W: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_dextr_w(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_DEXTR_R_W: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_dextr_r_w(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_DEXTR_RS_W: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_dextr_rs_w(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_DEXTR_S_H: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_DEXTRV_S_H: + tcg_gen_movi_tl(t0, v2); + tcg_gen_movi_tl(t1, v1); + gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env); + break; + case OPC_DEXTRV_L: + tcg_gen_movi_tl(t0, v2); + gen_helper_dextr_l(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_DEXTRV_R_L: + tcg_gen_movi_tl(t0, v2); + gen_helper_dextr_r_l(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_DEXTRV_RS_L: + tcg_gen_movi_tl(t0, v2); + gen_helper_dextr_rs_l(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_DEXTRV_W: + tcg_gen_movi_tl(t0, v2); + gen_helper_dextr_w(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_DEXTRV_R_W: + tcg_gen_movi_tl(t0, v2); + gen_helper_dextr_r_w(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + case OPC_DEXTRV_RS_W: + tcg_gen_movi_tl(t0, v2); + gen_helper_dextr_rs_w(cpu_gpr[ret], t0, v1_t, cpu_env); + break; + } + break; +#endif + } + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(v1_t); + tcg_temp_free(v2_t); + + (void)opn; /* avoid a compiler warning */ + MIPS_DEBUG("%s", opn); +} + /* End MIPSDSP functions. */ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) @@ -14665,6 +14950,38 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) op2 = MASK_APPEND(ctx->opcode); gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rt, rs, rd, 1); break; + case OPC_EXTR_W_DSP: + op2 = MASK_EXTR_W(ctx->opcode); + switch (op2) { + case OPC_EXTR_W: + case OPC_EXTR_R_W: + case OPC_EXTR_RS_W: + case OPC_EXTR_S_H: + case OPC_EXTRV_S_H: + case OPC_EXTRV_W: + case OPC_EXTRV_R_W: + case OPC_EXTRV_RS_W: + case OPC_EXTP: + case OPC_EXTPV: + case OPC_EXTPDP: + case OPC_EXTPDPV: + gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1); + break; + case OPC_RDDSP: + gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 1); + break; + case OPC_SHILO: + case OPC_SHILOV: + case OPC_MTHLIP: + case OPC_WRDSP: + gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0); + break; + default: /* Invalid */ + MIPS_INVAL("MASK EXTR.W"); + generate_exception(ctx, EXCP_RI); + break; + } + break; #if defined(TARGET_MIPS64) case OPC_DEXTM ... OPC_DEXT: case OPC_DINSM ... OPC_DINS: @@ -14809,6 +15126,40 @@ static void decode_opc (CPUMIPSState *env, DisasContext *ctx, int *is_branch) op2 = MASK_DAPPEND(ctx->opcode); gen_mipsdsp_add_cmp_pick(ctx, op1, op2, rt, rs, rd, 1); break; + case OPC_DEXTR_W_DSP: + op2 = MASK_DEXTR_W(ctx->opcode); + switch (op2) { + case OPC_DEXTP: + case OPC_DEXTPDP: + case OPC_DEXTPDPV: + case OPC_DEXTPV: + case OPC_DEXTR_L: + case OPC_DEXTR_R_L: + case OPC_DEXTR_RS_L: + case OPC_DEXTR_W: + case OPC_DEXTR_R_W: + case OPC_DEXTR_RS_W: + case OPC_DEXTR_S_H: + case OPC_DEXTRV_L: + case OPC_DEXTRV_R_L: + case OPC_DEXTRV_RS_L: + case OPC_DEXTRV_S_H: + case OPC_DEXTRV_W: + case OPC_DEXTRV_R_W: + case OPC_DEXTRV_RS_W: + gen_mipsdsp_accinsn(ctx, op1, op2, rt, rs, rd, 1); + break; + case OPC_DMTHLIP: + case OPC_DSHILO: + case OPC_DSHILOV: + gen_mipsdsp_accinsn(ctx, op1, op2, rd, rs, rt, 0); + break; + default: /* Invalid */ + MIPS_INVAL("MASK EXTR.W"); + generate_exception(ctx, EXCP_RI); + break; + } + break; case OPC_DPAQ_W_QH_DSP: op2 = MASK_DPAQ_W_QH(ctx->opcode); switch (op2) { From af13ae03f8dbc02974d53b11b80b3ae4dd9f30b4 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:12 +0800 Subject: [PATCH 142/291] target-mips: Add ASE DSP processors Add 74kf and mips64dspr2-generic-cpu model for test. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/translate_init.c | 52 ++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index c39138f3c5..7cf238f34b 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -311,6 +311,29 @@ static const mips_def_t mips_defs[] = .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT, .mmu_type = MMU_TYPE_R4000, }, + { + .name = "74Kf", + .CP0_PRid = 0x00019700, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) | + (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) | + (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | + (1 << CP0C1_CA), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 4, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x3778FF1F, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) | + (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID), + .SEGBITS = 32, + .PABITS = 32, + .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2, + .mmu_type = MMU_TYPE_R4000, + }, #if defined(TARGET_MIPS64) { .name = "R4000", @@ -484,6 +507,35 @@ static const mips_def_t mips_defs[] = .insn_flags = CPU_LOONGSON2F, .mmu_type = MMU_TYPE_R4000, }, + { + /* A generic CPU providing MIPS64 ASE DSP 2 features. + FIXME: Eventually this should be replaced by a real CPU model. */ + .name = "mips64dspr2", + .CP0_PRid = 0x00010000, + .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | + (MMU_TYPE_R4000 << CP0C0_MT), + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) | + (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | + (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | + (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), + .CP0_Config2 = MIPS_CONFIG2, + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_LLAddr_rw_bitmask = 0, + .CP0_LLAddr_shift = 0, + .SYNCI_Step = 32, + .CCRes = 2, + .CP0_Status_rw_bitmask = 0x37FBFFFF, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .SEGBITS = 42, + /* The architectural limit is 59, but we have hardcoded 36 bit + in some places... + .PABITS = 59, */ /* the architectural limit */ + .PABITS = 36, + .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2, + .mmu_type = MMU_TYPE_R4000, + }, #endif }; From d70080c4e37fc533fa10904b286f29449decc6f8 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:13 +0800 Subject: [PATCH 143/291] target-mips: Add ASE DSP testcases Add MIPS ASE DSP testcases. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- tests/tcg/mips/mips32-dsp/Makefile | 136 ++++++++ tests/tcg/mips/mips32-dsp/absq_s_ph.c | 31 ++ tests/tcg/mips/mips32-dsp/absq_s_w.c | 37 +++ tests/tcg/mips/mips32-dsp/addq_ph.c | 46 +++ tests/tcg/mips/mips32-dsp/addq_s_ph.c | 69 ++++ tests/tcg/mips/mips32-dsp/addq_s_w.c | 44 +++ tests/tcg/mips/mips32-dsp/addsc.c | 33 ++ tests/tcg/mips/mips32-dsp/addu_qb.c | 35 ++ tests/tcg/mips/mips32-dsp/addu_s_qb.c | 35 ++ tests/tcg/mips/mips32-dsp/addwc.c | 49 +++ tests/tcg/mips/mips32-dsp/bitrev.c | 20 ++ tests/tcg/mips/mips32-dsp/bposge32.c | 44 +++ tests/tcg/mips/mips32-dsp/cmp_eq_ph.c | 35 ++ tests/tcg/mips/mips32-dsp/cmp_le_ph.c | 35 ++ tests/tcg/mips/mips32-dsp/cmp_lt_ph.c | 35 ++ tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c | 31 ++ tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c | 31 ++ tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c | 31 ++ tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c | 35 ++ tests/tcg/mips/mips32-dsp/cmpu_le_qb.c | 35 ++ tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c | 35 ++ tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c | 31 ++ tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c | 77 +++++ tests/tcg/mips/mips32-dsp/dpau_h_qbl.c | 27 ++ tests/tcg/mips/mips32-dsp/dpau_h_qbr.c | 27 ++ tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c | 45 +++ tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c | 55 ++++ tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c | 27 ++ tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c | 27 ++ tests/tcg/mips/mips32-dsp/extp.c | 44 +++ tests/tcg/mips/mips32-dsp/extpdp.c | 46 +++ tests/tcg/mips/mips32-dsp/extpdpv.c | 47 +++ tests/tcg/mips/mips32-dsp/extpv.c | 45 +++ tests/tcg/mips/mips32-dsp/extr_r_w.c | 48 +++ tests/tcg/mips/mips32-dsp/extr_rs_w.c | 48 +++ tests/tcg/mips/mips32-dsp/extr_s_h.c | 63 ++++ tests/tcg/mips/mips32-dsp/extr_w.c | 48 +++ tests/tcg/mips/mips32-dsp/extrv_r_w.c | 54 ++++ tests/tcg/mips/mips32-dsp/extrv_rs_w.c | 52 +++ tests/tcg/mips/mips32-dsp/extrv_s_h.c | 71 ++++ tests/tcg/mips/mips32-dsp/extrv_w.c | 54 ++++ tests/tcg/mips/mips32-dsp/insv.c | 23 ++ tests/tcg/mips/mips32-dsp/lbux.c | 25 ++ tests/tcg/mips/mips32-dsp/lhx.c | 25 ++ tests/tcg/mips/mips32-dsp/lwx.c | 25 ++ tests/tcg/mips/mips32-dsp/madd.c | 31 ++ tests/tcg/mips/mips32-dsp/maddu.c | 31 ++ tests/tcg/mips/mips32-dsp/main.c | 6 + tests/tcg/mips/mips32-dsp/maq_s_w_phl.c | 55 ++++ tests/tcg/mips/mips32-dsp/maq_s_w_phr.c | 55 ++++ tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c | 55 ++++ tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c | 55 ++++ tests/tcg/mips/mips32-dsp/mfhi.c | 21 ++ tests/tcg/mips/mips32-dsp/mflo.c | 21 ++ tests/tcg/mips/mips32-dsp/modsub.c | 30 ++ tests/tcg/mips/mips32-dsp/msub.c | 30 ++ tests/tcg/mips/mips32-dsp/msubu.c | 30 ++ tests/tcg/mips/mips32-dsp/mthi.c | 21 ++ tests/tcg/mips/mips32-dsp/mthlip.c | 58 ++++ tests/tcg/mips/mips32-dsp/mtlo.c | 21 ++ tests/tcg/mips/mips32-dsp/muleq_s_w_phl.c | 41 +++ tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c | 40 +++ tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c | 25 ++ tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c | 25 ++ tests/tcg/mips/mips32-dsp/mulq_rs_ph.c | 25 ++ tests/tcg/mips/mips32-dsp/mult.c | 24 ++ tests/tcg/mips/mips32-dsp/multu.c | 24 ++ tests/tcg/mips/mips32-dsp/packrl_ph.c | 21 ++ tests/tcg/mips/mips32-dsp/pick_ph.c | 49 +++ tests/tcg/mips/mips32-dsp/pick_qb.c | 36 +++ tests/tcg/mips/mips32-dsp/preceq_w_phl.c | 20 ++ tests/tcg/mips/mips32-dsp/preceq_w_phr.c | 20 ++ tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c | 20 ++ tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c | 20 ++ tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c | 20 ++ tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c | 20 ++ tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c | 20 ++ tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c | 20 ++ tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c | 20 ++ tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c | 20 ++ tests/tcg/mips/mips32-dsp/precrq_ph_w.c | 21 ++ tests/tcg/mips/mips32-dsp/precrq_qb_ph.c | 21 ++ tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c | 35 ++ tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c | 24 ++ tests/tcg/mips/mips32-dsp/raddu_w_qb.c | 20 ++ tests/tcg/mips/mips32-dsp/rddsp.c | 54 ++++ tests/tcg/mips/mips32-dsp/repl_ph.c | 23 ++ tests/tcg/mips/mips32-dsp/repl_qb.c | 16 + tests/tcg/mips/mips32-dsp/replv_ph.c | 19 ++ tests/tcg/mips/mips32-dsp/replv_qb.c | 19 ++ tests/tcg/mips/mips32-dsp/shilo.c | 27 ++ tests/tcg/mips/mips32-dsp/shilov.c | 29 ++ tests/tcg/mips/mips32-dsp/shll_ph.c | 24 ++ tests/tcg/mips/mips32-dsp/shll_qb.c | 36 +++ tests/tcg/mips/mips32-dsp/shll_s_ph.c | 24 ++ tests/tcg/mips/mips32-dsp/shll_s_w.c | 52 +++ tests/tcg/mips/mips32-dsp/shllv_ph.c | 40 +++ tests/tcg/mips/mips32-dsp/shllv_qb.c | 38 +++ tests/tcg/mips/mips32-dsp/shllv_s_ph.c | 40 +++ tests/tcg/mips/mips32-dsp/shllv_s_w.c | 40 +++ tests/tcg/mips/mips32-dsp/shra_ph.c | 30 ++ tests/tcg/mips/mips32-dsp/shra_r_ph.c | 30 ++ tests/tcg/mips/mips32-dsp/shra_r_w.c | 30 ++ tests/tcg/mips/mips32-dsp/shrav_ph.c | 32 ++ tests/tcg/mips/mips32-dsp/shrav_r_ph.c | 32 ++ tests/tcg/mips/mips32-dsp/shrav_r_w.c | 32 ++ tests/tcg/mips/mips32-dsp/shrl_qb.c | 31 ++ tests/tcg/mips/mips32-dsp/shrlv_qb.c | 32 ++ tests/tcg/mips/mips32-dsp/subq_ph.c | 40 +++ tests/tcg/mips/mips32-dsp/subq_s_ph.c | 40 +++ tests/tcg/mips/mips32-dsp/subq_s_w.c | 58 ++++ tests/tcg/mips/mips32-dsp/subu_qb.c | 25 ++ tests/tcg/mips/mips32-dsp/subu_s_qb.c | 25 ++ tests/tcg/mips/mips32-dsp/wrdsp.c | 54 ++++ tests/tcg/mips/mips32-dspr2/Makefile | 71 ++++ tests/tcg/mips/mips32-dspr2/absq_s_qb.c | 35 ++ tests/tcg/mips/mips32-dspr2/addqh_ph.c | 30 ++ tests/tcg/mips/mips32-dspr2/addqh_r_ph.c | 30 ++ tests/tcg/mips/mips32-dspr2/addqh_r_w.c | 34 ++ tests/tcg/mips/mips32-dspr2/addqh_w.c | 34 ++ tests/tcg/mips/mips32-dspr2/addu_ph.c | 33 ++ tests/tcg/mips/mips32-dspr2/addu_s_ph.c | 33 ++ tests/tcg/mips/mips32-dspr2/adduh_qb.c | 30 ++ tests/tcg/mips/mips32-dspr2/adduh_r_qb.c | 30 ++ tests/tcg/mips/mips32-dspr2/append.c | 30 ++ tests/tcg/mips/mips32-dspr2/balign.c | 30 ++ tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c | 37 +++ tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c | 37 +++ tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c | 37 +++ tests/tcg/mips/mips32-dspr2/dpa_w_ph.c | 44 +++ tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c | 79 +++++ tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c | 53 +++ tests/tcg/mips/mips32-dspr2/dpax_w_ph.c | 27 ++ tests/tcg/mips/mips32-dspr2/dps_w_ph.c | 27 ++ tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c | 54 ++++ tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c | 53 +++ tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c | 27 ++ tests/tcg/mips/mips32-dspr2/mul_ph.c | 47 +++ tests/tcg/mips/mips32-dspr2/mul_s_ph.c | 62 ++++ tests/tcg/mips/mips32-dspr2/mulq_rs_w.c | 36 +++ tests/tcg/mips/mips32-dspr2/mulq_s_ph.c | 25 ++ tests/tcg/mips/mips32-dspr2/mulq_s_w.c | 36 +++ tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c | 29 ++ tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c | 29 ++ tests/tcg/mips/mips32-dspr2/precr_qb_ph.c | 21 ++ tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c | 32 ++ .../tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c | 32 ++ tests/tcg/mips/mips32-dspr2/prepend.c | 30 ++ tests/tcg/mips/mips32-dspr2/shra_qb.c | 30 ++ tests/tcg/mips/mips32-dspr2/shra_r_qb.c | 30 ++ tests/tcg/mips/mips32-dspr2/shrav_qb.c | 32 ++ tests/tcg/mips/mips32-dspr2/shrav_r_qb.c | 32 ++ tests/tcg/mips/mips32-dspr2/shrl_ph.c | 20 ++ tests/tcg/mips/mips32-dspr2/shrlv_ph.c | 21 ++ tests/tcg/mips/mips32-dspr2/subqh_ph.c | 21 ++ tests/tcg/mips/mips32-dspr2/subqh_r_ph.c | 21 ++ tests/tcg/mips/mips32-dspr2/subqh_r_w.c | 21 ++ tests/tcg/mips/mips32-dspr2/subqh_w.c | 21 ++ tests/tcg/mips/mips32-dspr2/subu_ph.c | 40 +++ tests/tcg/mips/mips32-dspr2/subu_s_ph.c | 25 ++ tests/tcg/mips/mips32-dspr2/subuh_qb.c | 21 ++ tests/tcg/mips/mips32-dspr2/subuh_r_qb.c | 32 ++ tests/tcg/mips/mips64-dsp/Makefile | 306 ++++++++++++++++++ tests/tcg/mips/mips64-dsp/absq_s_ob.c | 63 ++++ tests/tcg/mips/mips64-dsp/absq_s_ph.c | 37 +++ tests/tcg/mips/mips64-dsp/absq_s_pw.c | 66 ++++ tests/tcg/mips/mips64-dsp/absq_s_qh.c | 40 +++ tests/tcg/mips/mips64-dsp/absq_s_w.c | 48 +++ tests/tcg/mips/mips64-dsp/addq_ph.c | 57 ++++ tests/tcg/mips/mips64-dsp/addq_pw.c | 46 +++ tests/tcg/mips/mips64-dsp/addq_qh.c | 28 ++ tests/tcg/mips/mips64-dsp/addq_s_ph.c | 84 +++++ tests/tcg/mips/mips64-dsp/addq_s_pw.c | 45 +++ tests/tcg/mips/mips64-dsp/addq_s_qh.c | 26 ++ tests/tcg/mips/mips64-dsp/addq_s_w.c | 48 +++ tests/tcg/mips/mips64-dsp/addsc.c | 39 +++ tests/tcg/mips/mips64-dsp/addu_ob.c | 28 ++ tests/tcg/mips/mips64-dsp/addu_qb.c | 40 +++ tests/tcg/mips/mips64-dsp/addu_s_ob.c | 27 ++ tests/tcg/mips/mips64-dsp/addu_s_qb.c | 40 +++ tests/tcg/mips/mips64-dsp/addwc.c | 59 ++++ tests/tcg/mips/mips64-dsp/bitrev.c | 23 ++ tests/tcg/mips/mips64-dsp/bposge32.c | 50 +++ tests/tcg/mips/mips64-dsp/bposge64.c | 50 +++ tests/tcg/mips/mips64-dsp/cmp_eq_ph.c | 42 +++ tests/tcg/mips/mips64-dsp/cmp_eq_pw.c | 46 +++ tests/tcg/mips/mips64-dsp/cmp_eq_qh.c | 46 +++ tests/tcg/mips/mips64-dsp/cmp_le_ph.c | 40 +++ tests/tcg/mips/mips64-dsp/cmp_le_pw.c | 46 +++ tests/tcg/mips/mips64-dsp/cmp_le_qh.c | 46 +++ tests/tcg/mips/mips64-dsp/cmp_lt_ph.c | 41 +++ tests/tcg/mips/mips64-dsp/cmp_lt_pw.c | 46 +++ tests/tcg/mips/mips64-dsp/cmp_lt_qh.c | 46 +++ tests/tcg/mips/mips64-dsp/cmpgu_eq_ob.c | 40 +++ tests/tcg/mips/mips64-dsp/cmpgu_eq_qb.c | 38 +++ tests/tcg/mips/mips64-dsp/cmpgu_le_ob.c | 40 +++ tests/tcg/mips/mips64-dsp/cmpgu_le_qb.c | 37 +++ tests/tcg/mips/mips64-dsp/cmpgu_lt_ob.c | 40 +++ tests/tcg/mips/mips64-dsp/cmpgu_lt_qb.c | 38 +++ tests/tcg/mips/mips64-dsp/cmpu_eq_ob.c | 46 +++ tests/tcg/mips/mips64-dsp/cmpu_eq_qb.c | 42 +++ tests/tcg/mips/mips64-dsp/cmpu_le_ob.c | 44 +++ tests/tcg/mips/mips64-dsp/cmpu_le_qb.c | 41 +++ tests/tcg/mips/mips64-dsp/cmpu_lt_ob.c | 44 +++ tests/tcg/mips/mips64-dsp/cmpu_lt_qb.c | 42 +++ tests/tcg/mips/mips64-dsp/dappend.c | 37 +++ tests/tcg/mips/mips64-dsp/dextp.c | 54 ++++ tests/tcg/mips/mips64-dsp/dextpdp.c | 59 ++++ tests/tcg/mips/mips64-dsp/dextpdpv.c | 63 ++++ tests/tcg/mips/mips64-dsp/dextpv.c | 58 ++++ tests/tcg/mips/mips64-dsp/dextr_l.c | 44 +++ tests/tcg/mips/mips64-dsp/dextr_r_l.c | 54 ++++ tests/tcg/mips/mips64-dsp/dextr_r_w.c | 54 ++++ tests/tcg/mips/mips64-dsp/dextr_rs_l.c | 52 +++ tests/tcg/mips/mips64-dsp/dextr_rs_w.c | 52 +++ tests/tcg/mips/mips64-dsp/dextr_s_h.c | 73 +++++ tests/tcg/mips/mips64-dsp/dextr_w.c | 44 +++ tests/tcg/mips/mips64-dsp/dextrv_l.c | 46 +++ tests/tcg/mips/mips64-dsp/dextrv_r_l.c | 56 ++++ tests/tcg/mips/mips64-dsp/dextrv_r_w.c | 56 ++++ tests/tcg/mips/mips64-dsp/dextrv_rs_l.c | 54 ++++ tests/tcg/mips/mips64-dsp/dextrv_rs_w.c | 54 ++++ tests/tcg/mips/mips64-dsp/dextrv_s_h.c | 32 ++ tests/tcg/mips/mips64-dsp/dextrv_w.c | 46 +++ tests/tcg/mips/mips64-dsp/dinsv.c | 26 ++ tests/tcg/mips/mips64-dsp/dmadd.c | 57 ++++ tests/tcg/mips/mips64-dsp/dmaddu.c | 56 ++++ tests/tcg/mips/mips64-dsp/dmsub.c | 59 ++++ tests/tcg/mips/mips64-dsp/dmsubu.c | 59 ++++ tests/tcg/mips/mips64-dsp/dmthlip.c | 41 +++ tests/tcg/mips/mips64-dsp/dpaq_s_w_ph.c | 32 ++ tests/tcg/mips/mips64-dsp/dpaq_s_w_qh.c | 57 ++++ tests/tcg/mips/mips64-dsp/dpaq_sa_l_pw.c | 88 +++++ tests/tcg/mips/mips64-dsp/dpaq_sa_l_w.c | 82 +++++ tests/tcg/mips/mips64-dsp/dpau_h_obl.c | 59 ++++ tests/tcg/mips/mips64-dsp/dpau_h_obr.c | 59 ++++ tests/tcg/mips/mips64-dsp/dpau_h_qbl.c | 29 ++ tests/tcg/mips/mips64-dsp/dpau_h_qbr.c | 29 ++ tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c | 51 +++ tests/tcg/mips/mips64-dsp/dpsq_s_w_qh.c | 56 ++++ tests/tcg/mips/mips64-dsp/dpsq_sa_l_pw.c | 76 +++++ tests/tcg/mips/mips64-dsp/dpsq_sa_l_w.c | 59 ++++ tests/tcg/mips/mips64-dsp/dpsu_h_obl.c | 32 ++ tests/tcg/mips/mips64-dsp/dpsu_h_obr.c | 32 ++ tests/tcg/mips/mips64-dsp/dpsu_h_qbl.c | 29 ++ tests/tcg/mips/mips64-dsp/dpsu_h_qbr.c | 29 ++ tests/tcg/mips/mips64-dsp/dshilo.c | 52 +++ tests/tcg/mips/mips64-dsp/dshilov.c | 54 ++++ tests/tcg/mips/mips64-dsp/extp.c | 50 +++ tests/tcg/mips/mips64-dsp/extpdp.c | 51 +++ tests/tcg/mips/mips64-dsp/extpdpv.c | 52 +++ tests/tcg/mips/mips64-dsp/extpv.c | 51 +++ tests/tcg/mips/mips64-dsp/extr_r_w.c | 53 +++ tests/tcg/mips/mips64-dsp/extr_rs_w.c | 53 +++ tests/tcg/mips/mips64-dsp/extr_s_h.c | 71 ++++ tests/tcg/mips/mips64-dsp/extr_w.c | 53 +++ tests/tcg/mips/mips64-dsp/extrv_r_w.c | 59 ++++ tests/tcg/mips/mips64-dsp/extrv_rs_w.c | 59 ++++ tests/tcg/mips/mips64-dsp/extrv_s_h.c | 79 +++++ tests/tcg/mips/mips64-dsp/extrv_w.c | 59 ++++ tests/tcg/mips/mips64-dsp/head.S | 16 + tests/tcg/mips/mips64-dsp/insv.c | 26 ++ tests/tcg/mips/mips64-dsp/io.h | 22 ++ tests/tcg/mips/mips64-dsp/lbux.c | 27 ++ tests/tcg/mips/mips64-dsp/ldx.c | 27 ++ tests/tcg/mips/mips64-dsp/lhx.c | 27 ++ tests/tcg/mips/mips64-dsp/lwx.c | 27 ++ tests/tcg/mips/mips64-dsp/madd.c | 33 ++ tests/tcg/mips/mips64-dsp/maddu.c | 33 ++ tests/tcg/mips/mips64-dsp/maq_s_l_pwl.c | 56 ++++ tests/tcg/mips/mips64-dsp/maq_s_l_pwr.c | 56 ++++ tests/tcg/mips/mips64-dsp/maq_s_w_phl.c | 60 ++++ tests/tcg/mips/mips64-dsp/maq_s_w_phr.c | 60 ++++ tests/tcg/mips/mips64-dsp/maq_s_w_qhll.c | 62 ++++ tests/tcg/mips/mips64-dsp/maq_s_w_qhlr.c | 62 ++++ tests/tcg/mips/mips64-dsp/maq_s_w_qhrl.c | 63 ++++ tests/tcg/mips/mips64-dsp/maq_s_w_qhrr.c | 63 ++++ tests/tcg/mips/mips64-dsp/maq_sa_w_phl.c | 60 ++++ tests/tcg/mips/mips64-dsp/maq_sa_w_phr.c | 60 ++++ tests/tcg/mips/mips64-dsp/maq_sa_w_qhll.c | 62 ++++ tests/tcg/mips/mips64-dsp/maq_sa_w_qhlr.c | 64 ++++ tests/tcg/mips/mips64-dsp/maq_sa_w_qhrl.c | 64 ++++ tests/tcg/mips/mips64-dsp/maq_sa_w_qhrr.c | 64 ++++ tests/tcg/mips/mips64-dsp/mfhi.c | 24 ++ tests/tcg/mips/mips64-dsp/mflo.c | 24 ++ tests/tcg/mips/mips64-dsp/mips_boot.lds | 31 ++ tests/tcg/mips/mips64-dsp/modsub.c | 37 +++ tests/tcg/mips/mips64-dsp/msub.c | 32 ++ tests/tcg/mips/mips64-dsp/msubu.c | 32 ++ tests/tcg/mips/mips64-dsp/mthi.c | 24 ++ tests/tcg/mips/mips64-dsp/mthlip.c | 61 ++++ tests/tcg/mips/mips64-dsp/mtlo.c | 22 ++ tests/tcg/mips/mips64-dsp/muleq_s_pw_qhl.c | 56 ++++ tests/tcg/mips/mips64-dsp/muleq_s_pw_qhr.c | 57 ++++ tests/tcg/mips/mips64-dsp/muleq_s_w_phl.c | 46 +++ tests/tcg/mips/mips64-dsp/muleq_s_w_phr.c | 45 +++ tests/tcg/mips/mips64-dsp/muleu_s_ph_qbl.c | 27 ++ tests/tcg/mips/mips64-dsp/muleu_s_ph_qbr.c | 27 ++ tests/tcg/mips/mips64-dsp/muleu_s_qh_obl.c | 30 ++ tests/tcg/mips/mips64-dsp/muleu_s_qh_obr.c | 31 ++ tests/tcg/mips/mips64-dsp/mulq_rs_ph.c | 27 ++ tests/tcg/mips/mips64-dsp/mulq_rs_qh.c | 33 ++ tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c | 59 ++++ tests/tcg/mips/mips64-dsp/mulsaq_s_w_qh.c | 57 ++++ tests/tcg/mips/mips64-dsp/mult.c | 26 ++ tests/tcg/mips/mips64-dsp/multu.c | 26 ++ tests/tcg/mips/mips64-dsp/packrl_ph.c | 24 ++ tests/tcg/mips/mips64-dsp/packrl_pw.c | 24 ++ tests/tcg/mips/mips64-dsp/pick_ob.c | 66 ++++ tests/tcg/mips/mips64-dsp/pick_ph.c | 60 ++++ tests/tcg/mips/mips64-dsp/pick_pw.c | 48 +++ tests/tcg/mips/mips64-dsp/pick_qb.c | 43 +++ tests/tcg/mips/mips64-dsp/pick_qh.c | 48 +++ tests/tcg/mips/mips64-dsp/preceq_l_pwl.c | 24 ++ tests/tcg/mips/mips64-dsp/preceq_l_pwr.c | 24 ++ tests/tcg/mips/mips64-dsp/preceq_pw_qhl.c | 21 ++ tests/tcg/mips/mips64-dsp/preceq_pw_qhla.c | 23 ++ tests/tcg/mips/mips64-dsp/preceq_pw_qhr.c | 21 ++ tests/tcg/mips/mips64-dsp/preceq_pw_qhra.c | 23 ++ tests/tcg/mips/mips64-dsp/preceq_w_phl.c | 23 ++ tests/tcg/mips/mips64-dsp/preceq_w_phr.c | 23 ++ tests/tcg/mips/mips64-dsp/precequ_ph_qbl.c | 23 ++ tests/tcg/mips/mips64-dsp/precequ_ph_qbla.c | 23 ++ tests/tcg/mips/mips64-dsp/precequ_ph_qbr.c | 23 ++ tests/tcg/mips/mips64-dsp/precequ_ph_qbra.c | 23 ++ tests/tcg/mips/mips64-dsp/precequ_qh_obl.c | 22 ++ tests/tcg/mips/mips64-dsp/precequ_qh_obla.c | 22 ++ tests/tcg/mips/mips64-dsp/precequ_qh_obr.c | 24 ++ tests/tcg/mips/mips64-dsp/precequ_qh_obra.c | 24 ++ tests/tcg/mips/mips64-dsp/preceu_ph_qbl.c | 23 ++ tests/tcg/mips/mips64-dsp/preceu_ph_qbla.c | 23 ++ tests/tcg/mips/mips64-dsp/preceu_ph_qbr.c | 23 ++ tests/tcg/mips/mips64-dsp/preceu_ph_qbra.c | 23 ++ tests/tcg/mips/mips64-dsp/preceu_qh_obl.c | 22 ++ tests/tcg/mips/mips64-dsp/preceu_qh_obla.c | 22 ++ tests/tcg/mips/mips64-dsp/preceu_qh_obr.c | 23 ++ tests/tcg/mips/mips64-dsp/preceu_qh_obra.c | 23 ++ tests/tcg/mips/mips64-dsp/precr_ob_qh.c | 25 ++ tests/tcg/mips/mips64-dsp/precr_sra_qh_pw.c | 40 +++ tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c | 40 +++ tests/tcg/mips/mips64-dsp/precrq_ob_qh.c | 25 ++ tests/tcg/mips/mips64-dsp/precrq_ph_w.c | 24 ++ tests/tcg/mips/mips64-dsp/precrq_pw_l.c | 25 ++ tests/tcg/mips/mips64-dsp/precrq_qb_ph.c | 24 ++ tests/tcg/mips/mips64-dsp/precrq_qh_pw.c | 25 ++ tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c | 41 +++ tests/tcg/mips/mips64-dsp/precrq_rs_qh_pw.c | 43 +++ tests/tcg/mips/mips64-dsp/precrqu_s_ob_qh.c | 27 ++ tests/tcg/mips/mips64-dsp/precrqu_s_qb_ph.c | 26 ++ tests/tcg/mips/mips64-dsp/prependd.c | 37 +++ tests/tcg/mips/mips64-dsp/prependw.c | 37 +++ tests/tcg/mips/mips64-dsp/printf.c | 266 +++++++++++++++ tests/tcg/mips/mips64-dsp/raddu_l_ob.c | 22 ++ tests/tcg/mips/mips64-dsp/raddu_w_qb.c | 23 ++ tests/tcg/mips/mips64-dsp/rddsp.c | 53 +++ tests/tcg/mips/mips64-dsp/repl_ob.c | 21 ++ tests/tcg/mips/mips64-dsp/repl_ph.c | 30 ++ tests/tcg/mips/mips64-dsp/repl_pw.c | 34 ++ tests/tcg/mips/mips64-dsp/repl_qb.c | 19 ++ tests/tcg/mips/mips64-dsp/repl_qh.c | 34 ++ tests/tcg/mips/mips64-dsp/replv_ob.c | 23 ++ tests/tcg/mips/mips64-dsp/replv_ph.c | 22 ++ tests/tcg/mips/mips64-dsp/replv_pw.c | 23 ++ tests/tcg/mips/mips64-dsp/replv_qb.c | 22 ++ tests/tcg/mips/mips64-dsp/shilo.c | 29 ++ tests/tcg/mips/mips64-dsp/shilov.c | 31 ++ tests/tcg/mips/mips64-dsp/shll_ob.c | 43 +++ tests/tcg/mips/mips64-dsp/shll_ph.c | 43 +++ tests/tcg/mips/mips64-dsp/shll_pw.c | 43 +++ tests/tcg/mips/mips64-dsp/shll_qb.c | 26 ++ tests/tcg/mips/mips64-dsp/shll_qh.c | 42 +++ tests/tcg/mips/mips64-dsp/shll_s_ph.c | 43 +++ tests/tcg/mips/mips64-dsp/shll_s_pw.c | 43 +++ tests/tcg/mips/mips64-dsp/shll_s_qh.c | 43 +++ tests/tcg/mips/mips64-dsp/shll_s_w.c | 26 ++ tests/tcg/mips/mips64-dsp/shllv_ob.c | 45 +++ tests/tcg/mips/mips64-dsp/shllv_ph.c | 27 ++ tests/tcg/mips/mips64-dsp/shllv_pw.c | 45 +++ tests/tcg/mips/mips64-dsp/shllv_qb.c | 27 ++ tests/tcg/mips/mips64-dsp/shllv_qh.c | 45 +++ tests/tcg/mips/mips64-dsp/shllv_s_ph.c | 27 ++ tests/tcg/mips/mips64-dsp/shllv_s_pw.c | 45 +++ tests/tcg/mips/mips64-dsp/shllv_s_qh.c | 45 +++ tests/tcg/mips/mips64-dsp/shllv_s_w.c | 27 ++ tests/tcg/mips/mips64-dsp/shra_ob.c | 23 ++ tests/tcg/mips/mips64-dsp/shra_ph.c | 23 ++ tests/tcg/mips/mips64-dsp/shra_pw.c | 36 +++ tests/tcg/mips/mips64-dsp/shra_qh.c | 37 +++ tests/tcg/mips/mips64-dsp/shra_r_ob.c | 22 ++ tests/tcg/mips/mips64-dsp/shra_r_ph.c | 23 ++ tests/tcg/mips/mips64-dsp/shra_r_pw.c | 36 +++ tests/tcg/mips/mips64-dsp/shra_r_qh.c | 37 +++ tests/tcg/mips/mips64-dsp/shra_r_w.c | 23 ++ tests/tcg/mips/mips64-dsp/shrav_ph.c | 24 ++ tests/tcg/mips/mips64-dsp/shrav_pw.c | 38 +++ tests/tcg/mips/mips64-dsp/shrav_qh.c | 39 +++ tests/tcg/mips/mips64-dsp/shrav_r_ph.c | 24 ++ tests/tcg/mips/mips64-dsp/shrav_r_pw.c | 37 +++ tests/tcg/mips/mips64-dsp/shrav_r_qh.c | 39 +++ tests/tcg/mips/mips64-dsp/shrav_r_w.c | 24 ++ tests/tcg/mips/mips64-dsp/shrl_ob.c | 38 +++ tests/tcg/mips/mips64-dsp/shrl_qb.c | 23 ++ tests/tcg/mips/mips64-dsp/shrl_qh.c | 22 ++ tests/tcg/mips/mips64-dsp/shrlv_ob.c | 39 +++ tests/tcg/mips/mips64-dsp/shrlv_qb.c | 24 ++ tests/tcg/mips/mips64-dsp/shrlv_qh.c | 23 ++ tests/tcg/mips/mips64-dsp/subq_ph.c | 27 ++ tests/tcg/mips/mips64-dsp/subq_pw.c | 44 +++ tests/tcg/mips/mips64-dsp/subq_qh.c | 26 ++ tests/tcg/mips/mips64-dsp/subq_s_ph.c | 27 ++ tests/tcg/mips/mips64-dsp/subq_s_pw.c | 63 ++++ tests/tcg/mips/mips64-dsp/subq_s_qh.c | 61 ++++ tests/tcg/mips/mips64-dsp/subq_s_w.c | 27 ++ tests/tcg/mips/mips64-dsp/subu_ob.c | 26 ++ tests/tcg/mips/mips64-dsp/subu_qb.c | 27 ++ tests/tcg/mips/mips64-dsp/subu_s_ob.c | 26 ++ tests/tcg/mips/mips64-dsp/subu_s_qb.c | 27 ++ tests/tcg/mips/mips64-dsp/wrdsp.c | 48 +++ tests/tcg/mips/mips64-dspr2/.directory | 2 + tests/tcg/mips/mips64-dspr2/Makefile | 116 +++++++ tests/tcg/mips/mips64-dspr2/absq_s_qb.c | 42 +++ tests/tcg/mips/mips64-dspr2/addqh_ph.c | 35 ++ tests/tcg/mips/mips64-dspr2/addqh_r_ph.c | 35 ++ tests/tcg/mips/mips64-dspr2/addqh_r_w.c | 38 +++ tests/tcg/mips/mips64-dspr2/addqh_w.c | 39 +++ tests/tcg/mips/mips64-dspr2/addu_ph.c | 37 +++ tests/tcg/mips/mips64-dspr2/addu_qh.c | 43 +++ tests/tcg/mips/mips64-dspr2/addu_s_ph.c | 37 +++ tests/tcg/mips/mips64-dspr2/addu_s_qh.c | 43 +++ tests/tcg/mips/mips64-dspr2/adduh_ob.c | 35 ++ tests/tcg/mips/mips64-dspr2/adduh_qb.c | 35 ++ tests/tcg/mips/mips64-dspr2/adduh_r_ob.c | 35 ++ tests/tcg/mips/mips64-dspr2/adduh_r_qb.c | 35 ++ tests/tcg/mips/mips64-dspr2/append.c | 35 ++ tests/tcg/mips/mips64-dspr2/balign.c | 35 ++ tests/tcg/mips/mips64-dspr2/cmpgdu_eq_ob.c | 44 +++ tests/tcg/mips/mips64-dspr2/cmpgdu_eq_qb.c | 41 +++ tests/tcg/mips/mips64-dspr2/cmpgdu_le_ob.c | 44 +++ tests/tcg/mips/mips64-dspr2/cmpgdu_le_qb.c | 48 +++ tests/tcg/mips/mips64-dspr2/cmpgdu_lt_ob.c | 44 +++ tests/tcg/mips/mips64-dspr2/cmpgdu_lt_qb.c | 48 +++ tests/tcg/mips/mips64-dspr2/dbalign.c | 39 +++ tests/tcg/mips/mips64-dspr2/dpa_w_ph.c | 47 +++ tests/tcg/mips/mips64-dspr2/dpa_w_qh.c | 56 ++++ tests/tcg/mips/mips64-dspr2/dpaqx_s_w_ph.c | 97 ++++++ tests/tcg/mips/mips64-dspr2/dpaqx_sa_w_ph.c | 54 ++++ tests/tcg/mips/mips64-dspr2/dpax_w_ph.c | 32 ++ tests/tcg/mips/mips64-dspr2/dps_w_ph.c | 28 ++ tests/tcg/mips/mips64-dspr2/dps_w_qh.c | 55 ++++ tests/tcg/mips/mips64-dspr2/dpsqx_s_w_ph.c | 55 ++++ tests/tcg/mips/mips64-dspr2/dpsqx_sa_w_ph.c | 53 +++ tests/tcg/mips/mips64-dspr2/dpsx_w_ph.c | 28 ++ tests/tcg/mips/mips64-dspr2/head.S | 16 + tests/tcg/mips/mips64-dspr2/io.h | 22 ++ tests/tcg/mips/mips64-dspr2/mips_boot.lds | 31 ++ tests/tcg/mips/mips64-dspr2/mul_ph.c | 50 +++ tests/tcg/mips/mips64-dspr2/mul_s_ph.c | 67 ++++ tests/tcg/mips/mips64-dspr2/mulq_rs_w.c | 40 +++ tests/tcg/mips/mips64-dspr2/mulq_s_ph.c | 26 ++ tests/tcg/mips/mips64-dspr2/mulq_s_w.c | 40 +++ tests/tcg/mips/mips64-dspr2/mulsa_w_ph.c | 30 ++ tests/tcg/mips/mips64-dspr2/mulsaq_s_w_ph.c | 30 ++ tests/tcg/mips/mips64-dspr2/precr_qb_ph.c | 23 ++ tests/tcg/mips/mips64-dspr2/precr_sra_ph_w.c | 37 +++ .../tcg/mips/mips64-dspr2/precr_sra_r_ph_w.c | 37 +++ tests/tcg/mips/mips64-dspr2/prepend.c | 35 ++ tests/tcg/mips/mips64-dspr2/printf.c | 266 +++++++++++++++ tests/tcg/mips/mips64-dspr2/shra_qb.c | 35 ++ tests/tcg/mips/mips64-dspr2/shra_r_qb.c | 35 ++ tests/tcg/mips/mips64-dspr2/shrav_ob.c | 22 ++ tests/tcg/mips/mips64-dspr2/shrav_qb.c | 37 +++ tests/tcg/mips/mips64-dspr2/shrav_r_ob.c | 22 ++ tests/tcg/mips/mips64-dspr2/shrav_r_qb.c | 37 +++ tests/tcg/mips/mips64-dspr2/shrl_ph.c | 22 ++ tests/tcg/mips/mips64-dspr2/shrlv_ph.c | 23 ++ tests/tcg/mips/mips64-dspr2/subqh_ph.c | 23 ++ tests/tcg/mips/mips64-dspr2/subqh_r_ph.c | 23 ++ tests/tcg/mips/mips64-dspr2/subqh_r_w.c | 23 ++ tests/tcg/mips/mips64-dspr2/subqh_w.c | 23 ++ tests/tcg/mips/mips64-dspr2/subu_ph.c | 26 ++ tests/tcg/mips/mips64-dspr2/subu_qh.c | 24 ++ tests/tcg/mips/mips64-dspr2/subu_s_ph.c | 25 ++ tests/tcg/mips/mips64-dspr2/subu_s_qh.c | 42 +++ tests/tcg/mips/mips64-dspr2/subuh_ob.c | 36 +++ tests/tcg/mips/mips64-dspr2/subuh_qb.c | 23 ++ tests/tcg/mips/mips64-dspr2/subuh_r_ob.c | 23 ++ tests/tcg/mips/mips64-dspr2/subuh_r_qb.c | 37 +++ 487 files changed, 19151 insertions(+) create mode 100644 tests/tcg/mips/mips32-dsp/Makefile create mode 100644 tests/tcg/mips/mips32-dsp/absq_s_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/absq_s_w.c create mode 100644 tests/tcg/mips/mips32-dsp/addq_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/addq_s_ph.c create mode 100644 tests/tcg/mips/mips32-dsp/addq_s_w.c create mode 100644 tests/tcg/mips/mips32-dsp/addsc.c create mode 100644 tests/tcg/mips/mips32-dsp/addu_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/addu_s_qb.c create mode 100644 tests/tcg/mips/mips32-dsp/addwc.c create mode 100644 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tests/tcg/mips/mips64-dspr2/shrlv_ph.c create mode 100644 tests/tcg/mips/mips64-dspr2/subqh_ph.c create mode 100644 tests/tcg/mips/mips64-dspr2/subqh_r_ph.c create mode 100644 tests/tcg/mips/mips64-dspr2/subqh_r_w.c create mode 100644 tests/tcg/mips/mips64-dspr2/subqh_w.c create mode 100644 tests/tcg/mips/mips64-dspr2/subu_ph.c create mode 100644 tests/tcg/mips/mips64-dspr2/subu_qh.c create mode 100644 tests/tcg/mips/mips64-dspr2/subu_s_ph.c create mode 100644 tests/tcg/mips/mips64-dspr2/subu_s_qh.c create mode 100644 tests/tcg/mips/mips64-dspr2/subuh_ob.c create mode 100644 tests/tcg/mips/mips64-dspr2/subuh_qb.c create mode 100644 tests/tcg/mips/mips64-dspr2/subuh_r_ob.c create mode 100644 tests/tcg/mips/mips64-dspr2/subuh_r_qb.c diff --git a/tests/tcg/mips/mips32-dsp/Makefile b/tests/tcg/mips/mips32-dsp/Makefile new file mode 100644 index 0000000000..c3a0a00944 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/Makefile @@ -0,0 +1,136 @@ +-include ../../config-host.mak + +CROSS=mips64el-unknown-linux-gnu- + +SIM=qemu-mipsel +SIM_FLAGS=-cpu 74Kf + +CC = $(CROSS)gcc +CFLAGS = -mabi=32 -march=mips32r2 -mgp32 -mdsp -static + +TESTCASES = absq_s_ph.tst +TESTCASES += absq_s_w.tst +TESTCASES += addq_ph.tst +TESTCASES += addq_s_ph.tst +TESTCASES += addq_s_w.tst +TESTCASES += addsc.tst +TESTCASES += addu_qb.tst +TESTCASES += addu_s_qb.tst +TESTCASES += addwc.tst +TESTCASES += bitrev.tst +TESTCASES += bposge32.tst +TESTCASES += cmp_eq_ph.tst +TESTCASES += cmpgu_eq_qb.tst +TESTCASES += cmpgu_le_qb.tst +TESTCASES += cmpgu_lt_qb.tst +TESTCASES += cmp_le_ph.tst +TESTCASES += cmp_lt_ph.tst +TESTCASES += cmpu_eq_qb.tst +TESTCASES += cmpu_le_qb.tst +TESTCASES += cmpu_lt_qb.tst +TESTCASES += dpaq_sa_l_w.tst +TESTCASES += dpaq_s_w_ph.tst +TESTCASES += dpau_h_qbl.tst +TESTCASES += dpau_h_qbr.tst +TESTCASES += dpsq_sa_l_w.tst +TESTCASES += dpsq_s_w_ph.tst +TESTCASES += dpsu_h_qbl.tst +TESTCASES += dpsu_h_qbr.tst +TESTCASES += extp.tst +TESTCASES += extpdp.tst +TESTCASES += extpdpv.tst +TESTCASES += extpv.tst +TESTCASES += extr_rs_w.tst +TESTCASES += extr_r_w.tst +TESTCASES += extr_s_h.tst +TESTCASES += extrv_rs_w.tst +TESTCASES += extrv_r_w.tst +TESTCASES += extrv_s_h.tst +TESTCASES += extrv_w.tst +TESTCASES += extr_w.tst +TESTCASES += insv.tst +TESTCASES += lbux.tst +TESTCASES += lhx.tst +TESTCASES += lwx.tst +TESTCASES += madd.tst +TESTCASES += maddu.tst +TESTCASES += maq_sa_w_phl.tst +TESTCASES += maq_sa_w_phr.tst +TESTCASES += maq_s_w_phl.tst +TESTCASES += maq_s_w_phr.tst +TESTCASES += mfhi.tst +TESTCASES += mflo.tst +TESTCASES += modsub.tst +TESTCASES += msub.tst +TESTCASES += msubu.tst +TESTCASES += mthi.tst +TESTCASES += mthlip.tst +TESTCASES += mtlo.tst +TESTCASES += muleq_s_w_phl.tst +TESTCASES += muleq_s_w_phr.tst +TESTCASES += muleu_s_ph_qbl.tst +TESTCASES += muleu_s_ph_qbr.tst +TESTCASES += mulq_rs_ph.tst +TESTCASES += mult.tst +TESTCASES += multu.tst +TESTCASES += packrl_ph.tst +TESTCASES += pick_ph.tst +TESTCASES += pick_qb.tst +TESTCASES += precequ_ph_qbla.tst +TESTCASES += precequ_ph_qbl.tst +TESTCASES += precequ_ph_qbra.tst +TESTCASES += precequ_ph_qbr.tst +TESTCASES += preceq_w_phl.tst +TESTCASES += preceq_w_phr.tst +TESTCASES += preceu_ph_qbla.tst +TESTCASES += preceu_ph_qbl.tst +TESTCASES += preceu_ph_qbra.tst +TESTCASES += preceu_ph_qbr.tst +TESTCASES += precrq_ph_w.tst +TESTCASES += precrq_qb_ph.tst +TESTCASES += precrq_rs_ph_w.tst +TESTCASES += precrqu_s_qb_ph.tst +TESTCASES += raddu_w_qb.tst +TESTCASES += rddsp.tst +TESTCASES += repl_ph.tst +TESTCASES += repl_qb.tst +TESTCASES += replv_ph.tst +TESTCASES += replv_qb.tst +TESTCASES += shilo.tst +TESTCASES += shilov.tst +TESTCASES += shll_ph.tst +TESTCASES += shll_qb.tst +TESTCASES += shll_s_ph.tst +TESTCASES += shll_s_w.tst +TESTCASES += shllv_ph.tst +TESTCASES += shllv_qb.tst +TESTCASES += shllv_s_ph.tst +TESTCASES += shllv_s_w.tst +TESTCASES += shra_ph.tst +TESTCASES += shra_r_ph.tst +TESTCASES += shra_r_w.tst +TESTCASES += shrav_ph.tst +TESTCASES += shrav_r_ph.tst +TESTCASES += shrav_r_w.tst +TESTCASES += shrl_qb.tst +TESTCASES += shrlv_qb.tst +TESTCASES += subq_ph.tst +TESTCASES += subq_s_ph.tst +TESTCASES += subq_s_w.tst +TESTCASES += subu_qb.tst +TESTCASES += subu_s_qb.tst +TESTCASES += wrdsp.tst + +all: $(TESTCASES) + +%.tst: %.c + $(CC) $(CFLAGS) $< -o $@ + +check: $(TESTCASES) + @for case in $(TESTCASES); do \ + echo $(SIM) $(SIM_FLAGS) ./$$case;\ + $(SIM) $(SIM_FLAGS) ./$$case; \ + done + +clean: + $(RM) -rf $(TESTCASES) diff --git a/tests/tcg/mips/mips32-dsp/absq_s_ph.c b/tests/tcg/mips/mips32-dsp/absq_s_ph.c new file mode 100644 index 0000000000..aa8411202e --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/absq_s_ph.c @@ -0,0 +1,31 @@ +#include +#include + + +int main() +{ + int rd, rt; + int result; + + rt = 0x10017EFD; + result = 0x10017EFD; + + __asm + ("absq_s.ph %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + rt = 0x8000A536; + result = 0x7FFF5ACA; + + __asm + ("absq_s.ph %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/absq_s_w.c b/tests/tcg/mips/mips32-dsp/absq_s_w.c new file mode 100644 index 0000000000..3f52a48039 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/absq_s_w.c @@ -0,0 +1,37 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x80000000; + result = 0x7FFFFFFF; + __asm + ("absq_s.w %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + rt = 0x80030000; + result = 0x7FFD0000; + __asm + ("absq_s.w %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + rt = 0x31036080; + result = 0x31036080; + __asm + ("absq_s.w %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/addq_ph.c b/tests/tcg/mips/mips32-dsp/addq_ph.c new file mode 100644 index 0000000000..96a549637b --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addq_ph.c @@ -0,0 +1,46 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0xFFFFFFFF; + rt = 0x10101010; + result = 0x100F100F; + __asm + ("addq.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + rs = 0x3712847D; + rt = 0x0031AF2D; + result = 0x374333AA; + __asm + ("addq.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + rs = 0x7fff847D; + rt = 0x0031AF2D; + result = 0x803033AA; + __asm + ("addq.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + __asm("rddsp %0\n\t" + : "=r"(dsp) + ); + assert(((dsp >> 20) & 0x01) == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/addq_s_ph.c b/tests/tcg/mips/mips32-dsp/addq_s_ph.c new file mode 100644 index 0000000000..5f865f6cff --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addq_s_ph.c @@ -0,0 +1,69 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0xFFFFFFFF; + rt = 0x10101010; + result = 0x100F100F; + __asm + ("addq_s.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + rs = 0x3712847D; + rt = 0x0031AF2D; + result = 0x37438000; + __asm + ("addq_s.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + __asm + ("rddsp %0\n\t" + : "=r"(dsp) + ); + assert(((dsp >> 20) & 0x01) == 1); + + rs = 0x7fff847D; + rt = 0x0031AF2D; + result = 0x7fff8000; + __asm + ("addq_s.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + __asm + ("rddsp %0\n\t" + : "=r"(dsp) + ); + assert(((dsp >> 20) & 0x01) == 1); + + rs = 0x8030847D; + rt = 0x8a00AF2D; + result = 0x80008000; + __asm + ("addq_s.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + __asm + ("rddsp %0\n\t" + : "=r"(dsp) + ); + assert(((dsp >> 20) & 0x01) == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/addq_s_w.c b/tests/tcg/mips/mips32-dsp/addq_s_w.c new file mode 100644 index 0000000000..1e13acf68f --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addq_s_w.c @@ -0,0 +1,44 @@ +#include +#include + + +int main() +{ + int rd, rs, rt; + int result; + + rt = 0x10017EFD; + rs = 0x11111111; + result = 0x2112900e; + + __asm + ("addq_s.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rt = 0x80017EFD; + rs = 0x81111111; + result = 0x80000000; + + __asm + ("addq_s.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rt = 0x7fffffff; + rs = 0x01111111; + result = 0x7fffffff; + + __asm + ("addq_s.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/addsc.c b/tests/tcg/mips/mips32-dsp/addsc.c new file mode 100644 index 0000000000..ace749f667 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addsc.c @@ -0,0 +1,33 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x0000000F; + rt = 0x00000001; + result = 0x00000010; + __asm + ("addsc %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x00001110; + __asm + ("addsc %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + assert(((dsp >> 13) & 0x01) == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/addu_qb.c b/tests/tcg/mips/mips32-dsp/addu_qb.c new file mode 100644 index 0000000000..23ba2e90d1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addu_qb.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x00FF00FF; + rt = 0x00010001; + result = 0x00000000; + __asm + ("addu.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + assert(((dsp >> 20) & 0x01) == 1); + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0xFF011112; + __asm + ("addu.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + assert(((dsp >> 20) & 0x01) == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/addu_s_qb.c b/tests/tcg/mips/mips32-dsp/addu_s_qb.c new file mode 100644 index 0000000000..fe7fd3e6aa --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addu_s_qb.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x10FF01FF; + rt = 0x10010001; + result = 0x20FF01FF; + __asm + ("addu_s.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + assert(((dsp >> 20) & 0x1) == 1); + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0xFFFF1112; + __asm + ("addu_s.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + assert(((dsp >> 20) & 0x1) == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/addwc.c b/tests/tcg/mips/mips32-dsp/addwc.c new file mode 100644 index 0000000000..8a8d81fab4 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/addwc.c @@ -0,0 +1,49 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dspi, dspo; + int result; + + rs = 0x10FF01FF; + rt = 0x10010001; + dspi = 0x00002000; + result = 0x21000201; + __asm + ("wrdsp %3\n" + "addwc %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dspi) + ); + assert(rd == result); + + rs = 0xFFFF1111; + rt = 0x00020001; + dspi = 0x00; + result = 0x00011112; + __asm + ("wrdsp %3\n" + "addwc %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dspi) + ); + assert(rd == result); + + rs = 0x8FFF1111; + rt = 0x80020001; + dspi = 0x00; + result = 0x10011112; + __asm + ("wrdsp %4\n" + "addwc %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspo) + : "r"(rs), "r"(rt), "r"(dspi) + ); + assert(rd == result); + assert(((dspo >> 20) & 0x01) == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/bitrev.c b/tests/tcg/mips/mips32-dsp/bitrev.c new file mode 100644 index 0000000000..04d8a3844e --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/bitrev.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x00001E6A; + + __asm + ("bitrev %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/bposge32.c b/tests/tcg/mips/mips32-dsp/bposge32.c new file mode 100644 index 0000000000..d25417ea77 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/bposge32.c @@ -0,0 +1,44 @@ +#include +#include + +int main() +{ + int dsp, sum; + int result; + + dsp = 0x20; + sum = 0x01; + result = 0x02; + + __asm + ("wrdsp %1\n\t" + "bposge32 test1\n\t" + "nop\n\t" + "addi %0, 0xA2\n\t" + "nop\n\t" + "test1:\n\t" + "addi %0, 0x01\n\t" + : "+r"(sum) + : "r"(dsp) + ); + assert(sum == result); + + dsp = 0x10; + sum = 0x01; + result = 0xA4; + + __asm + ("wrdsp %1\n\t" + "bposge32 test2\n\t" + "nop\n\t" + "addi %0, 0xA2\n\t" + "nop\n\t" + "test2:\n\t" + "addi %0, 0x01\n\t" + : "+r"(sum) + : "r"(dsp) + ); + assert(sum == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/cmp_eq_ph.c b/tests/tcg/mips/mips32-dsp/cmp_eq_ph.c new file mode 100644 index 0000000000..957bd88ce0 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmp_eq_ph.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA33FF; + result = 0x00; + __asm + ("cmp.eq.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + rd = (rd >> 24) & 0x03; + assert(rd == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x03; + __asm + ("cmp.eq.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + rd = (rd >> 24) & 0x03; + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/cmp_le_ph.c b/tests/tcg/mips/mips32-dsp/cmp_le_ph.c new file mode 100644 index 0000000000..356f156c5d --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmp_le_ph.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA33FF; + result = 0x02; + __asm + ("cmp.le.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + rd = (rd >> 24) & 0x03; + assert(rd == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x03; + __asm + ("cmp.le.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + rd = (rd >> 24) & 0x03; + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/cmp_lt_ph.c b/tests/tcg/mips/mips32-dsp/cmp_lt_ph.c new file mode 100644 index 0000000000..3fb4827ad7 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmp_lt_ph.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA33FF; + result = 0x02; + __asm + ("cmp.lt.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + rd = (rd >> 24) & 0x03; + assert(rd == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x00; + __asm + ("cmp.lt.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + rd = (rd >> 24) & 0x03; + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c b/tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c new file mode 100644 index 0000000000..2615c84c75 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpgu_eq_qb.c @@ -0,0 +1,31 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x02; + __asm + ("cmpgu.eq.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + assert(rd == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm + ("cmpgu.eq.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c b/tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c new file mode 100644 index 0000000000..65d0813c3b --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpgu_le_qb.c @@ -0,0 +1,31 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0F; + __asm + ("cmpgu.le.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + assert(rd == result); + + rs = 0x11777066; + rt = 0x11766066; + result = 0x09; + __asm + ("cmpgu.le.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c b/tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c new file mode 100644 index 0000000000..7dddad9853 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpgu_lt_qb.c @@ -0,0 +1,31 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0D; + __asm + ("cmpgu.lt.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + assert(rd == result); + + rs = 0x11777066; + rt = 0x11766066; + result = 0x00; + __asm + ("cmpgu.lt.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c b/tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c new file mode 100644 index 0000000000..680f2a1999 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpu_eq_qb.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x02; + __asm + ("cmpu.eq.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm + ("cmpu.eq.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/cmpu_le_qb.c b/tests/tcg/mips/mips32-dsp/cmpu_le_qb.c new file mode 100644 index 0000000000..43cfa509ca --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpu_le_qb.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0F; + __asm + ("cmpu.le.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm + ("cmpu.le.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c b/tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c new file mode 100644 index 0000000000..074ca5b402 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/cmpu_lt_qb.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0D; + __asm + ("cmpu.lt.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x00; + __asm + ("cmpu.lt.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(dsp == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c b/tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c new file mode 100644 index 0000000000..a6425b6edc --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpaq_s_w_ph.c @@ -0,0 +1,31 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 0, acl = 0; + int resulth, resultl, resultdsp; + + rs = 0x800000FF; + rt = 0x80000002; + resulth = 0x00; + resultl = 0x800003FB; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaq_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = dsp >> 17 & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c b/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c new file mode 100644 index 0000000000..ce864844d9 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpaq_sa_l_w.c @@ -0,0 +1,77 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 0, acl = 0; + int resulth, resultl, resultdsp; + + rs = 0x80000000; + rt = 0x80000000; + resulth = 0x7FFFFFFF; + resultl = 0xFFFFFFFF; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %0, $ac1\n\t" + "dpaq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 0x12; + acl = 0x48; + rs = 0x80000000; + rt = 0x80000000; + + resulth = 0x7FFFFFFF; + resultl = 0xFFFFFFFF; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %0, $ac1\n\t" + "dpaq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 0x741532A0; + acl = 0xfceabb08; + rs = 0x80000000; + rt = 0x80000000; + + resulth = 0x7fffffff; + resultl = 0xffffffff; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %0, $ac1\n\t" + "dpaq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/dpau_h_qbl.c b/tests/tcg/mips/mips32-dsp/dpau_h_qbl.c new file mode 100644 index 0000000000..6017b5e73a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpau_h_qbl.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 3; + int resulth, resultl; + + rs = 0x800000FF; + rt = 0x80000002; + resulth = 0x05; + resultl = 0x4003; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpau.h.qbl $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/dpau_h_qbr.c b/tests/tcg/mips/mips32-dsp/dpau_h_qbr.c new file mode 100644 index 0000000000..e4abb2e2af --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpau_h_qbr.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 3; + int resulth, resultl; + + rs = 0x800000FF; + rt = 0x80000002; + resulth = 0x05; + resultl = 0x0201; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpau.h.qbr $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c b/tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c new file mode 100644 index 0000000000..22ab4d57ba --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpsq_s_w_ph.c @@ -0,0 +1,45 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xEE9794A3; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_s.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + ach = 0x1424Ef1f; + acl = 0x1035219A; + rs = 0x800083AD; + rt = 0x80003721; + resulth = 0x1424ef1e; + resultl = 0x577ed901; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_s.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c b/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c new file mode 100644 index 0000000000..b7b73fdb66 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpsq_sa_l_w.c @@ -0,0 +1,55 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 5, acl = 5; + int resulth, resultl, resultdsp; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0xfdf4cbe0; + resultl = 0xd138776b; + resultdsp = 0x00; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 0x54321123; + acl = 5; + rs = 0x80000000; + rt = 0x80000000; + + resulth = 0xd4321123; + resultl = 0x06; + resultdsp = 0x01; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c b/tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c new file mode 100644 index 0000000000..94e2bf6254 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpsu_h_qbl.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xFFFFFEE5; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsu.h.qbl $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c b/tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c new file mode 100644 index 0000000000..a1e6635631 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/dpsu_h_qbr.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xFFFFE233; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsu.h.qbr $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extp.c b/tests/tcg/mips/mips32-dsp/extp.c new file mode 100644 index 0000000000..21a67af216 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extp.c @@ -0,0 +1,44 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + result = 0x000C; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 14) & 0x01; + assert(dsp == 0); + assert(result == rt); + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 14) & 0x01; + assert(dsp == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extpdp.c b/tests/tcg/mips/mips32-dsp/extpdp.c new file mode 100644 index 0000000000..15ba0828fb --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extpdp.c @@ -0,0 +1,46 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp, pos, efi; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + result = 0x000C; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl) + ); + pos = dsp & 0x3F; + efi = (dsp >> 14) & 0x01; + assert(pos == 3); + assert(efi == 0); + assert(result == rt); + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl) + ); + efi = (dsp >> 14) & 0x01; + assert(efi == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extpdpv.c b/tests/tcg/mips/mips32-dsp/extpdpv.c new file mode 100644 index 0000000000..f5774eed3c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extpdpv.c @@ -0,0 +1,47 @@ +#include +#include + +int main() +{ + int rt, rs, ach, acl, dsp, pos, efi; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0x000C; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl), "r"(rs) + ); + pos = dsp & 0x3F; + efi = (dsp >> 14) & 0x01; + assert(pos == 3); + assert(efi == 0); + assert(result == rt); + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl), "r"(rs) + ); + efi = (dsp >> 14) & 0x01; + assert(efi == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extpv.c b/tests/tcg/mips/mips32-dsp/extpv.c new file mode 100644 index 0000000000..401b94afad --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extpv.c @@ -0,0 +1,45 @@ +#include +#include + +int main() +{ + int rt, ac, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + ac = 0x03; + result = 0x000C; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl), "r"(ac) + ); + dsp = (dsp >> 14) & 0x01; + assert(dsp == 0); + assert(result == rt); + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl), "r"(ac) + ); + dsp = (dsp >> 14) & 0x01; + assert(dsp == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extr_r_w.c b/tests/tcg/mips/mips32-dsp/extr_r_w.c new file mode 100644 index 0000000000..0beeefd366 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extr_r_w.c @@ -0,0 +1,48 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + result = 0xA0001699; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_r.w %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4D; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_r.w %0, $ac1, 0x04\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 0); + assert(result == rt); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extr_rs_w.c b/tests/tcg/mips/mips32-dsp/extr_rs_w.c new file mode 100644 index 0000000000..24c748db20 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extr_rs_w.c @@ -0,0 +1,48 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + result = 0x7FFFFFFF; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_rs.w %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4D; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_rs.w %0, $ac1, 0x04\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 0); + assert(result == rt); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extr_s_h.c b/tests/tcg/mips/mips32-dsp/extr_s_h.c new file mode 100644 index 0000000000..b2129134c8 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extr_s_h.c @@ -0,0 +1,63 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + result = 0x00007FFF; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_s.h %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); + + ach = 0xffffffff; + acl = 0x12344321; + result = 0xFFFF8000; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_s.h %0, $ac1, 0x08\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); + + /* Clear dsp */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + ach = 0x00; + acl = 0x4321; + result = 0x432; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_s.h %0, $ac1, 0x04\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 0); + assert(result == rt); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extr_w.c b/tests/tcg/mips/mips32-dsp/extr_w.c new file mode 100644 index 0000000000..02ab9ecaae --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extr_w.c @@ -0,0 +1,48 @@ +#include +#include + +int main() +{ + int rt, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + result = 0xA0001699; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr.w %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4C; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr.w %0, $ac1, 0x04\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 0); + assert(result == rt); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extrv_r_w.c b/tests/tcg/mips/mips32-dsp/extrv_r_w.c new file mode 100644 index 0000000000..005807b142 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extrv_r_w.c @@ -0,0 +1,54 @@ +#include +#include + +int main() +{ + int rt, rs, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0xA0001699; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_r.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 4; + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4D; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_r.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 0); + assert(result == rt); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extrv_rs_w.c b/tests/tcg/mips/mips32-dsp/extrv_rs_w.c new file mode 100644 index 0000000000..c2d8513bb6 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extrv_rs_w.c @@ -0,0 +1,52 @@ +#include +#include + +int main() +{ + int rt, rs, ach, acl, dsp; + int result; + + rs = 0x03; + ach = 0x05; + acl = 0xB4CB; + result = 0x7FFFFFFF; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_rs.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 0x04; + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4D; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_rs.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 0); + assert(result == rt); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extrv_s_h.c b/tests/tcg/mips/mips32-dsp/extrv_s_h.c new file mode 100644 index 0000000000..8c13b5eda5 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extrv_s_h.c @@ -0,0 +1,71 @@ +#include +#include + +int main() +{ + int rt, rs, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0x00007FFF; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_s.h %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); + + rs = 0x08; + ach = 0xffffffff; + acl = 0x12344321; + result = 0xFFFF8000; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_s.h %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); + + /* Clear dsp */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 0x04; + ach = 0x00; + acl = 0x4321; + result = 0x432; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_s.h %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 0); + assert(result == rt); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/extrv_w.c b/tests/tcg/mips/mips32-dsp/extrv_w.c new file mode 100644 index 0000000000..9cb493df39 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/extrv_w.c @@ -0,0 +1,54 @@ +#include +#include + +int main() +{ + int rt, rs, ach, acl, dsp; + int result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0xA0001699; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 1); + assert(result == rt); + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 4; + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4C; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + assert(dsp == 0); + assert(result == rt); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/insv.c b/tests/tcg/mips/mips32-dsp/insv.c new file mode 100644 index 0000000000..7e3b047606 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/insv.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rt, rs, dsp; + int result; + + /* msb = 10, lsb = 5 */ + dsp = 0x305; + rt = 0x12345678; + rs = 0x87654321; + result = 0x12345338; + __asm + ("wrdsp %2, 0x03\n\t" + "insv %0, %1\n\t" + : "+r"(rt) + : "r"(rs), "r"(dsp) + ); + assert(rt == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/lbux.c b/tests/tcg/mips/mips32-dsp/lbux.c new file mode 100644 index 0000000000..2337abea2a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/lbux.c @@ -0,0 +1,25 @@ +#include +#include + +int main(void) +{ + int value, rd; + int *p; + unsigned long addr, index; + int result; + + value = 0xBCDEF389; + p = &value; + addr = (unsigned long)p; + index = 0; + result = value & 0xFF; + __asm + ("lbux %0, %1(%2)\n\t" + : "=r"(rd) + : "r"(index), "r"(addr) + ); + + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/lhx.c b/tests/tcg/mips/mips32-dsp/lhx.c new file mode 100644 index 0000000000..10be3b385f --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/lhx.c @@ -0,0 +1,25 @@ +#include +#include + +int main(void) +{ + int value, rd; + int *p; + unsigned long addr, index; + int result; + + value = 0xBCDEF389; + p = &value; + addr = (unsigned long)p; + index = 0; + result = 0xFFFFF389; + __asm + ("lhx %0, %1(%2)\n\t" + : "=r"(rd) + : "r"(index), "r"(addr) + ); + + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/lwx.c b/tests/tcg/mips/mips32-dsp/lwx.c new file mode 100644 index 0000000000..e6543c9e7e --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/lwx.c @@ -0,0 +1,25 @@ +#include +#include + +int main(void) +{ + int value, rd; + int *p; + unsigned long addr, index; + int result; + + value = 0xBCDEF389; + p = &value; + addr = (unsigned long)p; + index = 0; + result = 0xBCDEF389; + __asm + ("lwx %0, %1(%2)\n\t" + : "=r"(rd) + : "r"(index), "r"(addr) + ); + + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/madd.c b/tests/tcg/mips/mips32-dsp/madd.c new file mode 100644 index 0000000000..af4bfcfe9d --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/madd.c @@ -0,0 +1,31 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int acho, aclo; + int resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0x01; + rt = 0x01; + resulth = 0x05; + resultl = 0xB4CC; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "madd $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/maddu.c b/tests/tcg/mips/mips32-dsp/maddu.c new file mode 100644 index 0000000000..af4bfcfe9d --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/maddu.c @@ -0,0 +1,31 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int acho, aclo; + int resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0x01; + rt = 0x01; + resulth = 0x05; + resultl = 0xB4CC; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "madd $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/main.c b/tests/tcg/mips/mips32-dsp/main.c new file mode 100644 index 0000000000..b296b20c92 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/main.c @@ -0,0 +1,6 @@ +#include + +int main() +{ + printf("hello world\n"); +} diff --git a/tests/tcg/mips/mips32-dsp/maq_s_w_phl.c b/tests/tcg/mips/mips32-dsp/maq_s_w_phl.c new file mode 100644 index 0000000000..292d68566d --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/maq_s_w_phl.c @@ -0,0 +1,55 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int dsp; + int acho, aclo; + int resulth, resultl; + int resdsp; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF060000; + rt = 0xCB000000; + resulth = 0x04; + resultl = 0x947438CB; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.w.phl $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); + + achi = 0x06; + acli = 0xB4CB; + rs = 0x80000000; + rt = 0x80000000; + resulth = 0x6; + resultl = 0x8000b4ca; + resdsp = 1; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_s.w.phl $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); + assert(((dsp >> 17) & 0x01) == resdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/maq_s_w_phr.c b/tests/tcg/mips/mips32-dsp/maq_s_w_phr.c new file mode 100644 index 0000000000..7b2ef2ab71 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/maq_s_w_phr.c @@ -0,0 +1,55 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int dsp; + int acho, aclo; + int resulth, resultl; + int resdsp; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF06; + rt = 0xCB00; + resulth = 0x04; + resultl = 0x947438CB; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.w.phr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); + + achi = 0x06; + acli = 0xB4CB; + rs = 0x8000; + rt = 0x8000; + resulth = 0x6; + resultl = 0x8000b4ca; + resdsp = 1; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_s.w.phr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); + assert(((dsp >> 17) & 0x01) == resdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c b/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c new file mode 100644 index 0000000000..a756991723 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/maq_sa_w_phl.c @@ -0,0 +1,55 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int dsp; + int acho, aclo; + int resulth, resultl; + int resdsp; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF060000; + rt = 0xCB000000; + resulth = 0x00; + resultl = 0x7FFFFFFF; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_sa.w.phl $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); + + achi = 0x06; + acli = 0xB4CB; + rs = 0x80000000; + rt = 0x80000000; + resulth = 0x00; + resultl = 0x7fffffff; + resdsp = 0x01; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.phl $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); + assert(((dsp >> 17) & 0x01) == 0x01); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c b/tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c new file mode 100644 index 0000000000..d6498f8dfd --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/maq_sa_w_phr.c @@ -0,0 +1,55 @@ +#include +#include + +int main() +{ + int rt, rs; + int achi, acli; + int dsp; + int acho, aclo; + int resulth, resultl; + int resdsp; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF06; + rt = 0xCB00; + resulth = 0x00; + resultl = 0x7FFFFFFF; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_sa.w.phr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); + + achi = 0x06; + acli = 0xB4CB; + rs = 0x8000; + rt = 0x8000; + resulth = 0x00; + resultl = 0x7fffffff; + resdsp = 0x01; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.phr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(resulth == acho); + assert(resultl == aclo); + assert(((dsp >> 17) & 0x01) == 0x01); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/mfhi.c b/tests/tcg/mips/mips32-dsp/mfhi.c new file mode 100644 index 0000000000..43a80669d1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mfhi.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int achi, acho; + int result; + + achi = 0x004433; + result = 0x004433; + + __asm + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + : "=r"(acho) + : "r"(achi) + ); + assert(result == acho); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/mflo.c b/tests/tcg/mips/mips32-dsp/mflo.c new file mode 100644 index 0000000000..caeafdb05c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mflo.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int acli, aclo; + int result; + + acli = 0x004433; + result = 0x004433; + + __asm + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + : "=r"(aclo) + : "r"(acli) + ); + assert(result == aclo); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/modsub.c b/tests/tcg/mips/mips32-dsp/modsub.c new file mode 100644 index 0000000000..c294eebb51 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/modsub.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0xFFFFFFFF; + rt = 0x000000FF; + result = 0xFFFFFF00; + __asm + ("modsub %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + rs = 0x00000000; + rt = 0x00CD1FFF; + result = 0x0000CD1F; + __asm + ("modsub %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/msub.c b/tests/tcg/mips/mips32-dsp/msub.c new file mode 100644 index 0000000000..5779e6f47a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/msub.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int achi, acli, rs, rt; + int acho, aclo; + int resulth, resultl; + + rs = 0x00BBAACC; + rt = 0x0B1C3D2F; + achi = 0x00004433; + acli = 0xFFCC0011; + resulth = 0xFFF81F29; + resultl = 0xB355089D; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "msub $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(acho == resulth); + assert(aclo == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/msubu.c b/tests/tcg/mips/mips32-dsp/msubu.c new file mode 100644 index 0000000000..e0f9b5a77a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/msubu.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int achi, acli, rs, rt; + int acho, aclo; + int resulth, resultl; + + rs = 0x00BBAACC; + rt = 0x0B1C3D2F; + achi = 0x00004433; + acli = 0xFFCC0011; + resulth = 0xFFF81F29; + resultl = 0xB355089D; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "msubu $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + assert(acho == resulth); + assert(aclo == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/mthi.c b/tests/tcg/mips/mips32-dsp/mthi.c new file mode 100644 index 0000000000..43a80669d1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mthi.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int achi, acho; + int result; + + achi = 0x004433; + result = 0x004433; + + __asm + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + : "=r"(acho) + : "r"(achi) + ); + assert(result == acho); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/mthlip.c b/tests/tcg/mips/mips32-dsp/mthlip.c new file mode 100644 index 0000000000..9549aae36a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mthlip.c @@ -0,0 +1,58 @@ +#include +#include + +int main() +{ + int rs, ach, acl, dsp; + int result, resulth, resultl; + + dsp = 0x07; + ach = 0x05; + acl = 0xB4CB; + rs = 0x00FFBBAA; + resulth = 0xB4CB; + resultl = 0x00FFBBAA; + result = 0x27; + + __asm + ("wrdsp %0, 0x01\n\t" + "mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "mthlip %3, $ac1\n\t" + "mfhi %1, $ac1\n\t" + "mflo %2, $ac1\n\t" + "rddsp %0\n\t" + : "+r"(dsp), "+r"(ach), "+r"(acl) + : "r"(rs) + ); + dsp = dsp & 0x3F; + assert(dsp == result); + assert(ach == resulth); + assert(acl == resultl); + + dsp = 0x3f; + ach = 0x05; + acl = 0xB4CB; + rs = 0x00FFBBAA; + resulth = 0xB4CB; + resultl = 0x00FFBBAA; + result = 0x3f; + + __asm + ("wrdsp %0, 0x01\n\t" + "mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "mthlip %3, $ac1\n\t" + "mfhi %1, $ac1\n\t" + "mflo %2, $ac1\n\t" + "rddsp %0\n\t" + : "+r"(dsp), "+r"(ach), "+r"(acl) + : "r"(rs) + ); + dsp = dsp & 0x3F; + assert(dsp == result); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/mtlo.c b/tests/tcg/mips/mips32-dsp/mtlo.c new file mode 100644 index 0000000000..caeafdb05c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mtlo.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int acli, aclo; + int result; + + acli = 0x004433; + result = 0x004433; + + __asm + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + : "=r"(aclo) + : "r"(acli) + ); + assert(result == aclo); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/muleq_s_w_phl.c b/tests/tcg/mips/mips32-dsp/muleq_s_w_phl.c new file mode 100644 index 0000000000..b3a5370fe5 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/muleq_s_w_phl.c @@ -0,0 +1,41 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80001234; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm + ("muleq_s.w.phl %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + rs = 0x12349988; + rt = 0x43219988; + result = 0x98be968; + resultdsp = 1; + + __asm + ("muleq_s.w.phl %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} + diff --git a/tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c b/tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c new file mode 100644 index 0000000000..8066d7d02a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/muleq_s_w_phr.c @@ -0,0 +1,40 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x8000; + rt = 0x8000; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm + ("muleq_s.w.phr %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + rs = 0x1234; + rt = 0x4321; + result = 0x98be968; + resultdsp = 1; + + __asm + ("muleq_s.w.phr %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c b/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c new file mode 100644 index 0000000000..66a382806a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbl.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0xFFFF0000; + resultdsp = 1; + + __asm + ("muleu_s.ph.qbl %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c b/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c new file mode 100644 index 0000000000..4cc6c8f7cf --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/muleu_s_ph_qbr.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x8000; + rt = 0x80004321; + result = 0xFFFF0000; + resultdsp = 1; + + __asm + ("muleu_s.ph.qbr %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c new file mode 100644 index 0000000000..c7206039ea --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mulq_rs_ph.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x7FFF098C; + resultdsp = 1; + + __asm + ("mulq_rs.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/mult.c b/tests/tcg/mips/mips32-dsp/mult.c new file mode 100644 index 0000000000..15e6fde92c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/mult.c @@ -0,0 +1,24 @@ +#include +#include + +int main() +{ + int rs, rt, ach, acl; + int result, resulth, resultl; + + rs = 0x00FFBBAA; + rt = 0x4B231000; + resulth = 0x4b0f01; + resultl = 0x71f8a000; + __asm + ("mult $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(ach), "=r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/multu.c b/tests/tcg/mips/mips32-dsp/multu.c new file mode 100644 index 0000000000..85d36c1b62 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/multu.c @@ -0,0 +1,24 @@ +#include +#include + +int main() +{ + int rs, rt, ach, acl; + int result, resulth, resultl; + + rs = 0x00FFBBAA; + rt = 0x4B231000; + resulth = 0x4b0f01; + resultl = 0x71f8a000; + __asm + ("multu $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(ach), "=r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/packrl_ph.c b/tests/tcg/mips/mips32-dsp/packrl_ph.c new file mode 100644 index 0000000000..1f8e699925 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/packrl_ph.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x56788765; + + __asm + ("packrl.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/pick_ph.c b/tests/tcg/mips/mips32-dsp/pick_ph.c new file mode 100644 index 0000000000..929a002e75 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/pick_ph.c @@ -0,0 +1,49 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result; + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x0A000000; + result = 0x12344321; + + __asm + ("wrdsp %3, 0x10\n\t" + "pick.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dsp) + ); + assert(rd == result); + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x03000000; + result = 0x12345678; + + __asm + ("wrdsp %3, 0x10\n\t" + "pick.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dsp) + ); + assert(rd == result); + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x00000000; + result = 0x87654321; + + __asm + ("wrdsp %3, 0x10\n\t" + "pick.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dsp) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/pick_qb.c b/tests/tcg/mips/mips32-dsp/pick_qb.c new file mode 100644 index 0000000000..a790475246 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/pick_qb.c @@ -0,0 +1,36 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result; + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x0f000000; + result = 0x12345678; + + __asm + ("wrdsp %3, 0x10\n\t" + "pick.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dsp) + ); + assert(rd == result); + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x00000000; + result = 0x87654321; + + __asm + ("wrdsp %3, 0x10\n\t" + "pick.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dsp) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/preceq_w_phl.c b/tests/tcg/mips/mips32-dsp/preceq_w_phl.c new file mode 100644 index 0000000000..bf70bf7d3a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceq_w_phl.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x87650000; + + __asm + ("preceq.w.phl %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/preceq_w_phr.c b/tests/tcg/mips/mips32-dsp/preceq_w_phr.c new file mode 100644 index 0000000000..3f885ef584 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceq_w_phr.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x43210000; + + __asm + ("preceq.w.phr %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c b/tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c new file mode 100644 index 0000000000..63b7a95683 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precequ_ph_qbl.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x43803280; + + __asm + ("precequ.ph.qbl %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c b/tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c new file mode 100644 index 0000000000..31627f0bd6 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precequ_ph_qbla.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x43802180; + + __asm + ("precequ.ph.qbla %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c b/tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c new file mode 100644 index 0000000000..b6f72d3cbf --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precequ_ph_qbr.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x21801080; + + __asm + ("precequ.ph.qbr %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c b/tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c new file mode 100644 index 0000000000..4764fd031d --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precequ_ph_qbra.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x32801080; + + __asm + ("precequ.ph.qbra %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c b/tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c new file mode 100644 index 0000000000..fa95c26cc4 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceu_ph_qbl.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x00870065; + + __asm + ("preceu.ph.qbl %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c b/tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c new file mode 100644 index 0000000000..021f21a744 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceu_ph_qbla.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x00870043; + + __asm + ("preceu.ph.qbla %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c b/tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c new file mode 100644 index 0000000000..03df18c72c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceu_ph_qbr.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x00430021; + + __asm + ("preceu.ph.qbr %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c b/tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c new file mode 100644 index 0000000000..634327618c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/preceu_ph_qbra.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0x00650021; + + __asm + ("preceu.ph.qbra %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/precrq_ph_w.c b/tests/tcg/mips/mips32-dsp/precrq_ph_w.c new file mode 100644 index 0000000000..25d45f1a9a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precrq_ph_w.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x12348765; + + __asm + ("precrq.ph.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/precrq_qb_ph.c b/tests/tcg/mips/mips32-dsp/precrq_qb_ph.c new file mode 100644 index 0000000000..fe23acce8c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precrq_qb_ph.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x12568743; + + __asm + ("precrq.qb.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c new file mode 100644 index 0000000000..3535b37a58 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precrq_rs_ph_w.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x12348765; + + __asm + ("precrq_rs.ph.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + rs = 0x7fffC678; + rt = 0x865432A0; + result = 0x7fff8654; + + __asm + ("precrq_rs.ph.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(((dsp >> 22) & 0x01) == 1); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c b/tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c new file mode 100644 index 0000000000..7481d5af3a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/precrqu_s_qb_ph.c @@ -0,0 +1,24 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x12345678; + rt = 0x87657FFF; + result = 0x24AC00FF; + + __asm + ("precrqu_s.qb.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + assert(((dsp >> 22) & 0x01) == 0x01); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/raddu_w_qb.c b/tests/tcg/mips/mips32-dsp/raddu_w_qb.c new file mode 100644 index 0000000000..77a983c0d2 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/raddu_w_qb.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rs; + int result; + + rs = 0x12345678; + result = 0x114; + + __asm + ("raddu.w.qb %0, %1\n\t" + : "=r"(rd) + : "r"(rs) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/rddsp.c b/tests/tcg/mips/mips32-dsp/rddsp.c new file mode 100644 index 0000000000..e8948ec1d9 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/rddsp.c @@ -0,0 +1,54 @@ +#include +#include + +int main() +{ + int dsp_i, dsp_o; + int ccond_i, outflag_i, efi_i, c_i, scount_i, pos_i; + int ccond_o, outflag_o, efi_o, c_o, scount_o, pos_o; + int ccond_r, outflag_r, efi_r, c_r, scount_r, pos_r; + + ccond_i = 0x000000BC;/* 4 */ + outflag_i = 0x0000001B;/* 3 */ + efi_i = 0x00000001;/* 5 */ + c_i = 0x00000001;/* 2 */ + scount_i = 0x0000000F;/* 1 */ + pos_i = 0x0000000C;/* 0 */ + + dsp_i = (ccond_i << 24) | \ + (outflag_i << 16) | \ + (efi_i << 14) | \ + (c_i << 13) | \ + (scount_i << 7) | \ + pos_i; + + ccond_r = ccond_i; + outflag_r = outflag_i; + efi_r = efi_i; + c_r = c_i; + scount_r = scount_i; + pos_r = pos_i; + + __asm + ("wrdsp %1, 0x3F\n\t" + "rddsp %0, 0x3F\n\t" + : "=r"(dsp_o) + : "r"(dsp_i) + ); + + ccond_o = (dsp_o >> 24) & 0xFF; + outflag_o = (dsp_o >> 16) & 0xFF; + efi_o = (dsp_o >> 14) & 0x01; + c_o = (dsp_o >> 14) & 0x01; + scount_o = (dsp_o >> 7) & 0x3F; + pos_o = dsp_o & 0x1F; + + assert(ccond_o == ccond_r); + assert(outflag_o == outflag_r); + assert(efi_o == efi_r); + assert(c_o == c_r); + assert(scount_o == scount_r); + assert(pos_o == pos_r); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/repl_ph.c b/tests/tcg/mips/mips32-dsp/repl_ph.c new file mode 100644 index 0000000000..21074953bd --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/repl_ph.c @@ -0,0 +1,23 @@ +#include +#include + +int main() +{ + int rd, result; + + result = 0x01BF01BF; + __asm + ("repl.ph %0, 0x1BF\n\t" + : "=r"(rd) + ); + assert(rd == result); + + result = 0x01FF01FF; + __asm + ("repl.ph %0, 0x01FF\n\t" + : "=r"(rd) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/repl_qb.c b/tests/tcg/mips/mips32-dsp/repl_qb.c new file mode 100644 index 0000000000..6631393ea1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/repl_qb.c @@ -0,0 +1,16 @@ +#include +#include + +int main() +{ + int rd, result; + + result = 0xBFBFBFBF; + __asm + ("repl.qb %0, 0xBF\n\t" + : "=r"(rd) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/replv_ph.c b/tests/tcg/mips/mips32-dsp/replv_ph.c new file mode 100644 index 0000000000..07fb15f1f7 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/replv_ph.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x56785678; + __asm + ("replv.ph %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/replv_qb.c b/tests/tcg/mips/mips32-dsp/replv_qb.c new file mode 100644 index 0000000000..dd1271fedf --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/replv_qb.c @@ -0,0 +1,19 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x78787878; + __asm + ("replv.qb %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shilo.c b/tests/tcg/mips/mips32-dsp/shilo.c new file mode 100644 index 0000000000..b686616d80 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shilo.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int ach, acl; + int resulth, resultl; + + ach = 0xBBAACCFF; + acl = 0x1C3B001D; + + resulth = 0x17755; + resultl = 0x99fe3876; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "shilo $ac1, 0x0F\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shilov.c b/tests/tcg/mips/mips32-dsp/shilov.c new file mode 100644 index 0000000000..f186032a14 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shilov.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rs, ach, acl; + int resulth, resultl; + + rs = 0x0F; + ach = 0xBBAACCFF; + acl = 0x1C3B001D; + + resulth = 0x17755; + resultl = 0x99fe3876; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "shilov $ac1, %2\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shll_ph.c b/tests/tcg/mips/mips32-dsp/shll_ph.c new file mode 100644 index 0000000000..b8f1ff5285 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shll_ph.c @@ -0,0 +1,24 @@ +#include +#include + +int main() +{ + int rd, rt, dsp; + int result, resultdsp; + + rt = 0x12345678; + result = 0xA000C000; + resultdsp = 1; + + __asm + ("shll.ph %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shll_qb.c b/tests/tcg/mips/mips32-dsp/shll_qb.c new file mode 100644 index 0000000000..8c1b91c635 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shll_qb.c @@ -0,0 +1,36 @@ +#include +#include + +int main() +{ + int rd, rt, dsp; + int result, resultdsp; + + rt = 0x87654321; + result = 0x87654321; + resultdsp = 0x00; + + __asm + ("shll.qb %0, %2, 0x00\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(rd == result); + + rt = 0x87654321; + result = 0x38281808; + resultdsp = 0x01; + + __asm + ("shll.qb %0, %2, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shll_s_ph.c b/tests/tcg/mips/mips32-dsp/shll_s_ph.c new file mode 100644 index 0000000000..910fea3b31 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shll_s_ph.c @@ -0,0 +1,24 @@ +#include +#include + +int main() +{ + int rd, rt, dsp; + int result, resultdsp; + + rt = 0x12345678; + result = 0x7FFF7FFF; + resultdsp = 0x01; + + __asm + ("shll_s.ph %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shll_s_w.c b/tests/tcg/mips/mips32-dsp/shll_s_w.c new file mode 100644 index 0000000000..628c752102 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shll_s_w.c @@ -0,0 +1,52 @@ +#include +#include + +int main() +{ + int rd, rt, dsp; + int result, resultdsp; + + rt = 0x82345678; + result = 0x82345678; + resultdsp = 0x00; + + __asm + ("shll_s.w %0, %2, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rt = 0x82345678; + result = 0x80000000; + resultdsp = 0x01; + + __asm + ("shll_s.w %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rt = 0x12345678; + result = 0x7FFFFFFF; + resultdsp = 0x01; + + __asm + ("shll_s.w %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shllv_ph.c b/tests/tcg/mips/mips32-dsp/shllv_ph.c new file mode 100644 index 0000000000..f98a6322dc --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shllv_ph.c @@ -0,0 +1,40 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x0; + rt = 0x12345678; + result = 0x12345678; + resultdsp = 0; + + __asm + ("shllv.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rs = 0x0B; + rt = 0x12345678; + result = 0xA000C000; + resultdsp = 1; + + __asm + ("shllv.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shllv_qb.c b/tests/tcg/mips/mips32-dsp/shllv_qb.c new file mode 100644 index 0000000000..6d8ff4a259 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shllv_qb.c @@ -0,0 +1,38 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x03; + rt = 0x87654321; + result = 0x38281808; + resultdsp = 0x01; + + __asm + ("shllv.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(rd == result); + + rs = 0x00; + rt = 0x87654321; + result = 0x87654321; + resultdsp = 0x01; + + __asm + ("shllv.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shllv_s_ph.c b/tests/tcg/mips/mips32-dsp/shllv_s_ph.c new file mode 100644 index 0000000000..fc9bd32765 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shllv_s_ph.c @@ -0,0 +1,40 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x0; + rt = 0x12345678; + result = 0x12345678; + resultdsp = 0x0; + + __asm + ("shllv_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rs = 0x0B; + rt = 0x12345678; + result = 0x7FFF7FFF; + resultdsp = 0x01; + + __asm + ("shllv_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shllv_s_w.c b/tests/tcg/mips/mips32-dsp/shllv_s_w.c new file mode 100644 index 0000000000..350c25617a --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shllv_s_w.c @@ -0,0 +1,40 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x0B; + rt = 0x12345678; + result = 0x7FFFFFFF; + resultdsp = 0x01; + + __asm + ("shllv_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rs = 0x0; + rt = 0x12345678; + result = 0x12345678; + resultdsp = 0x01; + + __asm + ("shllv_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shra_ph.c b/tests/tcg/mips/mips32-dsp/shra_ph.c new file mode 100644 index 0000000000..5b2d840a6b --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shra_ph.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0xF0EC0864; + + __asm + ("shra.ph %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + rt = 0x87654321; + result = 0x87654321; + + __asm + ("shra.ph %0, %1, 0x00\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shra_r_ph.c b/tests/tcg/mips/mips32-dsp/shra_r_ph.c new file mode 100644 index 0000000000..adc4ae68bd --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shra_r_ph.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0xF0ED0864; + + __asm + ("shra_r.ph %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + rt = 0x87654321; + result = 0x87654321; + + __asm + ("shra_r.ph %0, %1, 0x00\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shra_r_w.c b/tests/tcg/mips/mips32-dsp/shra_r_w.c new file mode 100644 index 0000000000..ec0cf2c72c --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shra_r_w.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x87654321; + result = 0xF0ECA864; + + __asm + ("shra_r.w %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + rt = 0x87654321; + result = 0x87654321; + + __asm + ("shra_r.w %0, %1, 0x0\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shrav_ph.c b/tests/tcg/mips/mips32-dsp/shrav_ph.c new file mode 100644 index 0000000000..6e42aaf8e1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shrav_ph.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x03; + rt = 0x87654321; + result = 0xF0EC0864; + + __asm + ("shrav.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + rs = 0x00; + rt = 0x87654321; + result = 0x87654321; + + __asm + ("shrav.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shrav_r_ph.c b/tests/tcg/mips/mips32-dsp/shrav_r_ph.c new file mode 100644 index 0000000000..f03b978d05 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shrav_r_ph.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x03; + rt = 0x87654321; + result = 0xF0ED0864; + + __asm + ("shrav_r.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + rs = 0x00; + rt = 0x87654321; + result = 0x87654321; + + __asm + ("shrav_r.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shrav_r_w.c b/tests/tcg/mips/mips32-dsp/shrav_r_w.c new file mode 100644 index 0000000000..2ab03bb5da --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shrav_r_w.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x03; + rt = 0x87654321; + result = 0xF0ECA864; + + __asm + ("shrav_r.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + rs = 0x00; + rt = 0x40000000; + result = 0x40000000; + + __asm + ("shrav_r.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + assert(rd == result); + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shrl_qb.c b/tests/tcg/mips/mips32-dsp/shrl_qb.c new file mode 100644 index 0000000000..a7e4e6a5e4 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shrl_qb.c @@ -0,0 +1,31 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x00010203; + + __asm + ("shrl.qb %0, %1, 0x05\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + rt = 0x12345678; + result = 0x12345678; + + __asm + ("shrl.qb %0, %1, 0x0\n\t" + : "=r"(rd) + : "r"(rt) + ); + + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/shrlv_qb.c b/tests/tcg/mips/mips32-dsp/shrlv_qb.c new file mode 100644 index 0000000000..db77f6d0e1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/shrlv_qb.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x05; + rt = 0x12345678; + result = 0x00010203; + + __asm + ("shrlv.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + rs = 0x00; + rt = 0x12345678; + result = 0x12345678; + + __asm + ("shrlv.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/subq_ph.c b/tests/tcg/mips/mips32-dsp/subq_ph.c new file mode 100644 index 0000000000..fdd7b38b64 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/subq_ph.c @@ -0,0 +1,40 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x77777777; + rt = 0x67654321; + result = 0x10123456; + resultdsp = 0x0; + + __asm + ("subq.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rs = 0x12345678; + rt = 0x87654321; + result = 0x8ACF1357; + resultdsp = 0x01; + + __asm + ("subq.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/subq_s_ph.c b/tests/tcg/mips/mips32-dsp/subq_s_ph.c new file mode 100644 index 0000000000..8e36dadef9 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/subq_s_ph.c @@ -0,0 +1,40 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x7FFF1357; + resultdsp = 0x01; + + __asm + ("subq_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rs = 0x12348000; + rt = 0x87657000; + result = 0x7FFF8000; + resultdsp = 0x01; + + __asm + ("subq_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/subq_s_w.c b/tests/tcg/mips/mips32-dsp/subq_s_w.c new file mode 100644 index 0000000000..09022e9c85 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/subq_s_w.c @@ -0,0 +1,58 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x7FFFFFFF; + resultdsp = 0x01; + + __asm + ("subq_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rs = 0x66666; + rt = 0x55555; + result = 0x11111; + resultdsp = 0x01; + + __asm + ("subq_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + +#if 0 + rs = 0x35555555; + rt = 0xf5555555; + result = 0x80000000; + resultdsp = 0x01; + + __asm + ("subq_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); +#endif + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/subu_qb.c b/tests/tcg/mips/mips32-dsp/subu_qb.c new file mode 100644 index 0000000000..4209096155 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/subu_qb.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x8BCF1357; + resultdsp = 0x01; + + __asm + ("subu.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/subu_s_qb.c b/tests/tcg/mips/mips32-dsp/subu_s_qb.c new file mode 100644 index 0000000000..3d650533d1 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/subu_s_qb.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x00001357; + resultdsp = 0x01; + + __asm + ("subu_s.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dsp/wrdsp.c b/tests/tcg/mips/mips32-dsp/wrdsp.c new file mode 100644 index 0000000000..e8948ec1d9 --- /dev/null +++ b/tests/tcg/mips/mips32-dsp/wrdsp.c @@ -0,0 +1,54 @@ +#include +#include + +int main() +{ + int dsp_i, dsp_o; + int ccond_i, outflag_i, efi_i, c_i, scount_i, pos_i; + int ccond_o, outflag_o, efi_o, c_o, scount_o, pos_o; + int ccond_r, outflag_r, efi_r, c_r, scount_r, pos_r; + + ccond_i = 0x000000BC;/* 4 */ + outflag_i = 0x0000001B;/* 3 */ + efi_i = 0x00000001;/* 5 */ + c_i = 0x00000001;/* 2 */ + scount_i = 0x0000000F;/* 1 */ + pos_i = 0x0000000C;/* 0 */ + + dsp_i = (ccond_i << 24) | \ + (outflag_i << 16) | \ + (efi_i << 14) | \ + (c_i << 13) | \ + (scount_i << 7) | \ + pos_i; + + ccond_r = ccond_i; + outflag_r = outflag_i; + efi_r = efi_i; + c_r = c_i; + scount_r = scount_i; + pos_r = pos_i; + + __asm + ("wrdsp %1, 0x3F\n\t" + "rddsp %0, 0x3F\n\t" + : "=r"(dsp_o) + : "r"(dsp_i) + ); + + ccond_o = (dsp_o >> 24) & 0xFF; + outflag_o = (dsp_o >> 16) & 0xFF; + efi_o = (dsp_o >> 14) & 0x01; + c_o = (dsp_o >> 14) & 0x01; + scount_o = (dsp_o >> 7) & 0x3F; + pos_o = dsp_o & 0x1F; + + assert(ccond_o == ccond_r); + assert(outflag_o == outflag_r); + assert(efi_o == efi_r); + assert(c_o == c_r); + assert(scount_o == scount_r); + assert(pos_o == pos_r); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/Makefile b/tests/tcg/mips/mips32-dspr2/Makefile new file mode 100644 index 0000000000..ed19581c7e --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/Makefile @@ -0,0 +1,71 @@ +-include ../../config-host.mak + +CROSS=mips64el-unknown-linux-gnu- + +SIM=qemu-mipsel +SIM_FLAGS=-cpu 74Kf + +CC = $(CROSS)gcc +CFLAGS = -mabi=32 -march=mips32r2 -mgp32 -mdspr2 -static + +TESTCASES = absq_s_qb.tst +TESTCASES += addqh_ph.tst +TESTCASES += addqh_r_ph.tst +TESTCASES += addqh_r_w.tst +TESTCASES += addqh_w.tst +TESTCASES += adduh_qb.tst +TESTCASES += adduh_r_qb.tst +TESTCASES += addu_ph.tst +TESTCASES += addu_s_ph.tst +TESTCASES += append.tst +TESTCASES += balign.tst +TESTCASES += cmpgdu_eq_qb.tst +TESTCASES += cmpgdu_le_qb.tst +TESTCASES += cmpgdu_lt_qb.tst +TESTCASES += dpaqx_sa_w_ph.tst +TESTCASES += dpa_w_ph.tst +TESTCASES += dpax_w_ph.tst +TESTCASES += dpaqx_s_w_ph.tst +TESTCASES += dpsqx_sa_w_ph.tst +TESTCASES += dpsqx_s_w_ph.tst +TESTCASES += dps_w_ph.tst +TESTCASES += dpsx_w_ph.tst +TESTCASES += mul_ph.tst +TESTCASES += mulq_rs_w.tst +TESTCASES += mulq_s_ph.tst +TESTCASES += mulq_s_w.tst +TESTCASES += mulsaq_s_w_ph.tst +TESTCASES += mulsa_w_ph.tst +TESTCASES += mul_s_ph.tst +TESTCASES += precr_qb_ph.tst +TESTCASES += precr_sra_ph_w.tst +TESTCASES += precr_sra_r_ph_w.tst +TESTCASES += prepend.tst +TESTCASES += shra_qb.tst +TESTCASES += shra_r_qb.tst +TESTCASES += shrav_qb.tst +TESTCASES += shrav_r_qb.tst +TESTCASES += shrl_ph.tst +TESTCASES += shrlv_ph.tst +TESTCASES += subqh_ph.tst +TESTCASES += subqh_r_ph.tst +TESTCASES += subqh_r_w.tst +TESTCASES += subqh_w.tst +TESTCASES += subuh_qb.tst +TESTCASES += subuh_r_qb.tst +TESTCASES += subu_ph.tst +TESTCASES += subu_s_ph.tst + +all: $(TESTCASES) + +%.tst: %.c + $(CC) $(CFLAGS) $< -o $@ + +check: $(TESTCASES) + @for case in $(TESTCASES); do \ + echo $(SIM) $(SIM_FLAGS) ./$$case;\ + $(SIM) $(SIM_FLAGS) ./$$case; \ + done + +clean: + $(RM) -rf $(TESTCASES) diff --git a/tests/tcg/mips/mips32-dspr2/absq_s_qb.c b/tests/tcg/mips/mips32-dspr2/absq_s_qb.c new file mode 100644 index 0000000000..af4683f304 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/absq_s_qb.c @@ -0,0 +1,35 @@ +#include +#include + +int main() +{ + int input, result, dsp; + int hope; + + input = 0x701BA35E; + hope = 0x701B5D5E; + + __asm + ("absq_s.qb %0, %1\n\t" + : "=r"(result) + : "r"(input) + ); + assert(result == hope); + + + input = 0x801BA35E; + hope = 0x7F1B5D5E; + + __asm + ("absq_s.qb %0, %2\n\t" + "rddsp %1\n\t" + : "=r"(result), "=r"(dsp) + : "r"(input) + ); + dsp = dsp >> 20; + dsp &= 0x01; + assert(dsp == 1); + assert(result == hope); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/addqh_ph.c b/tests/tcg/mips/mips32-dspr2/addqh_ph.c new file mode 100644 index 0000000000..921f0eaf33 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addqh_ph.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x706A13FE; + rt = 0x13065174; + result = 0x41B832B9; + __asm + ("addqh.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0x81000100; + rt = 0xc2000100; + result = 0xa1800100; + __asm + ("addqh.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/addqh_r_ph.c b/tests/tcg/mips/mips32-dspr2/addqh_r_ph.c new file mode 100644 index 0000000000..213ba37250 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addqh_r_ph.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x706A13FE; + rt = 0x13065174; + result = 0x41B832B9; + __asm + ("addqh_r.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0x81010100; + rt = 0xc2000100; + result = 0xa1810100; + __asm + ("addqh_r.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/addqh_r_w.c b/tests/tcg/mips/mips32-dspr2/addqh_r_w.c new file mode 100644 index 0000000000..75a75c50f3 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addqh_r_w.c @@ -0,0 +1,34 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x00000010; + rt = 0x00000001; + result = 0x00000009; + + __asm + ("addqh_r.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + assert(rd == result); + + rs = 0xFFFFFFFE; + rt = 0x00000001; + result = 0x00000000; + + __asm + ("addqh_r.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/addqh_w.c b/tests/tcg/mips/mips32-dspr2/addqh_w.c new file mode 100644 index 0000000000..de6926ebbb --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addqh_w.c @@ -0,0 +1,34 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x00000010; + rt = 0x00000001; + result = 0x00000008; + + __asm + ("addqh.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + assert(rd == result); + + rs = 0xFFFFFFFE; + rt = 0x00000001; + result = 0xFFFFFFFF; + + __asm + ("addqh.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/addu_ph.c b/tests/tcg/mips/mips32-dspr2/addu_ph.c new file mode 100644 index 0000000000..1d7a25a2a7 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addu_ph.c @@ -0,0 +1,33 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x00FF00FF; + rt = 0x00010001; + result = 0x01000100; + __asm + ("addu.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0x00011112; + __asm + ("addu.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + assert(((dsp >> 20) & 0x01) == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/addu_s_ph.c b/tests/tcg/mips/mips32-dspr2/addu_s_ph.c new file mode 100644 index 0000000000..979651bfc9 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/addu_s_ph.c @@ -0,0 +1,33 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x00FE00FE; + rt = 0x00020001; + result = 0x010000FF; + __asm + ("addu_s.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0xFFFF1112; + __asm + ("addu_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + assert(((dsp >> 20) & 0x01) == 1); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/adduh_qb.c b/tests/tcg/mips/mips32-dspr2/adduh_qb.c new file mode 100644 index 0000000000..a1f5d631b5 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/adduh_qb.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0xFF0055AA; + rt = 0x0113421B; + result = 0x80094B62; + __asm + ("adduh.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x7F800888; + __asm + ("adduh.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/adduh_r_qb.c b/tests/tcg/mips/mips32-dspr2/adduh_r_qb.c new file mode 100644 index 0000000000..81e98c190d --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/adduh_r_qb.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0xFF0055AA; + rt = 0x01112211; + result = 0x80093C5E; + __asm + ("adduh_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x80800888; + __asm + ("adduh_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/append.c b/tests/tcg/mips/mips32-dspr2/append.c new file mode 100644 index 0000000000..9a91e1650d --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/append.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rs, rt; + int result; + + rs = 0xFF0055AA; + rt = 0x0113421B; + result = 0x02268436; + __asm + ("append %0, %1, 0x01\n\t" + : "+r"(rt) + : "r"(rs) + ); + assert(rt == result); + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x0010111F; + __asm + ("append %0, %1, 0x04\n\t" + : "+r"(rt) + : "r"(rs) + ); + assert(rt == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/balign.c b/tests/tcg/mips/mips32-dspr2/balign.c new file mode 100644 index 0000000000..537cf0451c --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/balign.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rs, rt; + int result; + + rs = 0xFF0055AA; + rt = 0x0113421B; + result = 0x13421BFF; + __asm + ("balign %0, %1, 0x01\n\t" + : "+r"(rt) + : "r"(rs) + ); + assert(rt == result); + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x11FFFF0F; + __asm + ("balign %0, %1, 0x03\n\t" + : "+r"(rt) + : "r"(rs) + ); + assert(rt == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c b/tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c new file mode 100644 index 0000000000..2d6340d6fb --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/cmpgdu_eq_qb.c @@ -0,0 +1,37 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x02; + __asm + ("cmpgdu.eq.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm + ("cmpgdu.eq.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c b/tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c new file mode 100644 index 0000000000..a0ecdca2ac --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/cmpgdu_le_qb.c @@ -0,0 +1,37 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0F; + __asm + ("cmpgdu.le.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11707066; + result = 0x0B; + __asm + ("cmpgdu.le.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c b/tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c new file mode 100644 index 0000000000..dba99e392c --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/cmpgdu_lt_qb.c @@ -0,0 +1,37 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int dsp; + int result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0D; + __asm + ("cmpgdu.lt.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); + + rs = 0x11777066; + rt = 0x11777066; + result = 0x00; + __asm + ("cmpgdu.lt.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + assert(rd == result); + assert(dsp == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/dpa_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpa_w_ph.c new file mode 100644 index 0000000000..1cfbdb080f --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpa_w_ph.c @@ -0,0 +1,44 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x05; + resultl = 0x0302; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpa.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + ach = 6, acl = 7; + rs = 0xFFFF00FF; + rt = 0xFFFF0002; + resulth = 0x05; + resultl = 0xfffe0206; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpa.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c new file mode 100644 index 0000000000..ce87830246 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpaqx_s_w_ph.c @@ -0,0 +1,79 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 5, acl = 5; + int resulth, resultl, resultdsp; + + rs = 0x800000FF; + rt = 0x00018000; + resulth = 0x05; + resultl = 0x80000202; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 5; + acl = 5; + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x05; + resultl = 0x05FF; + /*********************************************************** + * Because of we set outflag at last time, although this + * time we set nothing, but it is stay the last time value. + **********************************************************/ + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 5; + acl = 5; + rs = 0x800000FF; + rt = 0x00028000; + resulth = 0x05; + resultl = 0x80000400; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c new file mode 100644 index 0000000000..798c4da5ca --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpaqx_sa_w_ph.c @@ -0,0 +1,53 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 5, acl = 5; + int resulth, resultl, resultdsp; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x00; + resultl = 0x7FFFFFFF; + resultdsp = 0x01; + __asm + ("wrdsp %2\n\t" + "mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_sa.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "+r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(dsp >> (16 + 1) == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 9; + acl = 0xb; + rs = 0x800000FF; + rt = 0x00018000; + resulth = 0x00; + resultl = 0x7fffffff; + resultdsp = 0x01; + __asm + ("wrdsp %2\n\t" + "mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_sa.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "+r"(dsp) + : "r"(rs), "r"(rt) + ); + assert(dsp >> (16 + 1) == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/dpax_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpax_w_ph.c new file mode 100644 index 0000000000..f75699755c --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpax_w_ph.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x05; + resultl = 0x0302; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpax.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/dps_w_ph.c b/tests/tcg/mips/mips32-dspr2/dps_w_ph.c new file mode 100644 index 0000000000..8303643d18 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dps_w_ph.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x04; + resultl = 0xFFFFFD08; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dps.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c new file mode 100644 index 0000000000..14cdd7c0f5 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpsqx_s_w_ph.c @@ -0,0 +1,54 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 5, acl = 5; + int resulth, resultl, resultdsp; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xAEA3E09B; + resultdsp = 0x00; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 0x99f13005; + acl = 0x51730062; + rs = 0x80008000; + rt = 0x80008000; + + resulth = 0x99f13004; + resultl = 0x51730064; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c new file mode 100644 index 0000000000..7da278eacc --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpsqx_sa_w_ph.c @@ -0,0 +1,53 @@ +#include +#include + +int main() +{ + int rs, rt, dsp; + int ach = 5, acl = 5; + int resulth, resultl, resultdsp; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x00; + resultl = 0x7FFFFFFF; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsqx_sa.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + ach = 0x8c0b354A; + acl = 0xbbc02249; + rs = 0x800023AD; + rt = 0x01648000; + resulth = 0xffffffff; + resultl = 0x80000000; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsqx_sa.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + assert(dsp == resultdsp); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c b/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c new file mode 100644 index 0000000000..6db59a4ccd --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/dpsx_w_ph.c @@ -0,0 +1,27 @@ +#include +#include + +int main() +{ + int rs, rt; + int ach = 5, acl = 5; + int resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xD751F050; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsx.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/mul_ph.c b/tests/tcg/mips/mips32-dspr2/mul_ph.c new file mode 100644 index 0000000000..c7e9d60d12 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mul_ph.c @@ -0,0 +1,47 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x03FB1234; + rt = 0x0BCC4321; + result = 0xF504F4B4; + resultdsp = 1; + + __asm + ("mul.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 0x00210010; + rt = 0x00110005; + result = 0x2310050; + resultdsp = 0; + + __asm + ("mul.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/mul_s_ph.c b/tests/tcg/mips/mips32-dspr2/mul_s_ph.c new file mode 100644 index 0000000000..33da110de8 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mul_s_ph.c @@ -0,0 +1,62 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x03FB1234; + rt = 0x0BCC4321; + result = 0x7fff7FFF; + resultdsp = 1; + + __asm + ("mul_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + rs = 0x7fffff00; + rt = 0xff007fff; + result = 0x80008000; + resultdsp = 1; + + __asm + ("mul_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 0x00320001; + rt = 0x00210002; + result = 0x06720002; + resultdsp = 0; + + __asm + ("mul_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/mulq_rs_w.c b/tests/tcg/mips/mips32-dspr2/mulq_rs_w.c new file mode 100644 index 0000000000..669405faf1 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulq_rs_w.c @@ -0,0 +1,36 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x80005555; + + __asm + ("mulq_rs.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0x80000000; + rt = 0x80000000; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm + ("mulq_rs.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/mulq_s_ph.c b/tests/tcg/mips/mips32-dspr2/mulq_s_ph.c new file mode 100644 index 0000000000..d0f7674a38 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulq_s_ph.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x7FFF098B; + resultdsp = 1; + + __asm + ("mulq_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/mulq_s_w.c b/tests/tcg/mips/mips32-dspr2/mulq_s_w.c new file mode 100644 index 0000000000..df148b7ffb --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulq_s_w.c @@ -0,0 +1,36 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x80005555; + + __asm + ("mulq_s.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0x80000000; + rt = 0x80000000; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm + ("mulq_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + assert(rd == result); + assert(dsp == resultdsp); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c b/tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c new file mode 100644 index 0000000000..a6940939ca --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulsa_w_ph.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rs, rt, ach, acl; + int resulth, resultl; + + ach = 0x05; + acl = 0x00BBDDCC; + rs = 0x80001234; + rt = 0x80004321; + resulth = 0x05; + resultl = 0x3BF5E918; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "mulsa.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c b/tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c new file mode 100644 index 0000000000..06c91a43e7 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/mulsaq_s_w_ph.c @@ -0,0 +1,29 @@ +#include +#include + +int main() +{ + int rs, rt, ach, acl; + int resulth, resultl; + + ach = 0x05; + acl = 0x00BBDDCC; + rs = 0x80001234; + rt = 0x80004321; + resulth = 0x05; + resultl = 0x772ff463; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "mulsaq_s.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + assert(ach == resulth); + assert(acl == resultl); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/precr_qb_ph.c b/tests/tcg/mips/mips32-dspr2/precr_qb_ph.c new file mode 100644 index 0000000000..3a2b3fde05 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/precr_qb_ph.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x34786521; + + __asm + ("precr.qb.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(result == rd); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c b/tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c new file mode 100644 index 0000000000..5c9baab03d --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/precr_sra_ph_w.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x43215678; + + __asm + ("precr_sra.ph.w %0, %1, 0x00\n\t" + : "+r"(rt) + : "r"(rs) + ); + assert(result == rt); + + rs = 0x12345678; + rt = 0x87654321; + result = 0xFFFF0000; + + __asm + ("precr_sra.ph.w %0, %1, 0x1F\n\t" + : "+r"(rt) + : "r"(rs) + ); + assert(result == rt); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c b/tests/tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c new file mode 100644 index 0000000000..6474a108c0 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/precr_sra_r_ph_w.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x43215678; + + __asm + ("precr_sra_r.ph.w %0, %1, 0x00\n\t" + : "+r"(rt) + : "r"(rs) + ); + assert(result == rt); + + rs = 0x12345678; + rt = 0x87654321; + result = 0xFFFF0000; + + __asm + ("precr_sra_r.ph.w %0, %1, 0x1F\n\t" + : "+r"(rt) + : "r"(rs) + ); + assert(result == rt); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/prepend.c b/tests/tcg/mips/mips32-dspr2/prepend.c new file mode 100644 index 0000000000..f6bcd47b2d --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/prepend.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x87654321; + __asm + ("prepend %0, %1, 0x00\n\t" + : "+r"(rt) + : "r"(rs) + ); + assert(rt == result); + + rs = 0x12345678; + rt = 0x87654321; + result = 0xACF10ECA; + __asm + ("prepend %0, %1, 0x0F\n\t" + : "+r"(rt) + : "r"(rs) + ); + assert(rt == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/shra_qb.c b/tests/tcg/mips/mips32-dspr2/shra_qb.c new file mode 100644 index 0000000000..48193de87a --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shra_qb.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x02060A0F; + + __asm + ("shra.qb %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + rt = 0x87654321; + result = 0xF00C0804; + + __asm + ("shra.qb %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/shra_r_qb.c b/tests/tcg/mips/mips32-dspr2/shra_r_qb.c new file mode 100644 index 0000000000..29afa0e4b0 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shra_r_qb.c @@ -0,0 +1,30 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x02070B0F; + + __asm + ("shra_r.qb %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + rt = 0x87654321; + result = 0xF10D0804; + + __asm + ("shra_r.qb %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/shrav_qb.c b/tests/tcg/mips/mips32-dspr2/shrav_qb.c new file mode 100644 index 0000000000..b21e1b7ca6 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shrav_qb.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x03; + rt = 0x12345678; + result = 0x02060A0F; + + __asm + ("shrav.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + rs = 0x03; + rt = 0x87654321; + result = 0xF00C0804; + + __asm + ("shrav.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/shrav_r_qb.c b/tests/tcg/mips/mips32-dspr2/shrav_r_qb.c new file mode 100644 index 0000000000..9ea8aa0cbb --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shrav_r_qb.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x03; + rt = 0x12345678; + result = 0x02070B0F; + + __asm + ("shrav_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + rs = 0x03; + rt = 0x87654321; + result = 0xF10D0804; + + __asm + ("shrav_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/shrl_ph.c b/tests/tcg/mips/mips32-dspr2/shrl_ph.c new file mode 100644 index 0000000000..724b9a7a46 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shrl_ph.c @@ -0,0 +1,20 @@ +#include +#include + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x009102B3; + + __asm + ("shrl.ph %0, %1, 0x05\n\t" + : "=r"(rd) + : "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/shrlv_ph.c b/tests/tcg/mips/mips32-dspr2/shrlv_ph.c new file mode 100644 index 0000000000..ac79aa69ac --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/shrlv_ph.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x05; + rt = 0x12345678; + result = 0x009102B3; + + __asm + ("shrlv.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/subqh_ph.c b/tests/tcg/mips/mips32-dspr2/subqh_ph.c new file mode 100644 index 0000000000..dbc096734c --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subqh_ph.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456709AB; + + __asm + ("subqh.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/subqh_r_ph.c b/tests/tcg/mips/mips32-dspr2/subqh_r_ph.c new file mode 100644 index 0000000000..24ef0f1aeb --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subqh_r_ph.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456809AC; + + __asm + ("subqh_r.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/subqh_r_w.c b/tests/tcg/mips/mips32-dspr2/subqh_r_w.c new file mode 100644 index 0000000000..d460f8630f --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subqh_r_w.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456789AC; + + __asm + ("subqh_r.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/subqh_w.c b/tests/tcg/mips/mips32-dspr2/subqh_w.c new file mode 100644 index 0000000000..42be3deb80 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subqh_w.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456789AB; + + __asm + ("subqh.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/subu_ph.c b/tests/tcg/mips/mips32-dspr2/subu_ph.c new file mode 100644 index 0000000000..0d39a017c7 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subu_ph.c @@ -0,0 +1,40 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x87654321; + rt = 0x11111111; + result = 0x76543210; + resultdsp = 0x00; + + __asm + ("subu.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + rs = 0x87654321; + rt = 0x12345678; + result = 0x7531ECA9; + resultdsp = 0x01; + + __asm + ("subu.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/subu_s_ph.c b/tests/tcg/mips/mips32-dspr2/subu_s_ph.c new file mode 100644 index 0000000000..8e4da4f3e5 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subu_s_ph.c @@ -0,0 +1,25 @@ +#include +#include + +int main() +{ + int rd, rs, rt, dsp; + int result, resultdsp; + + rs = 0x87654321; + rt = 0x12345678; + result = 0x75310000; + resultdsp = 0x01; + + __asm + ("subu_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + assert(dsp == resultdsp); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/subuh_qb.c b/tests/tcg/mips/mips32-dspr2/subuh_qb.c new file mode 100644 index 0000000000..92cfc764b8 --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subuh_qb.c @@ -0,0 +1,21 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0xC5E7092B; + + __asm + ("subuh.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips32-dspr2/subuh_r_qb.c b/tests/tcg/mips/mips32-dspr2/subuh_r_qb.c new file mode 100644 index 0000000000..dac81d47db --- /dev/null +++ b/tests/tcg/mips/mips32-dspr2/subuh_r_qb.c @@ -0,0 +1,32 @@ +#include +#include + +int main() +{ + int rd, rs, rt; + int result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0xC6E80A2C; + + __asm + ("subuh_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + rs = 0xBEFC292A; + rt = 0x9205C1B4; + result = 0x167cb4bb; + + __asm + ("subuh_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + assert(rd == result); + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/Makefile b/tests/tcg/mips/mips64-dsp/Makefile new file mode 100644 index 0000000000..b2ac6b3ffd --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/Makefile @@ -0,0 +1,306 @@ + +CROSS_COMPILE ?= mips64el-unknown-linux-gnu- + +SIM = qemu-system-mips64el +SIMFLAGS = -nographic -cpu mips64dspr2 -kernel + +AS = $(CROSS_COMPILE)as +LD = $(CROSS_COMPILE)ld +CC = $(CROSS_COMPILE)gcc +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +STRIP = $(CROSS_COMPILE)strip +RANLIB = $(CROSS_COMPILE)ranlib +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump + +VECTORS_OBJ ?= ./head.o ./printf.o + +HEAD_FLAGS ?= -nostdinc -mabi=64 -G 0 -mno-abicalls -fno-pic -pipe \ + -msoft-float -march=mips64 -Wa,-mips64 -Wa,--trap \ + -msym32 -DKBUILD_64BIT_SYM32 -I./ + +CFLAGS ?= -nostdinc -mabi=64 -G 0 -mno-abicalls -fno-pic -fno-builtin \ + -pipe -march=mips64r2 -mgp64 -mdsp -static -Wa,--trap -msym32 \ + -DKBUILD_64BIT_SYM32 -I./ + +LDFLAGS = -T./mips_boot.lds -L./ +FLAGS = -nostdlib -mabi=64 -march=mips64r2 -mgp64 -mdsp + + +#TESTCASES = absq_s_ob.tst +TESTCASES = absq_s_ph.tst +TESTCASES += absq_s_pw.tst +TESTCASES += absq_s_qh.tst +TESTCASES += absq_s_w.tst +TESTCASES += addq_ph.tst +TESTCASES += addq_pw.tst +TESTCASES += addq_qh.tst +TESTCASES += addq_s_ph.tst +TESTCASES += addq_s_pw.tst +TESTCASES += addq_s_qh.tst +TESTCASES += addq_s_w.tst +TESTCASES += addsc.tst +TESTCASES += addu_ob.tst +TESTCASES += addu_qb.tst +TESTCASES += addu_s_ob.tst +TESTCASES += addu_s_qb.tst +TESTCASES += addwc.tst +TESTCASES += bitrev.tst +TESTCASES += bposge32.tst +TESTCASES += bposge64.tst +TESTCASES += cmp_eq_ph.tst +TESTCASES += cmp_eq_pw.tst +TESTCASES += cmp_eq_qh.tst +TESTCASES += cmpgu_eq_ob.tst +TESTCASES += cmpgu_eq_qb.tst +TESTCASES += cmpgu_le_ob.tst +TESTCASES += cmpgu_le_qb.tst +TESTCASES += cmpgu_lt_ob.tst +TESTCASES += cmpgu_lt_qb.tst +TESTCASES += cmp_le_ph.tst +TESTCASES += cmp_le_pw.tst +TESTCASES += cmp_le_qh.tst +TESTCASES += cmp_lt_ph.tst +TESTCASES += cmp_lt_pw.tst +TESTCASES += cmp_lt_qh.tst +TESTCASES += cmpu_eq_ob.tst +TESTCASES += cmpu_eq_qb.tst +TESTCASES += cmpu_le_ob.tst +TESTCASES += cmpu_le_qb.tst +TESTCASES += cmpu_lt_ob.tst +TESTCASES += cmpu_lt_qb.tst +#TESTCASES += dappend.tst +TESTCASES += dextp.tst +TESTCASES += dextpdp.tst +TESTCASES += dextpdpv.tst +TESTCASES += dextpv.tst +TESTCASES += dextr_l.tst +TESTCASES += dextr_r_l.tst +TESTCASES += dextr_rs_l.tst +TESTCASES += dextr_rs_w.tst +TESTCASES += dextr_r_w.tst +TESTCASES += dextr_s_h.tst +TESTCASES += dextrv_l.tst +TESTCASES += dextrv_r_l.tst +TESTCASES += dextrv_rs_l.tst +TESTCASES += dextrv_rs_w.tst +TESTCASES += dextrv_r_w.tst +TESTCASES += dextrv_s_h.tst +TESTCASES += dextrv_w.tst +TESTCASES += dextr_w.tst +TESTCASES += dinsv.tst +TESTCASES += dmadd.tst +TESTCASES += dmaddu.tst +TESTCASES += dmsub.tst +TESTCASES += dmsubu.tst +TESTCASES += dmthlip.tst +TESTCASES += dpaq_sa_l_pw.tst +TESTCASES += dpaq_sa_l_w.tst +TESTCASES += dpaq_s_w_ph.tst +TESTCASES += dpaq_s_w_qh.tst +TESTCASES += dpau_h_obl.tst +TESTCASES += dpau_h_obr.tst +TESTCASES += dpau_h_qbl.tst +TESTCASES += dpau_h_qbr.tst +TESTCASES += dpsq_sa_l_pw.tst +TESTCASES += dpsq_sa_l_w.tst +TESTCASES += dpsq_s_w_ph.tst +TESTCASES += dpsq_s_w_qh.tst +TESTCASES += dpsu_h_obl.tst +TESTCASES += dpsu_h_obr.tst +TESTCASES += dpsu_h_qbl.tst +TESTCASES += dpsu_h_qbr.tst +TESTCASES += dshilo.tst +TESTCASES += dshilov.tst +TESTCASES += extp.tst +TESTCASES += extpdp.tst +TESTCASES += extpdpv.tst +TESTCASES += extpv.tst +TESTCASES += extr_rs_w.tst +TESTCASES += extr_r_w.tst +TESTCASES += extr_s_h.tst +TESTCASES += extrv_rs_w.tst +TESTCASES += extrv_r_w.tst +TESTCASES += extrv_s_h.tst +TESTCASES += extrv_w.tst +TESTCASES += extr_w.tst +TESTCASES += insv.tst +TESTCASES += lbux.tst +TESTCASES += lhx.tst +TESTCASES += lwx.tst +TESTCASES += ldx.tst +TESTCASES += madd.tst +TESTCASES += maddu.tst +TESTCASES += maq_sa_w_phl.tst +TESTCASES += maq_sa_w_phr.tst +TESTCASES += maq_sa_w_qhll.tst +TESTCASES += maq_sa_w_qhlr.tst +TESTCASES += maq_sa_w_qhrl.tst +TESTCASES += maq_sa_w_qhrr.tst +TESTCASES += maq_s_l_pwl.tst +TESTCASES += maq_s_l_pwr.tst +TESTCASES += maq_s_w_phl.tst +TESTCASES += maq_s_w_phr.tst +TESTCASES += maq_s_w_qhll.tst +TESTCASES += maq_s_w_qhlr.tst +TESTCASES += maq_s_w_qhrl.tst +TESTCASES += maq_s_w_qhrr.tst +TESTCASES += mfhi.tst +TESTCASES += mflo.tst +TESTCASES += modsub.tst +TESTCASES += msub.tst +TESTCASES += msubu.tst +TESTCASES += mthi.tst +TESTCASES += mthlip.tst +TESTCASES += mtlo.tst +TESTCASES += muleq_s_pw_qhl.tst +TESTCASES += muleq_s_pw_qhr.tst +TESTCASES += muleq_s_w_phl.tst +TESTCASES += muleq_s_w_phr.tst +TESTCASES += muleu_s_ph_qbl.tst +TESTCASES += muleu_s_ph_qbr.tst +TESTCASES += muleu_s_qh_obl.tst +TESTCASES += muleu_s_qh_obr.tst +TESTCASES += mulq_rs_ph.tst +TESTCASES += mulq_rs_qh.tst +TESTCASES += mulsaq_s_l_pw.tst +TESTCASES += mulsaq_s_w_qh.tst +TESTCASES += mult.tst +TESTCASES += multu.tst +TESTCASES += packrl_ph.tst +TESTCASES += packrl_pw.tst +TESTCASES += pick_ob.tst +TESTCASES += pick_ph.tst +TESTCASES += pick_pw.tst +TESTCASES += pick_qb.tst +TESTCASES += pick_qh.tst +#TESTCASES += preceq_l_pwl.tst +#TESTCASES += preceq_l_pwr.tst +TESTCASES += preceq_pw_qhla.tst +TESTCASES += preceq_pw_qhl.tst +TESTCASES += preceq_pw_qhra.tst +TESTCASES += preceq_pw_qhr.tst +TESTCASES += precequ_ph_qbla.tst +TESTCASES += precequ_ph_qbl.tst +TESTCASES += precequ_ph_qbra.tst +TESTCASES += precequ_ph_qbr.tst +#TESTCASES += precequ_qh_obla.tst +#TESTCASES += precequ_qh_obl.tst +#TESTCASES += precequ_qh_obra.tst +#TESTCASES += precequ_qh_obr.tst +TESTCASES += preceq_w_phl.tst +TESTCASES += preceq_w_phr.tst +TESTCASES += preceu_ph_qbla.tst +TESTCASES += preceu_ph_qbl.tst +TESTCASES += preceu_ph_qbra.tst +TESTCASES += preceu_ph_qbr.tst +TESTCASES += preceu_qh_obla.tst +TESTCASES += preceu_qh_obl.tst +TESTCASES += preceu_qh_obra.tst +TESTCASES += preceu_qh_obr.tst +#TESTCASES += precr_ob_qh.tst +TESTCASES += precrq_ob_qh.tst +TESTCASES += precrq_ph_w.tst +TESTCASES += precrq_pw_l.tst +TESTCASES += precrq_qb_ph.tst +TESTCASES += precrq_qh_pw.tst +TESTCASES += precrq_rs_ph_w.tst +TESTCASES += precrq_rs_qh_pw.tst +TESTCASES += precrqu_s_ob_qh.tst +TESTCASES += precrqu_s_qb_ph.tst +#TESTCASES += precr_sra_qh_pw.tst +#TESTCASES += precr_sra_r_qh_pw.tst +#TESTCASES += prependd.tst +#TESTCASES += prependw.tst +#TESTCASES += raddu_l_ob.tst +TESTCASES += raddu_w_qb.tst +TESTCASES += rddsp.tst +TESTCASES += repl_ob.tst +TESTCASES += repl_ph.tst +TESTCASES += repl_pw.tst +TESTCASES += repl_qb.tst +TESTCASES += repl_qh.tst +TESTCASES += replv_ob.tst +TESTCASES += replv_ph.tst +TESTCASES += replv_pw.tst +TESTCASES += replv_qb.tst +TESTCASES += shilo.tst +TESTCASES += shilov.tst +TESTCASES += shll_ob.tst +TESTCASES += shll_ph.tst +TESTCASES += shll_pw.tst +TESTCASES += shll_qb.tst +TESTCASES += shll_qh.tst +TESTCASES += shll_s_ph.tst +TESTCASES += shll_s_pw.tst +TESTCASES += shll_s_qh.tst +TESTCASES += shll_s_w.tst +TESTCASES += shllv_ob.tst +TESTCASES += shllv_ph.tst +TESTCASES += shllv_pw.tst +TESTCASES += shllv_qb.tst +TESTCASES += shllv_qh.tst +TESTCASES += shllv_s_ph.tst +TESTCASES += shllv_s_pw.tst +TESTCASES += shllv_s_qh.tst +TESTCASES += shllv_s_w.tst +#TESTCASES += shra_ob.tst +TESTCASES += shra_ph.tst +TESTCASES += shra_pw.tst +TESTCASES += shra_qh.tst +#TESTCASES += shra_r_ob.tst +TESTCASES += shra_r_ph.tst +TESTCASES += shra_r_pw.tst +TESTCASES += shra_r_qh.tst +TESTCASES += shra_r_w.tst +TESTCASES += shrav_ph.tst +TESTCASES += shrav_pw.tst +TESTCASES += shrav_qh.tst +TESTCASES += shrav_r_ph.tst +TESTCASES += shrav_r_pw.tst +TESTCASES += shrav_r_qh.tst +TESTCASES += shrav_r_w.tst +TESTCASES += shrl_ob.tst +TESTCASES += shrl_qb.tst +#TESTCASES += shrl_qh.tst +TESTCASES += shrlv_ob.tst +TESTCASES += shrlv_qb.tst +#TESTCASES += shrlv_qh.tst +TESTCASES += subq_ph.tst +TESTCASES += subq_pw.tst +TESTCASES += subq_qh.tst +TESTCASES += subq_s_ph.tst +TESTCASES += subq_s_pw.tst +TESTCASES += subq_s_qh.tst +TESTCASES += subq_s_w.tst +TESTCASES += subu_ob.tst +TESTCASES += subu_qb.tst +TESTCASES += subu_s_ob.tst +TESTCASES += subu_s_qb.tst +TESTCASES += wrdsp.tst + +all: build + +head.o : head.S + $(Q)$(CC) $(HEAD_FLAGS) -D"STACK_TOP=0xffffffff80200000" -c $< -o $@ + +%.o : %.S + $(CC) $(CFLAGS) -c $< -o $@ + +%.o : %.c + $(CC) $(CFLAGS) -c $< -o $@ + +%.tst: %.o $(VECTORS_OBJ) + $(CC) $(VECTORS_OBJ) $(FLAGS) $(LDFLAGS) $< -o $@ + +build: $(VECTORS_OBJ) $(MIPSSOC_LIB) $(TESTCASES) + +check: $(VECTORS_OBJ) $(MIPSSOC_LIB) $(TESTCASES) + @for case in $(TESTCASES); do \ + echo $(SIM) $(SIMFLAGS) ./$$case; \ + $(SIM) $(SIMFLAGS) ./$$case & (sleep 1; killall $(SIM)); \ + done + +clean: + $(Q)rm -f *.o *.tst *.a diff --git a/tests/tcg/mips/mips64-dsp/absq_s_ob.c b/tests/tcg/mips/mips64-dsp/absq_s_ob.c new file mode 100644 index 0000000000..6214031578 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/absq_s_ob.c @@ -0,0 +1,63 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result, dspcontrol; + rt = 0x7F7F7F7F7F7F7F7F; + result = 0x7F7F7F7F7F7F7F7F; + + + __asm + (".set mips64\n\t" + "absq_s.ob %0 %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("absq_s.ob test 1 error\n"); + + return -1; + } + + __asm + ("rddsp %0\n\t" + : "=r"(rd) + ); + rd >> 20; + rd = rd & 0x1; + if (rd != 0) { + printf("absq_s.ob test 1 dspcontrol overflow flag error\n"); + + return -1; + } + + rt = 0x80FFFFFFFFFFFFFF; + result = 0x7F01010101010101; + + __asm + ("absq_s.ob %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("absq_s.ob test 2 error\n"); + + return -1; + } + + __asm + ("rddsp %0\n\t" + : "=r"(rd) + ); + rd = rd >> 20; + rd = rd & 0x1; + if (rd != 1) { + printf("absq_s.ob test 2 dspcontrol overflow flag error\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/absq_s_ph.c b/tests/tcg/mips/mips64-dsp/absq_s_ph.c new file mode 100644 index 0000000000..238416d438 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/absq_s_ph.c @@ -0,0 +1,37 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x10017EFD; + result = 0x10017EFD; + + __asm + ("absq_s.ph %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("absq_s.ph wrong\n"); + + return -1; + } + + rt = 0x8000A536; + result = 0x7FFF5ACA; + + __asm + ("absq_s.ph %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("absq_s.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/absq_s_pw.c b/tests/tcg/mips/mips64-dsp/absq_s_pw.c new file mode 100644 index 0000000000..48fc763b4f --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/absq_s_pw.c @@ -0,0 +1,66 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result, dspcontrol; + rd = 0; + rt = 0x7F7F7F7F7F7F7F7F; + result = 0x7F7F7F7F7F7F7F7F; + + + __asm + ("absq_s.pw %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("absq_s.pw test 1 error\n"); + + return -1; + } + + rd = 0; + __asm + ("rddsp %0\n\t" + : "=r"(rd) + ); + rd >> 20; + rd = rd & 0x1; + if (rd != 0) { + printf("absq_s.pw test 1 dspcontrol overflow flag error\n"); + + return -1; + } + + rd = 0; + rt = 0x80000000FFFFFFFF; + result = 0x7FFFFFFF00000001; + + __asm + ("absq_s.pw %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("absq_s.pw test 2 error\n"); + + return -1; + } + + rd = 0; + __asm + ("rddsp %0\n\t" + : "=r"(rd) + ); + rd = rd >> 20; + rd = rd & 0x1; + if (rd != 1) { + printf("absq_s.pw test 2 dspcontrol overflow flag error\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/absq_s_qh.c b/tests/tcg/mips/mips64-dsp/absq_s_qh.c new file mode 100644 index 0000000000..9001a9e164 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/absq_s_qh.c @@ -0,0 +1,40 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result, dspcontrol; + rd = 0; + rt = 0x7F7F7F7F7F7F7F7F; + result = 0x7F7F7F7F7F7F7F7F; + + + __asm + ("absq_s.qh %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("absq_s.qh test 1 error\n"); + + return -1; + } + + rd = 0; + rt = 0x8000FFFFFFFFFFFF; + result = 0x7FFF000100000001; + + __asm + ("absq_s.pw %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("absq_s.rw test 2 error\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/absq_s_w.c b/tests/tcg/mips/mips64-dsp/absq_s_w.c new file mode 100644 index 0000000000..414c8bd3f6 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/absq_s_w.c @@ -0,0 +1,48 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x80000000; + result = 0x7FFFFFFF; + __asm + ("absq_s.w %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("absq_s_w.ph wrong\n"); + + return -1; + } + + rt = 0x80030000; + result = 0x7FFD0000; + __asm + ("absq_s.w %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("absq_s_w.ph wrong\n"); + + return -1; + } + + rt = 0x31036080; + result = 0x31036080; + __asm + ("absq_s.w %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("absq_s_w.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addq_ph.c b/tests/tcg/mips/mips64-dsp/addq_ph.c new file mode 100644 index 0000000000..22a36d9805 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addq_ph.c @@ -0,0 +1,57 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0xFFFFFFFF; + rt = 0x10101010; + result = 0x100F100F; + __asm + ("addq.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("1 addq.ph wrong\n"); + + return -1; + } + + rs = 0x3712847D; + rt = 0x0031AF2D; + result = 0x374333AA; + __asm + ("addq.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("2 addq.ph wrong\n"); + + return -1; + } + + rs = 0x7fff847D; + rt = 0x0031AF2D; + result = 0xffffffff803033AA; + __asm + ("addq.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + __asm("rddsp %0\n\t" + : "=r"(dsp) + ); + + if (rd != result || (((dsp >> 20) & 0x01) != 1)) { + printf("3 addq.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addq_pw.c b/tests/tcg/mips/mips64-dsp/addq_pw.c new file mode 100644 index 0000000000..99a7668c0c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addq_pw.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + + rs = 0x123456787FFFFFFF; + rt = 0x1111111100000101; + result = 0x2345678980000100; + dspresult = 0x1; + + __asm + ("addq.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("addq.pw error\n"); + + return -1; + } + + rs = 0x1234567880FFFFFF; + rt = 0x1111111180000001; + result = 0x2345678901000000; + dspresult = 0x1; + + __asm + ("addq.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("addq.pw error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addq_qh.c b/tests/tcg/mips/mips64-dsp/addq_qh.c new file mode 100644 index 0000000000..4b874afb8a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addq_qh.c @@ -0,0 +1,28 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + + rs = 0x123456787FFF8010; + rt = 0x1111111100018000; + result = 0x2345678980000010; + dspresult = 0x1; + + __asm + ("addq.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + + if ((rd != result) || (dspreg != dspresult)) { + printf("addq.qh error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addq_s_ph.c b/tests/tcg/mips/mips64-dsp/addq_s_ph.c new file mode 100644 index 0000000000..ad84cdcfe0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addq_s_ph.c @@ -0,0 +1,84 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0xFFFFFFFF; + rt = 0x10101010; + result = 0x100F100F; + __asm + ("addq_s.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("1 addq_s.ph wrong\n"); + + return -1; + } + + rs = 0x3712847D; + rt = 0x0031AF2D; + result = 0x37438000; + __asm + ("addq_s.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + __asm + ("rddsp %0\n\t" + : "=r"(dsp) + ); + + if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) { + printf("2 addq_s.ph wrong\n"); + + return -1; + } + + rs = 0x7fff847D; + rt = 0x0031AF2D; + result = 0x7fff8000; + __asm + ("addq_s.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + __asm + ("rddsp %0\n\t" + : "=r"(dsp) + ); + + if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) { + printf("3 addq_s.ph wrong\n"); + + return -1; + } + + rs = 0x8030847D; + rt = 0x8a00AF2D; + result = 0xffffffff80008000; + __asm + ("addq_s.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + __asm + ("rddsp %0\n\t" + : "=r"(dsp) + ); + + if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) { + printf("4 addq_s.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addq_s_pw.c b/tests/tcg/mips/mips64-dsp/addq_s_pw.c new file mode 100644 index 0000000000..2e380bbfc5 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addq_s_pw.c @@ -0,0 +1,45 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + rs = 0x123456787FFFFFFF; + rt = 0x1111111100000001; + result = 0x234567897FFFFFFF; + dspresult = 0x1; + + __asm + ("addq_s.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("addq_s.pw error\n"); + + return -1; + } + + rs = 0x80FFFFFFE00000FF; + rt = 0x80000001200000DD; + result = 0x80000000000001DC; + dspresult = 0x01; + + __asm + ("addq_s.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("addq_s.pw error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addq_s_qh.c b/tests/tcg/mips/mips64-dsp/addq_s_qh.c new file mode 100644 index 0000000000..b638a2b93a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addq_s_qh.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + rs = 0x123456787FFF8000; + rt = 0x1111111100028000; + result = 0x234567897FFF8000; + dspresult = 0x1; + + __asm + ("addq_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("addq_s.qh error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addq_s_w.c b/tests/tcg/mips/mips64-dsp/addq_s_w.c new file mode 100644 index 0000000000..3e08f5d482 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addq_s_w.c @@ -0,0 +1,48 @@ +#include "io.h" + +int main() +{ + long long rd, rs, rt; + long long result; + + rt = 0x10017EFD; + rs = 0x11111111; + result = 0x2112900e; + + __asm + ("addq_s.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("addq_s.w error\n"); + } + + rt = 0x80017EFD; + rs = 0x81111111; + result = 0xffffffff80000000; + + __asm + ("addq_s.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("addq_s.w error\n"); + } + + rt = 0x7fffffff; + rs = 0x01111111; + result = 0x7fffffff; + + __asm + ("addq_s.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("addq_s.w error\n"); + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addsc.c b/tests/tcg/mips/mips64-dsp/addsc.c new file mode 100644 index 0000000000..4b684b9b99 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addsc.c @@ -0,0 +1,39 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x0000000F; + rt = 0x00000001; + result = 0x00000010; + __asm + ("addsc %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("1 addsc wrong\n"); + + return -1; + } + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x00001110; + __asm + ("addsc %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((rd != result) || (((dsp >> 13) & 0x01) != 1)) { + printf("2 addsc wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addu_ob.c b/tests/tcg/mips/mips64-dsp/addu_ob.c new file mode 100644 index 0000000000..17f9c668c0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addu_ob.c @@ -0,0 +1,28 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + + rs = 0x123456789ABCDEF0; + rt = 0x3456123498DEF390; + result = 0x468A68AC329AD180; + dspresult = 0x01; + + __asm + ("addu.ob %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + + if ((rd != result) || (dspreg != dspresult)) { + printf("addu.ob error\n\t"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addu_qb.c b/tests/tcg/mips/mips64-dsp/addu_qb.c new file mode 100644 index 0000000000..3b9b5fc5bb --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addu_qb.c @@ -0,0 +1,40 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x00FF00FF; + rt = 0x00010001; + result = 0x00000000; + __asm + ("addu.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) { + printf("1 addu.qb wrong\n"); + + return -1; + } + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0xFFFFFFFFFF011112; + __asm + ("addu.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) { + printf("2 addu.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addu_s_ob.c b/tests/tcg/mips/mips64-dsp/addu_s_ob.c new file mode 100644 index 0000000000..e89a4638b7 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addu_s_ob.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + rs = 0x123456789ABCDEF0; + rt = 0x3456123498DEF390; + result = 0x468A68ACFFFFFFFF; + dspresult = 0x01; + + __asm + ("addu_s.ob %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + + if ((rd != result) || (dspreg != dspresult)) { + printf("addu_s.ob error\n\t"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addu_s_qb.c b/tests/tcg/mips/mips64-dsp/addu_s_qb.c new file mode 100644 index 0000000000..cb84293ade --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addu_s_qb.c @@ -0,0 +1,40 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x10FF01FF; + rt = 0x10010001; + result = 0x20FF01FF; + __asm + ("addu_s.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((rd != result) || (((dsp >> 20) & 0x1) != 1)) { + printf("1 addu_s.qb error 1\n"); + + return -1; + } + + rs = 0xFFFFFFFFFFFF1111; + rt = 0x00020001; + result = 0xFFFFFFFFFFFF1112; + __asm + ("addu_s.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((rd != result) || (((dsp >> 20) & 0x1) != 1)) { + printf("2 addu_s.qb error 2\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/addwc.c b/tests/tcg/mips/mips64-dsp/addwc.c new file mode 100644 index 0000000000..5929cd2f5c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/addwc.c @@ -0,0 +1,59 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dspi, dspo; + long long result; + + rs = 0x10FF01FF; + rt = 0x10010001; + dspi = 0x00002000; + result = 0x21000201; + __asm + ("wrdsp %3\n" + "addwc %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dspi) + ); + if (rd != result) { + printf("1 addwc wrong\n"); + + return -1; + } + + rs = 0xFFFF1111; + rt = 0x00020001; + dspi = 0x00; + result = 0x00011112; + __asm + ("wrdsp %3\n" + "addwc %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dspi) + ); + if (rd != result) { + printf("2 addwc wrong\n"); + + return -1; + } + + rs = 0x8FFF1111; + rt = 0x80020001; + dspi = 0x00; + result = 0x10011112; + __asm + ("wrdsp %4\n" + "addwc %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspo) + : "r"(rs), "r"(rt), "r"(dspi) + ); + if ((rd != result) || (((dspo >> 20) & 0x01) != 1)) { + printf("3 addwc wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/bitrev.c b/tests/tcg/mips/mips64-dsp/bitrev.c new file mode 100644 index 0000000000..ac24ef3f5c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/bitrev.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x12345678; + result = 0x00001E6A; + + __asm + ("bitrev %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("bitrev wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/bposge32.c b/tests/tcg/mips/mips64-dsp/bposge32.c new file mode 100644 index 0000000000..97bce44602 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/bposge32.c @@ -0,0 +1,50 @@ +#include "io.h" + +int main(void) +{ + long long dsp, sum; + long long result; + + dsp = 0x20; + sum = 0x01; + result = 0x02; + + __asm + ("wrdsp %1\n\t" + "bposge32 test1\n\t" + "nop\n\t" + "addi %0, 0xA2\n\t" + "nop\n\t" + "test1:\n\t" + "addi %0, 0x01\n\t" + : "+r"(sum) + : "r"(dsp) + ); + if (sum != result) { + printf("bposge32 wrong\n"); + + return -1; + } + + dsp = 0x10; + sum = 0x01; + result = 0xA4; + + __asm + ("wrdsp %1\n\t" + "bposge32 test2\n\t" + "nop\n\t" + "addi %0, 0xA2\n\t" + "nop\n\t" + "test2:\n\t" + "addi %0, 0x01\n\t" + : "+r"(sum) + : "r"(dsp) + ); + if (sum != result) { + printf("bposge32 wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/bposge64.c b/tests/tcg/mips/mips64-dsp/bposge64.c new file mode 100644 index 0000000000..36161ad852 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/bposge64.c @@ -0,0 +1,50 @@ +#include "io.h" + +int main(void) +{ + long long dsp, sum; + long long result; + + dsp = 0x40; + sum = 0x01; + result = 0x02; + + __asm + ("wrdsp %1\n\t" + "bposge64 test1\n\t" + "nop\n\t" + "addi %0, 0xA2\n\t" + "nop\n\t" + "test1:\n\t" + "addi %0, 0x01\n\t" + : "+r"(sum) + : "r"(dsp) + ); + if (sum != result) { + printf("bposge64 wrong\n"); + + return -1; + } + + dsp = 0x10; + sum = 0x01; + result = 0xA4; + + __asm + ("wrdsp %1\n\t" + "bposge64 test2\n\t" + "nop\n\t" + "addi %0, 0xA2\n\t" + "nop\n\t" + "test2:\n\t" + "addi %0, 0x01\n\t" + : "+r"(sum) + : "r"(dsp) + ); + if (sum != result) { + printf("bposge64 wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmp_eq_ph.c b/tests/tcg/mips/mips64-dsp/cmp_eq_ph.c new file mode 100644 index 0000000000..63069d0dab --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmp_eq_ph.c @@ -0,0 +1,42 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x11777066; + rt = 0x55AA33FF; + result = 0x00; + __asm + ("cmp.eq.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + rd = (rd >> 24) & 0x03; + if (rd != result) { + printf("cmp.eq.ph wrong\n"); + + return -1; + } + + rs = 0x11777066; + rt = 0x11777066; + result = 0x03; + __asm + ("cmp.eq.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + rd = (rd >> 24) & 0x03; + if (rd != result) { + printf("cmp.eq.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmp_eq_pw.c b/tests/tcg/mips/mips64-dsp/cmp_eq_pw.c new file mode 100644 index 0000000000..bae4c06ccb --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmp_eq_pw.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dspreg, dspresult; + + rs = 0x123456789ABCDEFF; + rt = 0x123456789ABCDEFF; + dspresult = 0x03; + + __asm + ("cmp.eq.pw %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x03); + + if (dspreg != dspresult) { + printf("1 cmp.eq.pw error\n"); + + return -1; + } + + rs = 0x123456799ABCDEFe; + rt = 0x123456789ABCDEFF; + dspresult = 0x00; + + __asm + ("cmp.eq.pw %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x03); + + if (dspreg != dspresult) { + printf("2 cmp.eq.pw error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmp_eq_qh.c b/tests/tcg/mips/mips64-dsp/cmp_eq_qh.c new file mode 100644 index 0000000000..49ea271003 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmp_eq_qh.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dspreg, dspresult; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x0E; + + __asm + ("cmp.eq.qh %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x0F); + + if (dspreg != dspresult) { + printf("cmp.eq.qh error\n"); + + return -1; + } + + rs = 0x12355a789A4CD3F0; + rt = 0x123456789ABCDEFF; + dspresult = 0x00; + + __asm + ("cmp.eq.qh %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x0F); + + if (dspreg != dspresult) { + printf("cmp.eq.qh error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmp_le_ph.c b/tests/tcg/mips/mips64-dsp/cmp_le_ph.c new file mode 100644 index 0000000000..12d24f1783 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmp_le_ph.c @@ -0,0 +1,40 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x11777066; + rt = 0x55AA33FF; + result = 0x02; + __asm + ("cmp.le.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + rd = (rd >> 24) & 0x03; + if (rd != result) { + printf("cmp.le.ph wrong\n"); + + return -1; + } + rs = 0x11777066; + rt = 0x11777066; + result = 0x03; + __asm + ("cmp.le.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + rd = (rd >> 24) & 0x03; + if (rd != result) { + printf("cmp.le.ph wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmp_le_pw.c b/tests/tcg/mips/mips64-dsp/cmp_le_pw.c new file mode 100644 index 0000000000..6acc43cd5b --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmp_le_pw.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dspreg, dspresult; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x03; + + __asm + ("cmp.le.pw %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x03); + + if (dspreg != dspresult) { + printf("1 cmp.le.pw error\n"); + + return -1; + } + + rs = 0x123456799ABCEEFF; + rt = 0x123456789ABCDEFF; + dspresult = 0x00; + + __asm + ("cmp.le.pw %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x03); + + if (dspreg != dspresult) { + printf("2 cmp.le.pw error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmp_le_qh.c b/tests/tcg/mips/mips64-dsp/cmp_le_qh.c new file mode 100644 index 0000000000..c9ce21667f --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmp_le_qh.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dspreg, dspresult; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x0F; + + __asm + ("cmp.le.qh %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x0F); + + if (dspreg != dspresult) { + printf("cmp.le.qh error\n"); + + return -1; + } + + rs = 0x823456789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x0f; + + __asm + ("cmp.le.qh %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x0F); + + if (dspreg != dspresult) { + printf("cmp.le.qh error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmp_lt_ph.c b/tests/tcg/mips/mips64-dsp/cmp_lt_ph.c new file mode 100644 index 0000000000..1d91228c3a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmp_lt_ph.c @@ -0,0 +1,41 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x11777066; + rt = 0x55AA33FF; + result = 0x02; + __asm + ("cmp.lt.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + rd = (rd >> 24) & 0x03; + if (rd != result) { + printf("cmp.lt.ph wrong\n"); + + return -1; + } + rs = 0x11777066; + rt = 0x11777066; + result = 0x00; + __asm + ("cmp.lt.ph %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + rd = (rd >> 24) & 0x03; + if (rd != result) { + printf("cmp.lt.ph2 wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmp_lt_pw.c b/tests/tcg/mips/mips64-dsp/cmp_lt_pw.c new file mode 100644 index 0000000000..87e74caf38 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmp_lt_pw.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dspreg, dspresult; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x01; + + __asm + ("cmp.lt.pw %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x03); + + if (dspreg != dspresult) { + printf("cmp.lt.pw error\n"); + + return -1; + } + + rs = 0x123456779ABCDEFf; + rt = 0x123456789ABCDEFF; + dspresult = 0x02; + + __asm + ("cmp.lt.pw %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x03); + + if (dspreg != dspresult) { + printf("cmp.lt.pw error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmp_lt_qh.c b/tests/tcg/mips/mips64-dsp/cmp_lt_qh.c new file mode 100644 index 0000000000..0a13a5eaae --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmp_lt_qh.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dspreg, dspresult; + + rs = 0x123558789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x01; + + __asm + ("cmp.lt.qh %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x0F); + + if (dspreg != dspresult) { + printf("cmp.lt.qh error\n"); + + return -1; + } + + rs = 0x123356779ABbDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x0f; + + __asm + ("cmp.lt.qh %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0x0F); + + if (dspreg != dspresult) { + printf("cmp.lt.qh error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpgu_eq_ob.c b/tests/tcg/mips/mips64-dsp/cmpgu_eq_ob.c new file mode 100644 index 0000000000..697d73dd1a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpgu_eq_ob.c @@ -0,0 +1,40 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + result = 0xFE; + + __asm + ("cmpgu.eq.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("cmpgu.eq.ob error\n"); + + return -1; + } + + rs = 0x133456789ABCDEF0; + rt = 0x123556789ABCDEFF; + result = 0x3E; + + __asm + ("cmpgu.eq.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("cmpgu.eq.ob error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpgu_eq_qb.c b/tests/tcg/mips/mips64-dsp/cmpgu_eq_qb.c new file mode 100644 index 0000000000..b41c4430fd --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpgu_eq_qb.c @@ -0,0 +1,38 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x02; + __asm + ("cmpgu.eq.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("cmpgu.eq.ph wrong\n"); + + return -1; + } + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm + ("cmpgu.eq.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("cmpgu.eq.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpgu_le_ob.c b/tests/tcg/mips/mips64-dsp/cmpgu_le_ob.c new file mode 100644 index 0000000000..8b65f18c00 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpgu_le_ob.c @@ -0,0 +1,40 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + result = 0xFF; + + __asm + ("cmpgu.le.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("cmpgu.le.ob error\n"); + + return -1; + } + + rs = 0x823556789ABCDEF0; + rt = 0x123456789ABCDEFF; + result = 0x3F; + + __asm + ("cmpgu.le.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("cmpgu.le.ob error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpgu_le_qb.c b/tests/tcg/mips/mips64-dsp/cmpgu_le_qb.c new file mode 100644 index 0000000000..dd2b091f61 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpgu_le_qb.c @@ -0,0 +1,37 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0F; + __asm + ("cmpgu.le.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("cmpgu.le.qb wrong\n"); + + return -1; + } + + rs = 0x11777066; + rt = 0x11766066; + result = 0x09; + __asm + ("cmpgu.le.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("cmpgu.le.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpgu_lt_ob.c b/tests/tcg/mips/mips64-dsp/cmpgu_lt_ob.c new file mode 100644 index 0000000000..3e5c9dd6da --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpgu_lt_ob.c @@ -0,0 +1,40 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + result = 0x01; + + __asm + ("cmpgu.lt.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("cmpgu.lt.ob error\n"); + + return -1; + } + + rs = 0x823455789ABCDEF0; + rt = 0x123356789ABCDEFF; + result = 0x21; + + __asm + ("cmpgu.lt.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("cmpgu.lt.ob error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpgu_lt_qb.c b/tests/tcg/mips/mips64-dsp/cmpgu_lt_qb.c new file mode 100644 index 0000000000..a467cb78db --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpgu_lt_qb.c @@ -0,0 +1,38 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0D; + __asm + ("cmpgu.lt.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("cmpgu.lt.qb wrong\n"); + + return -1; + } + + rs = 0x11777066; + rt = 0x11766066; + result = 0x00; + __asm + ("cmpgu.lt.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("cmpgu.lt.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpu_eq_ob.c b/tests/tcg/mips/mips64-dsp/cmpu_eq_ob.c new file mode 100644 index 0000000000..4d1983e5ea --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpu_eq_ob.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dspreg, dspresult; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0xFE; + + __asm + ("cmpu.eq.ob %1, %2\n\t" + "rddsp %0" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0xFF); + + if (dspreg != dspresult) { + printf("cmpu.eq.ob error\n"); + + return -1; + } + + rs = 0x133516713A0CD1F0; + rt = 0x123456789ABCDEFF; + dspresult = 0x00; + + __asm + ("cmpu.eq.ob %1, %2\n\t" + "rddsp %0" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0xFF); + + if (dspreg != dspresult) { + printf("cmpu.eq.ob error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpu_eq_qb.c b/tests/tcg/mips/mips64-dsp/cmpu_eq_qb.c new file mode 100644 index 0000000000..28f3bec252 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpu_eq_qb.c @@ -0,0 +1,42 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long dsp; + long long result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x02; + __asm + ("cmpu.eq.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if (dsp != result) { + printf("cmpu.eq.qb wrong\n"); + + return -1; + } + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm + ("cmpu.eq.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if (dsp != result) { + printf("cmpu.eq.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpu_le_ob.c b/tests/tcg/mips/mips64-dsp/cmpu_le_ob.c new file mode 100644 index 0000000000..8acbd1c4ba --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpu_le_ob.c @@ -0,0 +1,44 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dspreg, dspresult; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0xFF; + + __asm + ("cmpu.le.ob %1, %2\n\t" + "rddsp %0" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = dspreg >> 24; + if (dspreg != dspresult) { + printf("cmpu.le.ob error\n"); + + return -1; + } + + rs = 0x823656789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x3F; + + __asm + ("cmpu.le.ob %1, %2\n\t" + "rddsp %0" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = dspreg >> 24; + if (dspreg != dspresult) { + printf("cmpu.le.ob error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpu_le_qb.c b/tests/tcg/mips/mips64-dsp/cmpu_le_qb.c new file mode 100644 index 0000000000..8a17a08513 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpu_le_qb.c @@ -0,0 +1,41 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long dsp; + long long result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0F; + __asm + ("cmpu.le.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if (dsp != result) { + printf("cmpu.le.qb wrong\n"); + + return -1; + } + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm + ("cmpu.le.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if (dsp != result) { + printf("cmpu.le.qb wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpu_lt_ob.c b/tests/tcg/mips/mips64-dsp/cmpu_lt_ob.c new file mode 100644 index 0000000000..34e312d818 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpu_lt_ob.c @@ -0,0 +1,44 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dspreg, dspresult; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x01; + + __asm + ("cmpu.lt.ob %1, %2\n\t" + "rddsp %0" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = dspreg >> 24; + if (dspreg != dspresult) { + printf("cmpu.lt.ob error\n"); + + return -1; + } + + rs = 0x823156789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x41; + + __asm + ("cmpu.lt.ob %1, %2\n\t" + "rddsp %0" + : "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = dspreg >> 24; + if (dspreg != dspresult) { + printf("cmpu.lt.ob error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/cmpu_lt_qb.c b/tests/tcg/mips/mips64-dsp/cmpu_lt_qb.c new file mode 100644 index 0000000000..adb75eed52 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/cmpu_lt_qb.c @@ -0,0 +1,42 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long dsp; + long long result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0D; + __asm + ("cmpu.lt.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if (dsp != result) { + printf("cmpu.lt.qb wrong\n"); + + return -1; + } + + rs = 0x11777066; + rt = 0x11777066; + result = 0x00; + __asm + ("cmpu.lt.qb %1, %2\n\t" + "rddsp %0\n\t" + : "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if (dsp != result) { + printf("cmpu.lt.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dappend.c b/tests/tcg/mips/mips64-dsp/dappend.c new file mode 100644 index 0000000000..ba8e12182e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dappend.c @@ -0,0 +1,37 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long res; + rt = 0x1234567887654321; + rs = 0xabcd1234abcd8765; + + res = 0x1234567887654321; + __asm + ("dappend %0, %1, 0x0\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("dappend error\n"); + return -1; + } + + rt = 0x1234567887654321; + rs = 0xabcd1234abcd8765; + + res = 0x2345678876543215; + __asm + ("dappend %0, %1, 0x4\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("dappend error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextp.c b/tests/tcg/mips/mips64-dsp/dextp.c new file mode 100644 index 0000000000..a469cc0366 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextp.c @@ -0,0 +1,54 @@ +#include "io.h" + +int main(void) +{ + long long rt, dsp; + long long achi, acli; + long long res, resdsp; + int rs; + + rs = 0xabcd1234; + + achi = 0x12345678; + acli = 0x87654321; + res = 0xff; + resdsp = 0x0; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "wrdsp %4\n\t" + "dextp %0, $ac1, 0x7\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + dsp = (dsp >> 14) & 0x1; + if ((dsp != resdsp) || (rt != res)) { + printf("dextp error\n"); + return -1; + } + + rs = 0xabcd1200; + + achi = 0x12345678; + acli = 0x87654321; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "wrdsp %4\n\t" + "dextp %0, $ac1, 0x7\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + dsp = (dsp >> 14) & 0x1; + if (dsp != resdsp) { + printf("dextp error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextpdp.c b/tests/tcg/mips/mips64-dsp/dextpdp.c new file mode 100644 index 0000000000..a2361e2d42 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextpdp.c @@ -0,0 +1,59 @@ +#include "io.h" + +int main(void) +{ + long long rt, dsp; + long long achi, acli; + long long res, resdsp, resdsppos; + int rs; + int tmp1, tmp2; + + rs = 0xabcd1234; + + achi = 0x12345678; + acli = 0x87654321; + res = 0xff; + resdsp = 0x0; + resdsppos = 0x2c; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "wrdsp %4\n\t" + "dextpdp %0, $ac1, 0x7\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + tmp1 = (dsp >> 14) & 0x1; + tmp2 = dsp & 0x3f; + + if ((tmp1 != resdsp) || (rt != res) || (tmp2 != resdsppos)) { + printf("dextpdp error\n"); + return -1; + } + + rs = 0xabcd1200; + + achi = 0x12345678; + acli = 0x87654321; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "wrdsp %4\n\t" + "dextpdp %0, $ac1, 0x7\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + tmp1 = (dsp >> 14) & 0x1; + + if (tmp1 != resdsp) { + printf("dextpdp error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextpdpv.c b/tests/tcg/mips/mips64-dsp/dextpdpv.c new file mode 100644 index 0000000000..09c0b5b412 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextpdpv.c @@ -0,0 +1,63 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long res, resdsp, resdsppos; + int rsdsp; + int tmp1, tmp2; + + rsdsp = 0xabcd1234; + rs = 0x7; + achi = 0x12345678; + acli = 0x87654321; + res = 0xff; + resdsp = 0x0; + resdsppos = 0x2c; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "wrdsp %4, 0x1\n\t" + "wrdsp %4\n\t" + "dextpdpv %0, $ac1, %5\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rsdsp), "r"(rs) + ); + + tmp1 = (dsp >> 14) & 0x1; + tmp2 = dsp & 0x3f; + + if ((tmp1 != resdsp) || (rt != res) || (tmp2 != resdsppos)) { + printf("dextpdpv error\n"); + return -1; + } + + rsdsp = 0xabcd1200; + rs = 0x7; + achi = 0x12345678; + acli = 0x87654321; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "wrdsp %4, 0x1\n\t" + "wrdsp %4\n\t" + "dextpdpv %0, $ac1, %5\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rsdsp), "r"(rs) + ); + + tmp1 = (dsp >> 14) & 0x1; + + if (tmp1 != resdsp) { + printf("dextpdpv error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextpv.c b/tests/tcg/mips/mips64-dsp/dextpv.c new file mode 100644 index 0000000000..2626f3d98c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextpv.c @@ -0,0 +1,58 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long res, resdsp; + int rsdsp; + + rsdsp = 0xabcd1234; + rs = 0x7; + + achi = 0x12345678; + acli = 0x87654321; + res = 0xff; + resdsp = 0x0; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "wrdsp %4, 0x1\n\t" + "wrdsp %4\n\t" + "dextpv %0, $ac1, %5\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rsdsp), "r"(rs) + ); + dsp = (dsp >> 14) & 0x1; + if ((dsp != resdsp) || (rt != res)) { + printf("dextpv error\n"); + return -1; + } + + rsdsp = 0xabcd1200; + rs = 0x7; + + achi = 0x12345678; + acli = 0x87654321; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "wrdsp %4, 0x1\n\t" + "wrdsp %4\n\t" + "dextpv %0, $ac1, %5\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rsdsp), "r"(rs) + ); + dsp = (dsp >> 14) & 0x1; + if (dsp != resdsp) { + printf("dextpv error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextr_l.c b/tests/tcg/mips/mips64-dsp/dextr_l.c new file mode 100644 index 0000000000..538846df18 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextr_l.c @@ -0,0 +1,44 @@ +#include "io.h" + +int main(void) +{ + long long rt; + long long achi, acli; + long long res; + + achi = 0x87654321; + acli = 0x12345678; + + res = 0x2100000000123456; + + __asm + ("mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "dextr.l %0, $ac1, 0x8\n\t" + : "=r"(rt) + : "r"(achi), "r"(acli) + ); + if (rt != res) { + printf("dextr.l error\n"); + return -1; + } + + achi = 0x87654321; + acli = 0x12345678; + + res = 0x12345678; + + __asm + ("mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "dextr.l %0, $ac1, 0x0\n\t" + : "=r"(rt) + : "r"(achi), "r"(acli) + ); + if (rt != res) { + printf("dextr.l error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextr_r_l.c b/tests/tcg/mips/mips64-dsp/dextr_r_l.c new file mode 100644 index 0000000000..a10a9ab40e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextr_r_l.c @@ -0,0 +1,54 @@ +#include "io.h" + +int main(void) +{ + long long rt, dsp; + long long achi, acli; + long long res, resdsp; + + achi = 0x87654321; + acli = 0x12345678; + + res = 0x2100000000123456; + resdsp = 0x01; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_r.l %0, $ac1, 0x8\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextr_r.l error\n"); + return -1; + } + + achi = 0x87654321; + acli = 0x12345678; + + res = 0x12345678; + resdsp = 0x01; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_r.l %0, $ac1, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextr_r.l error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextr_r_w.c b/tests/tcg/mips/mips64-dsp/dextr_r_w.c new file mode 100644 index 0000000000..2774e9bfcc --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextr_r_w.c @@ -0,0 +1,54 @@ +#include "io.h" + +int main(void) +{ + long long rt, dsp; + long long achi, acli; + long long res, resdsp; + + achi = 0x87654321; + acli = 0x12345678; + + res = 0x123456; + resdsp = 0x01; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_r.w %0, $ac1, 0x8\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextr_r.w error\n"); + return -1; + } + + achi = 0x87654321; + acli = 0x12345678; + + res = 0x12345678; + resdsp = 0x01; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_r.w %0, $ac1, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextr_r.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextr_rs_l.c b/tests/tcg/mips/mips64-dsp/dextr_rs_l.c new file mode 100644 index 0000000000..1a202fefa2 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextr_rs_l.c @@ -0,0 +1,52 @@ +#include "io.h" + +int main(void) +{ + long long rt, dsp; + long long achi, acli; + long long res, resdsp; + + achi = 0x87654321; + acli = 0x12345678; + + res = 0x8000000000000000; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_rs.l %0, $ac1, 0x8\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextr_rs.l error\n"); + return -1; + } + + achi = 0x00; + acli = 0x12345678; + + res = 0x12345678; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_rs.l %0, $ac1, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextr_rs.l error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextr_rs_w.c b/tests/tcg/mips/mips64-dsp/dextr_rs_w.c new file mode 100644 index 0000000000..ebe5f99db0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextr_rs_w.c @@ -0,0 +1,52 @@ +#include "io.h" + +int main(void) +{ + long long rt, dsp; + long long achi, acli; + long long res, resdsp; + + achi = 0x87654321; + acli = 0x12345678; + + res = 0xffffffff80000000; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_rs.w %0, $ac1, 0x8\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextr_rs.w error\n"); + return -1; + } + + achi = 0x00; + acli = 0x12345678; + + res = 0x123456; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_rs.w %0, $ac1, 0x8\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextr_rs.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextr_s_h.c b/tests/tcg/mips/mips64-dsp/dextr_s_h.c new file mode 100644 index 0000000000..1adb5549a9 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextr_s_h.c @@ -0,0 +1,73 @@ +#include "io.h" + +int main(void) +{ + long long rt, dsp; + long long achi, acli; + long long res, resdsp; + + achi = 0x87654321; + acli = 0x12345678; + + res = 0xffffffffffff8000; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_s.h %0, $ac1, 0x8\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("1 dextr_s.h error\n"); + return -1; + } + + achi = 0x77654321; + acli = 0x12345678; + + res = 0x7fff; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_s.h %0, $ac1, 0x8\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("2 dextr_s.h error\n"); + return -1; + } + + achi = 0x00; + acli = 0x78; + + res = 0x7; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextr_s.h %0, $ac1, 0x4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("3 dextr_s.h error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextr_w.c b/tests/tcg/mips/mips64-dsp/dextr_w.c new file mode 100644 index 0000000000..79bed5da35 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextr_w.c @@ -0,0 +1,44 @@ +#include "io.h" + +int main(void) +{ + long long rt; + long long achi, acli; + long long res; + + achi = 0x87654321; + acli = 0x12345678; + + res = 0x123456; + + __asm + ("mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "dextr.w %0, $ac1, 0x8\n\t" + : "=r"(rt) + : "r"(achi), "r"(acli) + ); + if (rt != res) { + printf("dextr.w error\n"); + return -1; + } + + achi = 0x87654321; + acli = 0x12345678; + + res = 0x12345678; + + __asm + ("mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "dextr.w %0, $ac1, 0x0\n\t" + : "=r"(rt) + : "r"(achi), "r"(acli) + ); + if (rt != res) { + printf("dextr.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextrv_l.c b/tests/tcg/mips/mips64-dsp/dextrv_l.c new file mode 100644 index 0000000000..2e6187f729 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextrv_l.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long res; + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x8; + + res = 0x2100000000123456; + + __asm + ("mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "dextrv.l %0, $ac1, %3\n\t" + : "=r"(rt) + : "r"(achi), "r"(acli), "r"(rs) + ); + if (rt != res) { + printf("dextrv.l error\n"); + return -1; + } + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x0; + + res = 0x12345678; + + __asm + ("mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "dextrv.l %0, $ac1, %3\n\t" + : "=r"(rt) + : "r"(achi), "r"(acli), "r"(rs) + ); + if (rt != res) { + printf("dextrv.l error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextrv_r_l.c b/tests/tcg/mips/mips64-dsp/dextrv_r_l.c new file mode 100644 index 0000000000..b47a0177d4 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextrv_r_l.c @@ -0,0 +1,56 @@ +#include "io.h" + +int main(void) +{ + long long rt, dsp, rs; + long long achi, acli; + long long res, resdsp; + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x8; + + res = 0x2100000000123456; + resdsp = 0x01; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextrv_r.l %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextrv_r.l error\n"); + return -1; + } + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x0; + + res = 0x12345678; + resdsp = 0x01; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextrv_r.l %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextrv_r.l error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextrv_r_w.c b/tests/tcg/mips/mips64-dsp/dextrv_r_w.c new file mode 100644 index 0000000000..cd201deb21 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextrv_r_w.c @@ -0,0 +1,56 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long res, resdsp; + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x8; + + res = 0x123456; + resdsp = 0x01; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextrv_r.w %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextrv_r.w error\n"); + return -1; + } + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x0; + + res = 0x12345678; + resdsp = 0x01; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextrv_r.w %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextrv_r.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextrv_rs_l.c b/tests/tcg/mips/mips64-dsp/dextrv_rs_l.c new file mode 100644 index 0000000000..6ce4185462 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextrv_rs_l.c @@ -0,0 +1,54 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long res, resdsp; + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x8; + + res = 0x8000000000000000; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextrv_rs.l %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextrv_rs.l error\n"); + return -1; + } + + achi = 0x00; + acli = 0x12345678; + rs = 0x0; + + res = 0x12345678; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextrv_rs.l %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextrv_rs.l error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextrv_rs_w.c b/tests/tcg/mips/mips64-dsp/dextrv_rs_w.c new file mode 100644 index 0000000000..a65183c030 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextrv_rs_w.c @@ -0,0 +1,54 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long res, resdsp; + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x8; + + res = 0xffffffff80000000; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextrv_rs.w %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextrv_rs.w error\n"); + return -1; + } + + achi = 0x00; + acli = 0x12345678; + rs = 0x8; + + res = 0x123456; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextrv_rs.w %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextrv_rs.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextrv_s_h.c b/tests/tcg/mips/mips64-dsp/dextrv_s_h.c new file mode 100644 index 0000000000..87d3aeedce --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextrv_s_h.c @@ -0,0 +1,32 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long res, resdsp; + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x8; + + res = 0xffffffffffff8000; + resdsp = 0x1; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dextrv_s.h %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs) + ); + dsp = (dsp >> 23) & 0x1; + + if ((dsp != resdsp) || (rt != res)) { + printf("dextrv_s.h error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dextrv_w.c b/tests/tcg/mips/mips64-dsp/dextrv_w.c new file mode 100644 index 0000000000..973765c1c0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dextrv_w.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long res; + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x8; + + res = 0x123456; + + __asm + ("mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "dextrv.w %0, $ac1, %3\n\t" + : "=r"(rt) + : "r"(achi), "r"(acli), "r"(rs) + ); + if (rt != res) { + printf("dextrv.w error\n"); + return -1; + } + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x0; + + res = 0x12345678; + + __asm + ("mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "dextrv.w %0, $ac1, %3\n\t" + : "=r"(rt) + : "r"(achi), "r"(acli), "r"(rs) + ); + if (rt != res) { + printf("dextrv.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dinsv.c b/tests/tcg/mips/mips64-dsp/dinsv.c new file mode 100644 index 0000000000..f6192188c0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dinsv.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dsp; + long long res; + + rs = 0x1234567887654321; + rt = 0x1234567812345678; + dsp = 0x2222; + res = 0x1234567812345678; + __asm + ("wrdsp %1, 0x3\n\t" + "wrdsp %1\n\t" + "dinsv %0, %2\n\t" + : "+r"(rt) + : "r"(dsp), "r"(rs) + ); + + if (rt != res) { + printf("dinsv error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dmadd.c b/tests/tcg/mips/mips64-dsp/dmadd.c new file mode 100644 index 0000000000..fb22614725 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dmadd.c @@ -0,0 +1,57 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long acho, aclo; + long long resh, resl; + + achi = 0x1; + acli = 0x1; + + rs = 0x0000000100000001; + rt = 0x0000000200000002; + + resh = 0x1; + resl = 0x5; + __asm + ("mthi %2, $ac1 \t\n" + "mtlo %3, $ac1 \t\n" + "dmadd $ac1, %4, %5\t\n" + "mfhi %0, $ac1 \t\n" + "mflo %1, $ac1 \t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resh) || (aclo != resl)) { + printf("1 dmadd error\n"); + + return -1; + } + + achi = 0x1; + acli = 0x1; + + rs = 0xaaaabbbbccccdddd; + rt = 0xaaaabbbbccccdddd; + + resh = 0x0000000000000000; + resl = 0xffffffffca860b63; + + __asm + ("mthi %2, $ac1 \t\n" + "mtlo %3, $ac1 \t\n" + "dmadd $ac1, %4, %5\t\n" + "mfhi %0, $ac1 \t\n" + "mflo %1, $ac1 \t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resh) || (aclo != resl)) { + printf("2 dmadd error\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dmaddu.c b/tests/tcg/mips/mips64-dsp/dmaddu.c new file mode 100644 index 0000000000..39ab0c10db --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dmaddu.c @@ -0,0 +1,56 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long acho, aclo; + long long resh, resl; + achi = 0x1; + acli = 0x2; + + rs = 0x0000000200000002; + rt = 0x0000000200000002; + resh = 0x1; + resl = 0xa; + __asm + ("mthi %2, $ac1 \t\n" + "mtlo %3, $ac1 \t\n" + "dmaddu $ac1, %4, %5\t\n" + "mfhi %0, $ac1 \t\n" + "mflo %1, $ac1 \t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resh) || (aclo != resl)) { + printf("1 dmaddu error\n"); + + return -1; + } + + achi = 0x1; + acli = 0x1; + + rs = 0xaaaabbbbccccdddd; + rt = 0xaaaabbbbccccdddd; + + resh = 0x0000000000000002; + resl = 0xffffffffca860b63; + + __asm + ("mthi %2, $ac1 \t\n" + "mtlo %3, $ac1 \t\n" + "dmaddu $ac1, %4, %5\t\n" + "mfhi %0, $ac1 \t\n" + "mflo %1, $ac1 \t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resh) || (aclo != resl)) { + printf("2 dmaddu error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dmsub.c b/tests/tcg/mips/mips64-dsp/dmsub.c new file mode 100644 index 0000000000..16be6170e4 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dmsub.c @@ -0,0 +1,59 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long acho, aclo; + long long resh, resl; + achi = 0x1; + acli = 0x8; + + rs = 0x0000000100000001; + rt = 0x0000000200000002; + + resh = 0x1; + resl = 0x4; + + __asm + ("mthi %2, $ac1 \t\n" + "mtlo %3, $ac1 \t\n" + "dmsub $ac1, %4, %5\t\n" + "mfhi %0, $ac1 \t\n" + "mflo %1, $ac1 \t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resh) || (aclo != resl)) { + printf("1 dmsub error\n"); + + return -1; + } + + achi = 0xfffffffF; + acli = 0xfffffffF; + + rs = 0x8888999977776666; + rt = 0x9999888877776666; + + resh = 0xffffffffffffffff; + resl = 0x789aae13; + + __asm + ("mthi %2, $ac1 \t\n" + "mtlo %3, $ac1 \t\n" + "dmsub $ac1, %4, %5\t\n" + "mfhi %0, $ac1 \t\n" + "mflo %1, $ac1 \t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("2 dmsub error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dmsubu.c b/tests/tcg/mips/mips64-dsp/dmsubu.c new file mode 100644 index 0000000000..cc4838ad5f --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dmsubu.c @@ -0,0 +1,59 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long acho, aclo; + long long resh, resl; + achi = 0x1; + acli = 0x8; + + rs = 0x0000000100000001; + rt = 0x0000000200000002; + + resh = 0x1; + resl = 0x4; + + __asm + ("mthi %2, $ac1 \t\n" + "mtlo %3, $ac1 \t\n" + "dmsubu $ac1, %4, %5\t\n" + "mfhi %0, $ac1 \t\n" + "mflo %1, $ac1 \t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resh) || (aclo != resl)) { + printf("1 dmsubu error\n"); + + return -1; + } + + achi = 0xfffffffF; + acli = 0xfffffffF; + + rs = 0x8888999977776666; + rt = 0x9999888877776666; + + resh = 0xffffffffffffffff; + resl = 0x789aae13; + + __asm + ("mthi %2, $ac1 \t\n" + "mtlo %3, $ac1 \t\n" + "dmsubu $ac1, %4, %5\t\n" + "mfhi %0, $ac1 \t\n" + "mflo %1, $ac1 \t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("2 dmsubu error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dmthlip.c b/tests/tcg/mips/mips64-dsp/dmthlip.c new file mode 100644 index 0000000000..027555fb53 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dmthlip.c @@ -0,0 +1,41 @@ +#include "io.h" + +int main(void) +{ + long long rs, dsp; + long long achi, acli; + + long long rsdsp; + long long acho, aclo; + + long long res; + long long reshi, reslo; + + + rs = 0xaaaabbbbccccdddd; + achi = 0x87654321; + acli = 0x12345678; + dsp = 0x22; + + res = 0x62; + reshi = 0x12345678; + reslo = 0xffffffffccccdddd; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "wrdsp %5\n\t" + "dmthlip %6, $ac1\n\t" + "rddsp %0\n\t" + "mfhi %1, $ac1\n\t" + "mflo %2, $ac1\n\t" + : "=r"(rsdsp), "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(dsp), "r"(rs) + ); + if ((rsdsp != res) || (acho != reshi) || (aclo != reslo)) { + printf("dmthlip error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpaq_s_w_ph.c b/tests/tcg/mips/mips64-dsp/dpaq_s_w_ph.c new file mode 100644 index 0000000000..1bca935008 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpaq_s_w_ph.c @@ -0,0 +1,32 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dsp; + long long ach = 0, acl = 0; + long long resulth, resultl, resultdsp; + + rs = 0x800000FF; + rt = 0x80000002; + resulth = 0x00; + resultl = 0xFFFFFFFF800003FB; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaq_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = dsp >> 17 & 0x01; + if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) { + printf("dpaq_w.w.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpaq_s_w_qh.c b/tests/tcg/mips/mips64-dsp/dpaq_s_w_qh.c new file mode 100644 index 0000000000..844a347429 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpaq_s_w_qh.c @@ -0,0 +1,57 @@ +#include"io.h" +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long acho, aclo; + long long resh, resl; + + achi = 0x1; + acli = 0x1; + rs = 0x0001000100010001; + rt = 0x0002000200020002; + resh = 0x1; + resl = 0x11; + + __asm + ("mthi %2, $ac1\t\n" + "mtlo %3, $ac1\t\n" + "dpaq_s.w.qh $ac1, %4, %5\t\n" + "mfhi %0, $ac1\t\n" + "mflo %1, $ac1\t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resh) || (aclo != resl)) { + printf("1 dpaq_s.w.qh error\n"); + + return -1; + } + + achi = 0xffffffff; + acli = 0xaaaaaaaa; + + rs = 0x1111222233334444; + rt = 0xffffeeeeddddcccc; + + resh = 0x00; + resl = 0xffffffffd27ad82e; + + __asm + ("mthi %2, $ac1\t\n" + "mtlo %3, $ac1\t\n" + "dpaq_s.w.qh $ac1, %4, %5\t\n" + "mfhi %0, $ac1\t\n" + "mflo %1, $ac1\t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("2 dpaq_s.w.qh error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpaq_sa_l_pw.c b/tests/tcg/mips/mips64-dsp/dpaq_sa_l_pw.c new file mode 100644 index 0000000000..1bb2ec2f26 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpaq_sa_l_pw.c @@ -0,0 +1,88 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long achi, acli; + long long acho, aclo; + long long dsp; + long long resh, resl; + long long resdsp; + + rs = 0x0000000100000001; + rt = 0x0000000200000002; + achi = 0x1; + acli = 0x1; + resh = 0xffffffffffffffff; + resl = 0x0; + resdsp = 0x01; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "dpaq_sa.l.pw $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl) || ((dsp >> (16 + 1)) != resdsp)) { + printf("1 dpaq_sa_l_pw error\n"); + + return -1; + } + + rs = 0xaaaabbbbccccdddd; + rt = 0x3333444455556666; + achi = 0x88888888; + acli = 0x66666666; + + resh = 0xffffffff88888887; + resl = 0xffffffff9e2661da; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dpaq_sa.l.pw $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("2 dpaq_sa_l_pw error\n"); + + return -1; + } + + rs = 0x8000000080000000; + rt = 0x8000000080000000; + achi = 0x88888888; + acli = 0x66666666; + + resh = 0xffffffffffffffff; + resl = 0x00; + resdsp = 0x01; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "dpaq_sa.l.pw $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl) || ((dsp >> (16 + 1)) != resdsp)) { + printf("2 dpaq_sa_l_pw error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpaq_sa_l_w.c b/tests/tcg/mips/mips64-dsp/dpaq_sa_l_w.c new file mode 100644 index 0000000000..f840cdd761 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpaq_sa_l_w.c @@ -0,0 +1,82 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dsp; + long long ach = 0, acl = 0; + long long resulth, resultl, resultdsp; + + rs = 0x80000000; + rt = 0x80000000; + resulth = 0x7FFFFFFF; + resultl = 0xffffffffFFFFFFFF; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %0, $ac1\n\t" + "dpaq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) { + printf("dpaq_sa.l.w error\n"); + + return -1; + } + + ach = 0x12; + acl = 0x48; + rs = 0x80000000; + rt = 0x80000000; + + resulth = 0x7FFFFFFF; + resultl = 0xffffffffFFFFFFFF; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %0, $ac1\n\t" + "dpaq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) { + printf("dpaq_sa.l.w error\n"); + + return -1; + } + + ach = 0x741532A0; + acl = 0xfceabb08; + rs = 0x80000000; + rt = 0x80000000; + + resulth = 0x7fffffff; + resultl = 0xffffffffffffffff; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %0, $ac1\n\t" + "dpaq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) { + printf("dpaq_sa.l.w error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpau_h_obl.c b/tests/tcg/mips/mips64-dsp/dpau_h_obl.c new file mode 100644 index 0000000000..54905e8f93 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpau_h_obl.c @@ -0,0 +1,59 @@ + +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long achi, acli; + long long acho, aclo; + long long resh, resl; + + rs = 0x0000000100000001; + rt = 0x0000000200000002; + achi = 0x1; + acli = 0x1; + resh = 0x1; + resl = 0x3; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dpau.h.obl $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("1 dpau.h.obl error\n"); + + return -1; + } + + rs = 0xaaaabbbbccccdddd; + rt = 0x3333444455556666; + achi = 0x88888888; + acli = 0x66666666; + + resh = 0xffffffff88888888; + resl = 0x66670d7a; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dpau.h.obl $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("1 dpau.h.obl error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpau_h_obr.c b/tests/tcg/mips/mips64-dsp/dpau_h_obr.c new file mode 100644 index 0000000000..d7aa60b4b1 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpau_h_obr.c @@ -0,0 +1,59 @@ + +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long achi, acli; + long long acho, aclo; + long long resh, resl; + + rs = 0x0000000100000001; + rt = 0x0000000200000002; + achi = 0x1; + acli = 0x1; + resh = 0x1; + resl = 0x3; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dpau.h.obr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("1 dpau.h.obr error\n"); + + return -1; + } + + rs = 0xccccddddaaaabbbb; + rt = 0x5555666633334444; + achi = 0x88888888; + acli = 0x66666666; + + resh = 0xffffffff88888888; + resl = 0x66670d7a; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dpau.h.obr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("1 dpau.h.obr error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpau_h_qbl.c b/tests/tcg/mips/mips64-dsp/dpau_h_qbl.c new file mode 100644 index 0000000000..fcfd764310 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpau_h_qbl.c @@ -0,0 +1,29 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long ach = 5, acl = 3; + long long resulth, resultl; + + rs = 0x800000FF; + rt = 0x80000002; + resulth = 0x05; + resultl = 0x4003; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpau.h.qbl $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("dpau.h.qbl wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpau_h_qbr.c b/tests/tcg/mips/mips64-dsp/dpau_h_qbr.c new file mode 100644 index 0000000000..3282461a7d --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpau_h_qbr.c @@ -0,0 +1,29 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long ach = 5, acl = 3; + long long resulth, resultl; + + rs = 0x800000FF; + rt = 0x80000002; + resulth = 0x05; + resultl = 0x0201; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpau.h.qbr $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("dpau.h.qbr wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c b/tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c new file mode 100644 index 0000000000..7660f037da --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpsq_s_w_ph.c @@ -0,0 +1,51 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long ach = 5, acl = 5; + long long resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xFFFFFFFFEE9794A3; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_s.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("1 dpsq_s.w.ph wrong\n"); + + return -1; + } + + ach = 0x1424Ef1f; + acl = 0x1035219A; + rs = 0x800083AD; + rt = 0x80003721; + resulth = 0x1424ef1e; + resultl = 0x577ed901; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_s.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("2 dpsq_s.w.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpsq_s_w_qh.c b/tests/tcg/mips/mips64-dsp/dpsq_s_w_qh.c new file mode 100644 index 0000000000..2cc50c577e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpsq_s_w_qh.c @@ -0,0 +1,56 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long achi, acli; + long long acho, aclo; + long long resh, resl; + + rs = 0xffffeeeeddddcccc; + rt = 0x9999888877776666; + achi = 0x67576; + acli = 0x98878; + + resh = 0x67576; + resl = 0x5b1682c4; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dpsq_s.w.qh $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resh) || (aclo != resl)) { + printf("1 dpsq_s.w.qh wrong\n"); + + return -1; + } + + rs = 0x8000800080008000; + rt = 0x8000800080008000; + achi = 0x67576; + acli = 0x98878; + + resh = 0x67575; + resl = 0x0009887c; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dpsq_s.w.qh $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resh) || (aclo != resl)) { + printf("2 dpsq_s.w.qh wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpsq_sa_l_pw.c b/tests/tcg/mips/mips64-dsp/dpsq_sa_l_pw.c new file mode 100644 index 0000000000..7fc2503fc5 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpsq_sa_l_pw.c @@ -0,0 +1,76 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dsp; + long long achi, acli; + long long resh, resl, resdsp; + + rs = 0x89789BC0123AD; + rt = 0x5467591643721; + + achi = 0x98765437; + acli = 0x65489709; + + resh = 0xffffffffffffffff; + resl = 0x00; + + resdsp = 0x01; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_sa.l.pw $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(achi), "+r"(acli), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x01; + if ((dsp != resdsp) || (achi != resh) || (acli != resl)) { + printf("1 dpsq_sa.l.pw wrong\n"); + + return -1; + } + + /* clear dspcontrol reg for next test use. */ + dsp = 0; + __asm + ("wrdsp %0" + : + : "r"(dsp) + ); + + rs = 0x8B78980000000; + rt = 0x5867580000000; + + achi = 0x98765437; + acli = 0x65489709; + + resh = 0xffffffff98765436; + resl = 0x11d367d0; + + resdsp = 0x01; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_sa.l.pw $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(achi), "+r"(acli), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x01; + if ((dsp != resdsp) || (achi != resh) || (acli != resl)) { + printf("2 dpsq_sa.l.pw wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpsq_sa_l_w.c b/tests/tcg/mips/mips64-dsp/dpsq_sa_l_w.c new file mode 100644 index 0000000000..f55afc9095 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpsq_sa_l_w.c @@ -0,0 +1,59 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dsp; + long long ach = 5, acl = 5; + long long resulth, resultl, resultdsp; + + rs = 0xBC0123AD; + rt = 0x01643721; + + resulth = 0xfffffffffdf4cbe0; + resultl = 0xFFFFFFFFd138776b; + resultdsp = 0x00; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) { + printf("1 dpsq_sa.l.w wrong\n"); + + return -1; + } + + ach = 0x54321123; + acl = 5; + rs = 0x80000000; + rt = 0x80000000; + + resulth = 0xffffffffd4321123; + resultl = 0x06; + resultdsp = 0x01; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsq_sa.l.w $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) { + printf("2 dpsq_sa.l.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpsu_h_obl.c b/tests/tcg/mips/mips64-dsp/dpsu_h_obl.c new file mode 100644 index 0000000000..c0a8f4d7aa --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpsu_h_obl.c @@ -0,0 +1,32 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long ach = 5, acl = 5; + long long resulth, resultl; + + rs = 0x88886666BC0123AD; + rt = 0x9999888801643721; + + resulth = 0x04; + resultl = 0xFFFFFFFFFFFEF115; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsu.h.obl $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + + if ((ach != resulth) || (acl != resultl)) { + printf("dpsu.h.obl wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpsu_h_obr.c b/tests/tcg/mips/mips64-dsp/dpsu_h_obr.c new file mode 100644 index 0000000000..aa0d47a065 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpsu_h_obr.c @@ -0,0 +1,32 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long ach = 5, acl = 5; + long long resulth, resultl; + + rs = 0x7878878888886666; + rt = 0x9865454399998888; + + resulth = 0x04; + resultl = 0xFFFFFFFFFFFeF115; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsu.h.obr $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + + if ((ach != resulth) || (acl != resultl)) { + printf("dpsu.h.qbr wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpsu_h_qbl.c b/tests/tcg/mips/mips64-dsp/dpsu_h_qbl.c new file mode 100644 index 0000000000..da6dbb6154 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpsu_h_qbl.c @@ -0,0 +1,29 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long ach = 5, acl = 5; + long long resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xFFFFFFFFFFFFFEE5; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsu.h.qbl $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("dpsu.h.qbl wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dpsu_h_qbr.c b/tests/tcg/mips/mips64-dsp/dpsu_h_qbr.c new file mode 100644 index 0000000000..bf00b70aa7 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dpsu_h_qbr.c @@ -0,0 +1,29 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long ach = 5, acl = 5; + long long resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xFFFFFFFFFFFFE233; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsu.h.qbr $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("dpsu.h.qbr wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dshilo.c b/tests/tcg/mips/mips64-dsp/dshilo.c new file mode 100644 index 0000000000..f50584b9c4 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dshilo.c @@ -0,0 +1,52 @@ +#include "io.h" + +int main(void) +{ + long long achi, acli; + long long acho, aclo; + long long reshi, reslo; + + achi = 0x87654321; + acli = 0x12345678; + + reshi = 0xfffffffff8765432; + reslo = 0x1234567; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dshilo $ac1, 0x4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli) + ); + + if ((acho != reshi) || (aclo != reslo)) { + printf("1 dshilo error\n"); + return -1; + } + + achi = 0x87654321; + acli = 0x12345678; + + reshi = 0x1234567; + reslo = 0x00; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dshilo $ac1, -60\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli) + ); + + if ((acho != reshi) || (aclo != reslo)) { + printf("2 dshilo error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/dshilov.c b/tests/tcg/mips/mips64-dsp/dshilov.c new file mode 100644 index 0000000000..792bd23730 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/dshilov.c @@ -0,0 +1,54 @@ +#include "io.h" + +int main(void) +{ + long long achi, acli, rs; + long long acho, aclo; + long long reshi, reslo; + + achi = 0x87654321; + acli = 0x12345678; + rs = 0x4; + + reshi = 0xfffffffff8765432; + reslo = 0x1234567; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dshilov $ac1, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs) + ); + + if ((acho != reshi) || (aclo != reslo)) { + printf("dshilov error\n"); + return -1; + } + + rs = 0x44; + achi = 0x87654321; + acli = 0x12345678; + + reshi = 0x1234567; + reslo = 0x00; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "dshilov $ac1, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs) + ); + + if ((acho != reshi) || (aclo != reslo)) { + printf("dshilov error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extp.c b/tests/tcg/mips/mips64-dsp/extp.c new file mode 100644 index 0000000000..c72f54bace --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extp.c @@ -0,0 +1,50 @@ +#include "io.h" + +int main(void) +{ + long long rt, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + result = 0x000C; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 14) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("extp wrong\n"); + + return -1; + } + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 14) & 0x01; + if (dsp != 1) { + printf("extp wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extpdp.c b/tests/tcg/mips/mips64-dsp/extpdp.c new file mode 100644 index 0000000000..f430193841 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extpdp.c @@ -0,0 +1,51 @@ +#include "io.h" + +int main(void) +{ + long long rt, ach, acl, dsp, pos, efi; + long long result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + result = 0x000C; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl) + ); + pos = dsp & 0x3F; + efi = (dsp >> 14) & 0x01; + if ((pos != 3) || (efi != 0) || (result != rt)) { + printf("extpdp wrong\n"); + + return -1; + } + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdp %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl) + ); + efi = (dsp >> 14) & 0x01; + if (efi != 1) { + printf("extpdp wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extpdpv.c b/tests/tcg/mips/mips64-dsp/extpdpv.c new file mode 100644 index 0000000000..ba57426d22 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extpdpv.c @@ -0,0 +1,52 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, ach, acl, dsp, pos, efi; + long long result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0x000C; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl), "r"(rs) + ); + pos = dsp & 0x3F; + efi = (dsp >> 14) & 0x01; + if ((pos != 3) || (efi != 0) || (result != rt)) { + printf("extpdpv wrong\n"); + + return -1; + } + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpdpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl), "r"(rs) + ); + efi = (dsp >> 14) & 0x01; + if (efi != 1) { + printf("extpdpv wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extpv.c b/tests/tcg/mips/mips64-dsp/extpv.c new file mode 100644 index 0000000000..158472bf93 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extpv.c @@ -0,0 +1,51 @@ +#include "io.h" + +int main(void) +{ + long long rt, ac, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + ac = 0x03; + result = 0x000C; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl), "r"(ac) + ); + dsp = (dsp >> 14) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("extpv wrong\n"); + + return -1; + } + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x01; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extpv %0, $ac1, %4\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(ach), "r"(acl), "r"(ac) + ); + dsp = (dsp >> 14) & 0x01; + if (dsp != 1) { + printf("extpv wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extr_r_w.c b/tests/tcg/mips/mips64-dsp/extr_r_w.c new file mode 100644 index 0000000000..94572ad154 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extr_r_w.c @@ -0,0 +1,53 @@ +#include "io.h" + +int main(void) +{ + long long rt, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + result = 0xFFFFFFFFA0001699; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_r.w %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 1) || (result != rt)) { + printf("1 extr_r.w wrong\n"); + + return -1; + } + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4D; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_r.w %0, $ac1, 0x04\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("2 extr_r.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extr_rs_w.c b/tests/tcg/mips/mips64-dsp/extr_rs_w.c new file mode 100644 index 0000000000..73551f96b3 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extr_rs_w.c @@ -0,0 +1,53 @@ +#include "io.h" + +int main(void) +{ + long long rt, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + result = 0x7FFFFFFF; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_rs.w %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 1) || (result != rt)) { + printf("1 extr_rs.w wrong\n"); + + return -1; + } + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4D; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_rs.w %0, $ac1, 0x04\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("2 extr_rs.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extr_s_h.c b/tests/tcg/mips/mips64-dsp/extr_s_h.c new file mode 100644 index 0000000000..de10cb57a5 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extr_s_h.c @@ -0,0 +1,71 @@ +#include "io.h" + +int main(void) +{ + long long rt, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + result = 0x00007FFF; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_s.h %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 1) || (result != rt)) { + printf("extr_s.h wrong\n"); + + return -1; + } + + ach = 0xffffffff; + acl = 0x12344321; + result = 0xffffffffFFFF8000; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_s.h %0, $ac1, 0x08\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 1) || (result != rt)) { + printf("extr_s.h wrong\n"); + + return -1; + } + + /* Clear dsp */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + ach = 0x00; + acl = 0x4321; + result = 0x432; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr_s.h %0, $ac1, 0x04\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("extr_s.h wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extr_w.c b/tests/tcg/mips/mips64-dsp/extr_w.c new file mode 100644 index 0000000000..bd69576687 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extr_w.c @@ -0,0 +1,53 @@ +#include "io.h" + +int main(void) +{ + long long rt, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + result = 0xFFFFFFFFA0001699; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr.w %0, $ac1, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 1) || (result != rt)) { + printf("extr.w wrong\n"); + + return -1; + } + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4C; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "extr.w %0, $ac1, 0x04\n\t" + "rddsp %1\n\t" + : "=r"(rt), "=r"(dsp) + : "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("extr.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extrv_r_w.c b/tests/tcg/mips/mips64-dsp/extrv_r_w.c new file mode 100644 index 0000000000..8379729787 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extrv_r_w.c @@ -0,0 +1,59 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0xFFFFFFFFA0001699; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_r.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 1) || (result != rt)) { + printf("extrv_r.w wrong\n"); + + return -1; + } + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 4; + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4D; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_r.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("extrv_r.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extrv_rs_w.c b/tests/tcg/mips/mips64-dsp/extrv_rs_w.c new file mode 100644 index 0000000000..8707cd1174 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extrv_rs_w.c @@ -0,0 +1,59 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0x7FFFFFFF; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_rs.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 1) || (result != rt)) { + printf("1 extrv_rs.w wrong\n"); + + return -1; + } + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 4; + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4D; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_rs.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("2 extrv_rs.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extrv_s_h.c b/tests/tcg/mips/mips64-dsp/extrv_s_h.c new file mode 100644 index 0000000000..b6dcaebcbc --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extrv_s_h.c @@ -0,0 +1,79 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0x00007FFF; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_s.h %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 1) || (result != rt)) { + printf("extrv_s.h wrong\n"); + + return -1; + } + + rs = 0x08; + ach = 0xffffffff; + acl = 0x12344321; + result = 0xffffffffFFFF8000; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_s.h %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 1) || (result != rt)) { + printf("extrv_s.h wrong\n"); + + return -1; + } + + /* Clear dsp */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 0x04; + ach = 0x00; + acl = 0x4321; + result = 0x432; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv_s.h %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("extrv_s.h wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/extrv_w.c b/tests/tcg/mips/mips64-dsp/extrv_w.c new file mode 100644 index 0000000000..8adffb3954 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/extrv_w.c @@ -0,0 +1,59 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, ach, acl, dsp; + long long result; + + ach = 0x05; + acl = 0xB4CB; + dsp = 0x07; + rs = 0x03; + result = 0xFFFFFFFFA0001699; + + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 1) || (result != rt)) { + printf("extrv.w wrong\n"); + + return -1; + } + + /* Clear dspcontrol */ + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 4; + ach = 0x01; + acl = 0xB4CB; + result = 0x10000B4C; + __asm + ("wrdsp %1, 0x01\n\t" + "mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "extrv.w %0, $ac1, %2\n\t" + "rddsp %1\n\t" + : "=r"(rt), "+r"(dsp) + : "r"(rs), "r"(ach), "r"(acl) + ); + dsp = (dsp >> 23) & 0x01; + if ((dsp != 0) || (result != rt)) { + printf("extrv.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/head.S b/tests/tcg/mips/mips64-dsp/head.S new file mode 100644 index 0000000000..9a099ae42f --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/head.S @@ -0,0 +1,16 @@ +/* + * Startup Code for MIPS64 CPU-core + * + */ +.text +.globl _start +.align 4 +_start: + ori $2, $2, 0xffff + sll $2, $2, 16 + ori $2, $2, 0xffff + mtc0 $2, $12, 0 + jal main + +end: + b end diff --git a/tests/tcg/mips/mips64-dsp/insv.c b/tests/tcg/mips/mips64-dsp/insv.c new file mode 100644 index 0000000000..fc5696f4c4 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/insv.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long result; + + /* msb = 10, lsb = 5 */ + dsp = 0x305; + rt = 0x12345678; + rs = 0xffffffff87654321; + result = 0x12345338; + __asm + ("wrdsp %2, 0x03\n\t" + "insv %0, %1\n\t" + : "+r"(rt) + : "r"(rs), "r"(dsp) + ); + if (rt != result) { + printf("insv wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/io.h b/tests/tcg/mips/mips64-dsp/io.h new file mode 100644 index 0000000000..b7db61d7c1 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/io.h @@ -0,0 +1,22 @@ +#ifndef _ASM_IO_H +#define _ASM_IO_H +extern int printf(const char *fmt, ...); +extern unsigned long get_ticks(void); + +#define _read(source) \ +({ unsigned long __res; \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __read(source) \ +({ unsigned long __res; \ + __asm__ __volatile__( \ + "move\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#endif diff --git a/tests/tcg/mips/mips64-dsp/lbux.c b/tests/tcg/mips/mips64-dsp/lbux.c new file mode 100644 index 0000000000..dbdc87bffe --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/lbux.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long value, rd; + long long *p; + unsigned long long addr, index; + long long result; + + value = 0xBCDEF389; + p = &value; + addr = (unsigned long long)p; + index = 0; + result = value & 0xFF; + __asm + ("lbux %0, %1(%2)\n\t" + : "=r"(rd) + : "r"(index), "r"(addr) + ); + if (rd != result) { + printf("lbux wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/ldx.c b/tests/tcg/mips/mips64-dsp/ldx.c new file mode 100644 index 0000000000..787d9f00b4 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/ldx.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long value, rd; + long long *p; + unsigned long long addr, index; + long long result; + + value = 0xBCDEF389; + p = &value; + addr = (unsigned long long)p; + index = 0; + result = 0xBCDEF389; + __asm + ("ldx %0, %1(%2)\n\t" + : "=r"(rd) + : "r"(index), "r"(addr) + ); + if (rd != result) { + printf("lwx wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/lhx.c b/tests/tcg/mips/mips64-dsp/lhx.c new file mode 100644 index 0000000000..2020e56866 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/lhx.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long value, rd; + long long *p; + unsigned long long addr, index; + long long result; + + value = 0xBCDEF389; + p = &value; + addr = (unsigned long long)p; + index = 0; + result = 0xFFFFFFFFFFFFF389; + __asm + ("lhx %0, %1(%2)\n\t" + : "=r"(rd) + : "r"(index), "r"(addr) + ); + if (rd != result) { + printf("lhx wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/lwx.c b/tests/tcg/mips/mips64-dsp/lwx.c new file mode 100644 index 0000000000..6a81414d65 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/lwx.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long value, rd; + long long *p; + unsigned long long addr, index; + long long result; + + value = 0xBCDEF389; + p = &value; + addr = (unsigned long long)p; + index = 0; + result = 0xFFFFFFFFBCDEF389; + __asm + ("lwx %0, %1(%2)\n\t" + : "=r"(rd) + : "r"(index), "r"(addr) + ); + if (rd != result) { + printf("lwx wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/madd.c b/tests/tcg/mips/mips64-dsp/madd.c new file mode 100644 index 0000000000..de6e44fbc5 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/madd.c @@ -0,0 +1,33 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0x01; + rt = 0x01; + resulth = 0x05; + resultl = 0xB4CC; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "madd $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo)) { + printf("madd wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maddu.c b/tests/tcg/mips/mips64-dsp/maddu.c new file mode 100644 index 0000000000..e9f426a374 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maddu.c @@ -0,0 +1,33 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0x01; + rt = 0x01; + resulth = 0x05; + resultl = 0xB4CC; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "madd $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo)) { + printf("maddu wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_s_l_pwl.c b/tests/tcg/mips/mips64-dsp/maq_s_l_pwl.c new file mode 100644 index 0000000000..c196b43537 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_s_l_pwl.c @@ -0,0 +1,56 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0x98765432FF060000; + rt = 0xfdeca987CB000000; + resulth = 0x05; + resultl = 0x18278587; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.l.pwl $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo)) { + printf("maq_s_l.w.pwl wrong 1\n"); + + return -1; + } + + achi = 0x05; + acli = 0xB4CB; + rs = 0x80000000FF060000; + rt = 0x80000000CB000000; + resulth = 0x05; + resultl = 0xb4ca; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_s.l.pwl $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (resulth != acho) || (resultl != aclo)) { + printf("maq_s_l.w.pwl wrong 2\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_s_l_pwr.c b/tests/tcg/mips/mips64-dsp/maq_s_l_pwr.c new file mode 100644 index 0000000000..e2af69fe2c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_s_l_pwr.c @@ -0,0 +1,56 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0xB4CB; + rs = 0x87898765432; + rt = 0x7878fdeca987; + resulth = 0x05; + resultl = 0x18278587; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.l.pwr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo)) { + printf("maq_s.w.pwr wrong\n"); + + return -1; + } + + achi = 0x05; + acli = 0xB4CB; + rs = 0x89899980000000; + rt = 0x88780000000; + resulth = 0x05; + resultl = 0xb4ca; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_s.l.pwr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (resulth != acho) || (resultl != aclo)) { + printf("maq_s.w.pwr wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_s_w_phl.c b/tests/tcg/mips/mips64-dsp/maq_s_w_phl.c new file mode 100644 index 0000000000..7dba8746e5 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_s_w_phl.c @@ -0,0 +1,60 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long dsp; + long long acho, aclo; + long long resulth, resultl; + long long resdsp; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF060000; + rt = 0xCB000000; + resulth = 0x04; + resultl = 0xffffffff947438CB; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.w.phl $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo)) { + printf("1 maq_s.w.phl error\n"); + + return -1; + } + + achi = 0x06; + acli = 0xB4CB; + rs = 0x80000000; + rt = 0x80000000; + resulth = 0x6; + resultl = 0xffffffff8000b4ca; + resdsp = 1; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_s.w.phl $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo) || + (((dsp >> 17) & 0x01) != resdsp)) { + printf("2 maq_s.w.phl error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_s_w_phr.c b/tests/tcg/mips/mips64-dsp/maq_s_w_phr.c new file mode 100644 index 0000000000..138ee2a691 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_s_w_phr.c @@ -0,0 +1,60 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long dsp; + long long acho, aclo; + long long resulth, resultl; + long long resdsp; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF06; + rt = 0xCB00; + resulth = 0x04; + resultl = 0xffffffff947438CB; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.w.phr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo)) { + printf("1 maq_s.w.phr error\n"); + + return -1; + } + + achi = 0x06; + acli = 0xB4CB; + rs = 0x8000; + rt = 0x8000; + resulth = 0x6; + resultl = 0xffffffff8000b4ca; + resdsp = 1; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_s.w.phr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo) || + (((dsp >> 17) & 0x01) != resdsp)) { + printf("2 maq_s.w.phr error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_s_w_qhll.c b/tests/tcg/mips/mips64-dsp/maq_s_w_qhll.c new file mode 100644 index 0000000000..234a0af293 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_s_w_qhll.c @@ -0,0 +1,62 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0x05; + + rs = 0x1234888899990000; + rt = 0x9876888899990000; + + resulth = 0x05; + resultl = 0x15ae87f5; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.w.qhll $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((resulth != acho) || (resultl != aclo)) { + printf("maq_s.w.qhll wrong\n"); + + return -1; + } + + + achi = 0x04; + acli = 0x06; + rs = 0x8000888899990000; + rt = 0x8000888899990000; + + resulth = 0x04; + resultl = 0xffffffff80000005; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_s.w.qhll $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (resulth != acho) || (resultl != aclo)) { + printf("maq_s.w.qhll wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_s_w_qhlr.c b/tests/tcg/mips/mips64-dsp/maq_s_w_qhlr.c new file mode 100644 index 0000000000..8768cbaa3d --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_s_w_qhlr.c @@ -0,0 +1,62 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0x05; + + rs = 0x1234123412340000; + rt = 0x9876987698760000; + + resulth = 0x05; + resultl = 0x15ae87f5; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.w.qhlr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((resulth != acho) || (resultl != aclo)) { + printf("1 maq_s.w.qhlr wrong\n"); + + return -1; + } + + + achi = 0x04; + acli = 0x06; + rs = 0x8000800080000000; + rt = 0x8000800080000000; + + resulth = 0x04; + resultl = 0xffffffff80000005; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_s.w.qhlr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (resulth != acho) || (resultl != aclo)) { + printf("2 maq_s.w.qhlr wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_s_w_qhrl.c b/tests/tcg/mips/mips64-dsp/maq_s_w_qhrl.c new file mode 100644 index 0000000000..5006e2be34 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_s_w_qhrl.c @@ -0,0 +1,63 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0x05; + + rs = 0x1234888812340000; + rt = 0x9876888898760000; + + resulth = 0x05; + resultl = 0x15ae87f5; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.w.qhrl $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((resulth != acho) || (resultl != aclo)) { + printf("1 maq_s.w.qhrl wrong\n"); + + return -1; + } + + + achi = 0x04; + acli = 0x06; + rs = 0x8888999980000000; + rt = 0x8888999980000000; + + resulth = 0x04; + resultl = 0xffffffff80000005; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_s.w.qhrl $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (resulth != acho) || (resultl != aclo)) { + printf("2 maq_s.w.qhrl wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_s_w_qhrr.c b/tests/tcg/mips/mips64-dsp/maq_s_w_qhrr.c new file mode 100644 index 0000000000..1d213a51b5 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_s_w_qhrr.c @@ -0,0 +1,63 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0x05; + + rs = 0x1234888812341234; + rt = 0x9876888898769876; + + resulth = 0x05; + resultl = 0x15ae87f5; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_s.w.qhrr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((resulth != acho) || (resultl != aclo)) { + printf("1 maq_s.w.qhrr wrong\n"); + + return -1; + } + + + achi = 0x04; + acli = 0x06; + rs = 0x8000888899998000; + rt = 0x8000888899998000; + + resulth = 0x04; + resultl = 0xffffffff80000005; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_s.w.qhrr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (resulth != acho) || (resultl != aclo)) { + printf("2 maq_s.w.qhrr wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_sa_w_phl.c b/tests/tcg/mips/mips64-dsp/maq_sa_w_phl.c new file mode 100644 index 0000000000..5530ffbe69 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_sa_w_phl.c @@ -0,0 +1,60 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long dsp; + long long acho, aclo; + long long resulth, resultl; + long long resdsp; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF060000; + rt = 0xCB000000; + resulth = 0xffffffffffffffff; + resultl = 0xffffffff947438cb; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_sa.w.phl $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo)) { + printf("1 maq_sa.w.phl error\n"); + + return -1; + } + + achi = 0x06; + acli = 0xB4CB; + rs = 0x80000000; + rt = 0x80000000; + resulth = 0x00; + resultl = 0x7fffffff; + resdsp = 0x01; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.phl $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo) || + (((dsp >> 17) & 0x01) != 0x01)) { + printf("2 maq_sa.w.phl error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_sa_w_phr.c b/tests/tcg/mips/mips64-dsp/maq_sa_w_phr.c new file mode 100644 index 0000000000..b611cfa91a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_sa_w_phr.c @@ -0,0 +1,60 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long dsp; + long long acho, aclo; + long long resulth, resultl; + long long resdsp; + + achi = 0x05; + acli = 0xB4CB; + rs = 0xFF06; + rt = 0xCB00; + resulth = 0xffffffffffffffff; + resultl = 0xffffffff947438cb; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_sa.w.phr $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo)) { + printf("1 maq_sa.w.phr error\n"); + + return -1; + } + + achi = 0x06; + acli = 0xB4CB; + rs = 0x8000; + rt = 0x8000; + resulth = 0x00; + resultl = 0x7fffffff; + resdsp = 0x01; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.phr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((resulth != acho) || (resultl != aclo) || + (((dsp >> 17) & 0x01) != 0x01)) { + printf("2 maq_sa.w.phr error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_sa_w_qhll.c b/tests/tcg/mips/mips64-dsp/maq_sa_w_qhll.c new file mode 100644 index 0000000000..136ff2d77b --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_sa_w_qhll.c @@ -0,0 +1,62 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0x05; + + rs = 0x1234888899990000; + rt = 0x9876888899990000; + + resulth = 0x00; + resultl = 0x15ae87f5; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "maq_sa.w.qhll $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((resulth != acho) || (resultl != aclo)) { + printf("1 maq_sa.w.qhll wrong\n"); + + return -1; + } + + + achi = 0x04; + acli = 0x06; + rs = 0x8000888899990000; + rt = 0x8000888899990000; + + resulth = 0x00; + resultl = 0x7fffffff; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.qhll $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (resulth != acho) || (resultl != aclo)) { + printf("2 maq_sa.w.qhll wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_sa_w_qhlr.c b/tests/tcg/mips/mips64-dsp/maq_sa_w_qhlr.c new file mode 100644 index 0000000000..dd0ae1cca2 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_sa_w_qhlr.c @@ -0,0 +1,64 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0x05; + + rs = 0x1234123412340000; + rt = 0x9876987699990000; + + resulth = 0x0; + resultl = 0x15ae87f5; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.qhlr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x0) || (resulth != acho) || (resultl != aclo)) { + printf("maq_sa.w.qhlr wrong\n"); + + return -1; + } + + + achi = 0x04; + acli = 0x06; + rs = 0x8000800099990000; + rt = 0x8000800099990000; + + resulth = 0x00; + resultl = 0x7fffffff; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.qhlr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (resulth != acho) || (resultl != aclo)) { + printf("maq_sa.w.qhlr wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_sa_w_qhrl.c b/tests/tcg/mips/mips64-dsp/maq_sa_w_qhrl.c new file mode 100644 index 0000000000..a3de6f8e2e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_sa_w_qhrl.c @@ -0,0 +1,64 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0x05; + + rs = 0x1234123412340000; + rt = 0x9876987698760000; + + resulth = 0x0; + resultl = 0x15ae87f5; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.qhrl $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x0) || (resulth != acho) || (resultl != aclo)) { + printf("1 maq_sa.w.qhrl wrong\n"); + + return -1; + } + + + achi = 0x04; + acli = 0x06; + rs = 0x8000800080000000; + rt = 0x8000800080000000; + + resulth = 0x00; + resultl = 0x7fffffff; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.qhrl $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (resulth != acho) || (resultl != aclo)) { + printf("2 maq_sa.w.qhrl wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/maq_sa_w_qhrr.c b/tests/tcg/mips/mips64-dsp/maq_sa_w_qhrr.c new file mode 100644 index 0000000000..f02173736a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/maq_sa_w_qhrr.c @@ -0,0 +1,64 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs, dsp; + long long achi, acli; + long long acho, aclo; + long long resulth, resultl; + + achi = 0x05; + acli = 0x05; + + rs = 0x1234123412341234; + rt = 0x9876987698769876; + + resulth = 0x0; + resultl = 0x15ae87f5; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.qhrr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x0) || (resulth != acho) || (resultl != aclo)) { + printf("1 maq_sa.w.qhrr wrong\n"); + + return -1; + } + + + achi = 0x04; + acli = 0x06; + rs = 0x8000800080008000; + rt = 0x8000800080008000; + + resulth = 0x00; + resultl = 0x7fffffff; + + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "maq_sa.w.qhrr $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (resulth != acho) || (resultl != aclo)) { + printf("2 maq_sa.w.qhrr wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mfhi.c b/tests/tcg/mips/mips64-dsp/mfhi.c new file mode 100644 index 0000000000..ee915f796e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mfhi.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long achi, acho; + long long result; + + achi = 0x004433; + result = 0x004433; + + __asm + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + : "=r"(acho) + : "r"(achi) + ); + if (result != acho) { + printf("mfhi wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mflo.c b/tests/tcg/mips/mips64-dsp/mflo.c new file mode 100644 index 0000000000..cdc646b5fc --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mflo.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long acli, aclo; + long long result; + + acli = 0x004433; + result = 0x004433; + + __asm + ("mtlo %1, $ac1\n\t" + "mflo %0, $ac1\n\t" + : "=r"(aclo) + : "r"(acli) + ); + if (result != aclo) { + printf("mflo wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mips_boot.lds b/tests/tcg/mips/mips64-dsp/mips_boot.lds new file mode 100644 index 0000000000..bd7c0c0f3f --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mips_boot.lds @@ -0,0 +1,31 @@ +OUTPUT_ARCH(mips) +SECTIONS +{ + . = 0xffffffff80100000; + . = ALIGN((1 << 13)); + .text : + { + *(.text) + *(.rodata) + *(.rodata.*) + } + + __init_begin = .; + . = ALIGN((1 << 12)); + .init.text : AT(ADDR(.init.text) - 0) + { + *(.init.text) + } + .init.data : AT(ADDR(.init.data) - 0) + { + *(.init.data) + } + . = ALIGN((1 << 12)); + __init_end = .; + + . = ALIGN((1 << 13)); + .data : + { + *(.data) + } +} diff --git a/tests/tcg/mips/mips64-dsp/modsub.c b/tests/tcg/mips/mips64-dsp/modsub.c new file mode 100644 index 0000000000..2c91cb4c59 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/modsub.c @@ -0,0 +1,37 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0xFFFFFFFF; + rt = 0x000000FF; + result = 0xFFFFFF00; + __asm + ("modsub %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (result != rd) { + printf("modsub wrong\n"); + + return -1; + } + + rs = 0x00000000; + rt = 0x00CD1FFF; + result = 0x0000CD1F; + __asm + ("modsub %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (result != rd) { + printf("modsub wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/msub.c b/tests/tcg/mips/mips64-dsp/msub.c new file mode 100644 index 0000000000..75066b5916 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/msub.c @@ -0,0 +1,32 @@ +#include "io.h" + +int main(void) +{ + long long achi, acli, rs, rt; + long long acho, aclo; + long long resulth, resultl; + + rs = 0x00BBAACC; + rt = 0x0B1C3D2F; + achi = 0x00004433; + acli = 0xFFCC0011; + resulth = 0xFFFFFFFFFFF81F29; + resultl = 0xFFFFFFFFB355089D; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "msub $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resulth) || (aclo != resultl)) { + printf("msub wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/msubu.c b/tests/tcg/mips/mips64-dsp/msubu.c new file mode 100644 index 0000000000..55f8ae046f --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/msubu.c @@ -0,0 +1,32 @@ +#include "io.h" + +int main(void) +{ + long long achi, acli, rs, rt; + long long acho, aclo; + long long resulth, resultl; + + rs = 0x00BBAACC; + rt = 0x0B1C3D2F; + achi = 0x00004433; + acli = 0xFFCC0011; + resulth = 0xFFFFFFFFFFF81F29; + resultl = 0xFFFFFFFFB355089D; + + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "msubu $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resulth) || (aclo != resultl)) { + printf("msubu wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mthi.c b/tests/tcg/mips/mips64-dsp/mthi.c new file mode 100644 index 0000000000..857005139b --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mthi.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long achi, acho; + long long result; + + achi = 0x004433; + result = 0x004433; + + __asm + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + : "=r"(acho) + : "r"(achi) + ); + if (result != acho) { + printf("mthi wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mthlip.c b/tests/tcg/mips/mips64-dsp/mthlip.c new file mode 100644 index 0000000000..957cd426f0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mthlip.c @@ -0,0 +1,61 @@ +#include "io.h" + +int main(void) +{ + long long rs, ach, acl, dsp; + long long result, resulth, resultl; + + dsp = 0x07; + ach = 0x05; + acl = 0xB4CB; + rs = 0x00FFBBAA; + resulth = 0xB4CB; + resultl = 0x00FFBBAA; + result = 0x27; + + __asm + ("wrdsp %0, 0x01\n\t" + "mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "mthlip %3, $ac1\n\t" + "mfhi %1, $ac1\n\t" + "mflo %2, $ac1\n\t" + "rddsp %0\n\t" + : "+r"(dsp), "+r"(ach), "+r"(acl) + : "r"(rs) + ); + dsp = dsp & 0x3F; + if ((dsp != result) || (ach != resulth) || (acl != resultl)) { + printf("mthlip wrong\n"); + + return -1; + } + + dsp = 0x3f; + ach = 0x05; + acl = 0xB4CB; + rs = 0x00FFBBAA; + resulth = 0xB4CB; + resultl = 0x00FFBBAA; + result = 0x3f; + + __asm + ("wrdsp %0, 0x01\n\t" + "mthi %1, $ac1\n\t" + "mtlo %2, $ac1\n\t" + "mthlip %3, $ac1\n\t" + "mfhi %1, $ac1\n\t" + "mflo %2, $ac1\n\t" + "rddsp %0\n\t" + : "+r"(dsp), "+r"(ach), "+r"(acl) + : "r"(rs) + ); + dsp = dsp & 0x3F; + if ((dsp != result) || (ach != resulth) || (acl != resultl)) { + printf("mthlip wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mtlo.c b/tests/tcg/mips/mips64-dsp/mtlo.c new file mode 100644 index 0000000000..304fffbe7c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mtlo.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long acli, aclo; + long long result; + + acli = 0x004433; + result = 0x004433; + + __asm + ("mthi %1, $ac1\n\t" + "mfhi %0, $ac1\n\t" + : "=r"(aclo) + : "r"(acli) + ); + if (result != aclo) { + printf("mtlo wrong\n"); + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/muleq_s_pw_qhl.c b/tests/tcg/mips/mips64-dsp/muleq_s_pw_qhl.c new file mode 100644 index 0000000000..6c68d45afe --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/muleq_s_pw_qhl.c @@ -0,0 +1,56 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result; + + rd = 0; + rs = 0x45BCFFFF12345678; + rt = 0x98529AD287654321; + result = 0x52fbec7035a2ca5c; + + __asm + ("muleq_s.pw.qhl %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (result != rd) { + printf("1 muleq_s.pw.qhl error\n"); + + return -1; + } + + rd = 0; + rs = 0x45BC800012345678; + rt = 0x9852800087654321; + result = 0x52fbec707FFFFFFF; + + __asm + ("muleq_s.pw.qhl %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (result != rd) { + printf("2 muleq_s.pw.qhl error\n"); + + return -1; + } + + rd = 0; + __asm + ("rddsp %0\n\t" + : "=r"(rd) + ); + rd = rd >> 21; + rd = rd & 0x1; + + if (rd != 1) { + printf("3 muleq_s.pw.qhl error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/muleq_s_pw_qhr.c b/tests/tcg/mips/mips64-dsp/muleq_s_pw_qhr.c new file mode 100644 index 0000000000..fa8b41fd39 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/muleq_s_pw_qhr.c @@ -0,0 +1,57 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rd = 0; + rs = 0x1234567845BCFFFF; + rt = 0x8765432198529AD2; + result = 0x52fbec7035a2ca5c; + + __asm + ("muleq_s.pw.qhr %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (result != rd) { + printf("1 muleq_s.pw.qhr error\n"); + + return -1; + } + + rd = 0; + rs = 0x1234567845BC8000; + rt = 0x8765432198528000; + result = 0x52fbec707FFFFFFF; + + __asm + ("muleq_s.pw.qhr %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (result != rd) { + printf("2 muleq_s.pw.qhr error\n"); + + return -1; + } + + rd = 0; + __asm + ("rddsp %0\n\t" + : "=r"(rd) + ); + rd = rd >> 21; + rd = rd & 0x1; + + if (rd != 1) { + printf("3 muleq_s.pw.qhr error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/muleq_s_w_phl.c b/tests/tcg/mips/mips64-dsp/muleq_s_w_phl.c new file mode 100644 index 0000000000..997a9f64d9 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/muleq_s_w_phl.c @@ -0,0 +1,46 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x80009988; + rt = 0x80009988; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm + ("muleq_s.w.phl %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if ((rd != result) || (dsp != resultdsp)) { + printf("muleq_s.w.phl wrong\n"); + + return -1; + } + + rs = 0x12343322; + rt = 0x43213322; + result = 0x98be968; + resultdsp = 1; + + __asm + ("muleq_s.w.phl %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if ((rd != result) || (dsp != resultdsp)) { + printf("muleq_s.w.phl wrong\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/muleq_s_w_phr.c b/tests/tcg/mips/mips64-dsp/muleq_s_w_phr.c new file mode 100644 index 0000000000..0e594794dd --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/muleq_s_w_phr.c @@ -0,0 +1,45 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x8000; + rt = 0x8000; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm + ("muleq_s.w.phr %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if ((rd != result) || (dsp != resultdsp)) { + printf("muleq_s.w.phr wrong\n"); + + return -1; + } + + rs = 0x1234; + rt = 0x4321; + result = 0x98be968; + resultdsp = 1; + + __asm + ("muleq_s.w.phr %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if ((rd != result) || (dsp != resultdsp)) { + printf("muleq_s.w.phr wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/muleu_s_ph_qbl.c b/tests/tcg/mips/mips64-dsp/muleu_s_ph_qbl.c new file mode 100644 index 0000000000..2f444c9f85 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/muleu_s_ph_qbl.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0xFFFFFFFFFFFF0000; + resultdsp = 1; + + __asm + ("muleu_s.ph.qbl %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if ((rd != result) || (dsp != resultdsp)) { + printf("muleu_s.ph.qbl wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/muleu_s_ph_qbr.c b/tests/tcg/mips/mips64-dsp/muleu_s_ph_qbr.c new file mode 100644 index 0000000000..8bd0e9942c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/muleu_s_ph_qbr.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x8000; + rt = 0x80004321; + result = 0xFFFFFFFFFFFF0000; + resultdsp = 1; + + __asm + ("muleu_s.ph.qbr %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if ((rd != result) || (dsp != resultdsp)) { + printf("muleu_s.ph.qbr wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/muleu_s_qh_obl.c b/tests/tcg/mips/mips64-dsp/muleu_s_qh_obl.c new file mode 100644 index 0000000000..db0d386e88 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/muleu_s_qh_obl.c @@ -0,0 +1,30 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long resdsp, result; + + rd = 0; + rs = 0x1234567802020202; + rt = 0x0034432112344321; + result = 0x03A8FFFFFFFFFFFF; + resdsp = 0x01; + + __asm + ("muleu_s.qh.obl %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 21) & 0x01; + if ((rd != result) || (resdsp != dsp)) { + printf("muleu_s.qh.obl error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/muleu_s_qh_obr.c b/tests/tcg/mips/mips64-dsp/muleu_s_qh_obr.c new file mode 100644 index 0000000000..52ed9c095a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/muleu_s_qh_obr.c @@ -0,0 +1,31 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long resdsp, result; + + rd = 0; + rs = 0x0202020212345678; + + rt = 0x0034432112344321; + result = 0x03A8FFFFFFFFFFFF; + resdsp = 0x01; + + __asm + ("muleu_s.qh.obr %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + + dsp = (dsp >> 21) & 0x01; + if ((rd != result) || (resdsp != dsp)) { + printf("muleu_s.qh.obr error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mulq_rs_ph.c b/tests/tcg/mips/mips64-dsp/mulq_rs_ph.c new file mode 100644 index 0000000000..fd6233d4df --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mulq_rs_ph.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x7FFF098C; + resultdsp = 1; + + __asm + ("mulq_rs.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if ((rd != result) || (dsp != resultdsp)) { + printf("mulq_rs.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mulq_rs_qh.c b/tests/tcg/mips/mips64-dsp/mulq_rs_qh.c new file mode 100644 index 0000000000..7863c05912 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mulq_rs_qh.c @@ -0,0 +1,33 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dsp, dspresult; + rt = 0x80003698CE8F9201; + rs = 0x800034634BCDE321; + result = 0x7fff16587a530313; + + dspresult = 0x01; + + __asm + ("mulq_rs.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + if (rd != result) { + printf("mulq_rs.qh error\n"); + + return -1; + } + + dsp = (dsp >> 21) & 0x01; + if (dsp != dspresult) { + printf("mulq_rs.qh DSPControl Reg ouflag error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c b/tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c new file mode 100644 index 0000000000..02548f85cf --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mulsaq_s_l_pw.c @@ -0,0 +1,59 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dsp; + long long achi, acli; + long long acho, aclo; + long long resl, resh; + + achi = 0x4; + acli = 0x4; + + rs = 0x1234567887654321; + rt = 0x8765432112345678; + + resh = 0x4; + resl = 0x4; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "mulsaq_s.l.pw $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("1 mulsaq_s.l.pw wrong\n"); + + return -1; + } + + achi = 0x4; + acli = 0x4; + + rs = 0x8000000087654321; + rt = 0x8000000012345678; + + resh = 0x4; + resl = 0x1e8ee513; + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "mulsaq_s.l.pw $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (acho != resh) || (aclo != resl)) { + printf("2 mulsaq_s.l.pw wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mulsaq_s_w_qh.c b/tests/tcg/mips/mips64-dsp/mulsaq_s_w_qh.c new file mode 100644 index 0000000000..92d7a0b4f2 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mulsaq_s_w_qh.c @@ -0,0 +1,57 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, dsp; + long long achi, acli; + long long acho, aclo; + long long resl, resh; + + achi = 0x4; + acli = 0x4; + + rs = 0x5678123443218765; + rt = 0x4321876556781234; + + resh = 0x4; + resl = 0x342fcbd4; + __asm + ("mthi %2, $ac1\n\t" + "mtlo %3, $ac1\n\t" + "mulsaq_s.w.qh $ac1, %4, %5\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("1 mulsaq_s.w.qh wrong\n"); + return -1; + } + + achi = 0x4; + acli = 0x4; + + rs = 0x8000800087654321; + rt = 0x8000800012345678; + + resh = 0x3; + resl = 0xffffffffe5e81a1c; + __asm + ("mthi %3, $ac1\n\t" + "mtlo %4, $ac1\n\t" + "mulsaq_s.w.qh $ac1, %5, %6\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "=r"(acho), "=r"(aclo), "=r"(dsp) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x1; + if ((dsp != 0x1) || (acho != resh) || (aclo != resl)) { + printf("2 mulsaq_s.w.qh wrong\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/mult.c b/tests/tcg/mips/mips64-dsp/mult.c new file mode 100644 index 0000000000..4a294d1a0c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/mult.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, ach, acl; + long long result, resulth, resultl; + + rs = 0x00FFBBAA; + rt = 0x4B231000; + resulth = 0x4b0f01; + resultl = 0x71f8a000; + __asm + ("mult $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(ach), "=r"(acl) + : "r"(rs), "r"(rt) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("mult wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/multu.c b/tests/tcg/mips/mips64-dsp/multu.c new file mode 100644 index 0000000000..21a8a7c77d --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/multu.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt, ach, acl; + long long result, resulth, resultl; + + rs = 0x00FFBBAA; + rt = 0x4B231000; + resulth = 0x4b0f01; + resultl = 0x71f8a000; + __asm + ("multu $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "=r"(ach), "=r"(acl) + : "r"(rs), "r"(rt) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("multu wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/packrl_ph.c b/tests/tcg/mips/mips64-dsp/packrl_ph.c new file mode 100644 index 0000000000..3722b0ae6c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/packrl_ph.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x56788765; + + __asm + ("packrl.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (result != rd) { + printf("packrl.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/packrl_pw.c b/tests/tcg/mips/mips64-dsp/packrl_pw.c new file mode 100644 index 0000000000..7807418834 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/packrl_pw.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long res; + + rs = 0x1234567887654321; + rt = 0xabcdef9812345678; + + res = 0x87654321abcdef98; + + __asm + ("packrl.pw %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != res) { + printf("packrl.pw error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/pick_ob.c b/tests/tcg/mips/mips64-dsp/pick_ob.c new file mode 100644 index 0000000000..160049ffd4 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/pick_ob.c @@ -0,0 +1,66 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long res; + + dsp = 0xff000000; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x1234567812345678; + + __asm + ("wrdsp %1, 0x10\n\t" + "pick.ob %0, %2, %3\n\t" + : "=r"(rd) + : "r"(dsp), "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("1 pick.ob error\n"); + return -1; + } + + dsp = 0x00000000; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x8765432187654321; + + __asm + ("wrdsp %1, 0x10\n\t" + "pick.ob %0, %2, %3\n\t" + : "=r"(rd) + : "r"(dsp), "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("2 pick.ob error\n"); + return -1; + } + + dsp = 0x34000000; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x8765567887344321; + + __asm + ("wrdsp %1, 0x10\n\t" + "pick.ob %0, %2, %3\n\t" + : "=r"(rd) + : "r"(dsp), "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("3 pick.ob error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/pick_ph.c b/tests/tcg/mips/mips64-dsp/pick_ph.c new file mode 100644 index 0000000000..8800c14d1e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/pick_ph.c @@ -0,0 +1,60 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x0A000000; + result = 0x12344321; + + __asm + ("wrdsp %3, 0x10\n\t" + "pick.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dsp) + ); + if (rd != result) { + printf("1 pick.ph wrong\n"); + + return -1; + } + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x03000000; + result = 0x12345678; + + __asm + ("wrdsp %3, 0x10\n\t" + "pick.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dsp) + ); + if (rd != result) { + printf("2 pick.ph wrong\n"); + + return -1; + } + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x00000000; + result = 0xffffffff87654321; + + __asm + ("wrdsp %3, 0x10\n\t" + "pick.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dsp) + ); + if (rd != result) { + printf("3 pick.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/pick_pw.c b/tests/tcg/mips/mips64-dsp/pick_pw.c new file mode 100644 index 0000000000..24d80f551a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/pick_pw.c @@ -0,0 +1,48 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long res; + dsp = 0xff000000; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x1234567812345678; + + __asm + ("wrdsp %1, 0x10\n\t" + "wrdsp %1\n\t" + "pick.pw %0, %2, %3\n\t" + : "=r"(rd), "+r"(dsp) + : "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("pick.pw error\n"); + return -1; + } + + dsp = 0x00000000; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x8765432187654321; + + __asm + ("wrdsp %1, 0x10\n\t" + "wrdsp %1\n\t" + "pick.pw %0, %2, %3\n\t" + : "=r"(rd), "+r"(dsp) + : "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("pick.pw error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/pick_qb.c b/tests/tcg/mips/mips64-dsp/pick_qb.c new file mode 100644 index 0000000000..0d5de9db9e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/pick_qb.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x0f000000; + result = 0x12345678; + + __asm + ("wrdsp %3, 0x10\n\t" + "pick.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dsp) + ); + if (rd != result) { + printf("pick.qb wrong\n"); + + return -1; + } + + rs = 0x12345678; + rt = 0x87654321; + dsp = 0x00000000; + result = 0xffffffff87654321; + + __asm + ("wrdsp %3, 0x10\n\t" + "pick.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt), "r"(dsp) + ); + if (rd != result) { + printf("pick.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/pick_qh.c b/tests/tcg/mips/mips64-dsp/pick_qh.c new file mode 100644 index 0000000000..aa2e2938af --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/pick_qh.c @@ -0,0 +1,48 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long res; + dsp = 0xff000000; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x1234567812345678; + + __asm + ("wrdsp %1, 0x10\n\t" + "wrdsp %1\n\t" + "pick.qh %0, %2, %3\n\t" + : "=r"(rd), "+r"(dsp) + : "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("pick.qh error\n"); + return -1; + } + + dsp = 0x00000000; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x8765432187654321; + + __asm + ("wrdsp %1, 0x10\n\t" + "wrdsp %1\n\t" + "pick.qh %0, %2, %3\n\t" + : "=r"(rd), "+r"(dsp) + : "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("pick.qh error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceq_l_pwl.c b/tests/tcg/mips/mips64-dsp/preceq_l_pwl.c new file mode 100644 index 0000000000..64551007cf --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceq_l_pwl.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + rt = 0xFFFFFFFF11111111; + result = 0xFFFFFFFF00000000; + + __asm + ("preceq.l.pwl %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("preceq.l.pwl wrong\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/preceq_l_pwr.c b/tests/tcg/mips/mips64-dsp/preceq_l_pwr.c new file mode 100644 index 0000000000..1e05339d23 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceq_l_pwr.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + rt = 0xFFFFFFFF11111111; + result = 0x1111111100000000; + + __asm + ("preceq.l.pwl %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("preceq.l.pwr wrong\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/preceq_pw_qhl.c b/tests/tcg/mips/mips64-dsp/preceq_pw_qhl.c new file mode 100644 index 0000000000..f44b940492 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceq_pw_qhl.c @@ -0,0 +1,21 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + rt = 0x0123456789ABCDEF; + result = 0x0123000045670000; + + __asm + ("preceq.pw.qhl %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("preceq.pw.qhl error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceq_pw_qhla.c b/tests/tcg/mips/mips64-dsp/preceq_pw_qhla.c new file mode 100644 index 0000000000..f0f78f43c5 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceq_pw_qhla.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + + rt = 0x123456789ABCDEF0; + result = 0x123400009ABC0000; + + __asm + ("preceq.pw.qhla %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("preceq.pw.qhla error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceq_pw_qhr.c b/tests/tcg/mips/mips64-dsp/preceq_pw_qhr.c new file mode 100644 index 0000000000..709d4f9004 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceq_pw_qhr.c @@ -0,0 +1,21 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + rt = 0x0123456789ABCDEF; + result = 0x89AB0000CDEF0000; + + __asm + ("preceq.pw.qhr %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("preceq.pw.qhr error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceq_pw_qhra.c b/tests/tcg/mips/mips64-dsp/preceq_pw_qhra.c new file mode 100644 index 0000000000..4d071ec863 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceq_pw_qhra.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + + rt = 0x123456789ABCDEF0; + result = 0x56780000DEF00000; + + __asm + ("preceq.pw.qhra %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("preceq.pw.qhra error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceq_w_phl.c b/tests/tcg/mips/mips64-dsp/preceq_w_phl.c new file mode 100644 index 0000000000..4ed3fc030c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceq_w_phl.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0xFFFFFFFF87650000; + + __asm + ("preceq.w.phl %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("preceq.w.phl wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceq_w_phr.c b/tests/tcg/mips/mips64-dsp/preceq_w_phr.c new file mode 100644 index 0000000000..e2ea0933b2 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceq_w_phr.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0x43210000; + + __asm + ("preceq.w.phr %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("preceq.w.phr wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precequ_ph_qbl.c b/tests/tcg/mips/mips64-dsp/precequ_ph_qbl.c new file mode 100644 index 0000000000..17b73311dc --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precequ_ph_qbl.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0x43803280; + + __asm + ("precequ.ph.qbl %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("precequ.ph.qbl wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precequ_ph_qbla.c b/tests/tcg/mips/mips64-dsp/precequ_ph_qbla.c new file mode 100644 index 0000000000..15e94946b1 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precequ_ph_qbla.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0x43802180; + + __asm + ("precequ.ph.qbla %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("precequ.ph.qbla wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precequ_ph_qbr.c b/tests/tcg/mips/mips64-dsp/precequ_ph_qbr.c new file mode 100644 index 0000000000..495368ce0b --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precequ_ph_qbr.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0x21801080; + + __asm + ("precequ.ph.qbr %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("precequ.ph.qbr wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precequ_ph_qbra.c b/tests/tcg/mips/mips64-dsp/precequ_ph_qbra.c new file mode 100644 index 0000000000..7c6636975c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precequ_ph_qbra.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0x32801080; + + __asm + ("precequ.ph.qbra %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("precequ.ph.qbra wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precequ_qh_obl.c b/tests/tcg/mips/mips64-dsp/precequ_qh_obl.c new file mode 100644 index 0000000000..176d2365a8 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precequ_qh_obl.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + rt = 0x123456789ABCDEF0; + result = 0x09001A002B003C00; + + __asm + ("precequ.qh.obla %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("precequ.qh.obla error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precequ_qh_obla.c b/tests/tcg/mips/mips64-dsp/precequ_qh_obla.c new file mode 100644 index 0000000000..93a36a4855 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precequ_qh_obla.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + rt = 0x123456789ABCDEF0; + result = 0x09002B004D006F00; + + __asm + ("precequ.qh.obla %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("precequ.qh.obla error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precequ_qh_obr.c b/tests/tcg/mips/mips64-dsp/precequ_qh_obr.c new file mode 100644 index 0000000000..121473083b --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precequ_qh_obr.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + + rt = 0x123456789ABCDEF0; + result = 0x4D005E006F007000; + + __asm + ("precequ.qh.obr %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("precequ.qh.obr error\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/precequ_qh_obra.c b/tests/tcg/mips/mips64-dsp/precequ_qh_obra.c new file mode 100644 index 0000000000..3aa0e096ca --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precequ_qh_obra.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + + rt = 0x123456789ABCDEF0; + result = 0x1A003C005D007000; + + __asm + ("precequ.qh.obra %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("precequ.qh.obra error\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/preceu_ph_qbl.c b/tests/tcg/mips/mips64-dsp/preceu_ph_qbl.c new file mode 100644 index 0000000000..81f7917c19 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceu_ph_qbl.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0x00870065; + + __asm + ("preceu.ph.qbl %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("preceu.ph.qbl wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceu_ph_qbla.c b/tests/tcg/mips/mips64-dsp/preceu_ph_qbla.c new file mode 100644 index 0000000000..38cf6a62b9 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceu_ph_qbla.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0x00870043; + + __asm + ("preceu.ph.qbla %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("preceu.ph.qbla wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceu_ph_qbr.c b/tests/tcg/mips/mips64-dsp/preceu_ph_qbr.c new file mode 100644 index 0000000000..70c32b6716 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceu_ph_qbr.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0x00430021; + + __asm + ("preceu.ph.qbr %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("preceu.ph.qbr wrong"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceu_ph_qbra.c b/tests/tcg/mips/mips64-dsp/preceu_ph_qbra.c new file mode 100644 index 0000000000..c6638aaafd --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceu_ph_qbra.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0x00650021; + + __asm + ("preceu.ph.qbra %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (result != rd) { + printf("preceu.ph.qbra wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceu_qh_obl.c b/tests/tcg/mips/mips64-dsp/preceu_qh_obl.c new file mode 100644 index 0000000000..63f9373b08 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceu_qh_obl.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + rt = 0x123456789ABCDEF0; + result = 0x0012003400560078; + + __asm + ("preceu.qh.obl %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("preceu.qh.obl error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceu_qh_obla.c b/tests/tcg/mips/mips64-dsp/preceu_qh_obla.c new file mode 100644 index 0000000000..5fb65e4049 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceu_qh_obla.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + rt = 0x123456789ABCDEF0; + result = 0x00120056009A00DE; + + __asm + ("preceu.qh.obla %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("preceu.qh.obla error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceu_qh_obr.c b/tests/tcg/mips/mips64-dsp/preceu_qh_obr.c new file mode 100644 index 0000000000..9af3b6372e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceu_qh_obr.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + + rt = 0x123456789ABCDEF0; + result = 0x009A00BC00DE00F0; + + __asm + ("preceu.qh.obr %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("preceu.qh.obr error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/preceu_qh_obra.c b/tests/tcg/mips/mips64-dsp/preceu_qh_obra.c new file mode 100644 index 0000000000..fd04083371 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/preceu_qh_obra.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + + rt = 0x123456789ABCDEF0; + result = 0x0034007800BC00F0; + + __asm + ("preceu.qh.obra %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("preceu.qh.obra error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precr_ob_qh.c b/tests/tcg/mips/mips64-dsp/precr_ob_qh.c new file mode 100644 index 0000000000..ce2da79af8 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precr_ob_qh.c @@ -0,0 +1,25 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long res; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x3478347865216521; + + __asm + ("precr.ob.qh %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("precr.ob.qh error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precr_sra_qh_pw.c b/tests/tcg/mips/mips64-dsp/precr_sra_qh_pw.c new file mode 100644 index 0000000000..8bb16de9af --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precr_sra_qh_pw.c @@ -0,0 +1,40 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long res; + + rt = 0x8765432187654321; + rs = 0x1234567812345678; + + res = 0x4321432156785678; + + __asm + ("precr_sra.qh.pw %0, %1, 0x0\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("precr_sra.qh.pw error\n"); + return -1; + } + + rt = 0x8765432187654321; + rs = 0x1234567812345678; + + res = 0x5432543245674567; + + __asm + ("precr_sra.qh.pw %0, %1, 0x4\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("precr_sra.qh.pw error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c b/tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c new file mode 100644 index 0000000000..734ac322e7 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precr_sra_r_qh_pw.c @@ -0,0 +1,40 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long res; + + rt = 0x8765432187654321; + rs = 0x1234567812345678; + + res = 0x4321432156785678; + + __asm + ("precr_sra_r.qh.pw %0, %1, 0x0\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("precr_sra_r.qh.pw error\n"); + return -1; + } + + rt = 0x8765432187654321; + rs = 0x1234567812345678; + + res = 0x5432543245684568; + + __asm + ("precr_sra_r.qh.pw %0, %1, 0x4\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("precr_sra_r.qh.pw error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precrq_ob_qh.c b/tests/tcg/mips/mips64-dsp/precrq_ob_qh.c new file mode 100644 index 0000000000..4f61b1709e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precrq_ob_qh.c @@ -0,0 +1,25 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long res; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x1256125687438743; + + __asm + ("precrq.ob.qh %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("precrq.ob.qh error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precrq_ph_w.c b/tests/tcg/mips/mips64-dsp/precrq_ph_w.c new file mode 100644 index 0000000000..f0946abdcb --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precrq_ph_w.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x12348765; + + __asm + ("precrq.ph.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (result != rd) { + printf("precrq.ph.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precrq_pw_l.c b/tests/tcg/mips/mips64-dsp/precrq_pw_l.c new file mode 100644 index 0000000000..da957c0743 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precrq_pw_l.c @@ -0,0 +1,25 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long res; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x1234567887654321; + + __asm + ("precrq.pw.l %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("precrq.pw.l error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precrq_qb_ph.c b/tests/tcg/mips/mips64-dsp/precrq_qb_ph.c new file mode 100644 index 0000000000..f417c9f342 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precrq_qb_ph.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x12568743; + + __asm + ("precrq.qb.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (result != rd) { + printf("precrq.qb.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precrq_qh_pw.c b/tests/tcg/mips/mips64-dsp/precrq_qh_pw.c new file mode 100644 index 0000000000..4a4ffef8ea --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precrq_qh_pw.c @@ -0,0 +1,25 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long res; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x1234123487658765; + + __asm + ("precrq.qh.pw %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("precrq.qh.pw error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c b/tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c new file mode 100644 index 0000000000..61da3331fb --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precrq_rs_ph_w.c @@ -0,0 +1,41 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x12348765; + + __asm + ("precrq_rs.ph.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (result != rd) { + printf("1 precrq_rs.ph.w wrong\n"); + + return -1; + } + + rs = 0x7fffC678; + rt = 0x865432A0; + result = 0x7fff8654; + + __asm + ("precrq_rs.ph.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((result != rd) || (((dsp >> 22) & 0x01) != 1)) { + printf("2 precrq_rs.ph.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precrq_rs_qh_pw.c b/tests/tcg/mips/mips64-dsp/precrq_rs_qh_pw.c new file mode 100644 index 0000000000..ac78728abf --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precrq_rs_qh_pw.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long res; + + rs = 0x1234567812345678; + rt = 0x8765432187654321; + + res = 0x1234123487658765; + + __asm + ("precrq_rs.qh.pw %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("precrq_rs.qh.pw error\n"); + return -1; + } + + rs = 0x7fffC67812345678; + rt = 0x8765432187654321; + + res = 0x7fff123487658765; + + __asm + ("precrq_rs.qh.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + + if (rd != res) { + printf("precrq_rs.qh.pw error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precrqu_s_ob_qh.c b/tests/tcg/mips/mips64-dsp/precrqu_s_ob_qh.c new file mode 100644 index 0000000000..e27c36b7fd --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precrqu_s_ob_qh.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long res, resdsp; + + rs = 0x7fff567812345678; + rt = 0x8765432187654321; + + res = 0xffac24ac00860086; + resdsp = 0x1; + + __asm + ("precrqu_s.ob.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 22) & 0x1; + if ((rd != res) || (dsp != resdsp)) { + printf("precrq_s.ob.qh error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/precrqu_s_qb_ph.c b/tests/tcg/mips/mips64-dsp/precrqu_s_qb_ph.c new file mode 100644 index 0000000000..cb1fee4508 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/precrqu_s_qb_ph.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x12345678; + rt = 0x87657fff; + result = 0x24AC00FF; + + __asm + ("precrqu_s.qb.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((result != rd) || (((dsp >> 22) & 0x01) != 0x01)) { + printf("precrqu_s.qb.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/prependd.c b/tests/tcg/mips/mips64-dsp/prependd.c new file mode 100644 index 0000000000..b4208c2dab --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/prependd.c @@ -0,0 +1,37 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long res; + rt = 0x1234567887654321; + rs = 0xabcd1234abcd8765; + + res = 0x1234567887654321; + __asm + ("prependd %0, %1, 0x0\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("prependd error\n"); + return -1; + } + + rt = 0x1234567887654321; + rs = 0xabcd1234abcd8765; + + res = 0xd876512345678876; + __asm + ("prependd %0, %1, 0x4\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("prependd error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/prependw.c b/tests/tcg/mips/mips64-dsp/prependw.c new file mode 100644 index 0000000000..d91bd2023c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/prependw.c @@ -0,0 +1,37 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long res; + rt = 0x1234567887654321; + rs = 0xabcd1234abcd8765; + + res = 0x1234567887654321; + __asm + ("prependw %0, %1, 0x0\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("prependw error\n"); + return -1; + } + + rt = 0x1234567887654321; + rs = 0xabcd1234abcd8765; + + res = 0x5123456788765432; + __asm + ("prependw %0, %1, 0x4\n\t" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("prependw error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/printf.c b/tests/tcg/mips/mips64-dsp/printf.c new file mode 100644 index 0000000000..cf8676d390 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/printf.c @@ -0,0 +1,266 @@ + +typedef unsigned long va_list; + +#define ACC 4 +#define __read(source) \ +({ va_list __res; \ + __asm__ __volatile__( \ + "move\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +enum format_type { + FORMAT_TYPE_NONE, + FORMAT_TYPE_HEX, + FORMAT_TYPE_ULONG, + FORMAT_TYPE_FLOAT +}; + +struct printf_spec { + char type; +}; + +static int format_decode(char *fmt, struct printf_spec *spec) +{ + char *start = fmt; + + for (; *fmt ; ++fmt) { + if (*fmt == '%') { + break; + } + } + + switch (*++fmt) { + case 'x': + spec->type = FORMAT_TYPE_HEX; + break; + + case 'd': + spec->type = FORMAT_TYPE_ULONG; + break; + + case 'f': + spec->type = FORMAT_TYPE_FLOAT; + break; + + default: + spec->type = FORMAT_TYPE_NONE; + } + + return ++fmt - start; +} + +void *memcpy(void *dest, void *src, int n) +{ + int i; + char *s = src; + char *d = dest; + + for (i = 0; i < n; i++) { + d[i] = s[i]; + } + return dest; +} + +char *number(char *buf, va_list num) +{ + int i; + char *str = buf; + static char digits[16] = "0123456789abcdef"; + str = str + sizeof(num) * 2; + + for (i = 0; i < sizeof(num) * 2; i++) { + *--str = digits[num & 15]; + num >>= 4; + } + + return buf + sizeof(num) * 2; +} + +char *__number(char *buf, va_list num) +{ + int i; + va_list mm = num; + char *str = buf; + + if (!num) { + *str++ = '0'; + return str; + } + + for (i = 0; mm; mm = mm/10, i++) { + /* Do nothing. */ + } + + str = str + i; + + while (num) { + *--str = num % 10 + 48; + num = num / 10; + } + + return str + i; +} + +va_list modf(va_list args, va_list *integer, va_list *num) +{ + int i; + double dot_v = 0; + va_list E, DOT, DOT_V; + + if (!args) { + return 0; + } + + for (i = 0, args = args << 1 >> 1; i < 52; i++) { + if ((args >> i) & 0x1) { + break; + } + } + + *integer = 0; + + if ((args >> 56 != 0x3f) || (args >> 52 == 0x3ff)) { + E = (args >> 52) - 1023; + DOT = 52 - E - i; + DOT_V = args << (12 + E) >> (12 + E) >> i; + *integer = ((args << 12 >> 12) >> (i + DOT)) | (1 << E); + } else { + E = ~((args >> 52) - 1023) + 1; + DOT_V = args << 12 >> 12; + + dot_v += 1.0 / (1 << E); + + for (i = 1; i <= 16; i++) { + if ((DOT_V >> (52 - i)) & 0x1) { + dot_v += 1.0 / (1 << E + i); + } + } + + for (i = 1, E = 0; i <= ACC; i++) { + dot_v *= 10; + if (!(va_list)dot_v) { + E++; + } + } + + *num = E; + + return dot_v; + } + + if (args & 0xf) { + for (i = 1; i <= 16; i++) { + if ((DOT_V >> (DOT - i)) & 0x1) { + dot_v += 1.0 / (1 << i); + } + } + + for (i = 1, E = 0; i <= ACC; i++) { + dot_v *= 10; + if (!(va_list)dot_v) { + E++; + } + } + + *num = E; + + return dot_v; + } else if (DOT) { + for (i = 1; i <= DOT; i++) { + if ((DOT_V >> (DOT - i)) & 0x1) { + dot_v += 1.0 / (1 << i); + } + } + + for (i = 1; i <= ACC; i++) { + dot_v = dot_v * 10; + } + + return dot_v; + } + + return 0; +} + +int vsnprintf(char *buf, int size, char *fmt, va_list args) +{ + char *str, *mm; + struct printf_spec spec = {0}; + + str = mm = buf; + + while (*fmt) { + char *old_fmt = fmt; + int read = format_decode(fmt, &spec); + + fmt += read; + + switch (spec.type) { + case FORMAT_TYPE_NONE: { + memcpy(str, old_fmt, read); + str += read; + break; + } + case FORMAT_TYPE_HEX: { + memcpy(str, old_fmt, read); + str = number(str + read, args); + for (; *mm ; ++mm) { + if (*mm == '%') { + *mm = '0'; + break; + } + } + break; + } + case FORMAT_TYPE_ULONG: { + memcpy(str, old_fmt, read - 2); + str = __number(str + read - 2, args); + break; + } + case FORMAT_TYPE_FLOAT: { + va_list integer, dot_v, num; + dot_v = modf(args, &integer, &num); + memcpy(str, old_fmt, read - 2); + str += read - 2; + if ((args >> 63 & 0x1)) { + *str++ = '-'; + } + str = __number(str, integer); + if (dot_v) { + *str++ = '.'; + while (num--) { + *str++ = '0'; + } + str = __number(str, dot_v); + } + break; + } + } + } + *str = '\0'; + + return str - buf; +} + +static void serial_out(char *str) +{ + while (*str) { + *(char *)0xffffffffb80003f8 = *str++; + } +} + +int vprintf(char *fmt, va_list args) +{ + int printed_len = 0; + static char printf_buf[512]; + printed_len = vsnprintf(printf_buf, sizeof(printf_buf), fmt, args); + serial_out(printf_buf); + return printed_len; +} + +int printf(char *fmt, ...) +{ + return vprintf(fmt, __read($5)); +} diff --git a/tests/tcg/mips/mips64-dsp/raddu_l_ob.c b/tests/tcg/mips/mips64-dsp/raddu_l_ob.c new file mode 100644 index 0000000000..76ddf25fb9 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/raddu_l_ob.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, result; + rs = 0x12345678ABCDEF0; + result = 0x000000000001E258; + + __asm + ("raddu.l.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs) + ); + + if (rd != result) { + printf("raddu.l.ob error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/raddu_w_qb.c b/tests/tcg/mips/mips64-dsp/raddu_w_qb.c new file mode 100644 index 0000000000..c9d6535bba --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/raddu_w_qb.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs; + long long result; + + rs = 0x12345678; + result = 0x114; + + __asm + ("raddu.w.qb %0, %1\n\t" + : "=r"(rd) + : "r"(rs) + ); + if (rd != result) { + printf("raddu.w.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/rddsp.c b/tests/tcg/mips/mips64-dsp/rddsp.c new file mode 100644 index 0000000000..7165572435 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/rddsp.c @@ -0,0 +1,53 @@ +#include "io.h" + +int main(void) +{ + long long dsp_i, dsp_o; + long long ccond_i, outflag_i, efi_i, c_i, scount_i, pos_i; + long long ccond_o, outflag_o, efi_o, c_o, scount_o, pos_o; + long long ccond_r, outflag_r, efi_r, c_r, scount_r, pos_r; + + ccond_i = 0x000000BC;/* 4 */ + outflag_i = 0x0000001B;/* 3 */ + efi_i = 0x00000001;/* 5 */ + c_i = 0x00000001;/* 2 */ + scount_i = 0x0000000F;/* 1 */ + pos_i = 0x0000000C;/* 0 */ + + dsp_i = (ccond_i << 24) | \ + (outflag_i << 16) | \ + (efi_i << 14) | \ + (c_i << 13) | \ + (scount_i << 7) | \ + pos_i; + + ccond_r = ccond_i; + outflag_r = outflag_i; + efi_r = efi_i; + c_r = c_i; + scount_r = scount_i; + pos_r = pos_i; + + __asm + ("wrdsp %1, 0x3F\n\t" + "rddsp %0, 0x3F\n\t" + : "=r"(dsp_o) + : "r"(dsp_i) + ); + + ccond_o = (dsp_o >> 24) & 0xFF; + outflag_o = (dsp_o >> 16) & 0xFF; + efi_o = (dsp_o >> 14) & 0x01; + c_o = (dsp_o >> 14) & 0x01; + scount_o = (dsp_o >> 7) & 0x3F; + pos_o = dsp_o & 0x1F; + + if ((ccond_o != ccond_r) || (outflag_o != outflag_r) || (efi_o != efi_r) \ + || (c_o != c_r) || (scount_o != scount_r) || (pos_o != pos_r)) { + printf("rddsp wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/repl_ob.c b/tests/tcg/mips/mips64-dsp/repl_ob.c new file mode 100644 index 0000000000..20cb780136 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/repl_ob.c @@ -0,0 +1,21 @@ +#include "io.h" + +int main(void) +{ + long long rd, result; + rd = 0; + result = 0xFFFFFFFFFFFFFFFF; + + __asm + ("repl.ob %0, 0xFF\n\t" + : "=r"(rd) + ); + + if (result != rd) { + printf("repl.ob error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/repl_ph.c b/tests/tcg/mips/mips64-dsp/repl_ph.c new file mode 100644 index 0000000000..11d29bdbc2 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/repl_ph.c @@ -0,0 +1,30 @@ +#include "io.h" + +int main(void) +{ + long long rd, result; + + result = 0x01BF01BF; + __asm + ("repl.ph %0, 0x1BF\n\t" + : "=r"(rd) + ); + if (rd != result) { + printf("repl.ph wrong\n"); + + return -1; + } + + result = 0x01FF01FF; + __asm + ("repl.ph %0, 0x01FF\n\t" + : "=r"(rd) + ); + if (rd != result) { + printf("repl.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/repl_pw.c b/tests/tcg/mips/mips64-dsp/repl_pw.c new file mode 100644 index 0000000000..d35376a2a3 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/repl_pw.c @@ -0,0 +1,34 @@ +#include "io.h" + +int main(void) +{ + long long rd, result; + rd = 0; + result = 0x000001FF000001FF; + + __asm + ("repl.pw %0, 0x1FF\n\t" + : "=r"(rd) + ); + + if (result != rd) { + printf("repl.pw error1\n"); + + return -1; + } + + rd = 0; + result = 0xFFFFFE00FFFFFE00; + __asm + ("repl.pw %0, 0xFFFFFFFFFFFFFE00\n\t" + : "=r"(rd) + ); + + if (result != rd) { + printf("repl.pw error2\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/repl_qb.c b/tests/tcg/mips/mips64-dsp/repl_qb.c new file mode 100644 index 0000000000..592feaecb0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/repl_qb.c @@ -0,0 +1,19 @@ +#include "io.h" + +int main(void) +{ + long long rd, result; + + result = 0xFFFFFFFFBFBFBFBF; + __asm + ("repl.qb %0, 0xBF\n\t" + : "=r"(rd) + ); + if (rd != result) { + printf("repl.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/repl_qh.c b/tests/tcg/mips/mips64-dsp/repl_qh.c new file mode 100644 index 0000000000..82afc37167 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/repl_qh.c @@ -0,0 +1,34 @@ +#include "io.h" + +int main(void) +{ + long long rd, result; + rd = 0; + result = 0x01FF01FF01FF01FF; + + __asm + ("repl.qh %0, 0x1FF\n\t" + : "=r"(rd) + ); + + if (result != rd) { + printf("repl.qh error 1\n"); + + return -1; + } + + rd = 0; + result = 0xFE00FE00FE00FE00; + __asm + ("repl.qh %0, 0xFFFFFFFFFFFFFE00\n\t" + : "=r"(rd) + ); + + if (result != rd) { + printf("repl.qh error 2\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/replv_ob.c b/tests/tcg/mips/mips64-dsp/replv_ob.c new file mode 100644 index 0000000000..31ff3186d3 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/replv_ob.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + + rt = 0xFF; + result = 0xFFFFFFFFFFFFFFFF; + + __asm + ("replv.ob %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("replv.ob error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/replv_ph.c b/tests/tcg/mips/mips64-dsp/replv_ph.c new file mode 100644 index 0000000000..0af7a36b40 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/replv_ph.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x12345678; + result = 0x56785678; + __asm + ("replv.ph %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("replv.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/replv_pw.c b/tests/tcg/mips/mips64-dsp/replv_pw.c new file mode 100644 index 0000000000..e1789af4c8 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/replv_pw.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, result; + rd = 0; + rt = 0xFFFFFFFF; + result = 0xFFFFFFFFFFFFFFFF; + + __asm + ("replv.pw %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (result != rd) { + printf("replv.pw error\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/replv_qb.c b/tests/tcg/mips/mips64-dsp/replv_qb.c new file mode 100644 index 0000000000..d99298c31e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/replv_qb.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x12345678; + result = 0x78787878; + __asm + ("replv.qb %0, %1\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("replv.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shilo.c b/tests/tcg/mips/mips64-dsp/shilo.c new file mode 100644 index 0000000000..5f454f69e0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shilo.c @@ -0,0 +1,29 @@ +#include "io.h" + +int main(void) +{ + long long ach, acl; + long long resulth, resultl; + + ach = 0xBBAACCFF; + acl = 0x1C3B001D; + + resulth = 0x17755; + resultl = 0xFFFFFFFF99fe3876; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "shilo $ac1, 0x0F\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("shilo wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shilov.c b/tests/tcg/mips/mips64-dsp/shilov.c new file mode 100644 index 0000000000..e82615a8c9 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shilov.c @@ -0,0 +1,31 @@ +#include "io.h" + +int main(void) +{ + long long rs, ach, acl; + long long resulth, resultl; + + rs = 0x0F; + ach = 0xBBAACCFF; + acl = 0x1C3B001D; + + resulth = 0x17755; + resultl = 0xFFFFFFFF99fe3876; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "shilov $ac1, %2\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("shilov wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shll_ob.c b/tests/tcg/mips/mips64-dsp/shll_ob.c new file mode 100644 index 0000000000..7dcb58ff46 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shll_ob.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, dsp; + long long res, resdsp; + + rt = 0x9ba8765433456789; + res = 0x9ba8765433456789; + resdsp = 0x0; + __asm + ("shll.ob %0, %2, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + + dsp = (dsp >> 22) & 0x1; + + if ((dsp != resdsp) || (rd != res)) { + printf("shll.ob error\n"); + return -1; + } + + rt = 0x9ba8765433456789; + res = 0xd840b0a098283848; + resdsp = 0x1; + __asm + ("shll.ob %0, %2, 0x3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + + dsp = (dsp >> 22) & 0x1; + + if ((dsp != resdsp) || (rd != res)) { + printf("shll.ob error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shll_ph.c b/tests/tcg/mips/mips64-dsp/shll_ph.c new file mode 100644 index 0000000000..42b462d20d --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shll_ph.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, dsp; + long long result, resultdsp; + + rt = 0x12345678; + result = 0x12345678; + resultdsp = 0; + + __asm + ("shll.ph %0, %2, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shll.ph wrong\n"); + + return -1; + } + + rt = 0x12345678; + result = 0xFFFFFFFFA000C000; + resultdsp = 1; + + __asm + ("shll.ph %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shll.ph wrong1\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shll_pw.c b/tests/tcg/mips/mips64-dsp/shll_pw.c new file mode 100644 index 0000000000..d7878b2792 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shll_pw.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, dsp; + long long result, resultdsp; + + rt = 0x8765432112345678; + result = 0x8765432112345678; + resultdsp = 0; + + __asm + ("shll.pw %0, %2, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shll.pw wrong\n"); + return -1; + } + + rt = 0x8765432112345678; + result = 0x6543210034567800; + resultdsp = 1; + + __asm + ("shll.pw %0, %2, 0x8\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shll.pw wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shll_qb.c b/tests/tcg/mips/mips64-dsp/shll_qb.c new file mode 100644 index 0000000000..c21ab6698a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shll_qb.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, dsp; + long long result, resultdsp; + + rt = 0x87654321; + result = 0x38281808; + resultdsp = 0x01; + + __asm + ("shll.qb %0, %2, 0x03\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + if (rd != result) { + printf("shll.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shll_qh.c b/tests/tcg/mips/mips64-dsp/shll_qh.c new file mode 100644 index 0000000000..1380825a32 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shll_qh.c @@ -0,0 +1,42 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, dsp; + long long res, resdsp; + + rt = 0x9ba8765433456789; + res = 0x9ba8765433456789; + resdsp = 0x0; + __asm + ("shll.qh %0, %2, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x1; + + if ((dsp != resdsp) || (rd != res)) { + printf("shll.qh error\n"); + return -1; + } + + rt = 0x9ba8765433456789; + res = 0xdd40b2a09a283c48; + resdsp = 0x1; + __asm + ("shll.qh %0, %2, 0x3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + + dsp = (dsp >> 22) & 0x1; + + if ((dsp != resdsp) || (rd != res)) { + printf("shll.qh error1\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shll_s_ph.c b/tests/tcg/mips/mips64-dsp/shll_s_ph.c new file mode 100644 index 0000000000..1cf5d6da6e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shll_s_ph.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, dsp; + long long result, resultdsp; + + rt = 0x12345678; + result = 0x12345678; + resultdsp = 0x0; + + __asm + ("shll_s.ph %0, %2, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shll_s.ph wrong\n"); + + return -1; + } + + rt = 0x12345678; + result = 0x7FFF7FFF; + resultdsp = 0x01; + + __asm + ("shll_s.ph %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shll_s.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shll_s_pw.c b/tests/tcg/mips/mips64-dsp/shll_s_pw.c new file mode 100644 index 0000000000..e38f6860c7 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shll_s_pw.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, dsp; + long long result, resultdsp; + + rt = 0x8765432112345678; + result = 0x8765432112345678; + resultdsp = 0; + + __asm + ("shll_s.pw %0, %2, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shll_s.pw wrong\n"); + return -1; + } + + rt = 0x8765432112345678; + result = 0x800000007fffffff; + resultdsp = 1; + + __asm + ("shll_s.pw %0, %2, 0x8\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shll_s.pw wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shll_s_qh.c b/tests/tcg/mips/mips64-dsp/shll_s_qh.c new file mode 100644 index 0000000000..f2f57fa27a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shll_s_qh.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, dsp; + long long res, resdsp; + + rt = 0x9ba8765433456789; + res = 0x9ba8765433456789; + resdsp = 0x0; + __asm + ("shll_s.qh %0, %2, 0x0\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + + dsp = (dsp >> 22) & 0x1; + + if ((dsp != resdsp) || (rd != res)) { + printf("shll_s.qh error\n"); + return -1; + } + + rt = 0x9ba8765433456789; + res = 0x80007fff7fff7fff; + resdsp = 0x1; + __asm + ("shll_s.qh %0, %2, 0x3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + + dsp = (dsp >> 22) & 0x1; + + if ((dsp != resdsp) || (rd != res)) { + printf("shll_s.qh error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shll_s_w.c b/tests/tcg/mips/mips64-dsp/shll_s_w.c new file mode 100644 index 0000000000..57800615d2 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shll_s_w.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, dsp; + long long result, resultdsp; + + rt = 0x12345678; + result = 0x7FFFFFFF; + resultdsp = 0x01; + + __asm + ("shll_s.w %0, %2, 0x0B\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt) + ); + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shll_s.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shllv_ob.c b/tests/tcg/mips/mips64-dsp/shllv_ob.c new file mode 100644 index 0000000000..96a2e6f55f --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shllv_ob.c @@ -0,0 +1,45 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs, dsp; + long long result, resultdsp; + + rt = 0x8765432112345678; + rs = 0x0; + result = 0x8765432112345678; + resultdsp = 0; + + __asm + ("shllv.ob %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv.ob wrong\n"); + return -1; + } + + rt = 0x8765432112345678; + rs = 0x4; + result = 0x7050301020406080; + resultdsp = 1; + + __asm + ("shllv.ob %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv.ob wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shllv_ph.c b/tests/tcg/mips/mips64-dsp/shllv_ph.c new file mode 100644 index 0000000000..532291f3fb --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shllv_ph.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x0B; + rt = 0x12345678; + result = 0xFFFFFFFFA000C000; + resultdsp = 1; + + __asm + ("shllv.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shllv_pw.c b/tests/tcg/mips/mips64-dsp/shllv_pw.c new file mode 100644 index 0000000000..8d4ec295bd --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shllv_pw.c @@ -0,0 +1,45 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs, dsp; + long long result, resultdsp; + rt = 0x8765432112345678; + rs = 0x0; + result = 0x8765432112345678; + resultdsp = 0; + + __asm + ("shllv.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv.pw wrong\n"); + return -1; + } + + + rt = 0x8765432112345678; + rs = 0x8; + result = 0x6543210034567800; + resultdsp = 1; + + __asm + ("shllv.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv.pw wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shllv_qb.c b/tests/tcg/mips/mips64-dsp/shllv_qb.c new file mode 100644 index 0000000000..e49356b8ec --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shllv_qb.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x03; + rt = 0x87654321; + result = 0x38281808; + resultdsp = 0x01; + + __asm + ("shllv.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + if (rd != result) { + printf("shllv.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shllv_qh.c b/tests/tcg/mips/mips64-dsp/shllv_qh.c new file mode 100644 index 0000000000..0de4077e7d --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shllv_qh.c @@ -0,0 +1,45 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs, dsp; + long long result, resultdsp; + + rt = 0x8765432112345678; + rs = 0x0; + result = 0x8765432112345678; + resultdsp = 0; + + __asm + ("shllv.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv.qh wrong\n"); + return -1; + } + + rt = 0x8765432112345678; + rs = 0x4; + result = 0x7650321023406780; + resultdsp = 1; + + __asm + ("shllv.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv.qh wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shllv_s_ph.c b/tests/tcg/mips/mips64-dsp/shllv_s_ph.c new file mode 100644 index 0000000000..7e69f941f4 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shllv_s_ph.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x0B; + rt = 0x12345678; + result = 0x7FFF7FFF; + resultdsp = 0x01; + + __asm + ("shllv_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv_s.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shllv_s_pw.c b/tests/tcg/mips/mips64-dsp/shllv_s_pw.c new file mode 100644 index 0000000000..f8dc8d2964 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shllv_s_pw.c @@ -0,0 +1,45 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs, dsp; + long long result, resultdsp; + + rt = 0x8765432112345678; + rs = 0x0; + result = 0x8765432112345678; + resultdsp = 0; + + __asm + ("shllv_s.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv_s.pw wrong\n"); + return -1; + } + + rt = 0x8765432112345678; + rs = 0x8; + result = 0x800000007fffffff; + resultdsp = 1; + + __asm + ("shllv_s.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv_s.pw wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shllv_s_qh.c b/tests/tcg/mips/mips64-dsp/shllv_s_qh.c new file mode 100644 index 0000000000..db3832d091 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shllv_s_qh.c @@ -0,0 +1,45 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs, dsp; + long long result, resultdsp; + + rt = 0x8765432112345678; + rs = 0x0; + result = 0x8765432112345678; + resultdsp = 0; + + __asm + ("shllv_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv_s.qh wrong\n"); + return -1; + } + + rt = 0x8765432112345678; + rs = 0x4; + result = 0x80007fff7fff7fff; + resultdsp = 1; + + __asm + ("shllv_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv_s.qh wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shllv_s_w.c b/tests/tcg/mips/mips64-dsp/shllv_s_w.c new file mode 100644 index 0000000000..5f6af8b8c0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shllv_s_w.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x0B; + rt = 0x12345678; + result = 0x7FFFFFFF; + resultdsp = 0x01; + + __asm + ("shllv_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rt), "r"(rs) + ); + dsp = (dsp >> 22) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("shllv_s.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shra_ob.c b/tests/tcg/mips/mips64-dsp/shra_ob.c new file mode 100644 index 0000000000..d7fcfa816b --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shra_ob.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main() +{ + long long rd, rt; + long long res; + + rt = 0xbc98756abc654389; + res = 0xfbf9f7f6fb0604f8; + + __asm + ("shra.ob %0, %1, 0x4\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shra.ob error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shra_ph.c b/tests/tcg/mips/mips64-dsp/shra_ph.c new file mode 100644 index 0000000000..a2dc014742 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shra_ph.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0xFFFFFFFFF0EC0864; + + __asm + ("shra.ph %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("shra.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shra_pw.c b/tests/tcg/mips/mips64-dsp/shra_pw.c new file mode 100644 index 0000000000..33b1b8fe72 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shra_pw.c @@ -0,0 +1,36 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long res; + + rt = 0x1234567887654321; + res = 0x01234567f8765432; + + __asm + ("shra.pw %0, %1, 0x4" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shra.pw error\n"); + return -1; + } + + rt = 0x1234567887654321; + res = 0x1234567887654321; + + __asm + ("shra.pw %0, %1, 0x0" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shra.pw error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shra_qh.c b/tests/tcg/mips/mips64-dsp/shra_qh.c new file mode 100644 index 0000000000..85dbfef3ea --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shra_qh.c @@ -0,0 +1,37 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long res; + + rt = 0x8512345654323454; + res = 0xf851034505430345; + + __asm + ("shra.qh %0, %1, 0x4\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shra.qh error\n"); + return -1; + } + + rt = 0x8512345654323454; + res = 0x8512345654323454; + + __asm + ("shra.qh %0, %1, 0x0\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shra.qh error1\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shra_r_ob.c b/tests/tcg/mips/mips64-dsp/shra_r_ob.c new file mode 100644 index 0000000000..184709443e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shra_r_ob.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main() +{ + long long rd, rt; + long long res; + + rt = 0xbc98756abc654389; + res = 0xfcfaf8f7fc0705f9; + + __asm + ("shra_r.ob %0, %1, 0x4\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shra_r.ob error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shra_r_ph.c b/tests/tcg/mips/mips64-dsp/shra_r_ph.c new file mode 100644 index 0000000000..e0943ad474 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shra_r_ph.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0xFFFFFFFFF0ED0864; + + __asm + ("shra_r.ph %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("shra_r.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shra_r_pw.c b/tests/tcg/mips/mips64-dsp/shra_r_pw.c new file mode 100644 index 0000000000..6a86e684b8 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shra_r_pw.c @@ -0,0 +1,36 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long res; + + rt = 0x1234567887654321; + res = 0x01234568f8765432; + + __asm + ("shra_r.pw %0, %1, 0x4" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shra_r.pw error\n"); + return -1; + } + + rt = 0x1234567887654321; + res = 0x1234567887654321; + + __asm + ("shra_r.pw %0, %1, 0x0" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shra_r.pw error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shra_r_qh.c b/tests/tcg/mips/mips64-dsp/shra_r_qh.c new file mode 100644 index 0000000000..d5c2110efe --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shra_r_qh.c @@ -0,0 +1,37 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long res; + + rt = 0x8512345654323454; + res = 0xf0a2068b0a86068b; + + __asm + ("shra_r.qh %0, %1, 0x3\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shra_r.qh error\n"); + return -1; + } + + rt = 0x8512345654323454; + res = 0x8512345654323454; + + __asm + ("shra_r.qh %0, %1, 0x0\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shra_r.qh error1\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shra_r_w.c b/tests/tcg/mips/mips64-dsp/shra_r_w.c new file mode 100644 index 0000000000..36d2c9c887 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shra_r_w.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x87654321; + result = 0xFFFFFFFFF0ECA864; + + __asm + ("shra_r.w %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("shra_r.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrav_ph.c b/tests/tcg/mips/mips64-dsp/shrav_ph.c new file mode 100644 index 0000000000..1b4e983746 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrav_ph.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x03; + rt = 0x87654321; + result = 0xFFFFFFFFF0EC0864; + + __asm + ("shrav.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + if (rd != result) { + printf("shrav.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrav_pw.c b/tests/tcg/mips/mips64-dsp/shrav_pw.c new file mode 100644 index 0000000000..e19d515797 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrav_pw.c @@ -0,0 +1,38 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs; + long long res; + + rt = 0x1234567887654321; + rs = 0x4; + res = 0x01234567f8765432; + + __asm + ("shrav.pw %0, %1, %2" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shrav.pw error\n"); + return -1; + } + + rt = 0x1234567887654321; + rs = 0x0; + res = 0x1234567887654321; + + __asm + ("shrav.pw %0, %1, %2" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shrav.pw error1\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrav_qh.c b/tests/tcg/mips/mips64-dsp/shrav_qh.c new file mode 100644 index 0000000000..dc92e09d44 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrav_qh.c @@ -0,0 +1,39 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs; + long long res; + + rt = 0x8512345654323454; + rs = 0x4; + res = 0xf851034505430345; + + __asm + ("shrav.qh %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shrav.qh error\n"); + return -1; + } + + rt = 0x8512345654323454; + rs = 0x0; + res = 0x8512345654323454; + + __asm + ("shrav.qh %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shrav.qh error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrav_r_ph.c b/tests/tcg/mips/mips64-dsp/shrav_r_ph.c new file mode 100644 index 0000000000..350d5294fc --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrav_r_ph.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x03; + rt = 0x87654321; + result = 0xFFFFFFFFF0ED0864; + + __asm + ("shrav_r.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + if (rd != result) { + printf("shrav_r.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrav_r_pw.c b/tests/tcg/mips/mips64-dsp/shrav_r_pw.c new file mode 100644 index 0000000000..25b0545931 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrav_r_pw.c @@ -0,0 +1,37 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs; + long long res; + + rt = 0x1234567887654321; + rs = 0x4; + res = 0x01234568f8765432; + + __asm + ("shrav_r.pw %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shrav_r.pw error\n"); + return -1; + } + + rt = 0x1234567887654321; + rs = 0x0; + res = 0x1234567887654321; + + __asm + ("shrav_r.pw %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + if (rd != res) { + printf("shrav_r.pw error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrav_r_qh.c b/tests/tcg/mips/mips64-dsp/shrav_r_qh.c new file mode 100644 index 0000000000..fd187a1e0b --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrav_r_qh.c @@ -0,0 +1,39 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs; + long long res; + + rt = 0x8512345654323454; + rs = 0x3; + res = 0xf0a2068b0a86068b; + + __asm + ("shrav_r.qh %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shrav_r.qh error\n"); + return -1; + } + + rt = 0x400000000000000; + rs = 0x0; + res = 0x400000000000000; + + __asm + ("shrav_r.qh %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shrav_r.qh error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrav_r_w.c b/tests/tcg/mips/mips64-dsp/shrav_r_w.c new file mode 100644 index 0000000000..3766c7255c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrav_r_w.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x03; + rt = 0x87654321; + result = 0xFFFFFFFFF0ECA864; + + __asm + ("shrav_r.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + if (rd != result) { + printf("shrav_r.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrl_ob.c b/tests/tcg/mips/mips64-dsp/shrl_ob.c new file mode 100644 index 0000000000..a1145713a0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrl_ob.c @@ -0,0 +1,38 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long res; + + rt = 0xab76543212345678; + res = 0x150e0a0602060a0f; + + __asm + ("shrl.ob %0, %1, 0x3\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shrl.ob error\n"); + return -1; + } + + rt = 0xab76543212345678; + res = 0xab76543212345678; + + __asm + ("shrl.ob %0, %1, 0x0\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shrl.ob error\n"); + return -1; + } + + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrl_qb.c b/tests/tcg/mips/mips64-dsp/shrl_qb.c new file mode 100644 index 0000000000..c0e36dba10 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrl_qb.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x12345678; + result = 0x00010203; + + __asm + ("shrl.qb %0, %1, 0x05\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("shrl.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrl_qh.c b/tests/tcg/mips/mips64-dsp/shrl_qh.c new file mode 100644 index 0000000000..c1562463e0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrl_qh.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt; + long long res; + + rt = 0x8765679abc543786; + res = 0x087606790bc50378; + + __asm + ("shrl.qh %0, %1, 0x4\n\t" + : "=r"(rd) + : "r"(rt) + ); + + if (rd != res) { + printf("shrl.qh error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrlv_ob.c b/tests/tcg/mips/mips64-dsp/shrlv_ob.c new file mode 100644 index 0000000000..cb39c46716 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrlv_ob.c @@ -0,0 +1,39 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs; + long long res; + + rt = 0xab76543212345678; + rs = 0x3; + res = 0x150e0a0602060a0f; + + __asm + ("shrlv.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shrlv.ob error\n"); + return -1; + } + + rt = 0xab76543212345678; + rs = 0x0; + res = 0xab76543212345678; + + __asm + ("shrlv.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shrlv.ob error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrlv_qb.c b/tests/tcg/mips/mips64-dsp/shrlv_qb.c new file mode 100644 index 0000000000..5616aa9c5b --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrlv_qb.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x05; + rt = 0x12345678; + result = 0x00010203; + + __asm + ("shrlv.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + if (rd != result) { + printf("shrlv.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/shrlv_qh.c b/tests/tcg/mips/mips64-dsp/shrlv_qh.c new file mode 100644 index 0000000000..05de2fd6c8 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/shrlv_qh.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs; + long long res; + + rt = 0x8765679abc543786; + rs = 0x4; + res = 0x087606790bc50378; + + __asm + ("shrlv.qh %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shrlv.qh error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/subq_ph.c b/tests/tcg/mips/mips64-dsp/subq_ph.c new file mode 100644 index 0000000000..6a1b18610c --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subq_ph.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0xFFFFFFFF8ACF1357; + resultdsp = 0x01; + + __asm + ("subq.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("subq.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/subq_pw.c b/tests/tcg/mips/mips64-dsp/subq_pw.c new file mode 100644 index 0000000000..32f96ba4bd --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subq_pw.c @@ -0,0 +1,44 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + rt = 0x123456789ABCDEF0; + rs = 0x123456789ABCDEF0; + result = 0x0; + dspresult = 0x0; + + __asm + ("subq.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + dspreg = (dspreg >> 20) & 0x1; + if ((rd != result) || (dspreg != dspresult)) { + printf("subq.pw error1\n\t"); + + return -1; + } + + rt = 0x123456789ABCDEF1; + rs = 0x123456789ABCDEF2; + result = 0x0000000000000001; + dspresult = 0x0; + + __asm + ("subq.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + dspreg = (dspreg >> 20) & 0x1; + if ((rd != result) || (dspreg != dspresult)) { + printf("subq.pw error2\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/subq_qh.c b/tests/tcg/mips/mips64-dsp/subq_qh.c new file mode 100644 index 0000000000..76d5f0a10a --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subq_qh.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + rt = 0x123456789ABCDEF0; + rs = 0x123456789ABCDEF0; + result = 0x0; + dspresult = 0x0; + + __asm + ("subq.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + dspreg = (dspreg >> 20) & 0x1; + if ((rd != result) || (dspreg != dspresult)) { + printf("subq.qh error\n\t"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/subq_s_ph.c b/tests/tcg/mips/mips64-dsp/subq_s_ph.c new file mode 100644 index 0000000000..0b162f07ea --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subq_s_ph.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x7FFF1357; + resultdsp = 0x01; + + __asm + ("subq_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("subq_s.ph wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/subq_s_pw.c b/tests/tcg/mips/mips64-dsp/subq_s_pw.c new file mode 100644 index 0000000000..e8e0b0567e --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subq_s_pw.c @@ -0,0 +1,63 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + rt = 0x9FFFFFFD9FFFFFFD; + rs = 0x4000000080000000; + result = 0x7fffffffe0000003; + dspresult = 0x1; + + __asm + ("subq_s.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + dspreg = (dspreg >> 20) & 0x1; + if ((rd != result) || (dspreg != dspresult)) { + printf("subq_s.pw error1\n"); + + return -1; + } + + rt = 0x123456789ABCDEF1; + rs = 0x123456789ABCDEF2; + result = 0x0000000000000001; + /* This time we do not set dspctrl, but it setted in pre-action. */ + dspresult = 0x1; + + __asm + ("subq_s.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + dspreg = (dspreg >> 20) & 0x1; + if ((rd != result) || (dspreg != dspresult)) { + printf("subq_s.pw error2\n"); + + return -1; + } + + rt = 0x8000000080000000; + rs = 0x7000000070000000; + dspresult = 0x1; + + __asm + ("subq_s.pw %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = (dspreg >> 20) & 0x1; + if ((dspreg != dspresult)) { + printf("subq_s.pw error3\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/subq_s_qh.c b/tests/tcg/mips/mips64-dsp/subq_s_qh.c new file mode 100644 index 0000000000..4053b6b884 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subq_s_qh.c @@ -0,0 +1,61 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEF0; + result = 0x0; + dspresult = 0x0; + + __asm + ("subq_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + dspreg = (dspreg >> 20) & 0x1; + if ((rd != result) || (dspreg != dspresult)) { + printf("subq_s.qh error1\n"); + + return -1; + } + + rs = 0x4000000080000000; + rt = 0x9FFD00009FFC0000; + result = 0x7FFF0000E0040000; + dspresult = 0x1; + + __asm + ("subq_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + dspreg = (dspreg >> 20) & 0x1; + if ((rd != result) || (dspreg != dspresult)) { + printf("subq_s.qh error2\n"); + + return -1; + } + + rs = 0x8000000000000000; + rt = 0x7000000000000000; + result = 0x8000000000000000; + dspresult = 0x1; + __asm + ("subq_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = (dspreg >> 20) & 0x1; + if ((rd != result) || (dspreg != dspresult)) { + printf("subq_s.qh error3\n"); + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/subq_s_w.c b/tests/tcg/mips/mips64-dsp/subq_s_w.c new file mode 100644 index 0000000000..91d32da172 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subq_s_w.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x7FFFFFFF; + resultdsp = 0x01; + + __asm + ("subq_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("subq_s.w wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/subu_ob.c b/tests/tcg/mips/mips64-dsp/subu_ob.c new file mode 100644 index 0000000000..f670967113 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subu_ob.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + rs = 0x6F6F6F6F6F6F6F6F; + rt = 0x5E5E5E5E5E5E5E5E; + result = 0x1111111111111111; + dspresult = 0x0; + + __asm + ("subu.ob %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + if ((rd != result) || (dspreg != dspresult)) { + printf("subu.ob error\n"); + + return -1; + } + + return 0; +} + diff --git a/tests/tcg/mips/mips64-dsp/subu_qb.c b/tests/tcg/mips/mips64-dsp/subu_qb.c new file mode 100644 index 0000000000..9eb80df379 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subu_qb.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0xFFFFFFFF8BCF1357; + resultdsp = 0x01; + + __asm + ("subu.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("subu.qb wrong\n"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/subu_s_ob.c b/tests/tcg/mips/mips64-dsp/subu_s_ob.c new file mode 100644 index 0000000000..5df64e5ff0 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subu_s_ob.c @@ -0,0 +1,26 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dspreg, result, dspresult; + rs = 0x12345678ABCDEF0; + rt = 0x12345678ABCDEF1; + result = 0x00000000000; + dspresult = 0x01; + + __asm + ("subu_s.ob %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("subu_s.ob error\n\t"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/subu_s_qb.c b/tests/tcg/mips/mips64-dsp/subu_s_qb.c new file mode 100644 index 0000000000..9de76f4a1f --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/subu_s_qb.c @@ -0,0 +1,27 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x00001357; + resultdsp = 0x01; + + __asm + ("subu_s.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + if ((dsp != resultdsp) || (rd != result)) { + printf("subu_s_qb wrong"); + + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dsp/wrdsp.c b/tests/tcg/mips/mips64-dsp/wrdsp.c new file mode 100644 index 0000000000..3033fd88d1 --- /dev/null +++ b/tests/tcg/mips/mips64-dsp/wrdsp.c @@ -0,0 +1,48 @@ +#include "io.h" + +int main(void) +{ + long long dsp_i, dsp_o; + long long ccond_i, outflag_i, efi_i, c_i, scount_i, pos_i; + long long ccond_o, outflag_o, efi_o, c_o, scount_o, pos_o; + long long ccond_r, outflag_r, efi_r, c_r, scount_r, pos_r; + + ccond_i = 0x000000BC;/* 4 */ + outflag_i = 0x0000001B;/* 3 */ + efi_i = 0x00000001;/* 5 */ + c_i = 0x00000001;/* 2 */ + scount_i = 0x0000000F;/* 1 */ + pos_i = 0x0000000C;/* 0 */ + + dsp_i = (ccond_i << 24) | (outflag_i << 16) | (efi_i << 14) | (c_i << 13) + | (scount_i << 7) | pos_i; + + ccond_r = ccond_i; + outflag_r = outflag_i; + efi_r = efi_i; + c_r = c_i; + scount_r = scount_i; + pos_r = pos_i; + + __asm + ("wrdsp %1, 0x3F\n\t" + "rddsp %0, 0x3F\n\t" + : "=r"(dsp_o) + : "r"(dsp_i) + ); + + ccond_o = (dsp_o >> 24) & 0xFF; + outflag_o = (dsp_o >> 16) & 0xFF; + efi_o = (dsp_o >> 14) & 0x01; + c_o = (dsp_o >> 14) & 0x01; + scount_o = (dsp_o >> 7) & 0x3F; + pos_o = dsp_o & 0x1F; + + if ((ccond_o != ccond_r) || (outflag_o != outflag_r) || (efi_o != efi_r) \ + || (c_o != c_r) || (scount_o != scount_r) || (pos_o != pos_r)) { + printf("wrddsp wrong\n"); + + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/.directory b/tests/tcg/mips/mips64-dspr2/.directory new file mode 100644 index 0000000000..c75a91451c --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/.directory @@ -0,0 +1,2 @@ +[Dolphin] +Timestamp=2012,8,3,16,41,52 diff --git a/tests/tcg/mips/mips64-dspr2/Makefile b/tests/tcg/mips/mips64-dspr2/Makefile new file mode 100644 index 0000000000..ba44bb9c0e --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/Makefile @@ -0,0 +1,116 @@ +CROSS_COMPILE ?= mips64el-unknown-linux-gnu- + +SIM = qemu-system-mips64el +SIMFLAGS = -nographic -cpu mips64dspr2 -kernel + +AS = $(CROSS_COMPILE)as +LD = $(CROSS_COMPILE)ld +CC = $(CROSS_COMPILE)gcc +AR = $(CROSS_COMPILE)ar +NM = $(CROSS_COMPILE)nm +STRIP = $(CROSS_COMPILE)strip +RANLIB = $(CROSS_COMPILE)ranlib +OBJCOPY = $(CROSS_COMPILE)objcopy +OBJDUMP = $(CROSS_COMPILE)objdump + +VECTORS_OBJ ?= ./head.o ./printf.o + +HEAD_FLAGS ?= -nostdinc -mabi=64 -G 0 -mno-abicalls -fno-pic -pipe \ + -msoft-float -march=mips64 -Wa,-mips64 -Wa,--trap \ + -msym32 -DKBUILD_64BIT_SYM32 -I./ + +CFLAGS ?= -nostdinc -mabi=64 -G 0 -mno-abicalls -fno-pic -fno-builtin \ + -pipe -march=mips64r2 -mgp64 -mdspr2 -static -Wa,--trap -msym32 \ + -DKBUILD_64BIT_SYM32 -I./ + +LDFLAGS = -T./mips_boot.lds -L./ +FLAGS = -nostdlib -mabi=64 -march=mips64r2 -mgp64 -mdspr2 + +TESTCASES = absq_s_qb.tst +TESTCASES += addqh_ph.tst +TESTCASES += addqh_r_ph.tst +TESTCASES += addqh_r_w.tst +TESTCASES += addqh_w.tst +#TESTCASES += adduh_ob.tst +TESTCASES += adduh_qb.tst +#TESTCASES += adduh_r_ob.tst +TESTCASES += adduh_r_qb.tst +TESTCASES += addu_ph.tst +#TESTCASES += addu_qh.tst +TESTCASES += addu_s_ph.tst +#TESTCASES += addu_s_qh.tst +TESTCASES += append.tst +TESTCASES += balign.tst +#TESTCASES += cmpgdu_eq_ob.tst +TESTCASES += cmpgdu_eq_qb.tst +#TESTCASES += cmpgdu_le_ob.tst +TESTCASES += cmpgdu_le_qb.tst +#TESTCASES += cmpgdu_lt_ob.tst +TESTCASES += cmpgdu_lt_qb.tst +#TESTCASES += dbalign.tst +TESTCASES += dpaqx_sa_w_ph.tst +TESTCASES += dpaqx_s_w_ph.tst +TESTCASES += dpa_w_ph.tst +#TESTCASES += dpa_w_qh.tst +TESTCASES += dpax_w_ph.tst +TESTCASES += dpsqx_sa_w_ph.tst +TESTCASES += dpsqx_s_w_ph.tst +TESTCASES += dps_w_ph.tst +#TESTCASES += dps_w_qh.tst +TESTCASES += dpsx_w_ph.tst +TESTCASES += mul_ph.tst +TESTCASES += mulq_rs_w.tst +TESTCASES += mulq_s_ph.tst +TESTCASES += mulq_s_w.tst +TESTCASES += mulsaq_s_w_ph.tst +TESTCASES += mulsa_w_ph.tst +TESTCASES += mul_s_ph.tst +TESTCASES += precr_qb_ph.tst +TESTCASES += precr_sra_ph_w.tst +TESTCASES += precr_sra_r_ph_w.tst +TESTCASES += prepend.tst +TESTCASES += shra_qb.tst +TESTCASES += shra_r_qb.tst +#TESTCASES += shrav_ob.tst +TESTCASES += shrav_qb.tst +#TESTCASES += shrav_r_ob.tst +TESTCASES += shrav_r_qb.tst +TESTCASES += shrl_ph.tst +TESTCASES += shrlv_ph.tst +TESTCASES += subqh_ph.tst +TESTCASES += subqh_r_ph.tst +TESTCASES += subqh_r_w.tst +TESTCASES += subqh_w.tst +#TESTCASES += subuh_ob.tst +TESTCASES += subuh_qb.tst +#TESTCASES += subuh_r_ob.tst +TESTCASES += subuh_r_qb.tst +TESTCASES += subu_ph.tst +#TESTCASES += subu_qh.tst +TESTCASES += subu_s_ph.tst +#TESTCASES += subu_s_qh.tst + +all: build + +head.o : head.S + $(Q)$(CC) $(HEAD_FLAGS) -D"STACK_TOP=0xffffffff80200000" -c $< -o $@ + +%.o : %.S + $(CC) $(CFLAGS) -c $< -o $@ + +%.o : %.c + $(CC) $(CFLAGS) -c $< -o $@ + +%.tst: %.o $(VECTORS_OBJ) + $(CC) $(VECTORS_OBJ) $(FLAGS) $(LDFLAGS) $< -o $@ + +build: $(VECTORS_OBJ) $(MIPSSOC_LIB) $(TESTCASES) + +check: $(VECTORS_OBJ) $(MIPSSOC_LIB) $(TESTCASES) + @for case in $(TESTCASES); do \ + echo $(SIM) $(SIMFLAGS) ./$$case; \ + $(SIM) $(SIMFLAGS) ./$$case & (sleep 1; killall $(SIM)); \ + done + +clean: + $(Q)rm -f *.o *.tst *.a diff --git a/tests/tcg/mips/mips64-dspr2/absq_s_qb.c b/tests/tcg/mips/mips64-dspr2/absq_s_qb.c new file mode 100644 index 0000000000..f7aec3e568 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/absq_s_qb.c @@ -0,0 +1,42 @@ +#include "io.h" +int main() +{ + long long input, result, dsp; + long long hope; + + input = 0x701BA35E; + hope = 0x701B5D5E; + + __asm + ("absq_s.qb %0, %1\n\t" + : "=r"(result) + : "r"(input) + ); + if (result != hope) { + printf("absq_s.qb error\n"); + return -1; + } + + input = 0x801BA35E; + hope = 0x7F1B5D5E; + + __asm + ("absq_s.qb %0, %2\n\t" + "rddsp %1\n\t" + : "=r"(result), "=r"(dsp) + : "r"(input) + ); + dsp = dsp >> 20; + dsp &= 0x01; + if (result != hope) { + printf("absq_s.qb error\n"); + return -1; + } + + if (dsp != 1) { + printf("absq_s.qb error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/addqh_ph.c b/tests/tcg/mips/mips64-dspr2/addqh_ph.c new file mode 100644 index 0000000000..6b43cb8d06 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/addqh_ph.c @@ -0,0 +1,35 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x706A13FE; + rt = 0x13065174; + result = 0x41B832B9; + __asm + ("addqh.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (result != rd) { + printf("addqh.ph error!\n"); + return -1; + } + + rs = 0x81000100; + rt = 0xc2000100; + result = 0xffffffffa1800100; + __asm + ("addqh.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (result != rd) { + printf("addqh.ph error!\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/addqh_r_ph.c b/tests/tcg/mips/mips64-dspr2/addqh_r_ph.c new file mode 100644 index 0000000000..890ec98d9b --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/addqh_r_ph.c @@ -0,0 +1,35 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x706A13FE; + rt = 0x13065174; + result = 0x41B832B9; + __asm + ("addqh_r.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("addqh_r.ph error\n"); + return -1; + } + + rs = 0x81010100; + rt = 0xc2000100; + result = 0xffffffffa1810100; + __asm + ("addqh_r.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("addqh_r.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/addqh_r_w.c b/tests/tcg/mips/mips64-dspr2/addqh_r_w.c new file mode 100644 index 0000000000..d324decbd3 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/addqh_r_w.c @@ -0,0 +1,38 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x00000010; + rt = 0x00000001; + result = 0x00000009; + + __asm + ("addqh_r.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("addqh_r.w error!\n"); + return -1; + } + rs = 0xFFFFFFFE; + rt = 0x00000001; + result = 0x00000000; + + __asm + ("addqh_r.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("addqh_r.w error!\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/addqh_w.c b/tests/tcg/mips/mips64-dspr2/addqh_w.c new file mode 100644 index 0000000000..78559e6784 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/addqh_w.c @@ -0,0 +1,39 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x00000010; + rt = 0x00000001; + result = 0x00000008; + + __asm + ("addqh.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("addqh.w wrong\n"); + return -1; + } + + rs = 0xFFFFFFFE; + rt = 0x00000001; + result = 0xFFFFFFFFFFFFFFFF; + + __asm + ("addqh.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("addqh.w wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/addu_ph.c b/tests/tcg/mips/mips64-dspr2/addu_ph.c new file mode 100644 index 0000000000..d64c8cde8a --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/addu_ph.c @@ -0,0 +1,37 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x00FF00FF; + rt = 0x00010001; + result = 0x01000100; + __asm + ("addu.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("1 addu.ph error\n"); + return -1; + } + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0x00011112; + __asm + ("addu.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) { + printf("2 addu.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/addu_qh.c b/tests/tcg/mips/mips64-dspr2/addu_qh.c new file mode 100644 index 0000000000..edcbf342ce --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/addu_qh.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dspreg; + long long result, dspresult; + + rs = 0x123456787FFF0000; + rt = 0x1111111180000000; + result = 0x23456789FFFF0000; + dspresult = 0x0; + + __asm("addu.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("addu.qh error\n"); + return -1; + } + + rs = 0x123456787FFF0000; + rt = 0x1111111180020000; + result = 0x23456789FFFF0000; + dspresult = 0x01; + + __asm("addu.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("addu.qh overflow error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/addu_s_ph.c b/tests/tcg/mips/mips64-dspr2/addu_s_ph.c new file mode 100644 index 0000000000..9250edb45c --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/addu_s_ph.c @@ -0,0 +1,37 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x00FE00FE; + rt = 0x00020001; + result = 0x010000FF; + __asm + ("addu_s.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("addu_s.ph error\n"); + return -1; + } + + rs = 0xFFFF1111; + rt = 0x00020001; + result = 0xFFFFFFFFFFFF1112; + __asm + ("addu_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((rd != result) || (((dsp >> 20) & 0x01) != 1)) { + printf("addu_s.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/addu_s_qh.c b/tests/tcg/mips/mips64-dspr2/addu_s_qh.c new file mode 100644 index 0000000000..b0c1626251 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/addu_s_qh.c @@ -0,0 +1,43 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dspreg; + long long result, dspresult; + + rs = 0x123456787FFF0000; + rt = 0x1111111180000000; + result = 0x23456789FFFF0000; + dspresult = 0x0; + + __asm("addu_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("1 addu_s.qh error\n"); + return -1; + } + + rs = 0x12345678FFFF0000; + rt = 0x11111111000F0000; + result = 0x23456789FFFF0000; + dspresult = 0x01; + + __asm("addu_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("2 addu_s.qh error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/adduh_ob.c b/tests/tcg/mips/mips64-dspr2/adduh_ob.c new file mode 100644 index 0000000000..9b309f6f16 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/adduh_ob.c @@ -0,0 +1,35 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result; + rs = 0xFF987CDEBCEF2356; + rt = 0xFF987CDEBCEF2354; + result = 0xFF987CDEBCEF2355; + + __asm("adduh.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("adduh.ob error\n\t"); + return -1; + } + + rs = 0xac50691729945316; + rt = 0xb9234ca3f5573162; + result = 0xb2395a5d8f75423c; + + __asm("adduh.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("adduh.ob error\n\t"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/adduh_qb.c b/tests/tcg/mips/mips64-dspr2/adduh_qb.c new file mode 100644 index 0000000000..796b409a86 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/adduh_qb.c @@ -0,0 +1,35 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0xFF0055AA; + rt = 0x0113421B; + result = 0xffffffff80094B62; + __asm + ("adduh.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("adduh.qb error\n"); + return -1; + } + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x7F800888; + + __asm + ("adduh.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("adduh.qb error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/adduh_r_ob.c b/tests/tcg/mips/mips64-dspr2/adduh_r_ob.c new file mode 100644 index 0000000000..832de833ef --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/adduh_r_ob.c @@ -0,0 +1,35 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result; + rs = 0xFF987CDEBCEF2356; + rt = 0xFF987CDEBCEF2355; + result = 0xFF987CDEBCEF2356; + + __asm("adduh_r.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("1 adduh_r.ob error\n\t"); + return -1; + } + + rs = 0xac50691729945316; + rt = 0xb9234ca3f5573162; + result = 0xb33a5b5d8f76423c; + + __asm("adduh_r.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("2 adduh_r.ob error\n\t"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/adduh_r_qb.c b/tests/tcg/mips/mips64-dspr2/adduh_r_qb.c new file mode 100644 index 0000000000..ae65fa5e18 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/adduh_r_qb.c @@ -0,0 +1,35 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0xFF0055AA; + rt = 0x01112211; + result = 0xffffffff80093C5E; + __asm + ("adduh_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("adduh_r.qb error\n"); + return -1; + } + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0xffffffff80800888; + __asm + ("adduh_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("adduh_r.qb error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/append.c b/tests/tcg/mips/mips64-dspr2/append.c new file mode 100644 index 0000000000..68a7cecc4b --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/append.c @@ -0,0 +1,35 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt; + long long result; + + rs = 0xFF0055AA; + rt = 0x0113421B; + result = 0x02268436; + __asm + ("append %0, %1, 0x01\n\t" + : "+r"(rt) + : "r"(rs) + ); + if (rt != result) { + printf("append error\n"); + return -1; + } + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x0010111F; + __asm + ("append %0, %1, 0x04\n\t" + : "+r"(rt) + : "r"(rs) + ); + if (rt != result) { + printf("append error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/balign.c b/tests/tcg/mips/mips64-dspr2/balign.c new file mode 100644 index 0000000000..7fbe815782 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/balign.c @@ -0,0 +1,35 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt; + long long result; + + rs = 0xFF0055AA; + rt = 0x0113421B; + result = 0x13421BFF; + __asm + ("balign %0, %1, 0x01\n\t" + : "+r"(rt) + : "r"(rs) + ); + if (rt != result) { + printf("balign error\n"); + return -1; + } + + rs = 0xFFFF0FFF; + rt = 0x00010111; + result = 0x11FFFF0F; + __asm + ("balign %0, %1, 0x03\n\t" + : "+r"(rt) + : "r"(rs) + ); + if (rt != result) { + printf("balign error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/cmpgdu_eq_ob.c b/tests/tcg/mips/mips64-dspr2/cmpgdu_eq_ob.c new file mode 100644 index 0000000000..61217f38cf --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/cmpgdu_eq_ob.c @@ -0,0 +1,44 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + result = 0xFE; + dspresult = 0xFE; + + __asm("cmpgdu.eq.ob %0, %2, %3\n\t" + "rddsp %1" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0xFF); + + if ((rd != result) || (dspreg != dspresult)) { + printf("1 cmpgdu.eq.ob error\n"); + return -1; + } + + rs = 0x133256789ABCDEF0; + rt = 0x123456789ABCDEFF; + result = 0x3E; + dspresult = 0x3E; + + __asm("cmpgdu.eq.ob %0, %2, %3\n\t" + "rddsp %1" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0xFF); + + if ((rd != result) || (dspreg != dspresult)) { + printf("2 cmpgdu.eq.ob error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/cmpgdu_eq_qb.c b/tests/tcg/mips/mips64-dspr2/cmpgdu_eq_qb.c new file mode 100644 index 0000000000..c63f6480eb --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/cmpgdu_eq_qb.c @@ -0,0 +1,41 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x02; + __asm + ("cmpgdu.eq.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if ((rd != result) || (dsp != result)) { + printf("cmpgdu.eq.qb error\n"); + return -1; + } + + rs = 0x11777066; + rt = 0x11777066; + result = 0x0F; + __asm + ("cmpgdu.eq.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + + if ((rd != result) || (dsp != result)) { + printf("cmpgdu.eq.qb error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/cmpgdu_le_ob.c b/tests/tcg/mips/mips64-dspr2/cmpgdu_le_ob.c new file mode 100644 index 0000000000..b3da098189 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/cmpgdu_le_ob.c @@ -0,0 +1,44 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + + rs = 0x123456789abcdef0; + rt = 0x123456789abcdeff; + dspresult = 0xff; + result = 0xff; + + __asm("cmpgdu.le.ob %0, %2, %3\n\t" + "rddsp %1" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0xff); + + if ((rd != result) || (dspreg != dspresult)) { + printf("cmpgdu.le.ob error\n"); + return -1; + } + + rs = 0x113556789ABCDEF0; + rt = 0x123456789ABCDEFF; + result = 0xBE; + dspresult = 0xFE; + + __asm("cmpgdu.eq.ob %0, %2, %3\n\t" + "rddsp %1" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0xFF); + + if ((rd != result) || (dspreg != dspresult)) { + printf("cmpgdu.eq.ob error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/cmpgdu_le_qb.c b/tests/tcg/mips/mips64-dspr2/cmpgdu_le_qb.c new file mode 100644 index 0000000000..f0a60ea4e0 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/cmpgdu_le_qb.c @@ -0,0 +1,48 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0F; + __asm + ("cmpgdu.le.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if (rd != result) { + printf("cmpgdu.le.qb error\n"); + return -1; + } + if (dsp != result) { + printf("cmpgdu.le.qb error\n"); + return -1; + } + + rs = 0x11777066; + rt = 0x11707066; + result = 0x0B; + __asm + ("cmpgdu.le.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if (rd != result) { + printf("cmpgdu.le.qb error\n"); + return -1; + } + if (dsp != result) { + printf("cmpgdu.le.qb error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/cmpgdu_lt_ob.c b/tests/tcg/mips/mips64-dspr2/cmpgdu_lt_ob.c new file mode 100644 index 0000000000..d80b4e6ab9 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/cmpgdu_lt_ob.c @@ -0,0 +1,44 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result, dspreg, dspresult; + + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x01; + result = 0x01; + + __asm("cmpgdu.lt.ob %0, %2, %3\n\t" + "rddsp %1" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0xFF); + + if ((rd != result) || (dspreg != dspresult)) { + printf("cmpgdu.lt.ob error\n"); + return -1; + } + + rs = 0x143356789ABCDEF0; + rt = 0x123456789ABCDEFF; + dspresult = 0x41; + result = 0x41; + + __asm("cmpgdu.lt.ob %0, %2, %3\n\t" + "rddsp %1" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 24) & 0xFF); + + if ((rd != result) || (dspreg != dspresult)) { + printf("cmpgdu.lt.ob error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/cmpgdu_lt_qb.c b/tests/tcg/mips/mips64-dspr2/cmpgdu_lt_qb.c new file mode 100644 index 0000000000..a71e4e307f --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/cmpgdu_lt_qb.c @@ -0,0 +1,48 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long dsp; + long long result; + + rs = 0x11777066; + rt = 0x55AA70FF; + result = 0x0D; + __asm + ("cmpgdu.lt.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if (rd != result) { + printf("cmpgdu.lt.qb error\n"); + return -1; + } + if (dsp != result) { + printf("cmpgdu.lt.qb error\n"); + return -1; + } + + rs = 0x11777066; + rt = 0x11777066; + result = 0x00; + __asm + ("cmpgdu.lt.qb %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 24) & 0x0F; + if (rd != result) { + printf("cmpgdu.lt.qb error\n"); + return -1; + } + if (dsp != result) { + printf("cmpgdu.lt.qb error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dbalign.c b/tests/tcg/mips/mips64-dspr2/dbalign.c new file mode 100644 index 0000000000..c7431b1857 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dbalign.c @@ -0,0 +1,39 @@ +#include "io.h" + +int main(void) +{ + long long rt, rs; + long long res; + + rt = 0x1234567887654321; + rs = 0xabcd1234abcd1234; + + res = 0x34567887654321ab; + + asm ("dbalign %0, %1, 0x1\n" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("dbalign error\n"); + return -1; + } + + rt = 0x1234567887654321; + rs = 0xabcd1234abcd1234; + + res = 0x7887654321abcd12; + + asm ("dbalign %0, %1, 0x3\n" + : "=r"(rt) + : "r"(rs) + ); + + if (rt != res) { + printf("dbalign error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dpa_w_ph.c b/tests/tcg/mips/mips64-dspr2/dpa_w_ph.c new file mode 100644 index 0000000000..39dc99aa55 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dpa_w_ph.c @@ -0,0 +1,47 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt; + long long ach = 5, acl = 5; + long long resulth, resultl; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x05; + resultl = 0x0302; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpa.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("1 dpa.w.ph error\n"); + return -1; + } + + ach = 6, acl = 7; + rs = 0xFFFF00FF; + rt = 0xFFFF0002; + resulth = 0x05; + resultl = 0xfffffffffffe0206; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpa.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if ((ach != resulth) || (acl != resultl)) { + printf("2 dpa.w.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dpa_w_qh.c b/tests/tcg/mips/mips64-dspr2/dpa_w_qh.c new file mode 100644 index 0000000000..1411e44be3 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dpa_w_qh.c @@ -0,0 +1,56 @@ +#include"io.h" +int main(void) +{ + long long rt, rs; + long long achi, acli; + long long acho, aclo; + long long resh, resl; + + achi = 0x1; + acli = 0x1; + + rs = 0x0001000100010001; + rt = 0x0002000200020002; + + resh = 0x1; + resl = 0x9; + + asm("mthi %2, $ac1\t\n" + "mtlo %3, $ac1\t\n" + "dpa.w.qh $ac1, %4, %5\t\n" + "mfhi %0, $ac1\t\n" + "mflo %1, $ac1\t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("1 dpa.w.qh error\n"); + return -1; + } + + + achi = 0xffffffff; + acli = 0xaaaaaaaa; + + rs = 0xaaaabbbbccccdddd; + rt = 0x7777888899996666; + + resh = 0xffffffffffffffff; + resl = 0x320cdf02; + + asm("mthi %2, $ac1\t\n" + "mtlo %3, $ac1\t\n" + "dpa.w.qh $ac1, %4, %5\t\n" + "mfhi %0, $ac1\t\n" + "mflo %1, $ac1\t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + if ((acho != resh) || (aclo != resl)) { + printf("2 dpa.w.qh error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dpaqx_s_w_ph.c b/tests/tcg/mips/mips64-dspr2/dpaqx_s_w_ph.c new file mode 100644 index 0000000000..51252fb980 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dpaqx_s_w_ph.c @@ -0,0 +1,97 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt, dsp; + long long ach = 5, acl = 5; + long long resulth, resultl, resultdsp; + + rs = 0x800000FF; + rt = 0x00018000; + resulth = 0x05; + resultl = 0xFFFFFFFF80000202; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if (dsp != resultdsp) { + printf("dpaqx_s.w.ph error\n"); + return -1; + } + if (ach != resulth) { + printf("dpaqx_s.w.ph error\n"); + return -1; + } + if (acl != resultl) { + printf("dpaqx_s.w.ph error\n"); + return -1; + } + + ach = 5; + acl = 5; + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x05; + resultl = 0x05FF; + /*********************************************************** + * Because of we set outflag at last time, although this + * time we set nothing, but it is stay the last time value. + **********************************************************/ + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if (dsp != resultdsp) { + printf("dpaqx_s.w.ph error\n"); + return -1; + } + if (ach != resulth) { + printf("dpaqx_s.w.ph error\n"); + return -1; + } + if (acl != resultl) { + printf("dpaqx_s.w.ph error\n"); + return -1; + } + + ach = 5; + acl = 5; + rs = 0x800000FF; + rt = 0x00028000; + resulth = 0x05; + resultl = 0xffffffff80000400; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if ((dsp != resultdsp) || (ach != resulth) || (acl != resultl)) { + printf("dpaqx_s.w.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dpaqx_sa_w_ph.c b/tests/tcg/mips/mips64-dspr2/dpaqx_sa_w_ph.c new file mode 100644 index 0000000000..18d6b3a98e --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dpaqx_sa_w_ph.c @@ -0,0 +1,54 @@ +#include "io.h" + +int main() +{ + long long rs, rt, dsp; + long long ach = 5, acl = 5; + long long resulth, resultl, resultdsp; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x00; + resultl = 0x7FFFFFFF; + resultdsp = 0x01; + __asm + ("wrdsp %2\n\t" + "mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_sa.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "+r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((dsp >> (16 + 1) != resultdsp) || (ach != resulth) || + (acl != resultl)) { + printf("dpaqx_sa.w.ph errror\n"); + } + + ach = 9; + acl = 0xb; + rs = 0x800000FF; + rt = 0x00018000; + resulth = 0x00; + resultl = 0x7fffffff; + resultdsp = 0x01; + __asm + ("wrdsp %2\n\t" + "mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpaqx_sa.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "+r"(dsp) + : "r"(rs), "r"(rt) + ); + if ((dsp >> (16 + 1) != resultdsp) || (ach != resulth) || + (acl != resultl)) { + printf("dpaqx_sa.w.ph errror\n"); + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dpax_w_ph.c b/tests/tcg/mips/mips64-dspr2/dpax_w_ph.c new file mode 100644 index 0000000000..9d595fc14a --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dpax_w_ph.c @@ -0,0 +1,32 @@ +#include"io.h" + +int main(void) +{ + long rs, rt; + long ach = 5, acl = 5; + long resulth, resultl; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x05; + resultl = 0x0302; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpax.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if (ach != resulth) { + printf("dpax.w.ph error\n"); + return -1; + } + if (acl != resultl) { + printf("dpax.w.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dps_w_ph.c b/tests/tcg/mips/mips64-dspr2/dps_w_ph.c new file mode 100644 index 0000000000..99f292ecb2 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dps_w_ph.c @@ -0,0 +1,28 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt; + long long ach = 5, acl = 5; + long long resulth, resultl; + + rs = 0x00FF00FF; + rt = 0x00010002; + resulth = 0x04; + resultl = 0xFFFFFFFFFFFFFFD08; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dps.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if (ach != resulth || acl != resultl) { + printf("dps.w.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dps_w_qh.c b/tests/tcg/mips/mips64-dspr2/dps_w_qh.c new file mode 100644 index 0000000000..61277eb30c --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dps_w_qh.c @@ -0,0 +1,55 @@ +#include "io.h" + +int main(void) +{ + long long rs, rt; + long long achi, acli; + long long acho, aclo; + long long resh, resl; + + rs = 0x0000000100000001; + rt = 0x0000000200000002; + achi = 0x1; + acli = 0x8; + + resh = 0x1; + resl = 0x4; + + asm ("mthi %2, $ac1\t\n" + "mtlo %3, $ac1\t\n" + "dps.w.qh $ac1, %4, %5\t\n" + "mfhi %0, $ac1\t\n" + "mflo %1, $ac1\t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("1 dps.w.qh error\n"); + return -1; + } + + rs = 0xaaaabbbbccccdddd; + rt = 0xaaaabbbbccccdddd; + + achi = 0x88888888; + achi = 0x55555555; + + resh = 0xfffffffff7777777; + resl = 0x0a38b181; + + asm ("mthi %2, $ac1\t\n" + "mtlo %3, $ac1\t\n" + "dps.w.qh $ac1, %4, %5\t\n" + "mfhi %0, $ac1\t\n" + "mflo %1, $ac1\t\n" + : "=r"(acho), "=r"(aclo) + : "r"(achi), "r"(acli), "r"(rs), "r"(rt) + ); + + if ((acho != resh) || (aclo != resl)) { + printf("1 dps.w.qh error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dpsqx_s_w_ph.c b/tests/tcg/mips/mips64-dspr2/dpsqx_s_w_ph.c new file mode 100644 index 0000000000..ba46a92698 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dpsqx_s_w_ph.c @@ -0,0 +1,55 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt, dsp; + long long ach = 5, acl = 5; + long long resulth, resultl, resultdsp; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xFFFFFFFFAEA3E09B; + resultdsp = 0x00; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if (dsp != resultdsp || ach != resulth || acl != resultl) { + printf("dpsqx_s.w.ph error\n"); + return -1; + } + + ach = 0x99f13005; + acl = 0x51730062; + rs = 0x80008000; + rt = 0x80008000; + + resulth = 0xffffffff99f13004; + resultl = 0x51730064; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsqx_s.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if (dsp != resultdsp || ach != resulth || acl != resultl) { + printf("dpsqx_s.w.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dpsqx_sa_w_ph.c b/tests/tcg/mips/mips64-dspr2/dpsqx_sa_w_ph.c new file mode 100644 index 0000000000..24c888134d --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dpsqx_sa_w_ph.c @@ -0,0 +1,53 @@ +#include"io.h" +int main() +{ + long long rs, rt, dsp; + long long ach = 5, acl = 5; + long long resulth, resultl, resultdsp; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x00; + resultl = 0x7FFFFFFF; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsqx_sa.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if (dsp != resultdsp || ach != resulth || acl != resultl) { + printf("dpsqx_sa.w.ph error\n"); + return -1; + } + + ach = 0x8c0b354A; + acl = 0xbbc02249; + rs = 0x800023AD; + rt = 0x01648000; + resulth = 0xffffffffffffffff; + resultl = 0xffffffff80000000; + resultdsp = 0x01; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsqx_sa.w.ph $ac1, %3, %4\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + "rddsp %2\n\t" + : "+r"(ach), "+r"(acl), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 17) & 0x01; + if (dsp != resultdsp || ach != resulth || acl != resultl) { + printf("dpsqx_sa.w.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/dpsx_w_ph.c b/tests/tcg/mips/mips64-dspr2/dpsx_w_ph.c new file mode 100644 index 0000000000..b6291b5eb6 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/dpsx_w_ph.c @@ -0,0 +1,28 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt; + long long ach = 5, acl = 5; + long long resulth, resultl; + + rs = 0xBC0123AD; + rt = 0x01643721; + resulth = 0x04; + resultl = 0xFFFFFFFFD751F050; + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "dpsx.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if (ach != resulth || acl != resultl) { + printf("dpsx.w.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/head.S b/tests/tcg/mips/mips64-dspr2/head.S new file mode 100644 index 0000000000..9a099ae42f --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/head.S @@ -0,0 +1,16 @@ +/* + * Startup Code for MIPS64 CPU-core + * + */ +.text +.globl _start +.align 4 +_start: + ori $2, $2, 0xffff + sll $2, $2, 16 + ori $2, $2, 0xffff + mtc0 $2, $12, 0 + jal main + +end: + b end diff --git a/tests/tcg/mips/mips64-dspr2/io.h b/tests/tcg/mips/mips64-dspr2/io.h new file mode 100644 index 0000000000..b7db61d7c1 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/io.h @@ -0,0 +1,22 @@ +#ifndef _ASM_IO_H +#define _ASM_IO_H +extern int printf(const char *fmt, ...); +extern unsigned long get_ticks(void); + +#define _read(source) \ +({ unsigned long __res; \ + __asm__ __volatile__( \ + "mfc0\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#define __read(source) \ +({ unsigned long __res; \ + __asm__ __volatile__( \ + "move\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +#endif diff --git a/tests/tcg/mips/mips64-dspr2/mips_boot.lds b/tests/tcg/mips/mips64-dspr2/mips_boot.lds new file mode 100644 index 0000000000..bd7c0c0f3f --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/mips_boot.lds @@ -0,0 +1,31 @@ +OUTPUT_ARCH(mips) +SECTIONS +{ + . = 0xffffffff80100000; + . = ALIGN((1 << 13)); + .text : + { + *(.text) + *(.rodata) + *(.rodata.*) + } + + __init_begin = .; + . = ALIGN((1 << 12)); + .init.text : AT(ADDR(.init.text) - 0) + { + *(.init.text) + } + .init.data : AT(ADDR(.init.data) - 0) + { + *(.init.data) + } + . = ALIGN((1 << 12)); + __init_end = .; + + . = ALIGN((1 << 13)); + .data : + { + *(.data) + } +} diff --git a/tests/tcg/mips/mips64-dspr2/mul_ph.c b/tests/tcg/mips/mips64-dspr2/mul_ph.c new file mode 100644 index 0000000000..5a3d05cb29 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/mul_ph.c @@ -0,0 +1,50 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x03FB1234; + rt = 0x0BCC4321; + result = 0xFFFFFFFFF504F4B4; + resultdsp = 1; + + __asm + ("mul.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if (rd != result || dsp != resultdsp) { + printf("mul.ph wrong\n"); + return -1; + } + + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 0x00210010; + rt = 0x00110005; + result = 0x2310050; + resultdsp = 0; + + __asm + ("mul.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if (rd != result || dsp != resultdsp) { + printf("mul.ph wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/mul_s_ph.c b/tests/tcg/mips/mips64-dspr2/mul_s_ph.c new file mode 100644 index 0000000000..7c8b2c718f --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/mul_s_ph.c @@ -0,0 +1,67 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x03FB1234; + rt = 0x0BCC4321; + result = 0x7fff7FFF; + resultdsp = 1; + + __asm + ("mul_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if (rd != result || dsp != resultdsp) { + printf("1 mul_s.ph error\n"); + return -1; + } + + rs = 0x7fffff00; + rt = 0xff007fff; + result = 0xffffffff80008000; + resultdsp = 1; + + __asm + ("mul_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if (rd != result || dsp != resultdsp) { + printf("2 mul_s.ph error\n"); + return -1; + } + + dsp = 0; + __asm + ("wrdsp %0\n\t" + : + : "r"(dsp) + ); + + rs = 0x00320001; + rt = 0x00210002; + result = 0x06720002; + resultdsp = 0; + + __asm + ("mul_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if (rd != result || dsp != resultdsp) { + printf("3 mul_s.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/mulq_rs_w.c b/tests/tcg/mips/mips64-dspr2/mulq_rs_w.c new file mode 100644 index 0000000000..ffdc66d54a --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/mulq_rs_w.c @@ -0,0 +1,40 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0xFFFFFFFF80005555; + + __asm + ("mulq_rs.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("mulq_rs.w error!\n"); + return -1; + } + + rs = 0x80000000; + rt = 0x80000000; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm + ("mulq_rs.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if (rd != result || dsp != resultdsp) { + printf("mulq_rs.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/mulq_s_ph.c b/tests/tcg/mips/mips64-dspr2/mulq_s_ph.c new file mode 100644 index 0000000000..b8c20c68cc --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/mulq_s_ph.c @@ -0,0 +1,26 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0x7FFF098B; + resultdsp = 1; + + __asm + ("mulq_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if (rd != result || dsp != resultdsp) { + printf("mulq_s.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/mulq_s_w.c b/tests/tcg/mips/mips64-dspr2/mulq_s_w.c new file mode 100644 index 0000000000..db74b713f2 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/mulq_s_w.c @@ -0,0 +1,40 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x80001234; + rt = 0x80004321; + result = 0xFFFFFFFF80005555; + + __asm + ("mulq_s.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("mulq_s.w error\n"); + return -1; + } + + rs = 0x80000000; + rt = 0x80000000; + result = 0x7FFFFFFF; + resultdsp = 1; + + __asm + ("mulq_s.w %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 21) & 0x01; + if (rd != result || dsp != resultdsp) { + printf("mulq_s.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/mulsa_w_ph.c b/tests/tcg/mips/mips64-dspr2/mulsa_w_ph.c new file mode 100644 index 0000000000..5b22a60a8d --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/mulsa_w_ph.c @@ -0,0 +1,30 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt, ach, acl; + long long resulth, resultl; + + ach = 0x05; + acl = 0x00BBDDCC; + rs = 0x80001234; + rt = 0x80004321; + resulth = 0x05; + resultl = 0x3BF5E918; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "mulsa.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if (ach != resulth || acl != resultl) { + printf("mulsa.w.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/mulsaq_s_w_ph.c b/tests/tcg/mips/mips64-dspr2/mulsaq_s_w_ph.c new file mode 100644 index 0000000000..835a73d479 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/mulsaq_s_w_ph.c @@ -0,0 +1,30 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt, ach, acl; + long long resulth, resultl; + + ach = 0x05; + acl = 0x00BBDDCC; + rs = 0x80001234; + rt = 0x80004321; + resulth = 0x05; + resultl = 0x772ff463; + + __asm + ("mthi %0, $ac1\n\t" + "mtlo %1, $ac1\n\t" + "mulsaq_s.w.ph $ac1, %2, %3\n\t" + "mfhi %0, $ac1\n\t" + "mflo %1, $ac1\n\t" + : "+r"(ach), "+r"(acl) + : "r"(rs), "r"(rt) + ); + if (ach != resulth || acl != resultl) { + printf("mulsaq_s.w.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/precr_qb_ph.c b/tests/tcg/mips/mips64-dspr2/precr_qb_ph.c new file mode 100644 index 0000000000..80d5e8dce9 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/precr_qb_ph.c @@ -0,0 +1,23 @@ +#include"io.h" + +int main() +{ + long long rd, rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x34786521; + + __asm + ("precr.qb.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (result != rd) { + printf("precr.qb.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/precr_sra_ph_w.c b/tests/tcg/mips/mips64-dspr2/precr_sra_ph_w.c new file mode 100644 index 0000000000..b1d7bcdf8e --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/precr_sra_ph_w.c @@ -0,0 +1,37 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x43215678; + + __asm + ("precr_sra.ph.w %0, %1, 0x00\n\t" + : "+r"(rt) + : "r"(rs) + ); + if (result != rt) { + printf("precr_sra.ph.w error\n"); + return -1; + } + + rs = 0x12345678; + rt = 0x87654321; + result = 0xFFFFFFFFFFFF0000; + + __asm + ("precr_sra.ph.w %0, %1, 0x1F\n\t" + : "+r"(rt) + : "r"(rs) + ); + if (result != rt) { + printf("precr_sra.ph.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/precr_sra_r_ph_w.c b/tests/tcg/mips/mips64-dspr2/precr_sra_r_ph_w.c new file mode 100644 index 0000000000..62d220dcae --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/precr_sra_r_ph_w.c @@ -0,0 +1,37 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x43215678; + + __asm + ("precr_sra_r.ph.w %0, %1, 0x00\n\t" + : "+r"(rt) + : "r"(rs) + ); + if (result != rt) { + printf("precr_sra_r.ph.w error\n"); + return -1; + } + + rs = 0x12345678; + rt = 0x87654321; + result = 0xFFFFFFFFFFFF0000; + + __asm + ("precr_sra_r.ph.w %0, %1, 0x1F\n\t" + : "+r"(rt) + : "r"(rs) + ); + if (result != rt) { + printf("precr_sra_r.ph.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/prepend.c b/tests/tcg/mips/mips64-dspr2/prepend.c new file mode 100644 index 0000000000..4ab083e969 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/prepend.c @@ -0,0 +1,35 @@ +#include"io.h" + +int main(void) +{ + long long rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0xFFFFFFFF87654321; + __asm + ("prepend %0, %1, 0x00\n\t" + : "+r"(rt) + : "r"(rs) + ); + if (rt != result) { + printf("prepend error\n"); + return -1; + } + + rs = 0x12345678; + rt = 0x87654321; + result = 0xFFFFFFFFACF10ECA; + __asm + ("prepend %0, %1, 0x0F\n\t" + : "+r"(rt) + : "r"(rs) + ); + if (rt != result) { + printf("prepend error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/printf.c b/tests/tcg/mips/mips64-dspr2/printf.c new file mode 100644 index 0000000000..cf8676d390 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/printf.c @@ -0,0 +1,266 @@ + +typedef unsigned long va_list; + +#define ACC 4 +#define __read(source) \ +({ va_list __res; \ + __asm__ __volatile__( \ + "move\t%0, " #source "\n\t" \ + : "=r" (__res)); \ + __res; \ +}) + +enum format_type { + FORMAT_TYPE_NONE, + FORMAT_TYPE_HEX, + FORMAT_TYPE_ULONG, + FORMAT_TYPE_FLOAT +}; + +struct printf_spec { + char type; +}; + +static int format_decode(char *fmt, struct printf_spec *spec) +{ + char *start = fmt; + + for (; *fmt ; ++fmt) { + if (*fmt == '%') { + break; + } + } + + switch (*++fmt) { + case 'x': + spec->type = FORMAT_TYPE_HEX; + break; + + case 'd': + spec->type = FORMAT_TYPE_ULONG; + break; + + case 'f': + spec->type = FORMAT_TYPE_FLOAT; + break; + + default: + spec->type = FORMAT_TYPE_NONE; + } + + return ++fmt - start; +} + +void *memcpy(void *dest, void *src, int n) +{ + int i; + char *s = src; + char *d = dest; + + for (i = 0; i < n; i++) { + d[i] = s[i]; + } + return dest; +} + +char *number(char *buf, va_list num) +{ + int i; + char *str = buf; + static char digits[16] = "0123456789abcdef"; + str = str + sizeof(num) * 2; + + for (i = 0; i < sizeof(num) * 2; i++) { + *--str = digits[num & 15]; + num >>= 4; + } + + return buf + sizeof(num) * 2; +} + +char *__number(char *buf, va_list num) +{ + int i; + va_list mm = num; + char *str = buf; + + if (!num) { + *str++ = '0'; + return str; + } + + for (i = 0; mm; mm = mm/10, i++) { + /* Do nothing. */ + } + + str = str + i; + + while (num) { + *--str = num % 10 + 48; + num = num / 10; + } + + return str + i; +} + +va_list modf(va_list args, va_list *integer, va_list *num) +{ + int i; + double dot_v = 0; + va_list E, DOT, DOT_V; + + if (!args) { + return 0; + } + + for (i = 0, args = args << 1 >> 1; i < 52; i++) { + if ((args >> i) & 0x1) { + break; + } + } + + *integer = 0; + + if ((args >> 56 != 0x3f) || (args >> 52 == 0x3ff)) { + E = (args >> 52) - 1023; + DOT = 52 - E - i; + DOT_V = args << (12 + E) >> (12 + E) >> i; + *integer = ((args << 12 >> 12) >> (i + DOT)) | (1 << E); + } else { + E = ~((args >> 52) - 1023) + 1; + DOT_V = args << 12 >> 12; + + dot_v += 1.0 / (1 << E); + + for (i = 1; i <= 16; i++) { + if ((DOT_V >> (52 - i)) & 0x1) { + dot_v += 1.0 / (1 << E + i); + } + } + + for (i = 1, E = 0; i <= ACC; i++) { + dot_v *= 10; + if (!(va_list)dot_v) { + E++; + } + } + + *num = E; + + return dot_v; + } + + if (args & 0xf) { + for (i = 1; i <= 16; i++) { + if ((DOT_V >> (DOT - i)) & 0x1) { + dot_v += 1.0 / (1 << i); + } + } + + for (i = 1, E = 0; i <= ACC; i++) { + dot_v *= 10; + if (!(va_list)dot_v) { + E++; + } + } + + *num = E; + + return dot_v; + } else if (DOT) { + for (i = 1; i <= DOT; i++) { + if ((DOT_V >> (DOT - i)) & 0x1) { + dot_v += 1.0 / (1 << i); + } + } + + for (i = 1; i <= ACC; i++) { + dot_v = dot_v * 10; + } + + return dot_v; + } + + return 0; +} + +int vsnprintf(char *buf, int size, char *fmt, va_list args) +{ + char *str, *mm; + struct printf_spec spec = {0}; + + str = mm = buf; + + while (*fmt) { + char *old_fmt = fmt; + int read = format_decode(fmt, &spec); + + fmt += read; + + switch (spec.type) { + case FORMAT_TYPE_NONE: { + memcpy(str, old_fmt, read); + str += read; + break; + } + case FORMAT_TYPE_HEX: { + memcpy(str, old_fmt, read); + str = number(str + read, args); + for (; *mm ; ++mm) { + if (*mm == '%') { + *mm = '0'; + break; + } + } + break; + } + case FORMAT_TYPE_ULONG: { + memcpy(str, old_fmt, read - 2); + str = __number(str + read - 2, args); + break; + } + case FORMAT_TYPE_FLOAT: { + va_list integer, dot_v, num; + dot_v = modf(args, &integer, &num); + memcpy(str, old_fmt, read - 2); + str += read - 2; + if ((args >> 63 & 0x1)) { + *str++ = '-'; + } + str = __number(str, integer); + if (dot_v) { + *str++ = '.'; + while (num--) { + *str++ = '0'; + } + str = __number(str, dot_v); + } + break; + } + } + } + *str = '\0'; + + return str - buf; +} + +static void serial_out(char *str) +{ + while (*str) { + *(char *)0xffffffffb80003f8 = *str++; + } +} + +int vprintf(char *fmt, va_list args) +{ + int printed_len = 0; + static char printf_buf[512]; + printed_len = vsnprintf(printf_buf, sizeof(printf_buf), fmt, args); + serial_out(printf_buf); + return printed_len; +} + +int printf(char *fmt, ...) +{ + return vprintf(fmt, __read($5)); +} diff --git a/tests/tcg/mips/mips64-dspr2/shra_qb.c b/tests/tcg/mips/mips64-dspr2/shra_qb.c new file mode 100644 index 0000000000..cac3102355 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/shra_qb.c @@ -0,0 +1,35 @@ +#include"io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x12345678; + result = 0x02060A0F; + + __asm + ("shra.qb %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("shra.qb error\n"); + return -1; + } + + rt = 0x87654321; + result = 0xFFFFFFFFF00C0804; + + __asm + ("shra.qb %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("shra.qb error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/shra_r_qb.c b/tests/tcg/mips/mips64-dspr2/shra_r_qb.c new file mode 100644 index 0000000000..9c64f75bd4 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/shra_r_qb.c @@ -0,0 +1,35 @@ +#include "io.h" + +int main() +{ + int rd, rt; + int result; + + rt = 0x12345678; + result = 0x02070B0F; + + __asm + ("shra_r.qb %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("shra_r.qb wrong\n"); + return -1; + } + + rt = 0x87654321; + result = 0xF10D0804; + + __asm + ("shra_r.qb %0, %1, 0x03\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("shra_r.qb wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/shrav_ob.c b/tests/tcg/mips/mips64-dspr2/shrav_ob.c new file mode 100644 index 0000000000..fbdfbab35a --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/shrav_ob.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs; + long long res; + + rt = 0x1234567887654321; + rs = 0x4; + res = 0xf1f3f5f7f8060402; + + asm ("shrav.ob %0, %1, %2" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shra.ob error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/shrav_qb.c b/tests/tcg/mips/mips64-dspr2/shrav_qb.c new file mode 100644 index 0000000000..a716203d80 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/shrav_qb.c @@ -0,0 +1,37 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x03; + rt = 0x12345678; + result = 0x02060A0F; + + __asm + ("shrav.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + if (rd != result) { + printf("shrav.qb error\n"); + return -1; + } + + rs = 0x03; + rt = 0x87654321; + result = 0xFFFFFFFFF00C0804; + + __asm + ("shrav.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + if (rd != result) { + printf("shrav.qb error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/shrav_r_ob.c b/tests/tcg/mips/mips64-dspr2/shrav_r_ob.c new file mode 100644 index 0000000000..b80100a7c2 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/shrav_r_ob.c @@ -0,0 +1,22 @@ +#include "io.h" + +int main(void) +{ + long long rd, rt, rs; + long long res; + + rt = 0x1234567887654321; + rs = 0x4; + res = 0xe3e7ebf0f1ede9e5; + + asm ("shrav_r.ob %0, %1, %2" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + + if (rd != res) { + printf("shra_r.ob error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/shrav_r_qb.c b/tests/tcg/mips/mips64-dspr2/shrav_r_qb.c new file mode 100644 index 0000000000..009080b2a7 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/shrav_r_qb.c @@ -0,0 +1,37 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x03; + rt = 0x12345678; + result = 0x02070B0F; + + __asm + ("shrav_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + if (rd != result) { + printf("shrav_r.qb error\n"); + return -1; + } + + rs = 0x03; + rt = 0x87654321; + result = 0xFFFFFFFFF10D0804; + + __asm + ("shrav_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + if (rd != result) { + printf("shrav_r.qb error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/shrl_ph.c b/tests/tcg/mips/mips64-dspr2/shrl_ph.c new file mode 100644 index 0000000000..e32d976625 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/shrl_ph.c @@ -0,0 +1,22 @@ +#include"io.h" + +int main(void) +{ + long long rd, rt; + long long result; + + rt = 0x12345678; + result = 0x009102B3; + + __asm + ("shrl.ph %0, %1, 0x05\n\t" + : "=r"(rd) + : "r"(rt) + ); + if (rd != result) { + printf("shrl.ph error!\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/shrlv_ph.c b/tests/tcg/mips/mips64-dspr2/shrlv_ph.c new file mode 100644 index 0000000000..58c5488b58 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/shrlv_ph.c @@ -0,0 +1,23 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x05; + rt = 0x12345678; + result = 0x009102B3; + + __asm + ("shrlv.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rt), "r"(rs) + ); + if (rd != result) { + printf("shrlv.ph error!\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subqh_ph.c b/tests/tcg/mips/mips64-dspr2/subqh_ph.c new file mode 100644 index 0000000000..90374019ae --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subqh_ph.c @@ -0,0 +1,23 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456709AB; + + __asm + ("subqh.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("subqh.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subqh_r_ph.c b/tests/tcg/mips/mips64-dspr2/subqh_r_ph.c new file mode 100644 index 0000000000..b8f9d2fee6 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subqh_r_ph.c @@ -0,0 +1,23 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456809AC; + + __asm + ("subqh_r.ph %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("subqh_r.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subqh_r_w.c b/tests/tcg/mips/mips64-dspr2/subqh_r_w.c new file mode 100644 index 0000000000..b025e40a35 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subqh_r_w.c @@ -0,0 +1,23 @@ +#include"io.h" + +int main() +{ + long long rd, rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456789AC; + + __asm + ("subqh_r.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("subqh_r.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subqh_w.c b/tests/tcg/mips/mips64-dspr2/subqh_w.c new file mode 100644 index 0000000000..65f17603d8 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subqh_w.c @@ -0,0 +1,23 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0x456789AB; + + __asm + ("subqh.w %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("subqh.w error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subu_ph.c b/tests/tcg/mips/mips64-dspr2/subu_ph.c new file mode 100644 index 0000000000..60a6b1b7da --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subu_ph.c @@ -0,0 +1,26 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x87654321; + rt = 0x12345678; + result = 0x7531ECA9; + resultdsp = 0x01; + + __asm + ("subu.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + if (dsp != resultdsp || rd != result) { + printf("subu.ph error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subu_qh.c b/tests/tcg/mips/mips64-dspr2/subu_qh.c new file mode 100644 index 0000000000..911cb349d4 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subu_qh.c @@ -0,0 +1,24 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dspreg, result, dspresult; + rs = 0x123456789ABCDEF0; + rt = 0x123456789ABCDEF1; + result = 0x000000000000000F; + dspresult = 0x01; + + __asm("subu.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("subu.qh error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subu_s_ph.c b/tests/tcg/mips/mips64-dspr2/subu_s_ph.c new file mode 100644 index 0000000000..ae32cc06f5 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subu_s_ph.c @@ -0,0 +1,25 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt, dsp; + long long result, resultdsp; + + rs = 0x87654321; + rt = 0x12345678; + result = 0x75310000; + resultdsp = 0x01; + + __asm + ("subu_s.ph %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dsp) + : "r"(rs), "r"(rt) + ); + dsp = (dsp >> 20) & 0x01; + if (dsp != resultdsp || rd != result) { + printf("subu_s.ph error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subu_s_qh.c b/tests/tcg/mips/mips64-dspr2/subu_s_qh.c new file mode 100644 index 0000000000..de7a29e775 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subu_s_qh.c @@ -0,0 +1,42 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, dspreg, result, dspresult; + rs = 0x1111111111111111; + rt = 0x2222222222222222; + result = 0x1111111111111111; + dspresult = 0x00; + + __asm("subu_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("subu_s.qh error\n\t"); + return -1; + } + + + rs = 0x8888888888888888; + rt = 0xa888a888a888a888; + result = 0x0000000000000000; + dspresult = 0x01; + + __asm("subu_s.qh %0, %2, %3\n\t" + "rddsp %1\n\t" + : "=r"(rd), "=r"(dspreg) + : "r"(rs), "r"(rt) + ); + + dspreg = ((dspreg >> 20) & 0x01); + if ((rd != result) || (dspreg != dspresult)) { + printf("subu_s.qh error\n\t"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subuh_ob.c b/tests/tcg/mips/mips64-dspr2/subuh_ob.c new file mode 100644 index 0000000000..3fc452bf8e --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subuh_ob.c @@ -0,0 +1,36 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result; + + rd = 0x0; + rs = 0x246856789ABCDEF0; + rt = 0x123456789ABCDEF0; + result = 0x091A000000000000; + + __asm("subuh.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("subuh.ob error\n"); + return -1; + } + + rs = 0x246856789ABCDEF0; + rt = 0x1131517191B1D1F1; + result = 0x1b4f2d2d51637577; + + __asm("subuh.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("subuh.ob error\n"); + return -1; + } + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subuh_qb.c b/tests/tcg/mips/mips64-dspr2/subuh_qb.c new file mode 100644 index 0000000000..aac7a834ee --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subuh_qb.c @@ -0,0 +1,23 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0xC5E7092B; + + __asm + ("subuh.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("subuh.qb wrong\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subuh_r_ob.c b/tests/tcg/mips/mips64-dspr2/subuh_r_ob.c new file mode 100644 index 0000000000..fc20ffd09e --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subuh_r_ob.c @@ -0,0 +1,23 @@ +#include "io.h" + +int main(void) +{ + long long rd, rs, rt, result; + + rd = 0x0; + rs = 0x246956789ABCDEF0; + rt = 0x123456789ABCDEF0; + result = 0x091B000000000000; + + __asm("subuh.ob %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + + if (rd != result) { + printf("subuh.ob error\n"); + return -1; + } + + return 0; +} diff --git a/tests/tcg/mips/mips64-dspr2/subuh_r_qb.c b/tests/tcg/mips/mips64-dspr2/subuh_r_qb.c new file mode 100644 index 0000000000..66d4680440 --- /dev/null +++ b/tests/tcg/mips/mips64-dspr2/subuh_r_qb.c @@ -0,0 +1,37 @@ +#include"io.h" + +int main(void) +{ + long long rd, rs, rt; + long long result; + + rs = 0x12345678; + rt = 0x87654321; + result = 0xC6E80A2C; + + __asm + ("subuh_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("1 subuh_r.qb wrong\n"); + return -1; + } + + rs = 0xBEFC292A; + rt = 0x9205C1B4; + result = 0x167cb4bb; + + __asm + ("subuh_r.qb %0, %1, %2\n\t" + : "=r"(rd) + : "r"(rs), "r"(rt) + ); + if (rd != result) { + printf("2 subuh_r.qb wrong\n"); + return -1; + } + + return 0; +} From b30706dda79894c01768df23cde526061d609258 Mon Sep 17 00:00:00 2001 From: Jia Liu Date: Wed, 24 Oct 2012 22:17:14 +0800 Subject: [PATCH 144/291] target-mips: Change TODO file Change DSP r1 & DSP r2 into microMIPS DSP encodings in TODO file. Signed-off-by: Jia Liu Signed-off-by: Aurelien Jarno --- target-mips/TODO | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target-mips/TODO b/target-mips/TODO index 2a3546f624..1d782d8027 100644 --- a/target-mips/TODO +++ b/target-mips/TODO @@ -6,8 +6,7 @@ General - Unimplemented ASEs: - MDMX - SmartMIPS - - DSP r1 - - DSP r2 + - microMIPS DSP r1 & r2 encodings - MT ASE only partially implemented and not functional - Shadow register support only partially implemented, lacks set switching on interrupt/exception. From 40e3acc18f1c663ee8f0c981525316f864f7b8ea Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 31 Oct 2012 22:14:46 +0100 Subject: [PATCH 145/291] target-mips: remove #if defined(TARGET_MIPS64) in opcode enums All switch() decoding instruction have a default entry, so it is possible to have unused enum entries. Remove conditional definitions of MIPS64 opcode enums, as it only makes the code less readable. Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 36 ------------------------------------ 1 file changed, 36 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index fea4113092..6dc2b62844 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -318,46 +318,30 @@ enum { OPC_LX_DSP = 0x0A | OPC_SPECIAL3, /* MIPS DSP Arithmetic */ OPC_ADDU_QB_DSP = 0x10 | OPC_SPECIAL3, -#if defined(TARGET_MIPS64) OPC_ADDU_OB_DSP = 0x14 | OPC_SPECIAL3, -#endif OPC_ABSQ_S_PH_DSP = 0x12 | OPC_SPECIAL3, -#if defined(TARGET_MIPS64) OPC_ABSQ_S_QH_DSP = 0x16 | OPC_SPECIAL3, -#endif /* OPC_ADDUH_QB_DSP is same as OPC_MULT_G_2E. */ /* OPC_ADDUH_QB_DSP = 0x18 | OPC_SPECIAL3, */ OPC_CMPU_EQ_QB_DSP = 0x11 | OPC_SPECIAL3, -#if defined(TARGET_MIPS64) OPC_CMPU_EQ_OB_DSP = 0x15 | OPC_SPECIAL3, -#endif /* MIPS DSP GPR-Based Shift Sub-class */ OPC_SHLL_QB_DSP = 0x13 | OPC_SPECIAL3, -#if defined(TARGET_MIPS64) OPC_SHLL_OB_DSP = 0x17 | OPC_SPECIAL3, -#endif /* MIPS DSP Multiply Sub-class insns */ /* OPC_MUL_PH_DSP is same as OPC_ADDUH_QB_DSP. */ /* OPC_MUL_PH_DSP = 0x18 | OPC_SPECIAL3, */ OPC_DPA_W_PH_DSP = 0x30 | OPC_SPECIAL3, -#if defined(TARGET_MIPS64) OPC_DPAQ_W_QH_DSP = 0x34 | OPC_SPECIAL3, -#endif /* DSP Bit/Manipulation Sub-class */ OPC_INSV_DSP = 0x0C | OPC_SPECIAL3, -#if defined(TARGET_MIPS64) OPC_DINSV_DSP = 0x0D | OPC_SPECIAL3, -#endif /* MIPS DSP Compare-Pick Sub-class */ OPC_APPEND_DSP = 0x31 | OPC_SPECIAL3, -#if defined(TARGET_MIPS64) OPC_DAPPEND_DSP = 0x35 | OPC_SPECIAL3, -#endif /* MIPS DSP Accumulator and DSPControl Access Sub-class */ OPC_EXTR_W_DSP = 0x38 | OPC_SPECIAL3, -#if defined(TARGET_MIPS64) OPC_DEXTR_W_DSP = 0x3C | OPC_SPECIAL3, -#endif }; /* BSHFL opcodes */ @@ -380,9 +364,7 @@ enum { /* MIPS DSP REGIMM opcodes */ enum { OPC_BPOSGE32 = (0x1C << 16) | OPC_REGIMM, -#if defined(TARGET_MIPS64) OPC_BPOSGE64 = (0x1D << 16) | OPC_REGIMM, -#endif }; #define MASK_LX(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) @@ -391,9 +373,7 @@ enum { OPC_LBUX = (0x06 << 6) | OPC_LX_DSP, OPC_LHX = (0x04 << 6) | OPC_LX_DSP, OPC_LWX = (0x00 << 6) | OPC_LX_DSP, -#if defined(TARGET_MIPS64) OPC_LDX = (0x08 << 6) | OPC_LX_DSP, -#endif }; #define MASK_ADDU_QB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) @@ -591,9 +571,6 @@ enum { OPC_RDDSP = (0x12 << 6) | OPC_EXTR_W_DSP, }; - - -#if defined(TARGET_MIPS64) #define MASK_ABSQ_S_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* MIPS DSP Arithmetic Sub-class */ @@ -622,9 +599,7 @@ enum { OPC_REPLV_PW = (0x13 << 6) | OPC_ABSQ_S_QH_DSP, OPC_REPLV_QH = (0x0B << 6) | OPC_ABSQ_S_QH_DSP, }; -#endif -#if defined(TARGET_MIPS64) #define MASK_ADDU_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* MIPS DSP Multiply Sub-class insns */ @@ -656,9 +631,7 @@ enum { OPC_ADDUH_OB = (0x18 << 6) | OPC_ADDU_OB_DSP, OPC_ADDUH_R_OB = (0x1A << 6) | OPC_ADDU_OB_DSP, }; -#endif -#if defined(TARGET_MIPS64) #define MASK_CMPU_EQ_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* DSP Compare-Pick Sub-class */ @@ -691,9 +664,7 @@ enum { OPC_PRECRQ_RS_QH_PW = (0x15 << 6) | OPC_CMPU_EQ_OB_DSP, OPC_PRECRQU_S_OB_QH = (0x0F << 6) | OPC_CMPU_EQ_OB_DSP, }; -#endif -#if defined(TARGET_MIPS64) #define MASK_DAPPEND(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* DSP Compare-Pick Sub-class */ @@ -702,9 +673,7 @@ enum { OPC_PREPENDW = (0x01 << 6) | OPC_DAPPEND_DSP, OPC_DBALIGN = (0x10 << 6) | OPC_DAPPEND_DSP, }; -#endif -#if defined(TARGET_MIPS64) #define MASK_DEXTR_W(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* MIPS DSP Accumulator and DSPControl Access Sub-class */ @@ -736,9 +705,7 @@ enum { /* DSP Bit/Manipulation Sub-class */ OPC_DINSV = (0x00 << 6) | OPC_DINSV_DSP, }; -#endif -#if defined(TARGET_MIPS64) #define MASK_DPAQ_W_QH(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* MIPS DSP Multiply Sub-class insns */ @@ -769,9 +736,7 @@ enum { OPC_MULSAQ_S_L_PW = (0x0E << 6) | OPC_DPAQ_W_QH_DSP, OPC_MULSAQ_S_W_QH = (0x06 << 6) | OPC_DPAQ_W_QH_DSP, }; -#endif -#if defined(TARGET_MIPS64) #define MASK_SHLL_OB(op) (MASK_SPECIAL3(op) | (op & (0x1F << 6))) enum { /* MIPS DSP GPR-Based Shift Sub-class */ @@ -802,7 +767,6 @@ enum { OPC_SHRL_OB = (0x01 << 6) | OPC_SHLL_OB_DSP, OPC_SHRL_QH = (0x19 << 6) | OPC_SHLL_OB_DSP, }; -#endif /* Coprocessor 0 (rs field) */ #define MASK_CP0(op) MASK_OP_MAJOR(op) | (op & (0x1F << 21)) From ac4119c023c72b15f54238af43e4a178fcf41494 Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Fri, 12 Oct 2012 09:52:49 +0200 Subject: [PATCH 146/291] chardev: Use timer instead of bottom-half to postpone open event As the block layer may decide to flush bottom-halfs while the machine is still initializing (e.g. to read geometry data from the disk), our postponed open event may be processed before the last frontend registered with a muxed chardev. Until the semantics of BHs have been clarified, use an expired timer to achieve the same effect (suggested by Paolo Bonzini). This requires to perform the alarm timer initialization earlier as otherwise timer subsystem can be used before being ready. Signed-off-by: Jan Kiszka --- qemu-char.c | 13 +++++++------ qemu-char.h | 2 +- vl.c | 10 +++++----- 3 files changed, 13 insertions(+), 12 deletions(-) diff --git a/qemu-char.c b/qemu-char.c index afe2bfb4dd..88f40254b7 100644 --- a/qemu-char.c +++ b/qemu-char.c @@ -123,19 +123,20 @@ void qemu_chr_be_event(CharDriverState *s, int event) s->chr_event(s->handler_opaque, event); } -static void qemu_chr_generic_open_bh(void *opaque) +static void qemu_chr_fire_open_event(void *opaque) { CharDriverState *s = opaque; qemu_chr_be_event(s, CHR_EVENT_OPENED); - qemu_bh_delete(s->bh); - s->bh = NULL; + qemu_free_timer(s->open_timer); + s->open_timer = NULL; } void qemu_chr_generic_open(CharDriverState *s) { - if (s->bh == NULL) { - s->bh = qemu_bh_new(qemu_chr_generic_open_bh, s); - qemu_bh_schedule(s->bh); + if (s->open_timer == NULL) { + s->open_timer = qemu_new_timer_ms(vm_clock, + qemu_chr_fire_open_event, s); + qemu_mod_timer(s->open_timer, qemu_get_clock_ms(vm_clock) - 1); } } diff --git a/qemu-char.h b/qemu-char.h index 486644b3bd..297dd98342 100644 --- a/qemu-char.h +++ b/qemu-char.h @@ -69,7 +69,7 @@ struct CharDriverState { void (*chr_guest_open)(struct CharDriverState *chr); void (*chr_guest_close)(struct CharDriverState *chr); void *opaque; - QEMUBH *bh; + QEMUTimer *open_timer; char *label; char *filename; int opened; diff --git a/vl.c b/vl.c index 5a3d316980..5513d1518e 100644 --- a/vl.c +++ b/vl.c @@ -3551,6 +3551,11 @@ int main(int argc, char **argv, char **envp) add_device_config(DEV_VIRTCON, "vc:80Cx24C"); } + if (init_timer_alarm() < 0) { + fprintf(stderr, "could not initialize alarm timer\n"); + exit(1); + } + socket_init(); if (qemu_opts_foreach(qemu_find_opts("chardev"), chardev_init_func, NULL, 1) != 0) @@ -3618,11 +3623,6 @@ int main(int argc, char **argv, char **envp) os_set_line_buffering(); - if (init_timer_alarm() < 0) { - fprintf(stderr, "could not initialize alarm timer\n"); - exit(1); - } - #ifdef CONFIG_SPICE /* spice needs the timers to be initialized by this point */ qemu_spice_init(); From e1e1b25c97632cf68d6a11e20f8068282e3d7915 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Wed, 31 Oct 2012 10:30:55 +1100 Subject: [PATCH 147/291] target-alpha: Use TCG_CALL_NO_WG Mark helper functions that raise exceptions, but otherwise do not change TCG register state, with TCG_CALL_NO_WG. Signed-off-by: Richard Henderson --- target-alpha/helper.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target-alpha/helper.h b/target-alpha/helper.h index 162816fa73..dd55f89aad 100644 --- a/target-alpha/helper.h +++ b/target-alpha/helper.h @@ -3,12 +3,12 @@ DEF_HELPER_3(excp, noreturn, env, int, int) DEF_HELPER_FLAGS_1(load_pcc, TCG_CALL_NO_RWG_SE, i64, env) -DEF_HELPER_3(addqv, i64, env, i64, i64) -DEF_HELPER_3(addlv, i64, env, i64, i64) -DEF_HELPER_3(subqv, i64, env, i64, i64) -DEF_HELPER_3(sublv, i64, env, i64, i64) -DEF_HELPER_3(mullv, i64, env, i64, i64) -DEF_HELPER_3(mulqv, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(addqv, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(addlv, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(subqv, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(sublv, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(mullv, TCG_CALL_NO_WG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(mulqv, TCG_CALL_NO_WG, i64, env, i64, i64) DEF_HELPER_FLAGS_2(umulh, TCG_CALL_NO_RWG_SE, i64, i64, i64) DEF_HELPER_FLAGS_1(ctpop, TCG_CALL_NO_RWG_SE, i64, i64) @@ -92,11 +92,11 @@ DEF_HELPER_FLAGS_2(setroundmode, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_2(setflushzero, TCG_CALL_NO_RWG, void, env, i32) DEF_HELPER_FLAGS_1(fp_exc_clear, TCG_CALL_NO_RWG, void, env) DEF_HELPER_FLAGS_1(fp_exc_get, TCG_CALL_NO_RWG_SE, i32, env) -DEF_HELPER_3(fp_exc_raise, void, env, i32, i32) -DEF_HELPER_3(fp_exc_raise_s, void, env, i32, i32) +DEF_HELPER_FLAGS_3(fp_exc_raise, TCG_CALL_NO_WG, void, env, i32, i32) +DEF_HELPER_FLAGS_3(fp_exc_raise_s, TCG_CALL_NO_WG, void, env, i32, i32) -DEF_HELPER_2(ieee_input, void, env, i64) -DEF_HELPER_2(ieee_input_cmp, void, env, i64) +DEF_HELPER_FLAGS_2(ieee_input, TCG_CALL_NO_WG, void, env, i64) +DEF_HELPER_FLAGS_2(ieee_input_cmp, TCG_CALL_NO_WG, void, env, i64) #if !defined (CONFIG_USER_ONLY) DEF_HELPER_2(hw_ret, void, env, i64) From b3a1be87bac3a6aaa59bb88c1410f170dc9b22d5 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 31 Oct 2012 00:50:15 +0100 Subject: [PATCH 148/291] tcg: don't remove op if output needs to be synced to memory Commit 9c43b68de628a1e2cba556adfb71c17028eb802e do not correctly check for dead outputs when they need to be synced to memory in case of half-dead operations. Fix that by applying the same pattern than for the default case. Tested-by: Stefan Weil Signed-off-by: Aurelien Jarno --- tcg/tcg.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index c3a7f19bd7..11334387a0 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1329,8 +1329,8 @@ static void tcg_liveness_analysis(TCGContext *s) the low part. The result can be optimized to a simple add or sub. This happens often for x86_64 guest when the cpu mode is set to 32 bit. */ - if (dead_temps[args[1]]) { - if (dead_temps[args[0]]) { + if (dead_temps[args[1]] && !mem_temps[1]) { + if (dead_temps[args[0]] && !mem_temps[0]) { goto do_remove; } /* Create the single operation plus nop. */ @@ -1355,8 +1355,8 @@ static void tcg_liveness_analysis(TCGContext *s) nb_iargs = 2; nb_oargs = 2; /* Likewise, test for the high part of the operation dead. */ - if (dead_temps[args[1]]) { - if (dead_temps[args[0]]) { + if (dead_temps[args[1]] && !mem_temps[1]) { + if (dead_temps[args[0]] && !mem_temps[0]) { goto do_remove; } gen_opc_buf[op_index] = op = INDEX_op_mul_i32; From 4636401d99c113c67229ceabe93666767a619a25 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sun, 28 Oct 2012 15:42:55 +0100 Subject: [PATCH 149/291] target-mips: correctly restore btarget upon exception When the CPU state is restored through retranslation after an exception, btarget should also be restored. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/target-mips/translate.c b/target-mips/translate.c index 6dc2b62844..bf2cb0ba7c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1015,6 +1015,7 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static uint32_t gen_opc_hflags[OPC_BUF_SIZE]; +static target_ulong gen_opc_btarget[OPC_BUF_SIZE]; #include "gen-icount.h" @@ -15581,6 +15582,7 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, } gen_opc_pc[lj] = ctx.pc; gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK; + gen_opc_btarget[lj] = ctx.btarget; gen_opc_instr_start[lj] = 1; gen_opc_icount[lj] = num_insns; } @@ -16001,4 +16003,13 @@ void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos) env->active_tc.PC = gen_opc_pc[pc_pos]; env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= gen_opc_hflags[pc_pos]; + switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { + case MIPS_HFLAG_BR: + break; + case MIPS_HFLAG_BC: + case MIPS_HFLAG_BL: + case MIPS_HFLAG_B: + env->btarget = gen_opc_btarget[pc_pos]; + break; + } } From 1e0e239a89b5a5ffe475a8efce5e59383a88af44 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sun, 28 Oct 2012 15:55:47 +0100 Subject: [PATCH 150/291] target-mips: do not save CPU state when using retranslation When the CPU state after a possible retranslation is going to be handled through code retranslation, we don't need to save the CPU state before. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 20 -------------------- 1 file changed, 20 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index bf2cb0ba7c..a84ed6e547 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1626,13 +1626,11 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, switch (opc) { #if defined(TARGET_MIPS64) case OPC_LWU: - save_cpu_state(ctx, 0); op_ld_lwu(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lwu"; break; case OPC_LD: - save_cpu_state(ctx, 0); op_ld_ld(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "ld"; @@ -1658,7 +1656,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, opn = "ldr"; break; case OPC_LDPC: - save_cpu_state(ctx, 0); tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); op_ld_ld(t0, t0, ctx); @@ -1667,7 +1664,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; #endif case OPC_LWPC: - save_cpu_state(ctx, 0); tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); op_ld_lw(t0, t0, ctx); @@ -1675,31 +1671,26 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, opn = "lwpc"; break; case OPC_LW: - save_cpu_state(ctx, 0); op_ld_lw(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lw"; break; case OPC_LH: - save_cpu_state(ctx, 0); op_ld_lh(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lh"; break; case OPC_LHU: - save_cpu_state(ctx, 0); op_ld_lhu(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lhu"; break; case OPC_LB: - save_cpu_state(ctx, 0); op_ld_lb(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lb"; break; case OPC_LBU: - save_cpu_state(ctx, 0); op_ld_lbu(t0, t0, ctx); gen_store_gpr(t0, rt); opn = "lbu"; @@ -1744,7 +1735,6 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, switch (opc) { #if defined(TARGET_MIPS64) case OPC_SD: - save_cpu_state(ctx, 0); op_st_sd(t1, t0, ctx); opn = "sd"; break; @@ -1760,17 +1750,14 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, break; #endif case OPC_SW: - save_cpu_state(ctx, 0); op_st_sw(t1, t0, ctx); opn = "sw"; break; case OPC_SH: - save_cpu_state(ctx, 0); op_st_sh(t1, t0, ctx); opn = "sh"; break; case OPC_SB: - save_cpu_state(ctx, 0); op_st_sb(t1, t0, ctx); opn = "sb"; break; @@ -8691,7 +8678,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, } /* Don't do NOP if destination is zero: we must perform the actual memory access. */ - save_cpu_state(ctx, 0); switch (opc) { case OPC_LWXC1: check_cop1x(ctx); @@ -10964,7 +10950,6 @@ static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) gen_op_addr_add(ctx, t0, t1, t0); } - save_cpu_state(ctx, 0); op_ld_lw(t1, t0, ctx); gen_store_gpr(t1, rd); @@ -10994,7 +10979,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, generate_exception(ctx, EXCP_RI); return; } - save_cpu_state(ctx, 0); op_ld_lw(t1, t0, ctx); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 4); @@ -11004,7 +10988,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, opn = "lwp"; break; case SWP: - save_cpu_state(ctx, 0); gen_load_gpr(t1, rd); op_st_sw(t1, t0, ctx); tcg_gen_movi_tl(t1, 4); @@ -11019,7 +11002,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, generate_exception(ctx, EXCP_RI); return; } - save_cpu_state(ctx, 0); op_ld_ld(t1, t0, ctx); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 8); @@ -11029,7 +11011,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, opn = "ldp"; break; case SDP: - save_cpu_state(ctx, 0); gen_load_gpr(t1, rd); op_st_sd(t1, t0, ctx); tcg_gen_movi_tl(t1, 8); @@ -12671,7 +12652,6 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, gen_op_addr_add(ctx, t0, cpu_gpr[base], cpu_gpr[offset]); } - save_cpu_state(ctx, 0); switch (opc) { case OPC_LBUX: op_ld_lbu(t0, t0, ctx); From bbc1dedef6530917e34a94a2641932e636f9b02d Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:20 +0200 Subject: [PATCH 151/291] softfloat: implement fused multiply-add NaN propagation for MIPS Add a pickNaNMulAdd function for MIPS, implementing NaN propagation rules for MIPS fused multiply-add instructions. Cc: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- fpu/softfloat-specialize.h | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h index a1d489e425..518f694a68 100644 --- a/fpu/softfloat-specialize.h +++ b/fpu/softfloat-specialize.h @@ -486,6 +486,33 @@ static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, return 1; } } +#elif defined(TARGET_MIPS) +static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, + flag cIsQNaN, flag cIsSNaN, flag infzero STATUS_PARAM) +{ + /* For MIPS, the (inf,zero,qnan) case sets InvalidOp and returns + * the default NaN + */ + if (infzero) { + float_raise(float_flag_invalid STATUS_VAR); + return 3; + } + + /* Prefer sNaN over qNaN, in the a, b, c order. */ + if (aIsSNaN) { + return 0; + } else if (bIsSNaN) { + return 1; + } else if (cIsSNaN) { + return 2; + } else if (aIsQNaN) { + return 0; + } else if (bIsQNaN) { + return 1; + } else { + return 2; + } +} #elif defined(TARGET_PPC) static int pickNaNMulAdd(flag aIsQNaN, flag aIsSNaN, flag bIsQNaN, flag bIsSNaN, flag cIsQNaN, flag cIsSNaN, flag infzero STATUS_PARAM) From b3d6cd447d594217cbfd09a3ffdf7b7893a1aa92 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:20 +0200 Subject: [PATCH 152/291] target-mips: use the softfloat floatXX_muladd functions Use the new softfloat floatXX_muladd() functions to implement the madd, msub, nmadd and nmsub instructions. At the same time replace the name of the helpers by the name of the instruction, as the only reason for the previous names was to keep the macros simple. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/helper.h | 8 +-- target-mips/op_helper.c | 135 ++++++++++++++-------------------------- target-mips/translate.c | 24 +++---- 3 files changed, 63 insertions(+), 104 deletions(-) diff --git a/target-mips/helper.h b/target-mips/helper.h index 36a2e8da07..da8d9a1381 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -254,10 +254,10 @@ FOP_PROTO(rsqrt2) DEF_HELPER_4(float_ ## op ## _s, i32, env, i32, i32, i32) \ DEF_HELPER_4(float_ ## op ## _d, i64, env, i64, i64, i64) \ DEF_HELPER_4(float_ ## op ## _ps, i64, env, i64, i64, i64) -FOP_PROTO(muladd) -FOP_PROTO(mulsub) -FOP_PROTO(nmuladd) -FOP_PROTO(nmulsub) +FOP_PROTO(madd) +FOP_PROTO(msub) +FOP_PROTO(nmadd) +FOP_PROTO(nmsub) #undef FOP_PROTO #define FOP_PROTO(op) \ diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index d50334f45f..1abed8e3da 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -3031,95 +3031,54 @@ FLOAT_BINOP(mul) FLOAT_BINOP(div) #undef FLOAT_BINOP -/* ternary operations */ -#define FLOAT_TERNOP(name1, name2) \ -uint64_t helper_float_ ## name1 ## name2 ## _d(CPUMIPSState *env, \ - uint64_t fdt0, \ - uint64_t fdt1, \ - uint64_t fdt2) \ -{ \ - fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ - return float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ -} \ - \ -uint32_t helper_float_ ## name1 ## name2 ## _s(CPUMIPSState *env, \ - uint32_t fst0, \ - uint32_t fst1, \ - uint32_t fst2) \ -{ \ - fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ - return float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ -} \ - \ -uint64_t helper_float_ ## name1 ## name2 ## _ps(CPUMIPSState *env, \ - uint64_t fdt0, \ - uint64_t fdt1, \ - uint64_t fdt2) \ -{ \ - uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ - uint32_t fsth0 = fdt0 >> 32; \ - uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ - uint32_t fsth1 = fdt1 >> 32; \ - uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ - uint32_t fsth2 = fdt2 >> 32; \ - \ - fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ - fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ - fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ - fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ - return ((uint64_t)fsth2 << 32) | fst2; \ +/* FMA based operations */ +#define FLOAT_FMA(name, type) \ +uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ + uint64_t fdt0, uint64_t fdt1, \ + uint64_t fdt2) \ +{ \ + set_float_exception_flags(0, &env->active_fpu.fp_status); \ + fdt0 = float64_muladd(fdt0, fdt1, fdt2, type, \ + &env->active_fpu.fp_status); \ + update_fcr31(env); \ + return fdt0; \ +} \ + \ +uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ + uint32_t fst0, uint32_t fst1, \ + uint32_t fst2) \ +{ \ + set_float_exception_flags(0, &env->active_fpu.fp_status); \ + fst0 = float32_muladd(fst0, fst1, fst2, type, \ + &env->active_fpu.fp_status); \ + update_fcr31(env); \ + return fst0; \ +} \ + \ +uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ + uint64_t fdt0, uint64_t fdt1, \ + uint64_t fdt2) \ +{ \ + uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ + uint32_t fsth0 = fdt0 >> 32; \ + uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ + uint32_t fsth1 = fdt1 >> 32; \ + uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ + uint32_t fsth2 = fdt2 >> 32; \ + \ + set_float_exception_flags(0, &env->active_fpu.fp_status); \ + fst0 = float32_muladd(fst0, fst1, fst2, type, \ + &env->active_fpu.fp_status); \ + fsth0 = float32_muladd(fsth0, fsth1, fsth2, type, \ + &env->active_fpu.fp_status); \ + update_fcr31(env); \ + return ((uint64_t)fsth0 << 32) | fst0; \ } - -FLOAT_TERNOP(mul, add) -FLOAT_TERNOP(mul, sub) -#undef FLOAT_TERNOP - -/* negated ternary operations */ -#define FLOAT_NTERNOP(name1, name2) \ -uint64_t helper_float_n ## name1 ## name2 ## _d(CPUMIPSState *env, \ - uint64_t fdt0, \ - uint64_t fdt1, \ - uint64_t fdt2) \ -{ \ - fdt0 = float64_ ## name1 (fdt0, fdt1, &env->active_fpu.fp_status); \ - fdt2 = float64_ ## name2 (fdt0, fdt2, &env->active_fpu.fp_status); \ - return float64_chs(fdt2); \ -} \ - \ -uint32_t helper_float_n ## name1 ## name2 ## _s(CPUMIPSState *env, \ - uint32_t fst0, \ - uint32_t fst1, \ - uint32_t fst2) \ -{ \ - fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ - fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ - return float32_chs(fst2); \ -} \ - \ -uint64_t helper_float_n ## name1 ## name2 ## _ps(CPUMIPSState *env, \ - uint64_t fdt0, \ - uint64_t fdt1, \ - uint64_t fdt2) \ -{ \ - uint32_t fst0 = fdt0 & 0XFFFFFFFF; \ - uint32_t fsth0 = fdt0 >> 32; \ - uint32_t fst1 = fdt1 & 0XFFFFFFFF; \ - uint32_t fsth1 = fdt1 >> 32; \ - uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ - uint32_t fsth2 = fdt2 >> 32; \ - \ - fst0 = float32_ ## name1 (fst0, fst1, &env->active_fpu.fp_status); \ - fsth0 = float32_ ## name1 (fsth0, fsth1, &env->active_fpu.fp_status); \ - fst2 = float32_ ## name2 (fst0, fst2, &env->active_fpu.fp_status); \ - fsth2 = float32_ ## name2 (fsth0, fsth2, &env->active_fpu.fp_status); \ - fst2 = float32_chs(fst2); \ - fsth2 = float32_chs(fsth2); \ - return ((uint64_t)fsth2 << 32) | fst2; \ -} - -FLOAT_NTERNOP(mul, add) -FLOAT_NTERNOP(mul, sub) -#undef FLOAT_NTERNOP +FLOAT_FMA(madd, 0) +FLOAT_FMA(msub, float_muladd_negate_c) +FLOAT_FMA(nmadd, float_muladd_negate_result) +FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) +#undef FLOAT_FMA /* MIPS specific binary operations */ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) diff --git a/target-mips/translate.c b/target-mips/translate.c index a84ed6e547..e7184715bf 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -8817,7 +8817,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); - gen_helper_float_muladd_s(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_madd_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); @@ -8836,7 +8836,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_muladd_d(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_madd_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -8854,7 +8854,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_muladd_ps(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_madd_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -8872,7 +8872,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); - gen_helper_float_mulsub_s(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_msub_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); @@ -8891,7 +8891,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_mulsub_d(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_msub_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -8909,7 +8909,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_mulsub_ps(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_msub_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -8927,7 +8927,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); - gen_helper_float_nmuladd_s(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmadd_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); @@ -8946,7 +8946,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmuladd_d(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmadd_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -8964,7 +8964,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmuladd_ps(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmadd_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -8982,7 +8982,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr32(fp0, fs); gen_load_fpr32(fp1, ft); gen_load_fpr32(fp2, fr); - gen_helper_float_nmulsub_s(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmsub_s(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); gen_store_fpr32(fp2, fd); @@ -9001,7 +9001,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmulsub_d(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmsub_d(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); @@ -9019,7 +9019,7 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_load_fpr64(ctx, fp0, fs); gen_load_fpr64(ctx, fp1, ft); gen_load_fpr64(ctx, fp2, fr); - gen_helper_float_nmulsub_ps(fp2, cpu_env, fp0, fp1, fp2); + gen_helper_float_nmsub_ps(fp2, cpu_env, fp0, fp1, fp2); tcg_temp_free_i64(fp0); tcg_temp_free_i64(fp1); gen_store_fpr64(ctx, fp2, fd); From 4a587b2ccb336e36817712ab21c513e35baa0eca Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sun, 28 Oct 2012 18:08:27 +0100 Subject: [PATCH 153/291] target-mips: keep softfloat exception set to 0 between instructions Instead of clearing the softfloat exception flags before each floating point instruction, reset them to 0 in update_fcr31() when an exception is detected. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/op_helper.c | 73 ++++++----------------------------------- 1 file changed, 10 insertions(+), 63 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 1abed8e3da..82044990b0 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2445,10 +2445,16 @@ static inline void update_fcr31(CPUMIPSState *env) int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); SET_FP_CAUSE(env->active_fpu.fcr31, tmp); - if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) - helper_raise_exception(env, EXCP_FPE); - else - UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); + + if (tmp) { + set_float_exception_flags(0, &env->active_fpu.fp_status); + + if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) { + helper_raise_exception(env, EXCP_FPE); + } else { + UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); + } + } } /* Float support. @@ -2471,7 +2477,6 @@ uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) { uint64_t fdt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; @@ -2481,7 +2486,6 @@ uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) { uint64_t fdt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; @@ -2491,7 +2495,6 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) { uint64_t fdt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; @@ -2501,7 +2504,6 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) @@ -2513,7 +2515,6 @@ uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) @@ -2526,7 +2527,6 @@ uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) uint32_t fst2; uint32_t fsth2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); update_fcr31(env); @@ -2538,7 +2538,6 @@ uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) uint32_t wt2; uint32_t wth2; - set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); update_fcr31(env); @@ -2553,7 +2552,6 @@ uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t fst2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); update_fcr31(env); return fst2; @@ -2563,7 +2561,6 @@ uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) { uint32_t fst2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); update_fcr31(env); return fst2; @@ -2573,7 +2570,6 @@ uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) { uint32_t fst2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); update_fcr31(env); return fst2; @@ -2583,7 +2579,6 @@ uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = wt0; update_fcr31(env); return wt2; @@ -2593,7 +2588,6 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = wth0; update_fcr31(env); return wt2; @@ -2603,7 +2597,6 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) @@ -2615,7 +2608,6 @@ uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) @@ -2627,7 +2619,6 @@ uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2641,7 +2632,6 @@ uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2655,7 +2645,6 @@ uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2669,7 +2658,6 @@ uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2683,7 +2671,6 @@ uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) @@ -2695,7 +2682,6 @@ uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) @@ -2707,7 +2693,6 @@ uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) @@ -2719,7 +2704,6 @@ uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); update_fcr31(env); if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) @@ -2731,7 +2715,6 @@ uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2745,7 +2728,6 @@ uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2759,7 +2741,6 @@ uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2773,7 +2754,6 @@ uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2787,7 +2767,6 @@ uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t dt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2801,7 +2780,6 @@ uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) { uint64_t dt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2815,7 +2793,6 @@ uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2829,7 +2806,6 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) { uint32_t wt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; @@ -2867,7 +2843,6 @@ uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; @@ -2877,7 +2852,6 @@ uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); update_fcr31(env); return fst2; @@ -2887,7 +2861,6 @@ uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); update_fcr31(env); @@ -2898,7 +2871,6 @@ uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); update_fcr31(env); @@ -2909,7 +2881,6 @@ uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; @@ -2919,7 +2890,6 @@ uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); update_fcr31(env); return fst2; @@ -2930,7 +2900,6 @@ uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) uint32_t fst2; uint32_t fsth2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status); update_fcr31(env); @@ -2941,7 +2910,6 @@ uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); update_fcr31(env); @@ -2952,7 +2920,6 @@ uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); update_fcr31(env); @@ -2964,7 +2931,6 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) uint32_t fst2; uint32_t fsth2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); @@ -2982,7 +2948,6 @@ uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ { \ uint64_t dt2; \ \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ update_fcr31(env); \ if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ @@ -2995,7 +2960,6 @@ uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ { \ uint32_t wt2; \ \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ update_fcr31(env); \ if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ @@ -3014,7 +2978,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ uint32_t wt2; \ uint32_t wth2; \ \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ update_fcr31(env); \ @@ -3037,7 +3000,6 @@ uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ uint64_t fdt0, uint64_t fdt1, \ uint64_t fdt2) \ { \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ fdt0 = float64_muladd(fdt0, fdt1, fdt2, type, \ &env->active_fpu.fp_status); \ update_fcr31(env); \ @@ -3048,7 +3010,6 @@ uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ uint32_t fst0, uint32_t fst1, \ uint32_t fst2) \ { \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ fst0 = float32_muladd(fst0, fst1, fst2, type, \ &env->active_fpu.fp_status); \ update_fcr31(env); \ @@ -3066,7 +3027,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ uint32_t fst2 = fdt2 & 0XFFFFFFFF; \ uint32_t fsth2 = fdt2 >> 32; \ \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ fst0 = float32_muladd(fst0, fst1, fst2, type, \ &env->active_fpu.fp_status); \ fsth0 = float32_muladd(fsth0, fsth1, fsth2, type, \ @@ -3083,7 +3043,6 @@ FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) /* MIPS specific binary operations */ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { - set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); update_fcr31(env); @@ -3092,7 +3051,6 @@ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); update_fcr31(env); @@ -3106,7 +3064,6 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) uint32_t fst2 = fdt2 & 0XFFFFFFFF; uint32_t fsth2 = fdt2 >> 32; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); @@ -3117,7 +3074,6 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { - set_float_exception_flags(0, &env->active_fpu.fp_status); fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); @@ -3127,7 +3083,6 @@ uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); @@ -3142,7 +3097,6 @@ uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) uint32_t fst2 = fdt2 & 0XFFFFFFFF; uint32_t fsth2 = fdt2 >> 32; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); @@ -3162,7 +3116,6 @@ uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) uint32_t fst2; uint32_t fsth2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); update_fcr31(env); @@ -3178,7 +3131,6 @@ uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) uint32_t fst2; uint32_t fsth2; - set_float_exception_flags(0, &env->active_fpu.fp_status); fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); update_fcr31(env); @@ -3191,7 +3143,6 @@ void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ uint64_t fdt1, int cc) \ { \ int c; \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ c = cond; \ update_fcr31(env); \ if (c) \ @@ -3203,7 +3154,6 @@ void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ uint64_t fdt1, int cc) \ { \ int c; \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ fdt0 = float64_abs(fdt0); \ fdt1 = float64_abs(fdt1); \ c = cond; \ @@ -3240,7 +3190,6 @@ void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ uint32_t fst1, int cc) \ { \ int c; \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ c = cond; \ update_fcr31(env); \ if (c) \ @@ -3252,7 +3201,6 @@ void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ uint32_t fst1, int cc) \ { \ int c; \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ fst0 = float32_abs(fst0); \ fst1 = float32_abs(fst1); \ c = cond; \ @@ -3290,7 +3238,6 @@ void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ { \ uint32_t fst0, fsth0, fst1, fsth1; \ int ch, cl; \ - set_float_exception_flags(0, &env->active_fpu.fp_status); \ fst0 = fdt0 & 0XFFFFFFFF; \ fsth0 = fdt0 >> 32; \ fst1 = fdt1 & 0XFFFFFFFF; \ From 5dbe90bba778c6ffcd0c7991ec67c4e7469e1c09 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:20 +0200 Subject: [PATCH 154/291] target-mips: fix FPU exceptions For each FPU instruction that can trigger an FPU exception, to call call update_fcr31() after. Remove the manual NaN assignment in case of float to float operation, as softfloat is already taking care of that. However for float to int operation, the value has to be changed to the MIPS one. In the cvtpw_ps case, the two registers have to be handled separately to guarantee a correct final value in both registers. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/op_helper.c | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 82044990b0..7981ea2f3a 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2465,12 +2465,16 @@ static inline void update_fcr31(CPUMIPSState *env) /* unary operations, modifying fp status */ uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) { - return float64_sqrt(fdt0, &env->active_fpu.fp_status); + fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status); + update_fcr31(env); + return fdt0; } uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) { - return float32_sqrt(fst0, &env->active_fpu.fp_status); + fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status); + update_fcr31(env); + return fst0; } uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) @@ -2537,14 +2541,24 @@ uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) { uint32_t wt2; uint32_t wth2; + int excp, excph; wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); - wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) { + excp = get_float_exception_flags(&env->active_fpu.fp_status); + if (excp & (float_flag_overflow | float_flag_invalid)) { wt2 = FLOAT_SNAN32; + } + + set_float_exception_flags(0, &env->active_fpu.fp_status); + wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); + excph = get_float_exception_flags(&env->active_fpu.fp_status); + if (excph & (float_flag_overflow | float_flag_invalid)) { wth2 = FLOAT_SNAN32; } + + set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); + update_fcr31(env); + return ((uint64_t)wth2 << 32) | wt2; } @@ -2950,8 +2964,6 @@ uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ \ dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ update_fcr31(env); \ - if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ - dt2 = FLOAT_QNAN64; \ return dt2; \ } \ \ @@ -2962,8 +2974,6 @@ uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ update_fcr31(env); \ - if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) \ - wt2 = FLOAT_QNAN32; \ return wt2; \ } \ \ @@ -2981,10 +2991,6 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ update_fcr31(env); \ - if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) { \ - wt2 = FLOAT_QNAN32; \ - wth2 = FLOAT_QNAN32; \ - } \ return ((uint64_t)wth2 << 32) | wt2; \ } From 4cc2e5f989728424e913777c494d68dbf0d2ec09 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 23 Oct 2012 09:53:50 +0200 Subject: [PATCH 155/291] target-mips: cleanup float to int conversion helpers Instead of accessing the flags from the floating point control register after updating it, read the softfloat flags. This is just code cleanup and should not change the behaviour. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/op_helper.c | 118 +++++++++++++++++++++++++++------------- 1 file changed, 79 insertions(+), 39 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 7981ea2f3a..d3a317bea9 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2509,9 +2509,11 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) uint64_t dt2; dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { dt2 = FLOAT_SNAN64; + } + update_fcr31(env); return dt2; } @@ -2520,9 +2522,11 @@ uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) uint64_t dt2; dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { dt2 = FLOAT_SNAN64; + } + update_fcr31(env); return dt2; } @@ -2613,8 +2617,10 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { wt2 = FLOAT_SNAN32; + } return wt2; } @@ -2623,9 +2629,11 @@ uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) uint32_t wt2; wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { wt2 = FLOAT_SNAN32; + } + update_fcr31(env); return wt2; } @@ -2636,9 +2644,11 @@ uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { dt2 = FLOAT_SNAN64; + } + update_fcr31(env); return dt2; } @@ -2649,9 +2659,11 @@ uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { dt2 = FLOAT_SNAN64; + } + update_fcr31(env); return dt2; } @@ -2662,9 +2674,11 @@ uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { wt2 = FLOAT_SNAN32; + } + update_fcr31(env); return wt2; } @@ -2675,9 +2689,11 @@ uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { wt2 = FLOAT_SNAN32; + } + update_fcr31(env); return wt2; } @@ -2686,9 +2702,11 @@ uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) uint64_t dt2; dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { dt2 = FLOAT_SNAN64; + } + update_fcr31(env); return dt2; } @@ -2697,9 +2715,11 @@ uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) uint64_t dt2; dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { dt2 = FLOAT_SNAN64; + } + update_fcr31(env); return dt2; } @@ -2708,9 +2728,11 @@ uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) uint32_t wt2; wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { wt2 = FLOAT_SNAN32; + } + update_fcr31(env); return wt2; } @@ -2719,9 +2741,11 @@ uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) uint32_t wt2; wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { wt2 = FLOAT_SNAN32; + } + update_fcr31(env); return wt2; } @@ -2732,9 +2756,11 @@ uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { dt2 = FLOAT_SNAN64; + } + update_fcr31(env); return dt2; } @@ -2745,9 +2771,11 @@ uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { dt2 = FLOAT_SNAN64; + } + update_fcr31(env); return dt2; } @@ -2758,9 +2786,11 @@ uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { wt2 = FLOAT_SNAN32; + } + update_fcr31(env); return wt2; } @@ -2771,9 +2801,11 @@ uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { wt2 = FLOAT_SNAN32; + } + update_fcr31(env); return wt2; } @@ -2784,9 +2816,11 @@ uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { dt2 = FLOAT_SNAN64; + } + update_fcr31(env); return dt2; } @@ -2797,9 +2831,11 @@ uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { dt2 = FLOAT_SNAN64; + } + update_fcr31(env); return dt2; } @@ -2810,9 +2846,11 @@ uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { wt2 = FLOAT_SNAN32; + } + update_fcr31(env); return wt2; } @@ -2823,9 +2861,11 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status); wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); RESTORE_ROUNDING_MODE; - update_fcr31(env); - if (GET_FP_CAUSE(env->active_fpu.fcr31) & (FP_OVERFLOW | FP_INVALID)) + if (get_float_exception_flags(&env->active_fpu.fp_status) + & (float_flag_invalid | float_flag_overflow)) { wt2 = FLOAT_SNAN32; + } + update_fcr31(env); return wt2; } From 05993cd05fcdebc75f8432cf6ad558726dc8ec15 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 23 Oct 2012 10:12:00 +0200 Subject: [PATCH 156/291] target-mips: use softfloat constants when possible softfloat already has a few constants defined, use them instead of redefining them in target-mips. Rename FLOAT_SNAN32 and FLOAT_SNAN64 to FP_TO_INT32_OVERFLOW and FP_TO_INT64_OVERFLOW as even if they have the same value, they are technically different (and defined differently in the MIPS ISA). Remove the unused constants. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/op_helper.c | 92 ++++++++++++++++++++--------------------- 1 file changed, 44 insertions(+), 48 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index d3a317bea9..2f9ec5d26e 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -2332,14 +2332,10 @@ void cpu_unassigned_access(CPUMIPSState *env, hwaddr addr, /* Complex FPU operations which may need stack space. */ -#define FLOAT_ONE32 make_float32(0x3f8 << 20) -#define FLOAT_ONE64 make_float64(0x3ffULL << 52) #define FLOAT_TWO32 make_float32(1 << 30) #define FLOAT_TWO64 make_float64(1ULL << 62) -#define FLOAT_QNAN32 0x7fbfffff -#define FLOAT_QNAN64 0x7ff7ffffffffffffULL -#define FLOAT_SNAN32 0x7fffffff -#define FLOAT_SNAN64 0x7fffffffffffffffULL +#define FP_TO_INT32_OVERFLOW 0x7fffffff +#define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL /* convert MIPS rounding mode in FCR31 to IEEE library */ static unsigned int ieee_rm[] = { @@ -2511,7 +2507,7 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - dt2 = FLOAT_SNAN64; + dt2 = FP_TO_INT64_OVERFLOW; } update_fcr31(env); return dt2; @@ -2524,7 +2520,7 @@ uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - dt2 = FLOAT_SNAN64; + dt2 = FP_TO_INT64_OVERFLOW; } update_fcr31(env); return dt2; @@ -2550,14 +2546,14 @@ uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); excp = get_float_exception_flags(&env->active_fpu.fp_status); if (excp & (float_flag_overflow | float_flag_invalid)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } set_float_exception_flags(0, &env->active_fpu.fp_status); wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status); excph = get_float_exception_flags(&env->active_fpu.fp_status); if (excph & (float_flag_overflow | float_flag_invalid)) { - wth2 = FLOAT_SNAN32; + wth2 = FP_TO_INT32_OVERFLOW; } set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); @@ -2619,7 +2615,7 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) update_fcr31(env); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } return wt2; } @@ -2631,7 +2627,7 @@ uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } update_fcr31(env); return wt2; @@ -2646,7 +2642,7 @@ uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - dt2 = FLOAT_SNAN64; + dt2 = FP_TO_INT64_OVERFLOW; } update_fcr31(env); return dt2; @@ -2661,7 +2657,7 @@ uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - dt2 = FLOAT_SNAN64; + dt2 = FP_TO_INT64_OVERFLOW; } update_fcr31(env); return dt2; @@ -2676,7 +2672,7 @@ uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } update_fcr31(env); return wt2; @@ -2691,7 +2687,7 @@ uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } update_fcr31(env); return wt2; @@ -2704,7 +2700,7 @@ uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - dt2 = FLOAT_SNAN64; + dt2 = FP_TO_INT64_OVERFLOW; } update_fcr31(env); return dt2; @@ -2717,7 +2713,7 @@ uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - dt2 = FLOAT_SNAN64; + dt2 = FP_TO_INT64_OVERFLOW; } update_fcr31(env); return dt2; @@ -2730,7 +2726,7 @@ uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } update_fcr31(env); return wt2; @@ -2743,7 +2739,7 @@ uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } update_fcr31(env); return wt2; @@ -2758,7 +2754,7 @@ uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - dt2 = FLOAT_SNAN64; + dt2 = FP_TO_INT64_OVERFLOW; } update_fcr31(env); return dt2; @@ -2773,7 +2769,7 @@ uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - dt2 = FLOAT_SNAN64; + dt2 = FP_TO_INT64_OVERFLOW; } update_fcr31(env); return dt2; @@ -2788,7 +2784,7 @@ uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } update_fcr31(env); return wt2; @@ -2803,7 +2799,7 @@ uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } update_fcr31(env); return wt2; @@ -2818,7 +2814,7 @@ uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - dt2 = FLOAT_SNAN64; + dt2 = FP_TO_INT64_OVERFLOW; } update_fcr31(env); return dt2; @@ -2833,7 +2829,7 @@ uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - dt2 = FLOAT_SNAN64; + dt2 = FP_TO_INT64_OVERFLOW; } update_fcr31(env); return dt2; @@ -2848,7 +2844,7 @@ uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } update_fcr31(env); return wt2; @@ -2863,7 +2859,7 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) RESTORE_ROUNDING_MODE; if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { - wt2 = FLOAT_SNAN32; + wt2 = FP_TO_INT32_OVERFLOW; } update_fcr31(env); return wt2; @@ -2897,7 +2893,7 @@ uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; - fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); + fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; } @@ -2906,7 +2902,7 @@ uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; - fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); update_fcr31(env); return fst2; } @@ -2916,7 +2912,7 @@ uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) uint64_t fdt2; fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); - fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); + fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; } @@ -2926,7 +2922,7 @@ uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) uint32_t fst2; fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); - fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); update_fcr31(env); return fst2; } @@ -2935,7 +2931,7 @@ uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) { uint64_t fdt2; - fdt2 = float64_div(FLOAT_ONE64, fdt0, &env->active_fpu.fp_status); + fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; } @@ -2944,7 +2940,7 @@ uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) { uint32_t fst2; - fst2 = float32_div(FLOAT_ONE32, fst0, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); update_fcr31(env); return fst2; } @@ -2954,8 +2950,8 @@ uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) uint32_t fst2; uint32_t fsth2; - fst2 = float32_div(FLOAT_ONE32, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); - fsth2 = float32_div(FLOAT_ONE32, fdt0 >> 32, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); + fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status); update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } @@ -2965,7 +2961,7 @@ uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) uint64_t fdt2; fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); - fdt2 = float64_div(FLOAT_ONE64, fdt2, &env->active_fpu.fp_status); + fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); update_fcr31(env); return fdt2; } @@ -2975,7 +2971,7 @@ uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) uint32_t fst2; fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); - fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); update_fcr31(env); return fst2; } @@ -2987,8 +2983,8 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); - fst2 = float32_div(FLOAT_ONE32, fst2, &env->active_fpu.fp_status); - fsth2 = float32_div(FLOAT_ONE32, fsth2, &env->active_fpu.fp_status); + fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); + fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status); update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3090,7 +3086,7 @@ FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c) uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); - fdt2 = float64_chs(float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status)); + fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status)); update_fcr31(env); return fdt2; } @@ -3098,7 +3094,7 @@ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); + fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); update_fcr31(env); return fst2; } @@ -3112,8 +3108,8 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 = float32_chs(float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status)); - fsth2 = float32_chs(float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status)); + fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); + fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status)); update_fcr31(env); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3121,7 +3117,7 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); - fdt2 = float64_sub(fdt2, FLOAT_ONE64, &env->active_fpu.fp_status); + fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); update_fcr31(env); return fdt2; @@ -3130,7 +3126,7 @@ uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); - fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); + fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); update_fcr31(env); return fst2; @@ -3145,8 +3141,8 @@ uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); - fst2 = float32_sub(fst2, FLOAT_ONE32, &env->active_fpu.fp_status); - fsth2 = float32_sub(fsth2, FLOAT_ONE32, &env->active_fpu.fp_status); + fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); + fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); update_fcr31(env); From 5f7319cd84ecb82f65c67dd1033ec27647fcb7db Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Sun, 28 Oct 2012 19:34:03 +0100 Subject: [PATCH 157/291] target-mips: restore CPU state after an FPU exception Rework *raise_exception*() functions so that they can be called from other helpers, passing the return address as an argument. Use do_raise_exception() function in update_fcr31() to correctly restore the CPU state after an FPU exception. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/op_helper.c | 191 +++++++++++++++++++++------------------- 1 file changed, 98 insertions(+), 93 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 2f9ec5d26e..a7509ca885 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -33,35 +33,50 @@ static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global); /*****************************************************************************/ /* Exceptions processing helpers */ -void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, - int error_code) +static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, + uint32_t exception, + int error_code, + uintptr_t pc) { + TranslationBlock *tb; #if 1 if (exception < 0x100) qemu_log("%s: %d %d\n", __func__, exception, error_code); #endif env->exception_index = exception; env->error_code = error_code; + + if (pc) { + /* now we have a real cpu fault */ + tb = tb_find_pc(pc); + if (tb) { + /* the PC is inside the translated code. It means that we have + a virtual CPU fault */ + cpu_restore_state(tb, env, pc); + } + } + cpu_loop_exit(env); } +static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, + uint32_t exception, + uintptr_t pc) +{ + do_raise_exception_err(env, exception, 0, pc); +} + +void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code) +{ + do_raise_exception_err(env, exception, error_code, 0); +} + void helper_raise_exception(CPUMIPSState *env, uint32_t exception) { - helper_raise_exception_err(env, exception, 0); + do_raise_exception(env, exception, 0); } -#if !defined(CONFIG_USER_ONLY) -static void do_restore_state(CPUMIPSState *env, uintptr_t pc) -{ - TranslationBlock *tb; - - tb = tb_find_pc (pc); - if (tb) { - cpu_restore_state(tb, env, pc); - } -} -#endif - #if defined(CONFIG_USER_ONLY) #define HELPER_LD(name, insn, type) \ static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ @@ -2295,28 +2310,18 @@ static void do_unaligned_access(CPUMIPSState *env, target_ulong addr, int is_write, int is_user, uintptr_t retaddr) { env->CP0_BadVAddr = addr; - do_restore_state(env, retaddr); - helper_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL); + do_raise_exception(env, (is_write == 1) ? EXCP_AdES : EXCP_AdEL, retaddr); } void tlb_fill(CPUMIPSState *env, target_ulong addr, int is_write, int mmu_idx, uintptr_t retaddr) { - TranslationBlock *tb; int ret; ret = cpu_mips_handle_mmu_fault(env, addr, is_write, mmu_idx); if (ret) { - if (retaddr) { - /* now we have a real cpu fault */ - tb = tb_find_pc(retaddr); - if (tb) { - /* the PC is inside the translated code. It means that we have - a virtual CPU fault */ - cpu_restore_state(tb, env, retaddr); - } - } - helper_raise_exception_err(env, env->exception_index, env->error_code); + do_raise_exception_err(env, env->exception_index, + env->error_code, retaddr); } } @@ -2410,7 +2415,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t reg) RESTORE_FLUSH_MODE; set_float_exception_flags(0, &env->active_fpu.fp_status); if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31)) - helper_raise_exception(env, EXCP_FPE); + do_raise_exception(env, EXCP_FPE, GETPC()); } static inline int ieee_ex_to_mips(int xcpt) @@ -2436,7 +2441,7 @@ static inline int ieee_ex_to_mips(int xcpt) return ret; } -static inline void update_fcr31(CPUMIPSState *env) +static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc) { int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status)); @@ -2446,7 +2451,7 @@ static inline void update_fcr31(CPUMIPSState *env) set_float_exception_flags(0, &env->active_fpu.fp_status); if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) { - helper_raise_exception(env, EXCP_FPE); + do_raise_exception(env, EXCP_FPE, pc); } else { UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp); } @@ -2462,14 +2467,14 @@ static inline void update_fcr31(CPUMIPSState *env) uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0) { fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fdt0; } uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0) { fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fst0; } @@ -2478,7 +2483,7 @@ uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0) uint64_t fdt2; fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fdt2; } @@ -2487,7 +2492,7 @@ uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0) uint64_t fdt2; fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fdt2; } @@ -2496,7 +2501,7 @@ uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0) uint64_t fdt2; fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fdt2; } @@ -2509,7 +2514,7 @@ uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return dt2; } @@ -2522,7 +2527,7 @@ uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return dt2; } @@ -2533,7 +2538,7 @@ uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0) fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -2557,7 +2562,7 @@ uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0) } set_float_exception_flags(excp | excph, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return ((uint64_t)wth2 << 32) | wt2; } @@ -2567,7 +2572,7 @@ uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0) uint32_t fst2; fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fst2; } @@ -2576,7 +2581,7 @@ uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0) uint32_t fst2; fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fst2; } @@ -2585,7 +2590,7 @@ uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0) uint32_t fst2; fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fst2; } @@ -2594,7 +2599,7 @@ uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0) uint32_t wt2; wt2 = wt0; - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2603,7 +2608,7 @@ uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0) uint32_t wt2; wt2 = wth0; - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2612,7 +2617,7 @@ uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0) uint32_t wt2; wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); if (get_float_exception_flags(&env->active_fpu.fp_status) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; @@ -2629,7 +2634,7 @@ uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2644,7 +2649,7 @@ uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return dt2; } @@ -2659,7 +2664,7 @@ uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return dt2; } @@ -2674,7 +2679,7 @@ uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2689,7 +2694,7 @@ uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2702,7 +2707,7 @@ uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return dt2; } @@ -2715,7 +2720,7 @@ uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return dt2; } @@ -2728,7 +2733,7 @@ uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2741,7 +2746,7 @@ uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2756,7 +2761,7 @@ uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return dt2; } @@ -2771,7 +2776,7 @@ uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return dt2; } @@ -2786,7 +2791,7 @@ uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2801,7 +2806,7 @@ uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2816,7 +2821,7 @@ uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return dt2; } @@ -2831,7 +2836,7 @@ uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0) & (float_flag_invalid | float_flag_overflow)) { dt2 = FP_TO_INT64_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return dt2; } @@ -2846,7 +2851,7 @@ uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2861,7 +2866,7 @@ uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0) & (float_flag_invalid | float_flag_overflow)) { wt2 = FP_TO_INT32_OVERFLOW; } - update_fcr31(env); + update_fcr31(env, GETPC()); return wt2; } @@ -2894,7 +2899,7 @@ uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0) uint64_t fdt2; fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fdt2; } @@ -2903,7 +2908,7 @@ uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0) uint32_t fst2; fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fst2; } @@ -2913,7 +2918,7 @@ uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0) fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fdt2; } @@ -2923,7 +2928,7 @@ uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0) fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fst2; } @@ -2932,7 +2937,7 @@ uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0) uint64_t fdt2; fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fdt2; } @@ -2941,7 +2946,7 @@ uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0) uint32_t fst2; fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fst2; } @@ -2952,7 +2957,7 @@ uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0) fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status); fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -2962,7 +2967,7 @@ uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0) fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status); fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fdt2; } @@ -2972,7 +2977,7 @@ uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0) fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status); fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return fst2; } @@ -2985,7 +2990,7 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0) fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status); fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status); fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -2999,7 +3004,7 @@ uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ uint64_t dt2; \ \ dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ return dt2; \ } \ \ @@ -3009,7 +3014,7 @@ uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ uint32_t wt2; \ \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ return wt2; \ } \ \ @@ -3026,7 +3031,7 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ \ wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \ wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ return ((uint64_t)wth2 << 32) | wt2; \ } @@ -3044,7 +3049,7 @@ uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \ { \ fdt0 = float64_muladd(fdt0, fdt1, fdt2, type, \ &env->active_fpu.fp_status); \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ return fdt0; \ } \ \ @@ -3054,7 +3059,7 @@ uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \ { \ fst0 = float32_muladd(fst0, fst1, fst2, type, \ &env->active_fpu.fp_status); \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ return fst0; \ } \ \ @@ -3073,7 +3078,7 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \ &env->active_fpu.fp_status); \ fsth0 = float32_muladd(fsth0, fsth1, fsth2, type, \ &env->active_fpu.fp_status); \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ return ((uint64_t)fsth0 << 32) | fst0; \ } FLOAT_FMA(madd, 0) @@ -3087,7 +3092,7 @@ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) { fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status)); - update_fcr31(env); + update_fcr31(env, GETPC()); return fdt2; } @@ -3095,7 +3100,7 @@ uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) { fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); - update_fcr31(env); + update_fcr31(env, GETPC()); return fst2; } @@ -3110,7 +3115,7 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status); fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status)); fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status)); - update_fcr31(env); + update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3119,7 +3124,7 @@ uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status); fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status); fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status)); - update_fcr31(env); + update_fcr31(env, GETPC()); return fdt2; } @@ -3128,7 +3133,7 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2) fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status); fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); - update_fcr31(env); + update_fcr31(env, GETPC()); return fst2; } @@ -3145,7 +3150,7 @@ uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2) fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status); fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status)); fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status)); - update_fcr31(env); + update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3160,7 +3165,7 @@ uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status); fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3175,7 +3180,7 @@ uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1) fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status); fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status); - update_fcr31(env); + update_fcr31(env, GETPC()); return ((uint64_t)fsth2 << 32) | fst2; } @@ -3186,7 +3191,7 @@ void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ { \ int c; \ c = cond; \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3199,7 +3204,7 @@ void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \ fdt0 = float64_abs(fdt0); \ fdt1 = float64_abs(fdt1); \ c = cond; \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3233,7 +3238,7 @@ void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ { \ int c; \ c = cond; \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3246,7 +3251,7 @@ void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \ fst0 = float32_abs(fst0); \ fst1 = float32_abs(fst1); \ c = cond; \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ if (c) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3286,7 +3291,7 @@ void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ fsth1 = fdt1 >> 32; \ cl = condl; \ ch = condh; \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ if (cl) \ SET_FP_COND(cc, env->active_fpu); \ else \ @@ -3307,7 +3312,7 @@ void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \ fsth1 = float32_abs(fdt1 >> 32); \ cl = condl; \ ch = condh; \ - update_fcr31(env); \ + update_fcr31(env, GETPC()); \ if (cl) \ SET_FP_COND(cc, env->active_fpu); \ else \ From 2910c6cbaacf7b9d54be3ce8ca03d68db45767bb Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:20 +0200 Subject: [PATCH 158/291] target-mips: cleanup load/store operations Load/store operations use macros for historical reasons. Now that there is no point in keeping them, replace them by direct calls to qemu_ld/st. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 99 +++++++++++++++-------------------------- 1 file changed, 35 insertions(+), 64 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index e7184715bf..79c2e92e9d 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1484,35 +1484,6 @@ FOP_CONDS(abs, 1, ps, FMT_PS, 64) #undef gen_ldcmp_fpr64 /* load/store instructions. */ -#define OP_LD(insn,fname) \ -static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ -{ \ - tcg_gen_qemu_##fname(ret, arg1, ctx->mem_idx); \ -} -OP_LD(lb,ld8s); -OP_LD(lbu,ld8u); -OP_LD(lh,ld16s); -OP_LD(lhu,ld16u); -OP_LD(lw,ld32s); -#if defined(TARGET_MIPS64) -OP_LD(lwu,ld32u); -OP_LD(ld,ld64); -#endif -#undef OP_LD - -#define OP_ST(insn,fname) \ -static inline void op_st_##insn(TCGv arg1, TCGv arg2, DisasContext *ctx) \ -{ \ - tcg_gen_qemu_##fname(arg1, arg2, ctx->mem_idx); \ -} -OP_ST(sb,st8); -OP_ST(sh,st16); -OP_ST(sw,st32); -#if defined(TARGET_MIPS64) -OP_ST(sd,st64); -#endif -#undef OP_ST - #ifdef CONFIG_USER_ONLY #define OP_LD_ATOMIC(insn,fname) \ static inline void op_ld_##insn(TCGv ret, TCGv arg1, DisasContext *ctx) \ @@ -1626,12 +1597,12 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, switch (opc) { #if defined(TARGET_MIPS64) case OPC_LWU: - op_ld_lwu(t0, t0, ctx); + tcg_gen_qemu_ld32u(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "lwu"; break; case OPC_LD: - op_ld_ld(t0, t0, ctx); + tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "ld"; break; @@ -1658,7 +1629,7 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, case OPC_LDPC: tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - op_ld_ld(t0, t0, ctx); + tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "ldpc"; break; @@ -1666,32 +1637,32 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, case OPC_LWPC: tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); - op_ld_lw(t0, t0, ctx); + tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "lwpc"; break; case OPC_LW: - op_ld_lw(t0, t0, ctx); + tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "lw"; break; case OPC_LH: - op_ld_lh(t0, t0, ctx); + tcg_gen_qemu_ld16s(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "lh"; break; case OPC_LHU: - op_ld_lhu(t0, t0, ctx); + tcg_gen_qemu_ld16u(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "lhu"; break; case OPC_LB: - op_ld_lb(t0, t0, ctx); + tcg_gen_qemu_ld8s(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "lb"; break; case OPC_LBU: - op_ld_lbu(t0, t0, ctx); + tcg_gen_qemu_ld8u(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "lbu"; break; @@ -1735,7 +1706,7 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, switch (opc) { #if defined(TARGET_MIPS64) case OPC_SD: - op_st_sd(t1, t0, ctx); + tcg_gen_qemu_st64(t1, t0, ctx->mem_idx); opn = "sd"; break; case OPC_SDL: @@ -1750,15 +1721,15 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, break; #endif case OPC_SW: - op_st_sw(t1, t0, ctx); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); opn = "sw"; break; case OPC_SH: - op_st_sh(t1, t0, ctx); + tcg_gen_qemu_st16(t1, t0, ctx->mem_idx); opn = "sh"; break; case OPC_SB: - op_st_sb(t1, t0, ctx); + tcg_gen_qemu_st8(t1, t0, ctx->mem_idx); opn = "sb"; break; case OPC_SWL: @@ -9320,22 +9291,22 @@ static void gen_mips16_save (DisasContext *ctx, case 4: gen_base_offset_addr(ctx, t0, 29, 12); gen_load_gpr(t1, 7); - op_st_sw(t1, t0, ctx); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); /* Fall through */ case 3: gen_base_offset_addr(ctx, t0, 29, 8); gen_load_gpr(t1, 6); - op_st_sw(t1, t0, ctx); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); /* Fall through */ case 2: gen_base_offset_addr(ctx, t0, 29, 4); gen_load_gpr(t1, 5); - op_st_sw(t1, t0, ctx); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); /* Fall through */ case 1: gen_base_offset_addr(ctx, t0, 29, 0); gen_load_gpr(t1, 4); - op_st_sw(t1, t0, ctx); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); } gen_load_gpr(t0, 29); @@ -9343,7 +9314,7 @@ static void gen_mips16_save (DisasContext *ctx, #define DECR_AND_STORE(reg) do { \ tcg_gen_subi_tl(t0, t0, 4); \ gen_load_gpr(t1, reg); \ - op_st_sw(t1, t0, ctx); \ + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); \ } while (0) if (do_ra) { @@ -9441,10 +9412,10 @@ static void gen_mips16_restore (DisasContext *ctx, tcg_gen_addi_tl(t0, cpu_gpr[29], framesize); -#define DECR_AND_LOAD(reg) do { \ - tcg_gen_subi_tl(t0, t0, 4); \ - op_ld_lw(t1, t0, ctx); \ - gen_store_gpr(t1, reg); \ +#define DECR_AND_LOAD(reg) do { \ + tcg_gen_subi_tl(t0, t0, 4); \ + tcg_gen_qemu_ld32u(t1, t0, ctx->mem_idx); \ + gen_store_gpr(t1, reg); \ } while (0) if (do_ra) { @@ -10950,7 +10921,7 @@ static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) gen_op_addr_add(ctx, t0, t1, t0); } - op_ld_lw(t1, t0, ctx); + tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx); gen_store_gpr(t1, rd); tcg_temp_free(t0); @@ -10979,21 +10950,21 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, generate_exception(ctx, EXCP_RI); return; } - op_ld_lw(t1, t0, ctx); + tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); - op_ld_lw(t1, t0, ctx); + tcg_gen_qemu_ld32s(t1, t0, ctx->mem_idx); gen_store_gpr(t1, rd+1); opn = "lwp"; break; case SWP: gen_load_gpr(t1, rd); - op_st_sw(t1, t0, ctx); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); tcg_gen_movi_tl(t1, 4); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd+1); - op_st_sw(t1, t0, ctx); + tcg_gen_qemu_st32(t1, t0, ctx->mem_idx); opn = "swp"; break; #ifdef TARGET_MIPS64 @@ -11002,21 +10973,21 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, generate_exception(ctx, EXCP_RI); return; } - op_ld_ld(t1, t0, ctx); + tcg_gen_qemu_ld64(t1, t0, ctx->mem_idx); gen_store_gpr(t1, rd); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); - op_ld_ld(t1, t0, ctx); + tcg_gen_qemu_ld64(t1, t0, ctx->mem_idx); gen_store_gpr(t1, rd+1); opn = "ldp"; break; case SDP: gen_load_gpr(t1, rd); - op_st_sd(t1, t0, ctx); + tcg_gen_qemu_st64(t1, t0, ctx->mem_idx); tcg_gen_movi_tl(t1, 8); gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd+1); - op_st_sd(t1, t0, ctx); + tcg_gen_qemu_st64(t1, t0, ctx->mem_idx); opn = "sdp"; break; #endif @@ -12654,23 +12625,23 @@ static void gen_mipsdsp_ld(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, switch (opc) { case OPC_LBUX: - op_ld_lbu(t0, t0, ctx); + tcg_gen_qemu_ld8u(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rd); opn = "lbux"; break; case OPC_LHX: - op_ld_lh(t0, t0, ctx); + tcg_gen_qemu_ld16s(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rd); opn = "lhx"; break; case OPC_LWX: - op_ld_lw(t0, t0, ctx); + tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rd); opn = "lwx"; break; #if defined(TARGET_MIPS64) case OPC_LDX: - op_ld_ld(t0, t0, ctx); + tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rd); opn = "ldx"; break; From 3cee3050ce2d79837fa286a730a54e2a8b9dc5dc Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:20 +0200 Subject: [PATCH 159/291] target-mips: optimize load operations Only allocate t1 when needed. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 79c2e92e9d..a48a475806 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1591,7 +1591,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, } t0 = tcg_temp_new(); - t1 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, base, offset); switch (opc) { @@ -1614,29 +1613,35 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; case OPC_LDL: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(ldl, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "ldl"; break; case OPC_LDR: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(ldr, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "ldr"; break; case OPC_LDPC: - tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); + t1 = tcg_const_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); + tcg_temp_free(t1); tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "ldpc"; break; #endif case OPC_LWPC: - tcg_gen_movi_tl(t1, pc_relative_pc(ctx)); + t1 = tcg_const_tl(pc_relative_pc(ctx)); gen_op_addr_add(ctx, t0, t0, t1); + tcg_temp_free(t1); tcg_gen_qemu_ld32s(t0, t0, ctx->mem_idx); gen_store_gpr(t0, rt); opn = "lwpc"; @@ -1668,16 +1673,20 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, break; case OPC_LWL: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(lwl, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "lwl"; break; case OPC_LWR: save_cpu_state(ctx, 1); + t1 = tcg_temp_new(); gen_load_gpr(t1, rt); gen_helper_1e2i(lwr, t1, t1, t0, ctx->mem_idx); gen_store_gpr(t1, rt); + tcg_temp_free(t1); opn = "lwr"; break; case OPC_LL: @@ -1690,7 +1699,6 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); tcg_temp_free(t0); - tcg_temp_free(t1); } /* Store */ From 18bba4dc781a273c2c1ff5baec2909c214e2e0fa Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:20 +0200 Subject: [PATCH 160/291] target-mips: simplify load/store microMIPS helpers load/store microMIPS helpers are reinventing the wheel. Call do_lw, do_ll, do_sw and do_sl instead of using a macro calling the cpu_* load/store functions. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/op_helper.c | 73 +++++------------------------------------ 1 file changed, 9 insertions(+), 64 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index a7509ca885..78497d9a87 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -594,32 +594,19 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; -#ifdef CONFIG_USER_ONLY -#undef ldfun -#define ldfun(env, addr) ldl_raw(addr) -#else - uint32_t (*ldfun)(CPUMIPSState *env, target_ulong); - - switch (mem_idx) - { - case 0: ldfun = cpu_ldl_kernel; break; - case 1: ldfun = cpu_ldl_super; break; - default: - case 2: ldfun = cpu_ldl_user; break; - } -#endif if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { target_ulong i; for (i = 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] = (target_long)ldfun(env, addr); + env->active_tc.gpr[multiple_regs[i]] = + (target_long)do_lw(env, addr, mem_idx); addr += 4; } } if (do_r31) { - env->active_tc.gpr[31] = (target_long)ldfun(env, addr); + env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx); } } @@ -628,32 +615,18 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; -#ifdef CONFIG_USER_ONLY -#undef stfun -#define stfun(env, addr, val) stl_raw(addr, val) -#else - void (*stfun)(CPUMIPSState *env, target_ulong, uint32_t); - - switch (mem_idx) - { - case 0: stfun = cpu_stl_kernel; break; - case 1: stfun = cpu_stl_super; break; - default: - case 2: stfun = cpu_stl_user; break; - } -#endif if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { target_ulong i; for (i = 0; i < base_reglist; i++) { - stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]); + do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); addr += 4; } } if (do_r31) { - stfun(env, addr, env->active_tc.gpr[31]); + do_sw(env, addr, env->active_tc.gpr[31], mem_idx); } } @@ -663,32 +636,18 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; -#ifdef CONFIG_USER_ONLY -#undef ldfun -#define ldfun(env, addr) ldq_raw(addr) -#else - uint64_t (*ldfun)(CPUMIPSState *env, target_ulong); - - switch (mem_idx) - { - case 0: ldfun = cpu_ldq_kernel; break; - case 1: ldfun = cpu_ldq_super; break; - default: - case 2: ldfun = cpu_ldq_user; break; - } -#endif if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { target_ulong i; for (i = 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] = ldfun(env, addr); + env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx); addr += 8; } } if (do_r31) { - env->active_tc.gpr[31] = ldfun(env, addr); + env->active_tc.gpr[31] = do_ld(env, addr, mem_idx); } } @@ -697,32 +656,18 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, { target_ulong base_reglist = reglist & 0xf; target_ulong do_r31 = reglist & 0x10; -#ifdef CONFIG_USER_ONLY -#undef stfun -#define stfun(env, addr, val) stq_raw(addr, val) -#else - void (*stfun)(CPUMIPSState *env, target_ulong, uint64_t); - - switch (mem_idx) - { - case 0: stfun = cpu_stq_kernel; break; - case 1: stfun = cpu_stq_super; break; - default: - case 2: stfun = cpu_stq_user; break; - } -#endif if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) { target_ulong i; for (i = 0; i < base_reglist; i++) { - stfun(env, addr, env->active_tc.gpr[multiple_regs[i]]); + do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); addr += 8; } } if (do_r31) { - stfun(env, addr, env->active_tc.gpr[31]); + do_sd(env, addr, env->active_tc.gpr[31], mem_idx); } } #endif From fc40787abcf8452b8f50d92b7a13243a12972c7a Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:21 +0200 Subject: [PATCH 161/291] target-mips: implement unaligned loads using TCG Load/store from helpers should be avoided as they are quite inefficient. Rewrite unaligned loads instructions using TCG and aligned loads. The number of actual loads operations to implement an unaligned load instruction is reduced from up to 8 to 1. Note: As we can't rely on shift by 32 or 64 undefined behaviour, the code loads already shift by one constants. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/helper.h | 4 -- target-mips/op_helper.c | 142 ---------------------------------------- target-mips/translate.c | 75 +++++++++++++++++---- 3 files changed, 62 insertions(+), 159 deletions(-) diff --git a/target-mips/helper.h b/target-mips/helper.h index da8d9a1381..acf9ebd759 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -4,13 +4,9 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) DEF_HELPER_2(raise_exception, noreturn, env, i32) #ifdef TARGET_MIPS64 -DEF_HELPER_4(ldl, tl, env, tl, tl, int) -DEF_HELPER_4(ldr, tl, env, tl, tl, int) DEF_HELPER_4(sdl, void, env, tl, tl, int) DEF_HELPER_4(sdr, void, env, tl, tl, int) #endif -DEF_HELPER_4(lwl, tl, env, tl, tl, int) -DEF_HELPER_4(lwr, tl, env, tl, tl, int) DEF_HELPER_4(swl, void, env, tl, tl, int) DEF_HELPER_4(swr, void, env, tl, tl, int) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 78497d9a87..773c7104af 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -350,56 +350,6 @@ HELPER_ST_ATOMIC(scd, ld, sd, 0x7) #define GET_OFFSET(addr, offset) (addr - (offset)) #endif -target_ulong helper_lwl(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2, int mem_idx) -{ - target_ulong tmp; - - tmp = do_lbu(env, arg2, mem_idx); - arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); - - if (GET_LMASK(arg2) <= 2) { - tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx); - arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); - } - - if (GET_LMASK(arg2) <= 1) { - tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx); - arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); - } - - if (GET_LMASK(arg2) == 0) { - tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx); - arg1 = (arg1 & 0xFFFFFF00) | tmp; - } - return (int32_t)arg1; -} - -target_ulong helper_lwr(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2, int mem_idx) -{ - target_ulong tmp; - - tmp = do_lbu(env, arg2, mem_idx); - arg1 = (arg1 & 0xFFFFFF00) | tmp; - - if (GET_LMASK(arg2) >= 1) { - tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx); - arg1 = (arg1 & 0xFFFF00FF) | (tmp << 8); - } - - if (GET_LMASK(arg2) >= 2) { - tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx); - arg1 = (arg1 & 0xFF00FFFF) | (tmp << 16); - } - - if (GET_LMASK(arg2) == 3) { - tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx); - arg1 = (arg1 & 0x00FFFFFF) | (tmp << 24); - } - return (int32_t)arg1; -} - void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { @@ -440,98 +390,6 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, #define GET_LMASK64(v) (((v) & 7) ^ 7) #endif -target_ulong helper_ldl(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2, int mem_idx) -{ - uint64_t tmp; - - tmp = do_lbu(env, arg2, mem_idx); - arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); - - if (GET_LMASK64(arg2) <= 6) { - tmp = do_lbu(env, GET_OFFSET(arg2, 1), mem_idx); - arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); - } - - if (GET_LMASK64(arg2) <= 5) { - tmp = do_lbu(env, GET_OFFSET(arg2, 2), mem_idx); - arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); - } - - if (GET_LMASK64(arg2) <= 4) { - tmp = do_lbu(env, GET_OFFSET(arg2, 3), mem_idx); - arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); - } - - if (GET_LMASK64(arg2) <= 3) { - tmp = do_lbu(env, GET_OFFSET(arg2, 4), mem_idx); - arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); - } - - if (GET_LMASK64(arg2) <= 2) { - tmp = do_lbu(env, GET_OFFSET(arg2, 5), mem_idx); - arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); - } - - if (GET_LMASK64(arg2) <= 1) { - tmp = do_lbu(env, GET_OFFSET(arg2, 6), mem_idx); - arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); - } - - if (GET_LMASK64(arg2) == 0) { - tmp = do_lbu(env, GET_OFFSET(arg2, 7), mem_idx); - arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; - } - - return arg1; -} - -target_ulong helper_ldr(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2, int mem_idx) -{ - uint64_t tmp; - - tmp = do_lbu(env, arg2, mem_idx); - arg1 = (arg1 & 0xFFFFFFFFFFFFFF00ULL) | tmp; - - if (GET_LMASK64(arg2) >= 1) { - tmp = do_lbu(env, GET_OFFSET(arg2, -1), mem_idx); - arg1 = (arg1 & 0xFFFFFFFFFFFF00FFULL) | (tmp << 8); - } - - if (GET_LMASK64(arg2) >= 2) { - tmp = do_lbu(env, GET_OFFSET(arg2, -2), mem_idx); - arg1 = (arg1 & 0xFFFFFFFFFF00FFFFULL) | (tmp << 16); - } - - if (GET_LMASK64(arg2) >= 3) { - tmp = do_lbu(env, GET_OFFSET(arg2, -3), mem_idx); - arg1 = (arg1 & 0xFFFFFFFF00FFFFFFULL) | (tmp << 24); - } - - if (GET_LMASK64(arg2) >= 4) { - tmp = do_lbu(env, GET_OFFSET(arg2, -4), mem_idx); - arg1 = (arg1 & 0xFFFFFF00FFFFFFFFULL) | (tmp << 32); - } - - if (GET_LMASK64(arg2) >= 5) { - tmp = do_lbu(env, GET_OFFSET(arg2, -5), mem_idx); - arg1 = (arg1 & 0xFFFF00FFFFFFFFFFULL) | (tmp << 40); - } - - if (GET_LMASK64(arg2) >= 6) { - tmp = do_lbu(env, GET_OFFSET(arg2, -6), mem_idx); - arg1 = (arg1 & 0xFF00FFFFFFFFFFFFULL) | (tmp << 48); - } - - if (GET_LMASK64(arg2) == 7) { - tmp = do_lbu(env, GET_OFFSET(arg2, -7), mem_idx); - arg1 = (arg1 & 0x00FFFFFFFFFFFFFFULL) | (tmp << 56); - } - - return arg1; -} - void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { diff --git a/target-mips/translate.c b/target-mips/translate.c index a48a475806..05d88c4bfc 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1580,7 +1580,7 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int base, int16_t offset) { const char *opn = "ld"; - TCGv t0, t1; + TCGv t0, t1, t2; if (rt == 0 && env->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) { /* Loongson CPU uses a load to zero register for prefetch. @@ -1612,21 +1612,45 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, opn = "lld"; break; case OPC_LDL: - save_cpu_state(ctx, 1); t1 = tcg_temp_new(); + tcg_gen_andi_tl(t1, t0, 7); +#ifndef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 7); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~7); + tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx); + tcg_gen_shl_tl(t0, t0, t1); + tcg_gen_xori_tl(t1, t1, 63); + t2 = tcg_const_tl(0x7fffffffffffffffull); + tcg_gen_shr_tl(t2, t2, t1); gen_load_gpr(t1, rt); - gen_helper_1e2i(ldl, t1, t1, t0, ctx->mem_idx); - gen_store_gpr(t1, rt); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); tcg_temp_free(t1); + gen_store_gpr(t0, rt); opn = "ldl"; break; case OPC_LDR: - save_cpu_state(ctx, 1); t1 = tcg_temp_new(); + tcg_gen_andi_tl(t1, t0, 7); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 7); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~7); + tcg_gen_qemu_ld64(t0, t0, ctx->mem_idx); + tcg_gen_shr_tl(t0, t0, t1); + tcg_gen_xori_tl(t1, t1, 63); + t2 = tcg_const_tl(0xfffffffffffffffeull); + tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); - gen_helper_1e2i(ldr, t1, t1, t0, ctx->mem_idx); - gen_store_gpr(t1, rt); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); tcg_temp_free(t1); + gen_store_gpr(t0, rt); opn = "ldr"; break; case OPC_LDPC: @@ -1672,21 +1696,46 @@ static void gen_ld (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, opn = "lbu"; break; case OPC_LWL: - save_cpu_state(ctx, 1); t1 = tcg_temp_new(); + tcg_gen_andi_tl(t1, t0, 3); +#ifndef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 3); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~3); + tcg_gen_qemu_ld32u(t0, t0, ctx->mem_idx); + tcg_gen_shl_tl(t0, t0, t1); + tcg_gen_xori_tl(t1, t1, 31); + t2 = tcg_const_tl(0x7fffffffull); + tcg_gen_shr_tl(t2, t2, t1); gen_load_gpr(t1, rt); - gen_helper_1e2i(lwl, t1, t1, t0, ctx->mem_idx); - gen_store_gpr(t1, rt); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); tcg_temp_free(t1); + tcg_gen_ext32s_tl(t0, t0); + gen_store_gpr(t0, rt); opn = "lwl"; break; case OPC_LWR: - save_cpu_state(ctx, 1); t1 = tcg_temp_new(); + tcg_gen_andi_tl(t1, t0, 3); +#ifdef TARGET_WORDS_BIGENDIAN + tcg_gen_xori_tl(t1, t1, 3); +#endif + tcg_gen_shli_tl(t1, t1, 3); + tcg_gen_andi_tl(t0, t0, ~3); + tcg_gen_qemu_ld32u(t0, t0, ctx->mem_idx); + tcg_gen_shr_tl(t0, t0, t1); + tcg_gen_xori_tl(t1, t1, 31); + t2 = tcg_const_tl(0xfffffffeull); + tcg_gen_shl_tl(t2, t2, t1); gen_load_gpr(t1, rt); - gen_helper_1e2i(lwr, t1, t1, t0, ctx->mem_idx); - gen_store_gpr(t1, rt); + tcg_gen_and_tl(t1, t1, t2); + tcg_temp_free(t2); + tcg_gen_or_tl(t0, t0, t1); tcg_temp_free(t1); + gen_store_gpr(t0, rt); opn = "lwr"; break; case OPC_LL: From 2d2826b99ee810057c76b48377d286beb9ee943b Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:21 +0200 Subject: [PATCH 162/291] target-mips: don't use local temps for store conditional Store conditional operations only need local temps in user mode. Fix the code to use temp local only in user mode, this spares two memory stores in system mode. At the same time remove a wrong a wrong copied & pasted comment, store operations don't have a register destination. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 05d88c4bfc..2484b238db 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -1814,13 +1814,14 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, const char *opn = "st_cond"; TCGv t0, t1; +#ifdef CONFIG_USER_ONLY t0 = tcg_temp_local_new(); - - gen_base_offset_addr(ctx, t0, base, offset); - /* Don't do NOP if destination is zero: we must perform the actual - memory access. */ - t1 = tcg_temp_local_new(); +#else + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); +#endif + gen_base_offset_addr(ctx, t0, base, offset); gen_load_gpr(t1, rt); switch (opc) { #if defined(TARGET_MIPS64) From acf124655873cf7256877a35efd8dacca1b199d8 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:21 +0200 Subject: [PATCH 163/291] target-mips: implement movn/movz using movcond Avoid the branches in movn/movz implementation and replace them with movcond. Also update a wrong command. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 27 ++++++++++++--------------- 1 file changed, 12 insertions(+), 15 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index 2484b238db..c6b5862e16 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -2359,35 +2359,32 @@ static void gen_cond_move(CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { const char *opn = "cond move"; - int l1; + TCGv t0, t1, t2; if (rd == 0) { - /* If no destination, treat it as a NOP. - For add & sub, we must generate the overflow exception when needed. */ + /* If no destination, treat it as a NOP. */ MIPS_DEBUG("NOP"); return; } - l1 = gen_new_label(); + t0 = tcg_temp_new(); + gen_load_gpr(t0, rt); + t1 = tcg_const_tl(0); + t2 = tcg_temp_new(); + gen_load_gpr(t2, rs); switch (opc) { case OPC_MOVN: - if (likely(rt != 0)) - tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rt], 0, l1); - else - tcg_gen_br(l1); + tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); opn = "movn"; break; case OPC_MOVZ: - if (likely(rt != 0)) - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rt], 0, l1); + tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); opn = "movz"; break; } - if (rs != 0) - tcg_gen_mov_tl(cpu_gpr[rd], cpu_gpr[rs]); - else - tcg_gen_movi_tl(cpu_gpr[rd], 0); - gen_set_label(l1); + tcg_temp_free(t2); + tcg_temp_free(t1); + tcg_temp_free(t0); (void)opn; /* avoid a compiler warning */ MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); From 51127181cfac0315720e6ca502eb133a353f6b11 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:21 +0200 Subject: [PATCH 164/291] target-mips: optimize ddiv/ddivu/div/divu with movcond The result of a division by 0, or a division of INT_MIN by -1 in the signed case, is unpredictable. Just replace 0 by 1 in that case so that it doesn't trigger a floating point exception on the host. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 85 ++++++++++++++++++----------------------- 1 file changed, 37 insertions(+), 48 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index c6b5862e16..b92a84473c 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -2653,60 +2653,48 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, TCGv t0, t1; unsigned int acc; - switch (opc) { - case OPC_DIV: - case OPC_DIVU: -#if defined(TARGET_MIPS64) - case OPC_DDIV: - case OPC_DDIVU: -#endif - t0 = tcg_temp_local_new(); - t1 = tcg_temp_local_new(); - break; - default: - t0 = tcg_temp_new(); - t1 = tcg_temp_new(); - break; - } + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); gen_load_gpr(t0, rs); gen_load_gpr(t1, rt); + switch (opc) { case OPC_DIV: { - int l1 = gen_new_label(); - int l2 = gen_new_label(); - + TCGv t2 = tcg_temp_new(); + TCGv t3 = tcg_temp_new(); tcg_gen_ext32s_tl(t0, t0); tcg_gen_ext32s_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, INT_MIN, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1, l2); - - tcg_gen_mov_tl(cpu_LO[0], t0); - tcg_gen_movi_tl(cpu_HI[0], 0); - tcg_gen_br(l1); - gen_set_label(l2); + tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); + tcg_gen_and_tl(t2, t2, t3); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); + tcg_gen_or_tl(t2, t2, t3); + tcg_gen_movi_tl(t3, 0); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); tcg_gen_div_tl(cpu_LO[0], t0, t1); tcg_gen_rem_tl(cpu_HI[0], t0, t1); tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]); tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]); - gen_set_label(l1); + tcg_temp_free(t3); + tcg_temp_free(t2); } opn = "div"; break; case OPC_DIVU: { - int l1 = gen_new_label(); - + TCGv t2 = tcg_const_tl(0); + TCGv t3 = tcg_const_tl(1); tcg_gen_ext32u_tl(t0, t0); tcg_gen_ext32u_tl(t1, t1); - tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_tl(cpu_LO[0], t0, t1); tcg_gen_remu_tl(cpu_HI[0], t0, t1); tcg_gen_ext32s_tl(cpu_LO[0], cpu_LO[0]); tcg_gen_ext32s_tl(cpu_HI[0], cpu_HI[0]); - gen_set_label(l1); + tcg_temp_free(t3); + tcg_temp_free(t2); } opn = "divu"; break; @@ -2759,30 +2747,31 @@ static void gen_muldiv (DisasContext *ctx, uint32_t opc, #if defined(TARGET_MIPS64) case OPC_DDIV: { - int l1 = gen_new_label(); - int l2 = gen_new_label(); - - tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); - tcg_gen_brcondi_tl(TCG_COND_NE, t0, -1LL << 63, l2); - tcg_gen_brcondi_tl(TCG_COND_NE, t1, -1LL, l2); - tcg_gen_mov_tl(cpu_LO[0], t0); - tcg_gen_movi_tl(cpu_HI[0], 0); - tcg_gen_br(l1); - gen_set_label(l2); - tcg_gen_div_i64(cpu_LO[0], t0, t1); - tcg_gen_rem_i64(cpu_HI[0], t0, t1); - gen_set_label(l1); + TCGv t2 = tcg_temp_new(); + TCGv t3 = tcg_temp_new(); + tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); + tcg_gen_and_tl(t2, t2, t3); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); + tcg_gen_or_tl(t2, t2, t3); + tcg_gen_movi_tl(t3, 0); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_div_tl(cpu_LO[0], t0, t1); + tcg_gen_rem_tl(cpu_HI[0], t0, t1); + tcg_temp_free(t3); + tcg_temp_free(t2); } opn = "ddiv"; break; case OPC_DDIVU: { - int l1 = gen_new_label(); - - tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1); + TCGv t2 = tcg_const_tl(0); + TCGv t3 = tcg_const_tl(1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); tcg_gen_divu_i64(cpu_LO[0], t0, t1); tcg_gen_remu_i64(cpu_HI[0], t0, t1); - gen_set_label(l1); + tcg_temp_free(t3); + tcg_temp_free(t2); } opn = "ddivu"; break; From e0d002f17d1db1ade2b8d24b4a7c7ab361256726 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:21 +0200 Subject: [PATCH 165/291] target-mips: use deposit instead of hardcoded version MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Use the deposit op instead of and hardcoded bit field insertion. It allows the host to emit the corresponding instruction if available. At the same time remove the (lsb > msb) test. The MIPS64R2 instruction set manual says "Because of the instruction format, lsb can never be greater than msb, so there is no UNPREDICATABLE case for this instruction." (Bug reported as LP:1071149.) Cc: Никита Канунников Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno --- target-mips/translate.c | 32 ++++---------------------------- 1 file changed, 4 insertions(+), 28 deletions(-) diff --git a/target-mips/translate.c b/target-mips/translate.c index b92a84473c..8175da05d0 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -3928,7 +3928,6 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, { TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); - target_ulong mask; gen_load_gpr(t1, rs); switch (opc) { @@ -3961,45 +3960,22 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, case OPC_INS: if (lsb > msb) goto fail; - mask = ((msb - lsb + 1 < 32) ? ((1 << (msb - lsb + 1)) - 1) : ~0) << lsb; gen_load_gpr(t0, rt); - tcg_gen_andi_tl(t0, t0, ~mask); - tcg_gen_shli_tl(t1, t1, lsb); - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_or_tl(t0, t0, t1); + tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); tcg_gen_ext32s_tl(t0, t0); break; #if defined(TARGET_MIPS64) case OPC_DINSM: - if (lsb > msb) - goto fail; - mask = ((msb - lsb + 1 + 32 < 64) ? ((1ULL << (msb - lsb + 1 + 32)) - 1) : ~0ULL) << lsb; gen_load_gpr(t0, rt); - tcg_gen_andi_tl(t0, t0, ~mask); - tcg_gen_shli_tl(t1, t1, lsb); - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_or_tl(t0, t0, t1); + tcg_gen_deposit_tl(t0, t0, t1, lsb, msb + 32 - lsb + 1); break; case OPC_DINSU: - if (lsb > msb) - goto fail; - mask = ((1ULL << (msb - lsb + 1)) - 1) << (lsb + 32); gen_load_gpr(t0, rt); - tcg_gen_andi_tl(t0, t0, ~mask); - tcg_gen_shli_tl(t1, t1, lsb + 32); - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_or_tl(t0, t0, t1); + tcg_gen_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1); break; case OPC_DINS: - if (lsb > msb) - goto fail; gen_load_gpr(t0, rt); - mask = ((1ULL << (msb - lsb + 1)) - 1) << lsb; - gen_load_gpr(t0, rt); - tcg_gen_andi_tl(t0, t0, ~mask); - tcg_gen_shli_tl(t1, t1, lsb); - tcg_gen_andi_tl(t1, t1, mask); - tcg_gen_or_tl(t0, t0, t1); + tcg_gen_deposit_tl(t0, t0, t1, lsb, msb - lsb + 1); break; #endif default: From bc3e45e13a93b883f0369acb2e19c0cec8705a7a Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:21 +0200 Subject: [PATCH 166/291] target-mips: fix TLBR wrt SEGMask Like r4k_map_address(), r4k_helper_tlbp() should use SEGMask to mask the address. Signed-off-by: Aurelien Jarno --- target-mips/op_helper.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 773c7104af..cdd6880efc 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1856,6 +1856,9 @@ void r4k_helper_tlbp(CPUMIPSState *env) mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); tag = env->CP0_EntryHi & ~mask; VPN = tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &= env->SEGMask; +#endif /* Check ASID, virtual page number & size */ if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { /* TLB match */ @@ -1871,6 +1874,9 @@ void r4k_helper_tlbp(CPUMIPSState *env) mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); tag = env->CP0_EntryHi & ~mask; VPN = tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &= env->SEGMask; +#endif /* Check ASID, virtual page number & size */ if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) { r4k_mips_tlb_flush_extra (env, i); From 286d52ebfc0d0d53c2a878e454292fea14bad41b Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Tue, 9 Oct 2012 21:53:21 +0200 Subject: [PATCH 167/291] target-mips: don't flush extra TLB on permissions upgrade If the guest uses a TLBWI instruction for upgrading permissions, we don't need to flush the extra TLBs. This improve boot time performance by about 10%. Signed-off-by: Aurelien Jarno --- target-mips/op_helper.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index cdd6880efc..f45d494b14 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -1819,14 +1819,32 @@ static void r4k_fill_tlb(CPUMIPSState *env, int idx) void r4k_helper_tlbwi(CPUMIPSState *env) { + r4k_tlb_t *tlb; int idx; + target_ulong VPN; + uint8_t ASID; + bool G, V0, D0, V1, D1; idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb = &env->tlb->mmu.r4k.tlb[idx]; + VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + VPN &= env->SEGMask; +#endif + ASID = env->CP0_EntryHi & 0xff; + G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + V0 = (env->CP0_EntryLo0 & 2) != 0; + D0 = (env->CP0_EntryLo0 & 4) != 0; + V1 = (env->CP0_EntryLo1 & 2) != 0; + D1 = (env->CP0_EntryLo1 & 4) != 0; - /* Discard cached TLB entries. We could avoid doing this if the - tlbwi is just upgrading access permissions on the current entry; - that might be a further win. */ - r4k_mips_tlb_flush_extra (env, env->tlb->nb_tlb); + /* Discard cached TLB entries, unless tlbwi is just upgrading access + permissions on the current entry. */ + if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G || + (tlb->V0 && !V0) || (tlb->D0 && !D0) || + (tlb->V1 && !V1) || (tlb->D1 && !D1)) { + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + } r4k_invalidate_tlb(env, idx, 0); r4k_fill_tlb(env, idx); From e5b8b0d4ba29fe1268ba049519a1b0cf8552a21a Mon Sep 17 00:00:00 2001 From: Dmitry Fleytman Date: Fri, 19 Oct 2012 07:56:55 +0200 Subject: [PATCH 168/291] e1000: drop check_rxov, always treat RX ring with RDH == RDT as empty Real HW always treats RX ring with RDH == RDT as empty. Emulation is supposed to behave the same. Reported-by: Chris Webb Reported-by: Richard Davies Signed-off-by: Dmitry Fleytman Signed-off-by: Stefan Hajnoczi --- hw/e1000.c | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-) diff --git a/hw/e1000.c b/hw/e1000.c index e4f1ffef74..ec32f591af 100644 --- a/hw/e1000.c +++ b/hw/e1000.c @@ -92,7 +92,6 @@ typedef struct E1000State_st { uint32_t rxbuf_size; uint32_t rxbuf_min_shift; - int check_rxov; struct e1000_tx { unsigned char header[256]; unsigned char vlan_header[4]; @@ -741,11 +740,11 @@ static bool e1000_has_rxbufs(E1000State *s, size_t total_size) int bufs; /* Fast-path short packets */ if (total_size <= s->rxbuf_size) { - return s->mac_reg[RDH] != s->mac_reg[RDT] || !s->check_rxov; + return s->mac_reg[RDH] != s->mac_reg[RDT]; } if (s->mac_reg[RDH] < s->mac_reg[RDT]) { bufs = s->mac_reg[RDT] - s->mac_reg[RDH]; - } else if (s->mac_reg[RDH] > s->mac_reg[RDT] || !s->check_rxov) { + } else if (s->mac_reg[RDH] > s->mac_reg[RDT]) { bufs = s->mac_reg[RDLEN] / sizeof(struct e1000_rx_desc) + s->mac_reg[RDT] - s->mac_reg[RDH]; } else { @@ -848,7 +847,6 @@ e1000_receive(NetClientState *nc, const uint8_t *buf, size_t size) if (++s->mac_reg[RDH] * sizeof(desc) >= s->mac_reg[RDLEN]) s->mac_reg[RDH] = 0; - s->check_rxov = 1; /* see comment in start_xmit; same here */ if (s->mac_reg[RDH] == rdh_start) { DBGOUT(RXERR, "RDH wraparound @%x, RDT %x, RDLEN %x\n", @@ -925,7 +923,6 @@ mac_writereg(E1000State *s, int index, uint32_t val) static void set_rdt(E1000State *s, int index, uint32_t val) { - s->check_rxov = 0; s->mac_reg[index] = val & 0xffff; if (e1000_has_rxbufs(s, 1)) { qemu_flush_queued_packets(&s->nic->nc); From f0e3ac70341febed02591b61b579723279783053 Mon Sep 17 00:00:00 2001 From: Lei Li Date: Thu, 1 Nov 2012 17:39:55 +0800 Subject: [PATCH 169/291] net: use "socket" model name for UDP sockets Fix the problem that can not delete the udp socket. It's caused by passing "udp" model to net_socket_udp_init, but we do not have "udp" model in our model list. Pass the right model "socket" to init function. https://bugs.launchpad.net/qemu/+bug/1073585?comments=all Signed-off-by: Lei Li Signed-off-by: Stefan Hajnoczi --- net/socket.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/net/socket.c b/net/socket.c index b75d567695..c01323d4b0 100644 --- a/net/socket.c +++ b/net/socket.c @@ -747,7 +747,7 @@ int net_init_socket(const NetClientOptions *opts, const char *name, error_report("localaddr= is mandatory with udp="); return -1; } - if (net_socket_udp_init(peer, "udp", name, sock->udp, sock->localaddr) == + if (net_socket_udp_init(peer, "socket", name, sock->udp, sock->localaddr) == -1) { return -1; } From 645c9496f7083c105ecd32f32532496af6aadf62 Mon Sep 17 00:00:00 2001 From: Stefan Hajnoczi Date: Wed, 24 Oct 2012 14:34:12 +0200 Subject: [PATCH 170/291] net: Reject non-netdevs in qmp_netdev_del() The netdev_del command crashes when given a -net device, because it calls qemu_opts_del(NULL). Check that this is a -netdev before attempting to delete it and the QemuOpts. Note the subtle change from qemu_find_opts_err("netdev", errp) to qemu_find_opts_err("netdev", NULL). Since "netdev" is a built in options group and we don't check for NULL return anyway, there's no use in passing errp here. Signed-off-by: Stefan Hajnoczi --- net.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/net.c b/net.c index ae4bc0d431..e8ae13e283 100644 --- a/net.c +++ b/net.c @@ -827,6 +827,7 @@ exit_err: void qmp_netdev_del(const char *id, Error **errp) { NetClientState *nc; + QemuOpts *opts; nc = qemu_find_netdev(id); if (!nc) { @@ -834,8 +835,14 @@ void qmp_netdev_del(const char *id, Error **errp) return; } + opts = qemu_opts_find(qemu_find_opts_err("netdev", NULL), id); + if (!opts) { + error_setg(errp, "Device '%s' is not a netdev", id); + return; + } + qemu_del_net_client(nc); - qemu_opts_del(qemu_opts_find(qemu_find_opts_err("netdev", errp), id)); + qemu_opts_del(opts); } void print_net_client(Monitor *mon, NetClientState *nc) From 372254c6e5c078fb13b236bb648d2b9b2b0c70f1 Mon Sep 17 00:00:00 2001 From: "Gabriel L. Somlo" Date: Wed, 31 Oct 2012 14:15:39 -0400 Subject: [PATCH 171/291] e1000: pre-initialize RAH/RAL registers Some guest operating systems' drivers (Mac OS X in particular) fail to properly initialize the Receive Address registers (probably expecting them to be pre-initialized by an earlier component, such as a specific proprietary BIOS). This patch pre-initializes the RA registers, allowing OS X networking to function properly. Other guest operating systems are not affected, and free to (re)initialize these registers during boot. [According to the datasheet the Address Valid bits in the RA registers are cleared on PCI or software reset. This patch adds the NIC's MAC address and sets Address Valid on reset. So we diverge from real hardware behavior here. -- Stefan] Signed-off-by: Gabriel Somlo Signed-off-by: Stefan Hajnoczi --- hw/e1000.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/e1000.c b/hw/e1000.c index ec32f591af..cb7e7e8366 100644 --- a/hw/e1000.c +++ b/hw/e1000.c @@ -265,6 +265,8 @@ rxbufsize(uint32_t v) static void e1000_reset(void *opaque) { E1000State *d = opaque; + uint8_t *macaddr = d->conf.macaddr.a; + int i; qemu_del_timer(d->autoneg_timer); memset(d->phy_reg, 0, sizeof d->phy_reg); @@ -277,6 +279,14 @@ static void e1000_reset(void *opaque) if (d->nic->nc.link_down) { e1000_link_down(d); } + + /* Some guests expect pre-initialized RAH/RAL (AddrValid flag + MACaddr) */ + d->mac_reg[RA] = 0; + d->mac_reg[RA + 1] = E1000_RAH_AV; + for (i = 0; i < 4; i++) { + d->mac_reg[RA] |= macaddr[i] << (8 * i); + d->mac_reg[RA + 1] |= (i < 2) ? macaddr[i + 4] << (8 * i) : 0; + } } static void From a3cfa18eb075c7ef78358ca1956fe7b01caa1724 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 29 Oct 2012 17:24:57 +0000 Subject: [PATCH 172/291] Revert "PPC: pseries: Remove hack for PIO window" This reverts commit a178274efabcbbc5d44805b51def874e47051325. Contrary to that commit's message, the users of old_portio are not all gone. In particular VGA still uses it via portio_list_add(). Signed-off-by: David Gibson Signed-off-by: Alexander Graf --- hw/spapr_pci.c | 44 +++++++++++++++++++++++++++++++++++++++++++- hw/spapr_pci.h | 2 +- 2 files changed, 44 insertions(+), 2 deletions(-) diff --git a/hw/spapr_pci.c b/hw/spapr_pci.c index c2c3079d21..a08ed11166 100644 --- a/hw/spapr_pci.c +++ b/hw/spapr_pci.c @@ -439,6 +439,43 @@ static void pci_spapr_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(spapr_phb_lsi_qirq(phb, irq_num), level); } +static uint64_t spapr_io_read(void *opaque, hwaddr addr, + unsigned size) +{ + switch (size) { + case 1: + return cpu_inb(addr); + case 2: + return cpu_inw(addr); + case 4: + return cpu_inl(addr); + } + assert(0); +} + +static void spapr_io_write(void *opaque, hwaddr addr, + uint64_t data, unsigned size) +{ + switch (size) { + case 1: + cpu_outb(addr, data); + return; + case 2: + cpu_outw(addr, data); + return; + case 4: + cpu_outl(addr, data); + return; + } + assert(0); +} + +static const MemoryRegionOps spapr_io_ops = { + .endianness = DEVICE_LITTLE_ENDIAN, + .read = spapr_io_read, + .write = spapr_io_write +}; + /* * MSI/MSIX memory region implementation. * The handler handles both MSI and MSIX. @@ -508,9 +545,14 @@ static int spapr_phb_init(SysBusDevice *s) * old_portion are updated */ sprintf(namebuf, "%s.io", sphb->dtbusname); memory_region_init(&sphb->iospace, namebuf, SPAPR_PCI_IO_WIN_SIZE); + /* FIXME: fix to support multiple PHBs */ + memory_region_add_subregion(get_system_io(), 0, &sphb->iospace); + sprintf(namebuf, "%s.io-alias", sphb->dtbusname); + memory_region_init_io(&sphb->iowindow, &spapr_io_ops, sphb, + namebuf, SPAPR_PCI_IO_WIN_SIZE); memory_region_add_subregion(get_system_memory(), sphb->io_win_addr, - &sphb->iospace); + &sphb->iowindow); /* As MSI/MSIX interrupts trigger by writing at MSI/MSIX vectors, * we need to allocate some memory to catch those writes coming diff --git a/hw/spapr_pci.h b/hw/spapr_pci.h index a77d7d5448..e307ac8035 100644 --- a/hw/spapr_pci.h +++ b/hw/spapr_pci.h @@ -44,7 +44,7 @@ typedef struct sPAPRPHBState { MemoryRegion memspace, iospace; hwaddr mem_win_addr, mem_win_size, io_win_addr, io_win_size; hwaddr msi_win_addr; - MemoryRegion memwindow, msiwindow; + MemoryRegion memwindow, iowindow, msiwindow; uint32_t dma_liobn; uint64_t dma_window_start; From ac7d12ba256b7c9d4e122d0d6877e2312d6c19ed Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 29 Oct 2012 17:24:58 +0000 Subject: [PATCH 173/291] target-ppc: Rework storage of VPA registration state We change the storage of the VPA information to explicitly use fixed size integer types which will make life easier for syncing this data with KVM, which we will need in future. Signed-off-by: David Gibson [agraf: fix commit message] Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 286f42a808..e603d9f936 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1045,9 +1045,9 @@ struct CPUPPCState { #endif #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) - hwaddr vpa_addr; - hwaddr slb_shadow_addr, slb_shadow_size; - hwaddr dtl_addr, dtl_size; + uint64_t vpa_addr; + uint64_t slb_shadow_addr, slb_shadow_size; + uint64_t dtl_addr, dtl_size; #endif /* TARGET_PPC64 */ int error_code; From 3030442054e04b2538016920f0da6e94743f48be Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 29 Oct 2012 17:24:59 +0000 Subject: [PATCH 174/291] target-ppc: Extend FPU state for newer POWER CPUs This patch adds some extra FPU state to CPUPPCState. Specifically, fpscr is extended to a target_ulong bits, since some recent (64 bit) CPUs now have more status bits than fit inside 32 bits. Also, we add the 32 VSR registers present on CPUs with VSX (these extend the standard FP regs, which together with the Altivec/VMX registers form a 64 x 128bit register file for VSX). We don't actually support the instructions using these extra registers in TCG yet, but we still need a place to store the state so we can sync it with KVM and savevm/loadvm it. This patch updates the savevm code to not fail on the extended state, but also does not actually save it - that's a project for another patch. Signed-off-by: David Gibson Signed-off-by: Alexander Graf --- target-ppc/cpu.h | 4 +++- target-ppc/machine.c | 8 ++++++-- target-ppc/translate.c | 29 ++++++++++++++++++----------- 3 files changed, 27 insertions(+), 14 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index e603d9f936..380a8d2926 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -963,7 +963,7 @@ struct CPUPPCState { /* floating point registers */ float64 fpr[32]; /* floating point status and control register */ - uint32_t fpscr; + target_ulong fpscr; /* Next instruction pointer */ target_ulong nip; @@ -1014,6 +1014,8 @@ struct CPUPPCState { /* Altivec registers */ ppc_avr_t avr[32]; uint32_t vscr; + /* VSX registers */ + uint64_t vsr[32]; /* SPE registers */ uint64_t spe_acc; uint32_t spe_fscr; diff --git a/target-ppc/machine.c b/target-ppc/machine.c index 21ce7575e3..5e7bc00e26 100644 --- a/target-ppc/machine.c +++ b/target-ppc/machine.c @@ -6,6 +6,7 @@ void cpu_save(QEMUFile *f, void *opaque) { CPUPPCState *env = (CPUPPCState *)opaque; unsigned int i, j; + uint32_t fpscr; for (i = 0; i < 32; i++) qemu_put_betls(f, &env->gpr[i]); @@ -30,7 +31,8 @@ void cpu_save(QEMUFile *f, void *opaque) u.d = env->fpr[i]; qemu_put_be64(f, u.l); } - qemu_put_be32s(f, &env->fpscr); + fpscr = env->fpscr; + qemu_put_be32s(f, &fpscr); qemu_put_sbe32s(f, &env->access_type); #if defined(TARGET_PPC64) qemu_put_betls(f, &env->asr); @@ -90,6 +92,7 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) CPUPPCState *env = (CPUPPCState *)opaque; unsigned int i, j; target_ulong sdr1; + uint32_t fpscr; for (i = 0; i < 32; i++) qemu_get_betls(f, &env->gpr[i]); @@ -114,7 +117,8 @@ int cpu_load(QEMUFile *f, void *opaque, int version_id) u.l = qemu_get_be64(f); env->fpr[i] = u.d; } - qemu_get_be32s(f, &env->fpscr); + qemu_get_be32s(f, &fpscr); + env->fpscr = fpscr; qemu_get_sbe32s(f, &env->access_type); #if defined(TARGET_PPC64) qemu_get_betls(f, &env->asr); diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 1042268ecf..56725e6a61 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -68,7 +68,7 @@ static TCGv cpu_cfar; #endif static TCGv cpu_xer; static TCGv cpu_reserve; -static TCGv_i32 cpu_fpscr; +static TCGv cpu_fpscr; static TCGv_i32 cpu_access_type; #include "gen-icount.h" @@ -163,8 +163,8 @@ void ppc_translate_init(void) offsetof(CPUPPCState, reserve_addr), "reserve_addr"); - cpu_fpscr = tcg_global_mem_new_i32(TCG_AREG0, - offsetof(CPUPPCState, fpscr), "fpscr"); + cpu_fpscr = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUPPCState, fpscr), "fpscr"); cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0, offsetof(CPUPPCState, access_type), "access_type"); @@ -2302,6 +2302,7 @@ GEN_FLOAT_B(neg, 0x08, 0x01, 0, PPC_FLOAT); /* mcrfs */ static void gen_mcrfs(DisasContext *ctx) { + TCGv tmp = tcg_temp_new(); int bfa; if (unlikely(!ctx->fpu_enabled)) { @@ -2309,9 +2310,11 @@ static void gen_mcrfs(DisasContext *ctx) return; } bfa = 4 * (7 - crfS(ctx->opcode)); - tcg_gen_shri_i32(cpu_crf[crfD(ctx->opcode)], cpu_fpscr, bfa); + tcg_gen_shri_tl(tmp, cpu_fpscr, bfa); + tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp); + tcg_temp_free(tmp); tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf); - tcg_gen_andi_i32(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); + tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa)); } /* mffs */ @@ -2322,7 +2325,7 @@ static void gen_mffs(DisasContext *ctx) return; } gen_reset_fpstatus(); - tcg_gen_extu_i32_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); + tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr); gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0); } @@ -2346,7 +2349,8 @@ static void gen_mtfsb0(DisasContext *ctx) tcg_temp_free_i32(t0); } if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); + tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } } @@ -2371,7 +2375,8 @@ static void gen_mtfsb1(DisasContext *ctx) tcg_temp_free_i32(t0); } if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); + tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a differed exception */ gen_helper_float_check_status(cpu_env); @@ -2397,7 +2402,8 @@ static void gen_mtfsf(DisasContext *ctx) gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0); tcg_temp_free_i32(t0); if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); + tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a differed exception */ gen_helper_float_check_status(cpu_env); @@ -2425,7 +2431,8 @@ static void gen_mtfsfi(DisasContext *ctx) tcg_temp_free_i64(t0); tcg_temp_free_i32(t1); if (unlikely(Rc(ctx->opcode) != 0)) { - tcg_gen_shri_i32(cpu_crf[1], cpu_fpscr, FPSCR_OX); + tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr); + tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX); } /* We can raise a differed exception */ gen_helper_float_check_status(cpu_env); @@ -9463,7 +9470,7 @@ void cpu_dump_state (CPUPPCState *env, FILE *f, fprintf_function cpu_fprintf, if ((i & (RFPL - 1)) == (RFPL - 1)) cpu_fprintf(f, "\n"); } - cpu_fprintf(f, "FPSCR %08x\n", env->fpscr); + cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); #if !defined(CONFIG_USER_ONLY) cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", From bf0175de6c76779d4c8b0606de7bd2a5a0b87c7a Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 29 Oct 2012 17:25:00 +0000 Subject: [PATCH 175/291] pseries: Clean up inconsistent variable name in xics.c Throughout xics.c 'nr' is used to refer to a global interrupt number, and 'server' is used to refer to an interrupt server number (i.e. CPU number). Except in icp_set_mfrr(), where 'nr' is used as a server number. Fix this confusing inconsistency. Signed-off-by: David Gibson Signed-off-by: Alexander Graf --- hw/xics.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/xics.c b/hw/xics.c index ce88aa750b..7a899dd44f 100644 --- a/hw/xics.c +++ b/hw/xics.c @@ -108,13 +108,13 @@ static void icp_set_cppr(struct icp_state *icp, int server, uint8_t cppr) } } -static void icp_set_mfrr(struct icp_state *icp, int nr, uint8_t mfrr) +static void icp_set_mfrr(struct icp_state *icp, int server, uint8_t mfrr) { - struct icp_server_state *ss = icp->ss + nr; + struct icp_server_state *ss = icp->ss + server; ss->mfrr = mfrr; if (mfrr < CPPR(ss)) { - icp_check_ipi(icp, nr); + icp_check_ipi(icp, server); } } From 1ecbbab46925d4810fc35aba45cf93cb80ff0734 Mon Sep 17 00:00:00 2001 From: David Gibson Date: Mon, 29 Oct 2012 17:25:02 +0000 Subject: [PATCH 176/291] pseries: Cleanup duplications of ics_valid_irq() code A couple of places in xics.c open-coded the same logic as is already implemented in ics_valid_irq(). This patch fixes the code duplication. Signed-off-by: David Gibson Signed-off-by: Alexander Graf --- hw/xics.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/xics.c b/hw/xics.c index 7a899dd44f..ff4b5e210f 100644 --- a/hw/xics.c +++ b/hw/xics.c @@ -326,8 +326,7 @@ static void ics_eoi(struct ics_state *ics, int nr) qemu_irq xics_get_qirq(struct icp_state *icp, int irq) { - if ((irq < icp->ics->offset) - || (irq >= (icp->ics->offset + icp->ics->nr_irqs))) { + if (!ics_valid_irq(icp->ics, irq)) { return NULL; } @@ -336,8 +335,7 @@ qemu_irq xics_get_qirq(struct icp_state *icp, int irq) void xics_set_irq_type(struct icp_state *icp, int irq, bool lsi) { - assert((irq >= icp->ics->offset) - && (irq < (icp->ics->offset + icp->ics->nr_irqs))); + assert(ics_valid_irq(icp->ics, irq)); icp->ics->irqs[irq - icp->ics->offset].lsi = lsi; } From 87e487a14bd9f3fb4a2b27179377e011bdda7c51 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 4 Jun 2010 11:46:35 +0200 Subject: [PATCH 177/291] console: QLIST-ify display change listeners. Signed-off-by: Gerd Hoffmann --- console.h | 72 ++++++++++++++++++++++++++++-------------------------- hw/xenfb.c | 2 +- vl.c | 9 +++---- 3 files changed, 42 insertions(+), 41 deletions(-) diff --git a/console.h b/console.h index 6099d8d710..4239eb346c 100644 --- a/console.h +++ b/console.h @@ -164,7 +164,7 @@ struct DisplayChangeListener { int w, int h, uint32_t c); void (*dpy_text_cursor)(struct DisplayState *s, int x, int y); - struct DisplayChangeListener *next; + QLIST_ENTRY(DisplayChangeListener) next; }; struct DisplayAllocator { @@ -179,7 +179,7 @@ struct DisplayState { struct QEMUTimer *gui_timer; struct DisplayAllocator* allocator; - struct DisplayChangeListener* listeners; + QLIST_HEAD(, DisplayChangeListener) listeners; void (*mouse_set)(int x, int y, int on); void (*cursor_define)(QEMUCursor *cursor); @@ -231,72 +231,76 @@ static inline int is_buffer_shared(DisplaySurface *surface) static inline void register_displaychangelistener(DisplayState *ds, DisplayChangeListener *dcl) { - dcl->next = ds->listeners; - ds->listeners = dcl; + QLIST_INSERT_HEAD(&ds->listeners, dcl, next); } static inline void dpy_update(DisplayState *s, int x, int y, int w, int h) { - struct DisplayChangeListener *dcl = s->listeners; - while (dcl != NULL) { + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { dcl->dpy_update(s, x, y, w, h); - dcl = dcl->next; } } static inline void dpy_resize(DisplayState *s) { - struct DisplayChangeListener *dcl = s->listeners; - while (dcl != NULL) { + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { dcl->dpy_resize(s); - dcl = dcl->next; } } static inline void dpy_setdata(DisplayState *s) { - struct DisplayChangeListener *dcl = s->listeners; - while (dcl != NULL) { - if (dcl->dpy_setdata) dcl->dpy_setdata(s); - dcl = dcl->next; + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { + if (dcl->dpy_setdata) { + dcl->dpy_setdata(s); + } } } static inline void dpy_refresh(DisplayState *s) { - struct DisplayChangeListener *dcl = s->listeners; - while (dcl != NULL) { - if (dcl->dpy_refresh) dcl->dpy_refresh(s); - dcl = dcl->next; + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { + if (dcl->dpy_refresh) { + dcl->dpy_refresh(s); + } } } static inline void dpy_copy(struct DisplayState *s, int src_x, int src_y, - int dst_x, int dst_y, int w, int h) { - struct DisplayChangeListener *dcl = s->listeners; - while (dcl != NULL) { - if (dcl->dpy_copy) + int dst_x, int dst_y, int w, int h) +{ + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { + if (dcl->dpy_copy) { dcl->dpy_copy(s, src_x, src_y, dst_x, dst_y, w, h); - else /* TODO */ + } else { /* TODO */ dcl->dpy_update(s, dst_x, dst_y, w, h); - dcl = dcl->next; + } } } static inline void dpy_fill(struct DisplayState *s, int x, int y, - int w, int h, uint32_t c) { - struct DisplayChangeListener *dcl = s->listeners; - while (dcl != NULL) { - if (dcl->dpy_fill) dcl->dpy_fill(s, x, y, w, h, c); - dcl = dcl->next; + int w, int h, uint32_t c) +{ + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { + if (dcl->dpy_fill) { + dcl->dpy_fill(s, x, y, w, h, c); + } } } -static inline void dpy_cursor(struct DisplayState *s, int x, int y) { - struct DisplayChangeListener *dcl = s->listeners; - while (dcl != NULL) { - if (dcl->dpy_text_cursor) dcl->dpy_text_cursor(s, x, y); - dcl = dcl->next; +static inline void dpy_cursor(struct DisplayState *s, int x, int y) +{ + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { + if (dcl->dpy_text_cursor) { + dcl->dpy_text_cursor(s, x, y); + } } } diff --git a/hw/xenfb.c b/hw/xenfb.c index 338800a4d9..ef24c3315c 100644 --- a/hw/xenfb.c +++ b/hw/xenfb.c @@ -717,7 +717,7 @@ static void xenfb_update(void *opaque) if (xenfb_queue_full(xenfb)) return; - for (l = xenfb->c.ds->listeners; l != NULL; l = l->next) { + QLIST_FOREACH(l, &xenfb->c.ds->listeners, next) { if (l->idle) continue; idle = 0; diff --git a/vl.c b/vl.c index 5513d1518e..427e8a2d40 100644 --- a/vl.c +++ b/vl.c @@ -1359,15 +1359,14 @@ static void gui_update(void *opaque) { uint64_t interval = GUI_REFRESH_INTERVAL; DisplayState *ds = opaque; - DisplayChangeListener *dcl = ds->listeners; + DisplayChangeListener *dcl; dpy_refresh(ds); - while (dcl != NULL) { + QLIST_FOREACH(dcl, &ds->listeners, next) { if (dcl->gui_timer_interval && dcl->gui_timer_interval < interval) interval = dcl->gui_timer_interval; - dcl = dcl->next; } qemu_mod_timer(ds->gui_timer, interval + qemu_get_clock_ms(rt_clock)); } @@ -3846,14 +3845,12 @@ int main(int argc, char **argv, char **envp) /* display setup */ dpy_resize(ds); - dcl = ds->listeners; - while (dcl != NULL) { + QLIST_FOREACH(dcl, &ds->listeners, next) { if (dcl->dpy_refresh != NULL) { ds->gui_timer = qemu_new_timer_ms(rt_clock, gui_update, ds); qemu_mod_timer(ds->gui_timer, qemu_get_clock_ms(rt_clock)); break; } - dcl = dcl->next; } text_consoles_set_display(ds); From 35c9e0a5c2804b94d1a452a0a9a12d7a893b5318 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 4 Jun 2010 11:51:31 +0200 Subject: [PATCH 178/291] console: add unregister_displaychangelistener Also change the way the gui_timer is initialized: each time a displaychangelistener is registered or unregistered we'll check whether we need a timer (due to dpy_refresh callback being present) and if so setup a timer, otherwise zap it. This way the gui timer works correctly with displaychangelisteners coming and going. Signed-off-by: Gerd Hoffmann --- console.h | 10 ++++++++++ vl.c | 31 +++++++++++++++++++++++-------- 2 files changed, 33 insertions(+), 8 deletions(-) diff --git a/console.h b/console.h index 4239eb346c..f476ac810d 100644 --- a/console.h +++ b/console.h @@ -229,9 +229,19 @@ static inline int is_buffer_shared(DisplaySurface *surface) !(surface->flags & QEMU_REALPIXELS_FLAG)); } +void gui_setup_refresh(DisplayState *ds); + static inline void register_displaychangelistener(DisplayState *ds, DisplayChangeListener *dcl) { QLIST_INSERT_HEAD(&ds->listeners, dcl, next); + gui_setup_refresh(ds); +} + +static inline void unregister_displaychangelistener(DisplayState *ds, + DisplayChangeListener *dcl) +{ + QLIST_REMOVE(dcl, next); + gui_setup_refresh(ds); } static inline void dpy_update(DisplayState *s, int x, int y, int w, int h) diff --git a/vl.c b/vl.c index 427e8a2d40..4c45b02f05 100644 --- a/vl.c +++ b/vl.c @@ -1371,6 +1371,29 @@ static void gui_update(void *opaque) qemu_mod_timer(ds->gui_timer, interval + qemu_get_clock_ms(rt_clock)); } +void gui_setup_refresh(DisplayState *ds) +{ + DisplayChangeListener *dcl; + bool need_timer = false; + + QLIST_FOREACH(dcl, &ds->listeners, next) { + if (dcl->dpy_refresh != NULL) { + need_timer = true; + break; + } + } + + if (need_timer && ds->gui_timer == NULL) { + ds->gui_timer = qemu_new_timer_ms(rt_clock, gui_update, ds); + qemu_mod_timer(ds->gui_timer, qemu_get_clock_ms(rt_clock)); + } + if (!need_timer && ds->gui_timer != NULL) { + qemu_del_timer(ds->gui_timer); + qemu_free_timer(ds->gui_timer); + ds->gui_timer = NULL; + } +} + struct vm_change_state_entry { VMChangeStateHandler *cb; void *opaque; @@ -2454,7 +2477,6 @@ int main(int argc, char **argv, char **envp) const char *kernel_filename, *kernel_cmdline; char boot_devices[33] = "cad"; /* default to HD->floppy->CD-ROM */ DisplayState *ds; - DisplayChangeListener *dcl; int cyls, heads, secs, translation; QemuOpts *hda_opts = NULL, *opts, *machine_opts; QemuOptsList *olist; @@ -3845,13 +3867,6 @@ int main(int argc, char **argv, char **envp) /* display setup */ dpy_resize(ds); - QLIST_FOREACH(dcl, &ds->listeners, next) { - if (dcl->dpy_refresh != NULL) { - ds->gui_timer = qemu_new_timer_ms(rt_clock, gui_update, ds); - qemu_mod_timer(ds->gui_timer, qemu_get_clock_ms(rt_clock)); - break; - } - } text_consoles_set_display(ds); if (foreach_device_config(DEV_GDB, gdbserver_start) < 0) { From bf2fde70fea6b3245dab44253deafba95f2979e5 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 12 Sep 2012 07:56:45 +0200 Subject: [PATCH 179/291] console: move set_mouse + cursor_define callbacks When adding DisplayChangeListeners the set_mouse and cursor_define callbacks have been left in DisplayState for some reason. Fix it. Signed-off-by: Gerd Hoffmann --- console.c | 2 +- console.h | 39 +++++++++++++++++++++++++++++++++++---- hw/jazz_led.c | 2 +- hw/qxl-render.c | 2 +- hw/vga.c | 10 +++++----- hw/vmware_vga.c | 11 ++++++----- ui/sdl.c | 8 ++++---- ui/spice-display.c | 4 ++-- ui/vnc.c | 8 ++++---- 9 files changed, 59 insertions(+), 27 deletions(-) diff --git a/console.c b/console.c index 3f3d2547bf..260a029246 100644 --- a/console.c +++ b/console.c @@ -1242,7 +1242,7 @@ static void text_console_update(void *opaque, console_ch_t *chardata) s->text_y[1] = 0; } if (s->cursor_invalidate) { - dpy_cursor(s->ds, s->x, s->y); + dpy_text_cursor(s->ds, s->x, s->y); s->cursor_invalidate = 0; } } diff --git a/console.h b/console.h index f476ac810d..fb38ce9060 100644 --- a/console.h +++ b/console.h @@ -164,6 +164,9 @@ struct DisplayChangeListener { int w, int h, uint32_t c); void (*dpy_text_cursor)(struct DisplayState *s, int x, int y); + void (*dpy_mouse_set)(struct DisplayState *s, int x, int y, int on); + void (*dpy_cursor_define)(struct DisplayState *s, QEMUCursor *cursor); + QLIST_ENTRY(DisplayChangeListener) next; }; @@ -181,9 +184,6 @@ struct DisplayState { struct DisplayAllocator* allocator; QLIST_HEAD(, DisplayChangeListener) listeners; - void (*mouse_set)(int x, int y, int on); - void (*cursor_define)(QEMUCursor *cursor); - struct DisplayState *next; }; @@ -304,7 +304,7 @@ static inline void dpy_fill(struct DisplayState *s, int x, int y, } } -static inline void dpy_cursor(struct DisplayState *s, int x, int y) +static inline void dpy_text_cursor(struct DisplayState *s, int x, int y) { struct DisplayChangeListener *dcl; QLIST_FOREACH(dcl, &s->listeners, next) { @@ -314,6 +314,37 @@ static inline void dpy_cursor(struct DisplayState *s, int x, int y) } } +static inline void dpy_mouse_set(struct DisplayState *s, int x, int y, int on) +{ + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { + if (dcl->dpy_mouse_set) { + dcl->dpy_mouse_set(s, x, y, on); + } + } +} + +static inline void dpy_cursor_define(struct DisplayState *s, QEMUCursor *cursor) +{ + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { + if (dcl->dpy_cursor_define) { + dcl->dpy_cursor_define(s, cursor); + } + } +} + +static inline bool dpy_cursor_define_supported(struct DisplayState *s) +{ + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { + if (dcl->dpy_cursor_define) { + return true; + } + } + return false; +} + static inline int ds_get_linesize(DisplayState *ds) { return ds->surface->linesize; diff --git a/hw/jazz_led.c b/hw/jazz_led.c index a6a90ab283..853bf6d4c1 100644 --- a/hw/jazz_led.c +++ b/hw/jazz_led.c @@ -210,7 +210,7 @@ static void jazz_led_text_update(void *opaque, console_ch_t *chardata) LedState *s = opaque; char buf[2]; - dpy_cursor(s->ds, -1, -1); + dpy_text_cursor(s->ds, -1, -1); qemu_console_resize(s->ds, 2, 1); /* TODO: draw the segments */ diff --git a/hw/qxl-render.c b/hw/qxl-render.c index b66c168ef6..e8cf29e62a 100644 --- a/hw/qxl-render.c +++ b/hw/qxl-render.c @@ -234,7 +234,7 @@ int qxl_render_cursor(PCIQXLDevice *qxl, QXLCommandExt *ext) return 1; } - if (!qxl->ssd.ds->mouse_set || !qxl->ssd.ds->cursor_define) { + if (!dpy_cursor_define_supported(qxl->ssd.ds)) { return 0; } diff --git a/hw/vga.c b/hw/vga.c index e4220df25e..f3256cb6c7 100644 --- a/hw/vga.c +++ b/hw/vga.c @@ -2070,11 +2070,11 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) { cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20); if (cursor_visible && cursor_offset < size && cursor_offset >= 0) - dpy_cursor(s->ds, - TEXTMODE_X(cursor_offset), - TEXTMODE_Y(cursor_offset)); + dpy_text_cursor(s->ds, + TEXTMODE_X(cursor_offset), + TEXTMODE_Y(cursor_offset)); else - dpy_cursor(s->ds, -1, -1); + dpy_text_cursor(s->ds, -1, -1); s->cursor_offset = cursor_offset; s->cursor_start = s->cr[VGA_CRTC_CURSOR_START]; s->cursor_end = s->cr[VGA_CRTC_CURSOR_END]; @@ -2135,7 +2135,7 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) /* Display a message */ s->last_width = 60; s->last_height = height = 3; - dpy_cursor(s->ds, -1, -1); + dpy_text_cursor(s->ds, -1, -1); s->ds->surface->width = s->last_width; s->ds->surface->height = height; dpy_resize(s->ds); diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index badaf7cef4..dc9279064c 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -478,8 +478,7 @@ static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, qc = cursor_builtin_left_ptr(); } - if (s->vga.ds->cursor_define) - s->vga.ds->cursor_define(qc); + dpy_cursor_define(s->vga.ds, qc); cursor_put(qc); } #endif @@ -754,9 +753,10 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) caps |= SVGA_CAP_RECT_FILL; #endif #ifdef HW_MOUSE_ACCEL - if (s->vga.ds->mouse_set) + if (dpy_cursor_define_supported(s->vga.ds)) { caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 | SVGA_CAP_CURSOR_BYPASS; + } #endif return caps; @@ -903,8 +903,9 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW); s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE); #ifdef HW_MOUSE_ACCEL - if (s->vga.ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW) - s->vga.ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on); + if (value <= SVGA_CURSOR_ON_SHOW) { + dpy_mouse_set(s->vga.ds, s->cursor.x, s->cursor.y, s->cursor.on); + } #endif break; diff --git a/ui/sdl.c b/ui/sdl.c index f6f711c1bb..f8ead930ae 100644 --- a/ui/sdl.c +++ b/ui/sdl.c @@ -905,7 +905,7 @@ static void sdl_fill(DisplayState *ds, int x, int y, int w, int h, uint32_t c) SDL_FillRect(real_screen, &dst, c); } -static void sdl_mouse_warp(int x, int y, int on) +static void sdl_mouse_warp(DisplayState *ds, int x, int y, int on) { if (on) { if (!guest_cursor) @@ -921,7 +921,7 @@ static void sdl_mouse_warp(int x, int y, int on) guest_x = x, guest_y = y; } -static void sdl_mouse_define(QEMUCursor *c) +static void sdl_mouse_define(DisplayState *ds, QEMUCursor *c) { uint8_t *image, *mask; int bpl; @@ -1025,8 +1025,8 @@ void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) dcl->dpy_refresh = sdl_refresh; dcl->dpy_setdata = sdl_setdata; dcl->dpy_fill = sdl_fill; - ds->mouse_set = sdl_mouse_warp; - ds->cursor_define = sdl_mouse_define; + dcl->dpy_mouse_set = sdl_mouse_warp; + dcl->dpy_cursor_define = sdl_mouse_define; register_displaychangelistener(ds, dcl); da = g_malloc0(sizeof(DisplayAllocator)); diff --git a/ui/spice-display.c b/ui/spice-display.c index b61764f381..5779fa8ba6 100644 --- a/ui/spice-display.c +++ b/ui/spice-display.c @@ -404,12 +404,12 @@ void qemu_spice_display_resize(SimpleSpiceDisplay *ssd) void qemu_spice_cursor_refresh_unlocked(SimpleSpiceDisplay *ssd) { if (ssd->cursor) { - ssd->ds->cursor_define(ssd->cursor); + dpy_cursor_define(ssd->ds, ssd->cursor); cursor_put(ssd->cursor); ssd->cursor = NULL; } if (ssd->mouse_x != -1 && ssd->mouse_y != -1) { - ssd->ds->mouse_set(ssd->mouse_x, ssd->mouse_y, 1); + dpy_mouse_set(ssd->ds, ssd->mouse_x, ssd->mouse_y, 1); ssd->mouse_x = -1; ssd->mouse_y = -1; } diff --git a/ui/vnc.c b/ui/vnc.c index d0ffcc54af..1b70db7e05 100644 --- a/ui/vnc.c +++ b/ui/vnc.c @@ -802,7 +802,7 @@ static void vnc_dpy_copy(DisplayState *ds, int src_x, int src_y, int dst_x, int } } -static void vnc_mouse_set(int x, int y, int visible) +static void vnc_mouse_set(DisplayState *ds, int x, int y, int visible) { /* can we ask the client(s) to move the pointer ??? */ } @@ -829,7 +829,7 @@ static int vnc_cursor_define(VncState *vs) return -1; } -static void vnc_dpy_cursor_define(QEMUCursor *c) +static void vnc_dpy_cursor_define(DisplayState *ds, QEMUCursor *c) { VncDisplay *vd = vnc_display; VncState *vs; @@ -2757,9 +2757,9 @@ void vnc_display_init(DisplayState *ds) dcl->dpy_update = vnc_dpy_update; dcl->dpy_resize = vnc_dpy_resize; dcl->dpy_setdata = vnc_dpy_setdata; + dcl->dpy_mouse_set = vnc_mouse_set; + dcl->dpy_cursor_define = vnc_dpy_cursor_define; register_displaychangelistener(ds, dcl); - ds->mouse_set = vnc_mouse_set; - ds->cursor_define = vnc_dpy_cursor_define; } From 76ffb0b4d048aac18b54f8555c60b6d3b0e2bc37 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 28 Sep 2012 13:24:17 +0200 Subject: [PATCH 180/291] console: s/TextConsole/QemuConsole/ Signed-off-by: Gerd Hoffmann --- console.c | 72 +++++++++++++++++++++++++-------------------------- qemu-common.h | 3 +-- 2 files changed, 37 insertions(+), 38 deletions(-) diff --git a/console.c b/console.c index 260a029246..b53dc1b6f3 100644 --- a/console.c +++ b/console.c @@ -114,20 +114,20 @@ typedef enum { TEXT_CONSOLE_FIXED_SIZE } console_type_t; -/* ??? This is mis-named. - It is used for both text and graphical consoles. */ -struct TextConsole { +struct QemuConsole { int index; console_type_t console_type; DisplayState *ds; + /* Graphic console state. */ vga_hw_update_ptr hw_update; vga_hw_invalidate_ptr hw_invalidate; vga_hw_screen_dump_ptr hw_screen_dump; vga_hw_text_update_ptr hw_text_update; void *hw; - int g_width, g_height; + + /* Text console state */ int width; int height; int total_height; @@ -161,8 +161,8 @@ struct TextConsole { }; static DisplayState *display_state; -static TextConsole *active_console; -static TextConsole *consoles[MAX_CONSOLES]; +static QemuConsole *active_console; +static QemuConsole *consoles[MAX_CONSOLES]; static int nb_consoles = 0; void vga_hw_update(void) @@ -179,7 +179,7 @@ void vga_hw_invalidate(void) void qmp_screendump(const char *filename, Error **errp) { - TextConsole *previous_active_console; + QemuConsole *previous_active_console; bool cswitch; previous_active_console = active_console; @@ -521,7 +521,7 @@ static void vga_putcharxy(DisplayState *ds, int x, int y, int ch, } } -static void text_console_resize(TextConsole *s) +static void text_console_resize(QemuConsole *s) { TextCell *cells, *c, *c1; int w1, x, y, last_width; @@ -553,7 +553,7 @@ static void text_console_resize(TextConsole *s) s->cells = cells; } -static inline void text_update_xy(TextConsole *s, int x, int y) +static inline void text_update_xy(QemuConsole *s, int x, int y) { s->text_x[0] = MIN(s->text_x[0], x); s->text_x[1] = MAX(s->text_x[1], x); @@ -561,7 +561,7 @@ static inline void text_update_xy(TextConsole *s, int x, int y) s->text_y[1] = MAX(s->text_y[1], y); } -static void invalidate_xy(TextConsole *s, int x, int y) +static void invalidate_xy(QemuConsole *s, int x, int y) { if (s->update_x0 > x * FONT_WIDTH) s->update_x0 = x * FONT_WIDTH; @@ -573,7 +573,7 @@ static void invalidate_xy(TextConsole *s, int x, int y) s->update_y1 = (y + 1) * FONT_HEIGHT; } -static void update_xy(TextConsole *s, int x, int y) +static void update_xy(QemuConsole *s, int x, int y) { TextCell *c; int y1, y2; @@ -597,7 +597,7 @@ static void update_xy(TextConsole *s, int x, int y) } } -static void console_show_cursor(TextConsole *s, int show) +static void console_show_cursor(QemuConsole *s, int show) { TextCell *c; int y, y1; @@ -631,7 +631,7 @@ static void console_show_cursor(TextConsole *s, int show) } } -static void console_refresh(TextConsole *s) +static void console_refresh(QemuConsole *s) { TextCell *c; int x, y, y1; @@ -666,7 +666,7 @@ static void console_refresh(TextConsole *s) static void console_scroll(int ydelta) { - TextConsole *s; + QemuConsole *s; int i, y1; s = active_console; @@ -698,7 +698,7 @@ static void console_scroll(int ydelta) console_refresh(s); } -static void console_put_lf(TextConsole *s) +static void console_put_lf(QemuConsole *s) { TextCell *c; int x, y1; @@ -749,7 +749,7 @@ static void console_put_lf(TextConsole *s) * NOTE: I know this code is not very efficient (checking every color for it * self) but it is more readable and better maintainable. */ -static void console_handle_escape(TextConsole *s) +static void console_handle_escape(QemuConsole *s) { int i; @@ -842,7 +842,7 @@ static void console_handle_escape(TextConsole *s) } } -static void console_clear_xy(TextConsole *s, int x, int y) +static void console_clear_xy(QemuConsole *s, int x, int y) { int y1 = (s->y_base + y) % s->total_height; TextCell *c = &s->cells[y1 * s->width + x]; @@ -852,7 +852,7 @@ static void console_clear_xy(TextConsole *s, int x, int y) } /* set cursor, checking bounds */ -static void set_cursor(TextConsole *s, int x, int y) +static void set_cursor(QemuConsole *s, int x, int y) { if (x < 0) { x = 0; @@ -871,7 +871,7 @@ static void set_cursor(TextConsole *s, int x, int y) s->y = y; } -static void console_putchar(TextConsole *s, int ch) +static void console_putchar(QemuConsole *s, int ch) { TextCell *c; int y1, i; @@ -1078,7 +1078,7 @@ static void console_putchar(TextConsole *s, int ch) void console_select(unsigned int index) { - TextConsole *s; + QemuConsole *s; if (index >= MAX_CONSOLES) return; @@ -1111,7 +1111,7 @@ void console_select(unsigned int index) static int console_puts(CharDriverState *chr, const uint8_t *buf, int len) { - TextConsole *s = chr->opaque; + QemuConsole *s = chr->opaque; int i; s->update_x0 = s->width * FONT_WIDTH; @@ -1133,7 +1133,7 @@ static int console_puts(CharDriverState *chr, const uint8_t *buf, int len) static void kbd_send_chars(void *opaque) { - TextConsole *s = opaque; + QemuConsole *s = opaque; int len; uint8_t buf[16]; @@ -1156,7 +1156,7 @@ static void kbd_send_chars(void *opaque) /* called when an ascii key is pressed */ void kbd_put_keysym(int keysym) { - TextConsole *s; + QemuConsole *s; uint8_t buf[16], *q; int c; @@ -1211,7 +1211,7 @@ void kbd_put_keysym(int keysym) static void text_console_invalidate(void *opaque) { - TextConsole *s = (TextConsole *) opaque; + QemuConsole *s = (QemuConsole *) opaque; if (!ds_get_bits_per_pixel(s->ds) && s->console_type == TEXT_CONSOLE) { s->g_width = ds_get_width(s->ds); s->g_height = ds_get_height(s->ds); @@ -1222,7 +1222,7 @@ static void text_console_invalidate(void *opaque) static void text_console_update(void *opaque, console_ch_t *chardata) { - TextConsole *s = (TextConsole *) opaque; + QemuConsole *s = (QemuConsole *) opaque; int i, j, src; if (s->text_x[0] <= s->text_x[1]) { @@ -1247,10 +1247,10 @@ static void text_console_update(void *opaque, console_ch_t *chardata) } } -static TextConsole *get_graphic_console(DisplayState *ds) +static QemuConsole *get_graphic_console(DisplayState *ds) { int i; - TextConsole *s; + QemuConsole *s; for (i = 0; i < nb_consoles; i++) { s = consoles[i]; if (s->console_type == GRAPHIC_CONSOLE && s->ds == ds) @@ -1259,14 +1259,14 @@ static TextConsole *get_graphic_console(DisplayState *ds) return NULL; } -static TextConsole *new_console(DisplayState *ds, console_type_t console_type) +static QemuConsole *new_console(DisplayState *ds, console_type_t console_type) { - TextConsole *s; + QemuConsole *s; int i; if (nb_consoles >= MAX_CONSOLES) return NULL; - s = g_malloc0(sizeof(TextConsole)); + s = g_malloc0(sizeof(QemuConsole)); if (!active_console || ((active_console->console_type != GRAPHIC_CONSOLE) && (console_type == GRAPHIC_CONSOLE))) { active_console = s; @@ -1417,7 +1417,7 @@ DisplayState *graphic_console_init(vga_hw_update_ptr update, vga_hw_text_update_ptr text_update, void *opaque) { - TextConsole *s; + QemuConsole *s; DisplayState *ds; ds = (DisplayState *) g_malloc0(sizeof(DisplayState)); @@ -1463,14 +1463,14 @@ void console_color_init(DisplayState *ds) static void text_console_set_echo(CharDriverState *chr, bool echo) { - TextConsole *s = chr->opaque; + QemuConsole *s = chr->opaque; s->echo = echo; } static void text_console_update_cursor(void *opaque) { - TextConsole *s = opaque; + QemuConsole *s = opaque; s->cursor_visible_phase = !s->cursor_visible_phase; vga_hw_invalidate(); @@ -1480,7 +1480,7 @@ static void text_console_update_cursor(void *opaque) static void text_console_do_init(CharDriverState *chr, DisplayState *ds) { - TextConsole *s; + QemuConsole *s; static int color_inited; s = chr->opaque; @@ -1543,7 +1543,7 @@ static void text_console_do_init(CharDriverState *chr, DisplayState *ds) CharDriverState *text_console_init(QemuOpts *opts) { CharDriverState *chr; - TextConsole *s; + QemuConsole *s; unsigned width; unsigned height; @@ -1589,7 +1589,7 @@ void text_consoles_set_display(DisplayState *ds) void qemu_console_resize(DisplayState *ds, int width, int height) { - TextConsole *s = get_graphic_console(ds); + QemuConsole *s = get_graphic_console(ds); if (!s) return; s->g_width = width; diff --git a/qemu-common.h b/qemu-common.h index b54612b1a5..fdd0dbcf64 100644 --- a/qemu-common.h +++ b/qemu-common.h @@ -264,8 +264,7 @@ typedef struct DisplayChangeListener DisplayChangeListener; typedef struct DisplaySurface DisplaySurface; typedef struct DisplayAllocator DisplayAllocator; typedef struct PixelFormat PixelFormat; -typedef struct TextConsole TextConsole; -typedef TextConsole QEMUConsole; +typedef struct QemuConsole QemuConsole; typedef struct CharDriverState CharDriverState; typedef struct MACAddr MACAddr; typedef struct NetClientState NetClientState; From a93a4a226a2afba147ba5df688b85d844f537c68 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 28 Sep 2012 15:02:08 +0200 Subject: [PATCH 181/291] console: untangle gfx & txt updates Stop abusing displaysurface fields for text mode displays. (bpp = 0, width = cols, height = lines). Add flags to displaystate indicating whenever text mode display (curses) or gfx mode displays (sdl, vnc, ...) are present. Add separate displaychangelistener callbacks for text / gfx mode resize & updates. This allows to enable gfx and txt diplays at the same time and also paves the way for more cleanups in the future. Signed-off-by: Gerd Hoffmann --- console.c | 59 ++++++++++++++++++----------------- console.h | 74 +++++++++++++++++++++++++++++++------------- hw/blizzard.c | 4 +-- hw/exynos4210_fimd.c | 2 +- hw/g364fb.c | 7 +++-- hw/jazz_led.c | 4 +-- hw/milkymist-vgafb.c | 2 +- hw/musicpal.c | 2 +- hw/nseries.c | 2 +- hw/omap_lcdc.c | 2 +- hw/palm.c | 2 +- hw/pl110.c | 2 +- hw/pxa2xx_lcd.c | 8 ++--- hw/qxl-render.c | 10 +++--- hw/qxl.c | 4 +-- hw/sm501.c | 4 +-- hw/ssd0303.c | 2 +- hw/ssd0323.c | 2 +- hw/tc6393xb.c | 4 +-- hw/tcx.c | 16 +++++----- hw/vga.c | 34 +++++++++----------- hw/vmware_vga.c | 4 +-- ui/curses.c | 21 +++++-------- ui/sdl.c | 12 +++---- ui/spice-display.c | 4 +-- ui/vnc.c | 8 ++--- vl.c | 14 +++++++-- 27 files changed, 171 insertions(+), 138 deletions(-) diff --git a/console.c b/console.c index b53dc1b6f3..61812c7c7f 100644 --- a/console.c +++ b/console.c @@ -638,30 +638,33 @@ static void console_refresh(QemuConsole *s) if (s != active_console) return; - if (!ds_get_bits_per_pixel(s->ds)) { + + if (s->ds->have_text) { s->text_x[0] = 0; s->text_y[0] = 0; s->text_x[1] = s->width - 1; s->text_y[1] = s->height - 1; s->cursor_invalidate = 1; - return; } - vga_fill_rect(s->ds, 0, 0, ds_get_width(s->ds), ds_get_height(s->ds), - color_table[0][COLOR_BLACK]); - y1 = s->y_displayed; - for(y = 0; y < s->height; y++) { - c = s->cells + y1 * s->width; - for(x = 0; x < s->width; x++) { - vga_putcharxy(s->ds, x, y, c->ch, - &(c->t_attrib)); - c++; + if (s->ds->have_gfx) { + vga_fill_rect(s->ds, 0, 0, ds_get_width(s->ds), ds_get_height(s->ds), + color_table[0][COLOR_BLACK]); + y1 = s->y_displayed; + for (y = 0; y < s->height; y++) { + c = s->cells + y1 * s->width; + for (x = 0; x < s->width; x++) { + vga_putcharxy(s->ds, x, y, c->ch, + &(c->t_attrib)); + c++; + } + if (++y1 == s->total_height) { + y1 = 0; + } } - if (++y1 == s->total_height) - y1 = 0; + console_show_cursor(s, 1); + dpy_gfx_update(s->ds, 0, 0, ds_get_width(s->ds), ds_get_height(s->ds)); } - console_show_cursor(s, 1); - dpy_update(s->ds, 0, 0, ds_get_width(s->ds), ds_get_height(s->ds)); } static void console_scroll(int ydelta) @@ -1094,17 +1097,17 @@ void console_select(unsigned int index) qemu_del_timer(active_console->cursor_timer); } active_console = s; - if (ds_get_bits_per_pixel(s->ds)) { + if (ds->have_gfx) { ds->surface = qemu_resize_displaysurface(ds, s->g_width, s->g_height); - } else { - s->ds->surface->width = s->width; - s->ds->surface->height = s->height; + dpy_gfx_resize(ds); + } + if (ds->have_text) { + dpy_text_resize(ds, s->width, s->height); } if (s->cursor_timer) { qemu_mod_timer(s->cursor_timer, qemu_get_clock_ms(rt_clock) + CONSOLE_CURSOR_PERIOD / 2); } - dpy_resize(s->ds); vga_hw_invalidate(); } } @@ -1123,10 +1126,10 @@ static int console_puts(CharDriverState *chr, const uint8_t *buf, int len) console_putchar(s, buf[i]); } console_show_cursor(s, 1); - if (ds_get_bits_per_pixel(s->ds) && s->update_x0 < s->update_x1) { - dpy_update(s->ds, s->update_x0, s->update_y0, - s->update_x1 - s->update_x0, - s->update_y1 - s->update_y0); + if (s->ds->have_gfx && s->update_x0 < s->update_x1) { + dpy_gfx_update(s->ds, s->update_x0, s->update_y0, + s->update_x1 - s->update_x0, + s->update_y1 - s->update_y0); } return len; } @@ -1234,8 +1237,8 @@ static void text_console_update(void *opaque, console_ch_t *chardata) (s->cells[src].t_attrib.fgcol << 12) | (s->cells[src].t_attrib.bgcol << 8) | (s->cells[src].t_attrib.bold << 21)); - dpy_update(s->ds, s->text_x[0], s->text_y[0], - s->text_x[1] - s->text_x[0], i - s->text_y[0]); + dpy_text_update(s->ds, s->text_x[0], s->text_y[0], + s->text_x[1] - s->text_x[0], i - s->text_y[0]); s->text_x[0] = s->width; s->text_y[0] = s->height; s->text_x[1] = 0; @@ -1596,7 +1599,7 @@ void qemu_console_resize(DisplayState *ds, int width, int height) s->g_height = height; if (is_graphic_console()) { ds->surface = qemu_resize_displaysurface(ds, width, height); - dpy_resize(ds); + dpy_gfx_resize(ds); } } @@ -1604,7 +1607,7 @@ void qemu_console_copy(DisplayState *ds, int src_x, int src_y, int dst_x, int dst_y, int w, int h) { if (is_graphic_console()) { - dpy_copy(ds, src_x, src_y, dst_x, dst_y, w, h); + dpy_gfx_copy(ds, src_x, src_y, dst_x, dst_y, w, h); } } diff --git a/console.h b/console.h index fb38ce9060..00e2f03424 100644 --- a/console.h +++ b/console.h @@ -154,15 +154,19 @@ struct DisplayChangeListener { int idle; uint64_t gui_timer_interval; - void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h); - void (*dpy_resize)(struct DisplayState *s); - void (*dpy_setdata)(struct DisplayState *s); void (*dpy_refresh)(struct DisplayState *s); - void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, - int dst_x, int dst_y, int w, int h); - void (*dpy_fill)(struct DisplayState *s, int x, int y, - int w, int h, uint32_t c); + + void (*dpy_gfx_update)(struct DisplayState *s, int x, int y, int w, int h); + void (*dpy_gfx_resize)(struct DisplayState *s); + void (*dpy_gfx_setdata)(struct DisplayState *s); + void (*dpy_gfx_copy)(struct DisplayState *s, int src_x, int src_y, + int dst_x, int dst_y, int w, int h); + void (*dpy_gfx_fill)(struct DisplayState *s, int x, int y, + int w, int h, uint32_t c); + void (*dpy_text_cursor)(struct DisplayState *s, int x, int y); + void (*dpy_text_resize)(struct DisplayState *s, int w, int h); + void (*dpy_text_update)(struct DisplayState *s, int x, int y, int w, int h); void (*dpy_mouse_set)(struct DisplayState *s, int x, int y, int on); void (*dpy_cursor_define)(struct DisplayState *s, QEMUCursor *cursor); @@ -180,6 +184,8 @@ struct DisplayState { struct DisplaySurface *surface; void *opaque; struct QEMUTimer *gui_timer; + bool have_gfx; + bool have_text; struct DisplayAllocator* allocator; QLIST_HEAD(, DisplayChangeListener) listeners; @@ -244,28 +250,32 @@ static inline void unregister_displaychangelistener(DisplayState *ds, gui_setup_refresh(ds); } -static inline void dpy_update(DisplayState *s, int x, int y, int w, int h) +static inline void dpy_gfx_update(DisplayState *s, int x, int y, int w, int h) { struct DisplayChangeListener *dcl; QLIST_FOREACH(dcl, &s->listeners, next) { - dcl->dpy_update(s, x, y, w, h); + if (dcl->dpy_gfx_update) { + dcl->dpy_gfx_update(s, x, y, w, h); + } } } -static inline void dpy_resize(DisplayState *s) +static inline void dpy_gfx_resize(DisplayState *s) { struct DisplayChangeListener *dcl; QLIST_FOREACH(dcl, &s->listeners, next) { - dcl->dpy_resize(s); + if (dcl->dpy_gfx_resize) { + dcl->dpy_gfx_resize(s); + } } } -static inline void dpy_setdata(DisplayState *s) +static inline void dpy_gfx_setdata(DisplayState *s) { struct DisplayChangeListener *dcl; QLIST_FOREACH(dcl, &s->listeners, next) { - if (dcl->dpy_setdata) { - dcl->dpy_setdata(s); + if (dcl->dpy_gfx_setdata) { + dcl->dpy_gfx_setdata(s); } } } @@ -280,26 +290,26 @@ static inline void dpy_refresh(DisplayState *s) } } -static inline void dpy_copy(struct DisplayState *s, int src_x, int src_y, +static inline void dpy_gfx_copy(struct DisplayState *s, int src_x, int src_y, int dst_x, int dst_y, int w, int h) { struct DisplayChangeListener *dcl; QLIST_FOREACH(dcl, &s->listeners, next) { - if (dcl->dpy_copy) { - dcl->dpy_copy(s, src_x, src_y, dst_x, dst_y, w, h); + if (dcl->dpy_gfx_copy) { + dcl->dpy_gfx_copy(s, src_x, src_y, dst_x, dst_y, w, h); } else { /* TODO */ - dcl->dpy_update(s, dst_x, dst_y, w, h); + dcl->dpy_gfx_update(s, dst_x, dst_y, w, h); } } } -static inline void dpy_fill(struct DisplayState *s, int x, int y, - int w, int h, uint32_t c) +static inline void dpy_gfx_fill(struct DisplayState *s, int x, int y, + int w, int h, uint32_t c) { struct DisplayChangeListener *dcl; QLIST_FOREACH(dcl, &s->listeners, next) { - if (dcl->dpy_fill) { - dcl->dpy_fill(s, x, y, w, h, c); + if (dcl->dpy_gfx_fill) { + dcl->dpy_gfx_fill(s, x, y, w, h, c); } } } @@ -314,6 +324,26 @@ static inline void dpy_text_cursor(struct DisplayState *s, int x, int y) } } +static inline void dpy_text_update(DisplayState *s, int x, int y, int w, int h) +{ + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { + if (dcl->dpy_text_update) { + dcl->dpy_text_update(s, x, y, w, h); + } + } +} + +static inline void dpy_text_resize(DisplayState *s, int w, int h) +{ + struct DisplayChangeListener *dcl; + QLIST_FOREACH(dcl, &s->listeners, next) { + if (dcl->dpy_text_resize) { + dcl->dpy_text_resize(s, w, h); + } + } +} + static inline void dpy_mouse_set(struct DisplayState *s, int x, int y, int on) { struct DisplayChangeListener *dcl; diff --git a/hw/blizzard.c b/hw/blizzard.c index 06e19b364b..1b57eb5396 100644 --- a/hw/blizzard.c +++ b/hw/blizzard.c @@ -921,8 +921,8 @@ static void blizzard_update_display(void *opaque) for (; y < s->my[1]; y ++, src += bypl, dst += bypl) memcpy(dst, src, bwidth); - dpy_update(s->state, s->mx[0], s->my[0], - s->mx[1] - s->mx[0], y - s->my[0]); + dpy_gfx_update(s->state, s->mx[0], s->my[0], + s->mx[1] - s->mx[0], y - s->my[0]); s->mx[0] = s->x; s->mx[1] = 0; diff --git a/hw/exynos4210_fimd.c b/hw/exynos4210_fimd.c index 7cb2c31bee..f2443ca4af 100644 --- a/hw/exynos4210_fimd.c +++ b/hw/exynos4210_fimd.c @@ -1307,7 +1307,7 @@ static void exynos4210_fimd_update(void *opaque) fimd_copy_line_toqemu(global_width, s->ifb + global_width * line * RGBA_SIZE, d + global_width * line * bpp); } - dpy_update(s->console, 0, 0, global_width, global_height); + dpy_gfx_update(s->console, 0, 0, global_width, global_height); } s->invalidate = false; s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND; diff --git a/hw/g364fb.c b/hw/g364fb.c index f7b4bf5ae2..8192baf1c8 100644 --- a/hw/g364fb.c +++ b/hw/g364fb.c @@ -197,7 +197,8 @@ static void g364fb_draw_graphic8(G364State *s) reset_dirty(s, page_min, page_max); page_min = (ram_addr_t)-1; page_max = 0; - dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); + dpy_gfx_update(s->ds, xmin, ymin, + xmax - xmin + 1, ymax - ymin + 1); xmin = s->width; xmax = 0; ymin = s->height; @@ -216,7 +217,7 @@ static void g364fb_draw_graphic8(G364State *s) done: if (page_min != (ram_addr_t)-1) { - dpy_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); + dpy_gfx_update(s->ds, xmin, ymin, xmax - xmin + 1, ymax - ymin + 1); reset_dirty(s, page_min, page_max); } } @@ -238,7 +239,7 @@ static void g364fb_draw_blank(G364State *s) d += ds_get_linesize(s->ds); } - dpy_update(s->ds, 0, 0, s->width, s->height); + dpy_gfx_update(s->ds, 0, 0, s->width, s->height); s->blanked = 1; } diff --git a/hw/jazz_led.c b/hw/jazz_led.c index 853bf6d4c1..640e75ef2f 100644 --- a/hw/jazz_led.c +++ b/hw/jazz_led.c @@ -196,7 +196,7 @@ static void jazz_led_update_display(void *opaque) } s->state = REDRAW_NONE; - dpy_update(ds, 0, 0, ds_get_width(ds), ds_get_height(ds)); + dpy_gfx_update(ds, 0, 0, ds_get_width(ds), ds_get_height(ds)); } static void jazz_led_invalidate_display(void *opaque) @@ -218,7 +218,7 @@ static void jazz_led_text_update(void *opaque, console_ch_t *chardata) console_write_ch(chardata++, 0x00200100 | buf[0]); console_write_ch(chardata++, 0x00200100 | buf[1]); - dpy_update(s->ds, 0, 0, 2, 1); + dpy_text_update(s->ds, 0, 0, 2, 1); } static int jazz_led_post_load(void *opaque, int version_id) diff --git a/hw/milkymist-vgafb.c b/hw/milkymist-vgafb.c index 8d36bc10f6..833881cc6a 100644 --- a/hw/milkymist-vgafb.c +++ b/hw/milkymist-vgafb.c @@ -134,7 +134,7 @@ static void vgafb_update_display(void *opaque) &first, &last); if (first >= 0) { - dpy_update(s->ds, 0, first, s->regs[R_HRES], last - first + 1); + dpy_gfx_update(s->ds, 0, first, s->regs[R_HRES], last - first + 1); } s->invalidate = 0; } diff --git a/hw/musicpal.c b/hw/musicpal.c index beec76bf38..e0c57c84eb 100644 --- a/hw/musicpal.c +++ b/hw/musicpal.c @@ -526,7 +526,7 @@ static void lcd_refresh(void *opaque) ds_get_bits_per_pixel(s->ds)); } - dpy_update(s->ds, 0, 0, 128*3, 64*3); + dpy_gfx_update(s->ds, 0, 0, 128*3, 64*3); } static void lcd_invalidate(void *opaque) diff --git a/hw/nseries.c b/hw/nseries.c index 9306aa15a7..26d5e3507f 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -1376,7 +1376,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device, size until the guest activates the display. */ ds = get_displaystate(); ds->surface = qemu_resize_displaysurface(ds, 800, 480); - dpy_resize(ds); + dpy_gfx_resize(ds); } static struct arm_boot_info n800_binfo = { diff --git a/hw/omap_lcdc.c b/hw/omap_lcdc.c index bf177c22dd..d7ae3032be 100644 --- a/hw/omap_lcdc.c +++ b/hw/omap_lcdc.c @@ -219,7 +219,7 @@ static void omap_update_display(void *opaque) draw_line, omap_lcd->palette, &first, &last); if (first >= 0) { - dpy_update(omap_lcd->state, 0, first, width, last - first + 1); + dpy_gfx_update(omap_lcd->state, 0, first, width, last - first + 1); } omap_lcd->invalidate = 0; } diff --git a/hw/palm.c b/hw/palm.c index d26305159d..6f6f414e6e 100644 --- a/hw/palm.c +++ b/hw/palm.c @@ -273,7 +273,7 @@ static void palmte_init(QEMUMachineInitArgs *args) will set the size once configured, so this just sets an initial size until the guest activates the display. */ ds->surface = qemu_resize_displaysurface(ds, 320, 320); - dpy_resize(ds); + dpy_gfx_resize(ds); } static QEMUMachine palmte_machine = { diff --git a/hw/pl110.c b/hw/pl110.c index 82486b0c14..79a3f82ddf 100644 --- a/hw/pl110.c +++ b/hw/pl110.c @@ -239,7 +239,7 @@ static void pl110_update_display(void *opaque) fn, s->palette, &first, &last); if (first >= 0) { - dpy_update(s->ds, 0, first, s->cols, last - first + 1); + dpy_gfx_update(s->ds, 0, first, s->cols, last - first + 1); } s->invalidate = 0; } diff --git a/hw/pxa2xx_lcd.c b/hw/pxa2xx_lcd.c index 38c38890c9..b53dfaf3cf 100644 --- a/hw/pxa2xx_lcd.c +++ b/hw/pxa2xx_lcd.c @@ -871,20 +871,20 @@ static void pxa2xx_update_display(void *opaque) if (miny >= 0) { switch (s->orientation) { case 0: - dpy_update(s->ds, 0, miny, s->xres, maxy - miny + 1); + dpy_gfx_update(s->ds, 0, miny, s->xres, maxy - miny + 1); break; case 90: - dpy_update(s->ds, miny, 0, maxy - miny + 1, s->xres); + dpy_gfx_update(s->ds, miny, 0, maxy - miny + 1, s->xres); break; case 180: maxy = s->yres - maxy - 1; miny = s->yres - miny - 1; - dpy_update(s->ds, 0, maxy, s->xres, miny - maxy + 1); + dpy_gfx_update(s->ds, 0, maxy, s->xres, miny - maxy + 1); break; case 270: maxy = s->yres - maxy - 1; miny = s->yres - miny - 1; - dpy_update(s->ds, maxy, 0, miny - maxy + 1, s->xres); + dpy_gfx_update(s->ds, maxy, 0, miny - maxy + 1, s->xres); break; } } diff --git a/hw/qxl-render.c b/hw/qxl-render.c index e8cf29e62a..47eb8b4154 100644 --- a/hw/qxl-render.c +++ b/hw/qxl-render.c @@ -123,17 +123,17 @@ static void qxl_render_update_area_unlocked(PCIQXLDevice *qxl) qxl->guest_primary.surface.width, qxl->guest_primary.surface.height); } - dpy_resize(vga->ds); + dpy_gfx_resize(vga->ds); } for (i = 0; i < qxl->num_dirty_rects; i++) { if (qemu_spice_rect_is_empty(qxl->dirty+i)) { break; } qxl_blit(qxl, qxl->dirty+i); - dpy_update(vga->ds, - qxl->dirty[i].left, qxl->dirty[i].top, - qxl->dirty[i].right - qxl->dirty[i].left, - qxl->dirty[i].bottom - qxl->dirty[i].top); + dpy_gfx_update(vga->ds, + qxl->dirty[i].left, qxl->dirty[i].top, + qxl->dirty[i].right - qxl->dirty[i].left, + qxl->dirty[i].bottom - qxl->dirty[i].top); } qxl->num_dirty_rects = 0; } diff --git a/hw/qxl.c b/hw/qxl.c index d54daf6d3b..1f56fcd169 100644 --- a/hw/qxl.c +++ b/hw/qxl.c @@ -1864,8 +1864,8 @@ static void display_refresh(struct DisplayState *ds) } static DisplayChangeListener display_listener = { - .dpy_update = display_update, - .dpy_resize = display_resize, + .dpy_gfx_update = display_update, + .dpy_gfx_resize = display_resize, .dpy_refresh = display_refresh, }; diff --git a/hw/sm501.c b/hw/sm501.c index 4aafe49cce..50324cda53 100644 --- a/hw/sm501.c +++ b/hw/sm501.c @@ -1351,7 +1351,7 @@ static void sm501_draw_crt(SM501State * s) } else { if (y_start >= 0) { /* flush to display */ - dpy_update(s->ds, 0, y_start, width, y - y_start); + dpy_gfx_update(s->ds, 0, y_start, width, y - y_start); y_start = -1; } } @@ -1362,7 +1362,7 @@ static void sm501_draw_crt(SM501State * s) /* complete flush to display */ if (y_start >= 0) - dpy_update(s->ds, 0, y_start, width, y - y_start); + dpy_gfx_update(s->ds, 0, y_start, width, y - y_start); /* clear dirty flags */ if (page_min != ~0l) { diff --git a/hw/ssd0303.c b/hw/ssd0303.c index 4e1ee6e12b..d7fd828c65 100644 --- a/hw/ssd0303.c +++ b/hw/ssd0303.c @@ -252,7 +252,7 @@ static void ssd0303_update_display(void *opaque) } } s->redraw = 0; - dpy_update(s->ds, 0, 0, 96 * MAGNIFY, 16 * MAGNIFY); + dpy_gfx_update(s->ds, 0, 0, 96 * MAGNIFY, 16 * MAGNIFY); } static void ssd0303_invalidate_display(void * opaque) diff --git a/hw/ssd0323.c b/hw/ssd0323.c index 9c42d648e2..4098830c2b 100644 --- a/hw/ssd0323.c +++ b/hw/ssd0323.c @@ -260,7 +260,7 @@ static void ssd0323_update_display(void *opaque) } } s->redraw = 0; - dpy_update(s->ds, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY); + dpy_gfx_update(s->ds, 0, 0, 128 * MAGNIFY, 64 * MAGNIFY); } static void ssd0323_invalidate_display(void * opaque) diff --git a/hw/tc6393xb.c b/hw/tc6393xb.c index 31d4f26629..f0320271d4 100644 --- a/hw/tc6393xb.c +++ b/hw/tc6393xb.c @@ -454,7 +454,7 @@ static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update) return; } - dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); + dpy_gfx_update(s->ds, 0, 0, s->scr_width, s->scr_height); } static void tc6393xb_draw_blank(TC6393xbState *s, int full_update) @@ -472,7 +472,7 @@ static void tc6393xb_draw_blank(TC6393xbState *s, int full_update) d += ds_get_linesize(s->ds); } - dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height); + dpy_gfx_update(s->ds, 0, 0, s->scr_width, s->scr_height); } static void tc6393xb_update_display(void *opaque) diff --git a/hw/tcx.c b/hw/tcx.c index 7abe865e3f..7aee2a9bd3 100644 --- a/hw/tcx.c +++ b/hw/tcx.c @@ -268,8 +268,8 @@ static void tcx_update_display(void *opaque) } else { if (y_start >= 0) { /* flush to display */ - dpy_update(ts->ds, 0, y_start, - ts->width, y - y_start); + dpy_gfx_update(ts->ds, 0, y_start, + ts->width, y - y_start); y_start = -1; } d += dd * 4; @@ -278,8 +278,8 @@ static void tcx_update_display(void *opaque) } if (y_start >= 0) { /* flush to display */ - dpy_update(ts->ds, 0, y_start, - ts->width, y - y_start); + dpy_gfx_update(ts->ds, 0, y_start, + ts->width, y - y_start); } /* reset modified pages */ if (page_max >= page_min) { @@ -344,8 +344,8 @@ static void tcx24_update_display(void *opaque) } else { if (y_start >= 0) { /* flush to display */ - dpy_update(ts->ds, 0, y_start, - ts->width, y - y_start); + dpy_gfx_update(ts->ds, 0, y_start, + ts->width, y - y_start); y_start = -1; } d += dd * 4; @@ -356,8 +356,8 @@ static void tcx24_update_display(void *opaque) } if (y_start >= 0) { /* flush to display */ - dpy_update(ts->ds, 0, y_start, - ts->width, y - y_start); + dpy_gfx_update(ts->ds, 0, y_start, + ts->width, y - y_start); } /* reset modified pages */ if (page_max >= page_min) { diff --git a/hw/vga.c b/hw/vga.c index f3256cb6c7..dc8dddec80 100644 --- a/hw/vga.c +++ b/hw/vga.c @@ -1456,8 +1456,8 @@ static void vga_draw_text(VGACommonState *s, int full_update) ch_attr_ptr++; } if (cx_max != -1) { - dpy_update(s->ds, cx_min * cw, cy * cheight, - (cx_max - cx_min + 1) * cw, cheight); + dpy_gfx_update(s->ds, cx_min * cw, cy * cheight, + (cx_max - cx_min + 1) * cw, cheight); } dest += linesize * cheight; line1 = line + cheight; @@ -1688,7 +1688,7 @@ static void vga_draw_graphic(VGACommonState *s, int full_update) #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) s->ds->surface->pf = qemu_different_endianness_pixelformat(depth); #endif - dpy_resize(s->ds); + dpy_gfx_resize(s->ds); } else { qemu_console_resize(s->ds, disp_width, height); } @@ -1702,7 +1702,7 @@ static void vga_draw_graphic(VGACommonState *s, int full_update) } else if (is_buffer_shared(s->ds->surface) && (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) { s->ds->surface->data = s->vram_ptr + (s->start_addr * 4); - dpy_setdata(s->ds); + dpy_gfx_setdata(s->ds); } s->rgb_to_pixel = @@ -1807,8 +1807,8 @@ static void vga_draw_graphic(VGACommonState *s, int full_update) } else { if (y_start >= 0) { /* flush to display */ - dpy_update(s->ds, 0, y_start, - disp_width, y - y_start); + dpy_gfx_update(s->ds, 0, y_start, + disp_width, y - y_start); y_start = -1; } } @@ -1828,8 +1828,8 @@ static void vga_draw_graphic(VGACommonState *s, int full_update) } if (y_start >= 0) { /* flush to display */ - dpy_update(s->ds, 0, y_start, - disp_width, y - y_start); + dpy_gfx_update(s->ds, 0, y_start, + disp_width, y - y_start); } /* reset modified pages */ if (page_max >= page_min) { @@ -1863,8 +1863,8 @@ static void vga_draw_blank(VGACommonState *s, int full_update) memset(d, val, w); d += ds_get_linesize(s->ds); } - dpy_update(s->ds, 0, 0, - s->last_scr_width, s->last_scr_height); + dpy_gfx_update(s->ds, 0, 0, + s->last_scr_width, s->last_scr_height); } #define GMODE_TEXT 0 @@ -2052,9 +2052,7 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) cw != s->last_cw || cheight != s->last_ch) { s->last_scr_width = width * cw; s->last_scr_height = height * cheight; - s->ds->surface->width = width; - s->ds->surface->height = height; - dpy_resize(s->ds); + dpy_text_resize(s->ds, width, height); s->last_width = width; s->last_height = height; s->last_ch = cheight; @@ -2087,7 +2085,7 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) for (i = 0; i < size; src ++, dst ++, i ++) console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src))); - dpy_update(s->ds, 0, 0, width, height); + dpy_text_update(s->ds, 0, 0, width, height); } else { c_max = 0; @@ -2110,7 +2108,7 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) if (c_min <= c_max) { i = TEXTMODE_Y(c_min); - dpy_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1); + dpy_text_update(s->ds, 0, i, width, TEXTMODE_Y(c_max) - i + 1); } } @@ -2136,9 +2134,7 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) s->last_width = 60; s->last_height = height = 3; dpy_text_cursor(s->ds, -1, -1); - s->ds->surface->width = s->last_width; - s->ds->surface->height = height; - dpy_resize(s->ds); + dpy_text_resize(s->ds, s->last_width, height); for (dst = chardata, i = 0; i < s->last_width * height; i ++) console_write_ch(dst ++, ' '); @@ -2149,7 +2145,7 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) for (i = 0; i < size; i ++) console_write_ch(dst ++, 0x00200100 | msg_buffer[i]); - dpy_update(s->ds, 0, 0, s->last_width, height); + dpy_text_update(s->ds, 0, 0, s->last_width, height); } static uint64_t vga_mem_read(void *opaque, hwaddr addr, diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index dc9279064c..34532e5c3a 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -321,14 +321,14 @@ static inline void vmsvga_update_rect(struct vmsvga_state_s *s, for (; line > 0; line --, src += bypl, dst += bypl) memcpy(dst, src, width); - dpy_update(s->vga.ds, x, y, w, h); + dpy_gfx_update(s->vga.ds, x, y, w, h); } static inline void vmsvga_update_screen(struct vmsvga_state_s *s) { memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, s->bypp * s->width * s->height); - dpy_update(s->vga.ds, 0, 0, s->width, s->height); + dpy_gfx_update(s->vga.ds, 0, 0, s->width, s->height); } static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, diff --git a/ui/curses.c b/ui/curses.c index c2be2c641a..b40b22307d 100644 --- a/ui/curses.c +++ b/ui/curses.c @@ -95,17 +95,16 @@ static void curses_calc_pad(void) } } -static void curses_resize(DisplayState *ds) +static void curses_resize(DisplayState *ds, int width, int height) { - if (ds_get_width(ds) == gwidth && ds_get_height(ds) == gheight) + if (width == gwidth && height == gheight) { return; + } - gwidth = ds_get_width(ds); - gheight = ds_get_height(ds); + gwidth = width; + gheight = height; curses_calc_pad(); - ds->surface->width = width * FONT_WIDTH; - ds->surface->height = height * FONT_HEIGHT; } #ifndef _WIN32 @@ -167,8 +166,6 @@ static void curses_refresh(DisplayState *ds) clear(); refresh(); curses_calc_pad(); - ds->surface->width = FONT_WIDTH * width; - ds->surface->height = FONT_HEIGHT * height; vga_hw_invalidate(); invalidate = 0; } @@ -195,8 +192,6 @@ static void curses_refresh(DisplayState *ds) refresh(); curses_calc_pad(); curses_update(ds, 0, 0, width, height); - ds->surface->width = FONT_WIDTH * width; - ds->surface->height = FONT_HEIGHT * height; continue; } #endif @@ -355,13 +350,11 @@ void curses_display_init(DisplayState *ds, int full_screen) #endif dcl = (DisplayChangeListener *) g_malloc0(sizeof(DisplayChangeListener)); - dcl->dpy_update = curses_update; - dcl->dpy_resize = curses_resize; + dcl->dpy_text_update = curses_update; + dcl->dpy_text_resize = curses_resize; dcl->dpy_refresh = curses_refresh; dcl->dpy_text_cursor = curses_cursor_position; register_displaychangelistener(ds, dcl); - qemu_free_displaysurface(ds); - ds->surface = qemu_create_displaysurface_from(640, 400, 0, 0, (uint8_t*) screen); invalidate = 1; } diff --git a/ui/sdl.c b/ui/sdl.c index f8ead930ae..fac1a4740d 100644 --- a/ui/sdl.c +++ b/ui/sdl.c @@ -553,7 +553,7 @@ static void sdl_scale(DisplayState *ds, int width, int height) if (!is_buffer_shared(ds->surface)) { ds->surface = qemu_resize_displaysurface(ds, ds_get_width(ds), ds_get_height(ds)); - dpy_resize(ds); + dpy_gfx_resize(ds); } } @@ -1020,11 +1020,11 @@ void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) } dcl = g_malloc0(sizeof(DisplayChangeListener)); - dcl->dpy_update = sdl_update; - dcl->dpy_resize = sdl_resize; + dcl->dpy_gfx_update = sdl_update; + dcl->dpy_gfx_resize = sdl_resize; dcl->dpy_refresh = sdl_refresh; - dcl->dpy_setdata = sdl_setdata; - dcl->dpy_fill = sdl_fill; + dcl->dpy_gfx_setdata = sdl_setdata; + dcl->dpy_gfx_fill = sdl_fill; dcl->dpy_mouse_set = sdl_mouse_warp; dcl->dpy_cursor_define = sdl_mouse_define; register_displaychangelistener(ds, dcl); @@ -1034,7 +1034,7 @@ void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) da->resize_displaysurface = sdl_resize_displaysurface; da->free_displaysurface = sdl_free_displaysurface; if (register_displayallocator(ds, da) == da) { - dpy_resize(ds); + dpy_gfx_resize(ds); } mouse_mode_notifier.notify = sdl_mouse_mode_change; diff --git a/ui/spice-display.c b/ui/spice-display.c index 5779fa8ba6..fb99148349 100644 --- a/ui/spice-display.c +++ b/ui/spice-display.c @@ -571,8 +571,8 @@ static void display_refresh(struct DisplayState *ds) } static DisplayChangeListener display_listener = { - .dpy_update = display_update, - .dpy_resize = display_resize, + .dpy_gfx_update = display_update, + .dpy_gfx_resize = display_resize, .dpy_refresh = display_refresh, }; diff --git a/ui/vnc.c b/ui/vnc.c index 1b70db7e05..0ae1c74984 100644 --- a/ui/vnc.c +++ b/ui/vnc.c @@ -2753,10 +2753,10 @@ void vnc_display_init(DisplayState *ds) qemu_mutex_init(&vs->mutex); vnc_start_worker_thread(); - dcl->dpy_copy = vnc_dpy_copy; - dcl->dpy_update = vnc_dpy_update; - dcl->dpy_resize = vnc_dpy_resize; - dcl->dpy_setdata = vnc_dpy_setdata; + dcl->dpy_gfx_copy = vnc_dpy_copy; + dcl->dpy_gfx_update = vnc_dpy_update; + dcl->dpy_gfx_resize = vnc_dpy_resize; + dcl->dpy_gfx_setdata = vnc_dpy_setdata; dcl->dpy_mouse_set = vnc_mouse_set; dcl->dpy_cursor_define = vnc_dpy_cursor_define; register_displaychangelistener(ds, dcl); diff --git a/vl.c b/vl.c index 4c45b02f05..8716fc0a6c 100644 --- a/vl.c +++ b/vl.c @@ -1375,11 +1375,18 @@ void gui_setup_refresh(DisplayState *ds) { DisplayChangeListener *dcl; bool need_timer = false; + bool have_gfx = false; + bool have_text = false; QLIST_FOREACH(dcl, &ds->listeners, next) { if (dcl->dpy_refresh != NULL) { need_timer = true; - break; + } + if (dcl->dpy_gfx_update != NULL) { + have_gfx = true; + } + if (dcl->dpy_text_update != NULL) { + have_text = true; } } @@ -1392,6 +1399,9 @@ void gui_setup_refresh(DisplayState *ds) qemu_free_timer(ds->gui_timer); ds->gui_timer = NULL; } + + ds->have_gfx = have_gfx; + ds->have_text = have_text; } struct vm_change_state_entry { @@ -3866,7 +3876,7 @@ int main(int argc, char **argv, char **envp) #endif /* display setup */ - dpy_resize(ds); + dpy_gfx_resize(ds); text_consoles_set_display(ds); if (foreach_device_config(DEV_GDB, gdbserver_start) < 0) { From e250d949feb1334828f27f0d145c35f29c4b7639 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 28 Sep 2012 15:30:07 +0200 Subject: [PATCH 182/291] console: init displaychangelisteners on register Signed-off-by: Gerd Hoffmann --- console.h | 3 +++ vl.c | 1 - 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/console.h b/console.h index 00e2f03424..7e0ac760e3 100644 --- a/console.h +++ b/console.h @@ -241,6 +241,9 @@ static inline void register_displaychangelistener(DisplayState *ds, DisplayChang { QLIST_INSERT_HEAD(&ds->listeners, dcl, next); gui_setup_refresh(ds); + if (dcl->dpy_gfx_resize) { + dcl->dpy_gfx_resize(ds); + } } static inline void unregister_displaychangelistener(DisplayState *ds, diff --git a/vl.c b/vl.c index 8716fc0a6c..df776e91ad 100644 --- a/vl.c +++ b/vl.c @@ -3876,7 +3876,6 @@ int main(int argc, char **argv, char **envp) #endif /* display setup */ - dpy_gfx_resize(ds); text_consoles_set_display(ds); if (foreach_device_config(DEV_GDB, gdbserver_start) < 0) { From 9678aedd8e76978465698b9edeb069ccee15e975 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 9 Oct 2012 17:10:13 +0200 Subject: [PATCH 183/291] vga: fix text mode updating With both text (curses) and graphics (vnc/sdl/spice/...) display active vga text mode emulation fails to update both correctly. Depending on whenever vga_update_text() or vga_draw_text() happens to be called first only the text display or only the graphics display will see display resolution changes and full redraws. Fix it by calling both text/gfx resize functions in both code paths and keep track of full screen redraws needed in VGACommonState fields. Signed-off-by: Gerd Hoffmann --- hw/vga.c | 19 +++++++++++++++++++ hw/vga_int.h | 2 ++ 2 files changed, 21 insertions(+) diff --git a/hw/vga.c b/hw/vga.c index dc8dddec80..f31dbdd652 100644 --- a/hw/vga.c +++ b/hw/vga.c @@ -1346,6 +1346,7 @@ static void vga_draw_text(VGACommonState *s, int full_update) s->last_scr_width = width * cw; s->last_scr_height = height * cheight; qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height); + dpy_text_resize(s->ds, width, height); s->last_depth = 0; s->last_width = width; s->last_height = height; @@ -1359,6 +1360,14 @@ static void vga_draw_text(VGACommonState *s, int full_update) palette = s->last_palette; x_incr = cw * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3); + if (full_update) { + s->full_update_text = 1; + } + if (s->full_update_gfx) { + s->full_update_gfx = 0; + full_update |= 1; + } + cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) | s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr; if (cursor_offset != s->cursor_offset || @@ -2052,7 +2061,9 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) cw != s->last_cw || cheight != s->last_ch) { s->last_scr_width = width * cw; s->last_scr_height = height * cheight; + qemu_console_resize(s->ds, s->last_scr_width, s->last_scr_height); dpy_text_resize(s->ds, width, height); + s->last_depth = 0; s->last_width = width; s->last_height = height; s->last_ch = cheight; @@ -2060,6 +2071,14 @@ static void vga_update_text(void *opaque, console_ch_t *chardata) full_update = 1; } + if (full_update) { + s->full_update_gfx = 1; + } + if (s->full_update_text) { + s->full_update_text = 0; + full_update |= 1; + } + /* Update "hardware" cursor */ cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) | s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr; diff --git a/hw/vga_int.h b/hw/vga_int.h index 22f1706adf..d4da777e62 100644 --- a/hw/vga_int.h +++ b/hw/vga_int.h @@ -154,6 +154,8 @@ typedef struct VGACommonState { vga_hw_invalidate_ptr invalidate; vga_hw_screen_dump_ptr screen_dump; vga_hw_text_update_ptr text_update; + bool full_update_text; + bool full_update_gfx; /* hardware mouse cursor support */ uint32_t invalidated_y_table[VGA_MAX_HEIGHT / 32]; void (*cursor_invalidate)(struct VGACommonState *s); From 4dc6a39bbd1a03f86797e0df2db285318f086aee Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 28 Sep 2012 15:31:33 +0200 Subject: [PATCH 184/291] console: remove dpy_gfx_fill Unused code. 'nuff said. Signed-off-by: Gerd Hoffmann --- console.h | 13 ------------- ui/sdl.c | 7 ------- 2 files changed, 20 deletions(-) diff --git a/console.h b/console.h index 7e0ac760e3..6492e67bd2 100644 --- a/console.h +++ b/console.h @@ -161,8 +161,6 @@ struct DisplayChangeListener { void (*dpy_gfx_setdata)(struct DisplayState *s); void (*dpy_gfx_copy)(struct DisplayState *s, int src_x, int src_y, int dst_x, int dst_y, int w, int h); - void (*dpy_gfx_fill)(struct DisplayState *s, int x, int y, - int w, int h, uint32_t c); void (*dpy_text_cursor)(struct DisplayState *s, int x, int y); void (*dpy_text_resize)(struct DisplayState *s, int w, int h); @@ -306,17 +304,6 @@ static inline void dpy_gfx_copy(struct DisplayState *s, int src_x, int src_y, } } -static inline void dpy_gfx_fill(struct DisplayState *s, int x, int y, - int w, int h, uint32_t c) -{ - struct DisplayChangeListener *dcl; - QLIST_FOREACH(dcl, &s->listeners, next) { - if (dcl->dpy_gfx_fill) { - dcl->dpy_gfx_fill(s, x, y, w, h, c); - } - } -} - static inline void dpy_text_cursor(struct DisplayState *s, int x, int y) { struct DisplayChangeListener *dcl; diff --git a/ui/sdl.c b/ui/sdl.c index fac1a4740d..c3ba79fe43 100644 --- a/ui/sdl.c +++ b/ui/sdl.c @@ -899,12 +899,6 @@ static void sdl_refresh(DisplayState *ds) } } -static void sdl_fill(DisplayState *ds, int x, int y, int w, int h, uint32_t c) -{ - SDL_Rect dst = { x, y, w, h }; - SDL_FillRect(real_screen, &dst, c); -} - static void sdl_mouse_warp(DisplayState *ds, int x, int y, int on) { if (on) { @@ -1024,7 +1018,6 @@ void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) dcl->dpy_gfx_resize = sdl_resize; dcl->dpy_refresh = sdl_refresh; dcl->dpy_gfx_setdata = sdl_setdata; - dcl->dpy_gfx_fill = sdl_fill; dcl->dpy_mouse_set = sdl_mouse_warp; dcl->dpy_cursor_define = sdl_mouse_define; register_displaychangelistener(ds, dcl); From 187cd1d9f30d13f0d0ef682e4d91cfa3e4cbd472 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 26 Sep 2012 07:46:20 +0200 Subject: [PATCH 185/291] console: remove DisplayAllocator Causes [temporary] preformance regression with 24bpp vga modes @ sdl. Signed-off-by: Gerd Hoffmann --- console.c | 52 ++++++++-------------- console.h | 34 +++------------ qemu-common.h | 1 - ui/sdl.c | 117 +++----------------------------------------------- 4 files changed, 31 insertions(+), 173 deletions(-) diff --git a/console.c b/console.c index 61812c7c7f..71cc543b7b 100644 --- a/console.c +++ b/console.c @@ -1294,9 +1294,10 @@ static QemuConsole *new_console(DisplayState *ds, console_type_t console_type) return s; } -static DisplaySurface* defaultallocator_create_displaysurface(int width, int height) +DisplaySurface *qemu_create_displaysurface(DisplayState *ds, + int width, int height) { - DisplaySurface *surface = (DisplaySurface*) g_malloc0(sizeof(DisplaySurface)); + DisplaySurface *surface = g_new0(DisplaySurface, 1); int linesize = width * 4; qemu_alloc_display(surface, width, height, linesize, @@ -1304,13 +1305,15 @@ static DisplaySurface* defaultallocator_create_displaysurface(int width, int hei return surface; } -static DisplaySurface* defaultallocator_resize_displaysurface(DisplaySurface *surface, - int width, int height) +DisplaySurface *qemu_resize_displaysurface(DisplayState *ds, + int width, int height) { int linesize = width * 4; - qemu_alloc_display(surface, width, height, linesize, + + trace_displaysurface_resize(ds, ds->surface, width, height); + qemu_alloc_display(ds->surface, width, height, linesize, qemu_default_pixelformat(32), 0); - return surface; + return ds->surface; } void qemu_alloc_display(DisplaySurface *surface, int width, int height, @@ -1323,7 +1326,7 @@ void qemu_alloc_display(DisplaySurface *surface, int width, int height, surface->pf = pf; if (surface->flags & QEMU_ALLOCATED_FLAG) { data = g_realloc(surface->data, - surface->linesize * surface->height); + surface->linesize * surface->height); } else { data = g_malloc(surface->linesize * surface->height); } @@ -1334,7 +1337,7 @@ void qemu_alloc_display(DisplaySurface *surface, int width, int height, #endif } -DisplaySurface* qemu_create_displaysurface_from(int width, int height, int bpp, +DisplaySurface *qemu_create_displaysurface_from(int width, int height, int bpp, int linesize, uint8_t *data) { DisplaySurface *surface = (DisplaySurface*) g_malloc0(sizeof(DisplaySurface)); @@ -1351,28 +1354,24 @@ DisplaySurface* qemu_create_displaysurface_from(int width, int height, int bpp, return surface; } -static void defaultallocator_free_displaysurface(DisplaySurface *surface) +void qemu_free_displaysurface(DisplayState *ds) { - if (surface == NULL) + trace_displaysurface_free(ds, ds->surface); + if (ds->surface == NULL) { return; - if (surface->flags & QEMU_ALLOCATED_FLAG) - g_free(surface->data); - g_free(surface); + } + if (ds->surface->flags & QEMU_ALLOCATED_FLAG) { + g_free(ds->surface->data); + } + g_free(ds->surface); } -static struct DisplayAllocator default_allocator = { - defaultallocator_create_displaysurface, - defaultallocator_resize_displaysurface, - defaultallocator_free_displaysurface -}; - static void dumb_display_init(void) { DisplayState *ds = g_malloc0(sizeof(DisplayState)); int width = 640; int height = 480; - ds->allocator = &default_allocator; if (is_fixedsize_console()) { width = active_console->g_width; height = active_console->g_height; @@ -1402,18 +1401,6 @@ DisplayState *get_displaystate(void) return display_state; } -DisplayAllocator *register_displayallocator(DisplayState *ds, DisplayAllocator *da) -{ - if(ds->allocator == &default_allocator) { - DisplaySurface *surf; - surf = da->create_displaysurface(ds_get_width(ds), ds_get_height(ds)); - defaultallocator_free_displaysurface(ds->surface); - ds->surface = surf; - ds->allocator = da; - } - return ds->allocator; -} - DisplayState *graphic_console_init(vga_hw_update_ptr update, vga_hw_invalidate_ptr invalidate, vga_hw_screen_dump_ptr screen_dump, @@ -1424,7 +1411,6 @@ DisplayState *graphic_console_init(vga_hw_update_ptr update, DisplayState *ds; ds = (DisplayState *) g_malloc0(sizeof(DisplayState)); - ds->allocator = &default_allocator; ds->surface = qemu_create_displaysurface(ds, 640, 480); s = new_console(ds, GRAPHIC_CONSOLE); diff --git a/console.h b/console.h index 6492e67bd2..6be880a554 100644 --- a/console.h +++ b/console.h @@ -107,7 +107,6 @@ void kbd_put_keysym(int keysym); #define QEMU_BIG_ENDIAN_FLAG 0x01 #define QEMU_ALLOCATED_FLAG 0x02 -#define QEMU_REALPIXELS_FLAG 0x04 struct PixelFormat { uint8_t bits_per_pixel; @@ -172,12 +171,6 @@ struct DisplayChangeListener { QLIST_ENTRY(DisplayChangeListener) next; }; -struct DisplayAllocator { - DisplaySurface* (*create_displaysurface)(int width, int height); - DisplaySurface* (*resize_displaysurface)(DisplaySurface *surface, int width, int height); - void (*free_displaysurface)(DisplaySurface *surface); -}; - struct DisplayState { struct DisplaySurface *surface; void *opaque; @@ -185,7 +178,6 @@ struct DisplayState { bool have_gfx; bool have_text; - struct DisplayAllocator* allocator; QLIST_HEAD(, DisplayChangeListener) listeners; struct DisplayState *next; @@ -200,24 +192,11 @@ void qemu_alloc_display(DisplaySurface *surface, int width, int height, PixelFormat qemu_different_endianness_pixelformat(int bpp); PixelFormat qemu_default_pixelformat(int bpp); -DisplayAllocator *register_displayallocator(DisplayState *ds, DisplayAllocator *da); - -static inline DisplaySurface* qemu_create_displaysurface(DisplayState *ds, int width, int height) -{ - return ds->allocator->create_displaysurface(width, height); -} - -static inline DisplaySurface* qemu_resize_displaysurface(DisplayState *ds, int width, int height) -{ - trace_displaysurface_resize(ds, ds->surface, width, height); - return ds->allocator->resize_displaysurface(ds->surface, width, height); -} - -static inline void qemu_free_displaysurface(DisplayState *ds) -{ - trace_displaysurface_free(ds, ds->surface); - ds->allocator->free_displaysurface(ds->surface); -} +DisplaySurface *qemu_create_displaysurface(DisplayState *ds, + int width, int height); +DisplaySurface *qemu_resize_displaysurface(DisplayState *ds, + int width, int height); +void qemu_free_displaysurface(DisplayState *ds); static inline int is_surface_bgr(DisplaySurface *surface) { @@ -229,8 +208,7 @@ static inline int is_surface_bgr(DisplaySurface *surface) static inline int is_buffer_shared(DisplaySurface *surface) { - return (!(surface->flags & QEMU_ALLOCATED_FLAG) && - !(surface->flags & QEMU_REALPIXELS_FLAG)); + return !(surface->flags & QEMU_ALLOCATED_FLAG); } void gui_setup_refresh(DisplayState *ds); diff --git a/qemu-common.h b/qemu-common.h index fdd0dbcf64..89cec1d817 100644 --- a/qemu-common.h +++ b/qemu-common.h @@ -262,7 +262,6 @@ typedef struct DriveInfo DriveInfo; typedef struct DisplayState DisplayState; typedef struct DisplayChangeListener DisplayChangeListener; typedef struct DisplaySurface DisplaySurface; -typedef struct DisplayAllocator DisplayAllocator; typedef struct PixelFormat PixelFormat; typedef struct QemuConsole QemuConsole; typedef struct CharDriverState CharDriverState; diff --git a/ui/sdl.c b/ui/sdl.c index c3ba79fe43..37f01b217d 100644 --- a/ui/sdl.c +++ b/ui/sdl.c @@ -55,7 +55,6 @@ static int absolute_enabled = 0; static int guest_cursor = 0; static int guest_x, guest_y; static SDL_Cursor *guest_sprite = NULL; -static uint8_t allocator; static SDL_PixelFormat host_format; static int scaling_active = 0; static Notifier mouse_mode_notifier; @@ -117,108 +116,13 @@ static void do_sdl_resize(int width, int height, int bpp) static void sdl_resize(DisplayState *ds) { - if (!allocator) { - if (!scaling_active) - do_sdl_resize(ds_get_width(ds), ds_get_height(ds), 0); - else if (real_screen->format->BitsPerPixel != ds_get_bits_per_pixel(ds)) - do_sdl_resize(real_screen->w, real_screen->h, ds_get_bits_per_pixel(ds)); - sdl_setdata(ds); - } else { - if (guest_screen != NULL) { - SDL_FreeSurface(guest_screen); - guest_screen = NULL; - } + if (!scaling_active) { + do_sdl_resize(ds_get_width(ds), ds_get_height(ds), 0); + } else if (real_screen->format->BitsPerPixel != ds_get_bits_per_pixel(ds)) { + do_sdl_resize(real_screen->w, real_screen->h, + ds_get_bits_per_pixel(ds)); } -} - -static PixelFormat sdl_to_qemu_pixelformat(SDL_PixelFormat *sdl_pf) -{ - PixelFormat qemu_pf; - - memset(&qemu_pf, 0x00, sizeof(PixelFormat)); - - qemu_pf.bits_per_pixel = sdl_pf->BitsPerPixel; - qemu_pf.bytes_per_pixel = sdl_pf->BytesPerPixel; - qemu_pf.depth = (qemu_pf.bits_per_pixel) == 32 ? 24 : (qemu_pf.bits_per_pixel); - - qemu_pf.rmask = sdl_pf->Rmask; - qemu_pf.gmask = sdl_pf->Gmask; - qemu_pf.bmask = sdl_pf->Bmask; - qemu_pf.amask = sdl_pf->Amask; - - qemu_pf.rshift = sdl_pf->Rshift; - qemu_pf.gshift = sdl_pf->Gshift; - qemu_pf.bshift = sdl_pf->Bshift; - qemu_pf.ashift = sdl_pf->Ashift; - - qemu_pf.rbits = 8 - sdl_pf->Rloss; - qemu_pf.gbits = 8 - sdl_pf->Gloss; - qemu_pf.bbits = 8 - sdl_pf->Bloss; - qemu_pf.abits = 8 - sdl_pf->Aloss; - - qemu_pf.rmax = ((1 << qemu_pf.rbits) - 1); - qemu_pf.gmax = ((1 << qemu_pf.gbits) - 1); - qemu_pf.bmax = ((1 << qemu_pf.bbits) - 1); - qemu_pf.amax = ((1 << qemu_pf.abits) - 1); - - return qemu_pf; -} - -static DisplaySurface* sdl_create_displaysurface(int width, int height) -{ - DisplaySurface *surface = (DisplaySurface*) g_malloc0(sizeof(DisplaySurface)); - - surface->width = width; - surface->height = height; - - if (scaling_active) { - int linesize; - PixelFormat pf; - if (host_format.BytesPerPixel != 2 && host_format.BytesPerPixel != 4) { - linesize = width * 4; - pf = qemu_default_pixelformat(32); - } else { - linesize = width * host_format.BytesPerPixel; - pf = sdl_to_qemu_pixelformat(&host_format); - } - qemu_alloc_display(surface, width, height, linesize, pf, 0); - return surface; - } - - if (host_format.BitsPerPixel == 16) - do_sdl_resize(width, height, 16); - else - do_sdl_resize(width, height, 32); - - surface->pf = sdl_to_qemu_pixelformat(real_screen->format); - surface->linesize = real_screen->pitch; - surface->data = real_screen->pixels; - -#ifdef HOST_WORDS_BIGENDIAN - surface->flags = QEMU_REALPIXELS_FLAG | QEMU_BIG_ENDIAN_FLAG; -#else - surface->flags = QEMU_REALPIXELS_FLAG; -#endif - allocator = 1; - - return surface; -} - -static void sdl_free_displaysurface(DisplaySurface *surface) -{ - allocator = 0; - if (surface == NULL) - return; - - if (surface->flags & QEMU_ALLOCATED_FLAG) - g_free(surface->data); - g_free(surface); -} - -static DisplaySurface* sdl_resize_displaysurface(DisplaySurface *surface, int width, int height) -{ - sdl_free_displaysurface(surface); - return sdl_create_displaysurface(width, height); + sdl_setdata(ds); } /* generic keyboard conversion */ @@ -949,7 +853,6 @@ void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) { int flags; uint8_t data = 0; - DisplayAllocator *da; const SDL_VideoInfo *vi; char *filename; @@ -1022,14 +925,6 @@ void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) dcl->dpy_cursor_define = sdl_mouse_define; register_displaychangelistener(ds, dcl); - da = g_malloc0(sizeof(DisplayAllocator)); - da->create_displaysurface = sdl_create_displaysurface; - da->resize_displaysurface = sdl_resize_displaysurface; - da->free_displaysurface = sdl_free_displaysurface; - if (register_displayallocator(ds, da) == da) { - dpy_gfx_resize(ds); - } - mouse_mode_notifier.notify = sdl_mouse_mode_change; qemu_add_mouse_mode_change_notifier(&mouse_mode_notifier); From 9f2c7d7d67c228ae6a02f50082f0c6d10703f483 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Thu, 27 Sep 2012 09:52:35 +0200 Subject: [PATCH 186/291] pixman: add submodule Add pixman submodule as fallback for old distros. Picking version 0.18.4. This is shipped by rhel6 and also the minimum version needed by spice so this should serve well as baseline. Signed-off-by: Gerd Hoffmann --- .gitmodules | 3 +++ pixman | 1 + 2 files changed, 4 insertions(+) create mode 160000 pixman diff --git a/.gitmodules b/.gitmodules index eca876f85d..cfa2af9f7a 100644 --- a/.gitmodules +++ b/.gitmodules @@ -19,3 +19,6 @@ [submodule "roms/sgabios"] path = roms/sgabios url = git://git.qemu.org/sgabios.git +[submodule "pixman"] + path = pixman + url = git://anongit.freedesktop.org/pixman diff --git a/pixman b/pixman new file mode 160000 index 0000000000..97336fad32 --- /dev/null +++ b/pixman @@ -0,0 +1 @@ +Subproject commit 97336fad32acf802003855cd8bd6477fa49a12e3 From 85e05d825f7a9ecc1b5100bdd553fcc682c8366e Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 26 Oct 2012 10:10:54 +0200 Subject: [PATCH 187/291] xhci: add {get,set}_field macros & enum for pls Add {get,set}_field macros (simliar to ehci) to read and update some bits of a word. Put them into use for updating pls (port link state) values. Also add a enum for pls values. Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci.c | 39 +++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 7b65741dd5..c062330f8a 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -146,6 +146,21 @@ typedef struct XHCITRB { bool ccs; } XHCITRB; +enum { + PLS_U0 = 0, + PLS_U1 = 1, + PLS_U2 = 2, + PLS_U3 = 3, + PLS_DISABLED = 4, + PLS_RX_DETECT = 5, + PLS_INACTIVE = 6, + PLS_POLLING = 7, + PLS_RECOVERY = 8, + PLS_HOT_RESET = 9, + PLS_COMPILANCE_MODE = 10, + PLS_TEST_MODE = 11, + PLS_RESUME = 15, +}; typedef enum TRBType { TRB_RESERVED = 0, @@ -287,6 +302,16 @@ typedef enum TRBCCode { typedef struct XHCIState XHCIState; +#define get_field(data, field) \ + (((data) >> field##_SHIFT) & field##_MASK) + +#define set_field(data, newval, field) do { \ + uint32_t val = *data; \ + val &= ~(field##_MASK << field##_SHIFT); \ + val |= ((newval) & field##_MASK) << field##_SHIFT; \ + *data = val; \ + } while (0) + typedef enum EPType { ET_INVALID = 0, ET_ISO_OUT, @@ -2334,7 +2359,7 @@ static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) } } - if (xhci_running(xhci)) { + if (xhci_running(port->xhci)) { port->portsc |= PORTSC_CSC; XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, port->portnr << 24}; @@ -2368,7 +2393,7 @@ static void xhci_reset(DeviceState *dev) } for (i = 0; i < xhci->numports; i++) { - xhci_update_port(xhci, xhci->ports + i, 0); + xhci_update_port(xhci->ports + i, 0); } for (i = 0; i < xhci->numintrs; i++) { @@ -2499,8 +2524,8 @@ static void xhci_port_write(void *ptr, hwaddr reg, PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); if (val & PORTSC_LWS) { /* overwrite PLS only when LWS=1 */ - portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); - portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT); + uint32_t pls = get_field(val, PORTSC_PLS); + set_field(&portsc, pls, PORTSC_PLS); } /* read/write bits */ portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); @@ -2832,13 +2857,11 @@ static void xhci_wakeup(USBPort *usbport) XHCIPort *port = xhci_lookup_port(xhci, usbport); XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, port->portnr << 24}; - uint32_t pls; - pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK; - if (pls != 3) { + if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { return; } - port->portsc |= 0xf << PORTSC_PLS_SHIFT; + set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); if (port->portsc & PORTSC_PLC) { return; } From f321402785f443d7b95e746aae686e28d74e344c Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 26 Oct 2012 10:13:13 +0200 Subject: [PATCH 188/291] xhci: s/xhci_update_port/xhci_port_update/ Rename the function for xhci_port_* naming scheme, also drop the xhci parameter as port carries a pointer to xhci anyway. Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index c062330f8a..f5ab6928ae 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2337,7 +2337,7 @@ static void xhci_process_commands(XHCIState *xhci) } } -static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) +static void xhci_port_update(XHCIPort *port, int is_detach) { port->portsc = PORTSC_PP; if (port->uport->dev && port->uport->dev->attached && !is_detach && @@ -2363,7 +2363,7 @@ static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach) port->portsc |= PORTSC_CSC; XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, port->portnr << 24}; - xhci_event(xhci, &ev, 0); + xhci_event(port->xhci, &ev, 0); DPRINTF("xhci: port change event for port %d\n", port->portnr); } } @@ -2393,7 +2393,7 @@ static void xhci_reset(DeviceState *dev) } for (i = 0; i < xhci->numports; i++) { - xhci_update_port(xhci->ports + i, 0); + xhci_port_update(xhci->ports + i, 0); } for (i = 0; i < xhci->numintrs; i++) { @@ -2840,7 +2840,7 @@ static void xhci_attach(USBPort *usbport) XHCIState *xhci = usbport->opaque; XHCIPort *port = xhci_lookup_port(xhci, usbport); - xhci_update_port(xhci, port, 0); + xhci_port_update(port, 0); } static void xhci_detach(USBPort *usbport) @@ -2848,7 +2848,7 @@ static void xhci_detach(USBPort *usbport) XHCIState *xhci = usbport->opaque; XHCIPort *port = xhci_lookup_port(xhci, usbport); - xhci_update_port(xhci, port, 1); + xhci_port_update(port, 1); } static void xhci_wakeup(USBPort *usbport) From 6a32f80f056b577d275268e4f6f3477ba721c94f Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 26 Oct 2012 10:15:47 +0200 Subject: [PATCH 189/291] xhci: add xhci_port_have_device Factor out the code which checks whenever a usb device is attached to the port in question. No functional change. Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci.c | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index f5ab6928ae..62cca90a3c 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2337,11 +2337,21 @@ static void xhci_process_commands(XHCIState *xhci) } } +static bool xhci_port_have_device(XHCIPort *port) +{ + if (!port->uport->dev || !port->uport->dev->attached) { + return false; /* no device present */ + } + if (!((1 << port->uport->dev->speed) & port->speedmask)) { + return false; /* speed mismatch */ + } + return true; +} + static void xhci_port_update(XHCIPort *port, int is_detach) { port->portsc = PORTSC_PP; - if (port->uport->dev && port->uport->dev->attached && !is_detach && - (1 << port->uport->dev->speed) & port->speedmask) { + if (!is_detach && xhci_port_have_device(port)) { port->portsc |= PORTSC_CCS; switch (port->uport->dev->speed) { case USB_SPEED_LOW: From f705a362800733c363f0458f75942f8dc61b7abb Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 26 Oct 2012 10:19:02 +0200 Subject: [PATCH 190/291] xhci: add xhci_port_notify Create a function to notify the guest about port status changes and put it into use. Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci.c | 31 +++++++++++++++++-------------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 62cca90a3c..3af463986d 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2348,6 +2348,21 @@ static bool xhci_port_have_device(XHCIPort *port) return true; } +static void xhci_port_notify(XHCIPort *port, uint32_t bits) +{ + XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, + port->portnr << 24 }; + + if ((port->portsc & bits) == bits) { + return; + } + port->portsc |= bits; + if (!xhci_running(port->xhci)) { + return; + } + xhci_event(port->xhci, &ev, 0); +} + static void xhci_port_update(XHCIPort *port, int is_detach) { port->portsc = PORTSC_PP; @@ -2369,13 +2384,7 @@ static void xhci_port_update(XHCIPort *port, int is_detach) } } - if (xhci_running(port->xhci)) { - port->portsc |= PORTSC_CSC; - XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, - port->portnr << 24}; - xhci_event(port->xhci, &ev, 0); - DPRINTF("xhci: port change event for port %d\n", port->portnr); - } + xhci_port_notify(port, PORTSC_CSC); } static void xhci_reset(DeviceState *dev) @@ -2865,18 +2874,12 @@ static void xhci_wakeup(USBPort *usbport) { XHCIState *xhci = usbport->opaque; XHCIPort *port = xhci_lookup_port(xhci, usbport); - XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, - port->portnr << 24}; if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { return; } set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); - if (port->portsc & PORTSC_PLC) { - return; - } - port->portsc |= PORTSC_PLC; - xhci_event(xhci, &ev, 0); + xhci_port_notify(port, PORTSC_PLC); } static void xhci_complete(USBPort *port, USBPacket *packet) From 40030130d167f2bf762155a1a7e0073de5545e8b Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 26 Oct 2012 10:22:37 +0200 Subject: [PATCH 191/291] xhci: add xhci_port_reset Move port reset logic to its own function. Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 3af463986d..1db803cda9 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2387,6 +2387,13 @@ static void xhci_port_update(XHCIPort *port, int is_detach) xhci_port_notify(port, PORTSC_CSC); } +static void xhci_port_reset(XHCIPort *port) +{ + DPRINTF("xhci: port %d reset\n", port); + usb_device_reset(port->uport->dev); + port->portsc |= PORTSC_PRC | PORTSC_PED; +} + static void xhci_reset(DeviceState *dev) { XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev); @@ -2549,13 +2556,11 @@ static void xhci_port_write(void *ptr, hwaddr reg, /* read/write bits */ portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); + port->portsc = portsc; /* write-1-to-start bits */ if (val & PORTSC_PR) { - DPRINTF("xhci: port %d reset\n", port); - usb_device_reset(port->uport->dev); - portsc |= PORTSC_PRC | PORTSC_PED; + xhci_port_reset(port); } - port->portsc = portsc; break; case 0x04: /* PORTPMSC */ case 0x08: /* PORTLI */ From b62b08282d9539a109b02e217d0cc7f7dcdb87ac Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 26 Oct 2012 10:30:53 +0200 Subject: [PATCH 192/291] xhci: set pls in xhci_port_update & xhci_port_reset Set the port link state to the correct values in xhci_port_update and xhci_port_reset functions. Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci.c | 26 ++++++++++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 1db803cda9..84d1b26bbb 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2365,33 +2365,55 @@ static void xhci_port_notify(XHCIPort *port, uint32_t bits) static void xhci_port_update(XHCIPort *port, int is_detach) { + uint32_t pls = PLS_RX_DETECT; + port->portsc = PORTSC_PP; if (!is_detach && xhci_port_have_device(port)) { port->portsc |= PORTSC_CCS; switch (port->uport->dev->speed) { case USB_SPEED_LOW: port->portsc |= PORTSC_SPEED_LOW; + pls = PLS_POLLING; break; case USB_SPEED_FULL: port->portsc |= PORTSC_SPEED_FULL; + pls = PLS_POLLING; break; case USB_SPEED_HIGH: port->portsc |= PORTSC_SPEED_HIGH; + pls = PLS_POLLING; break; case USB_SPEED_SUPER: port->portsc |= PORTSC_SPEED_SUPER; + port->portsc |= PORTSC_PED; + pls = PLS_U0; break; } } - + set_field(&port->portsc, pls, PORTSC_PLS); xhci_port_notify(port, PORTSC_CSC); } static void xhci_port_reset(XHCIPort *port) { DPRINTF("xhci: port %d reset\n", port); + if (!xhci_port_have_device(port)) { + return; + } + usb_device_reset(port->uport->dev); - port->portsc |= PORTSC_PRC | PORTSC_PED; + + switch (port->uport->dev->speed) { + case USB_SPEED_LOW: + case USB_SPEED_FULL: + case USB_SPEED_HIGH: + set_field(&port->portsc, PLS_U0, PORTSC_PLS); + port->portsc |= PORTSC_PED; + break; + } + + port->portsc &= ~PORTSC_PR; + xhci_port_notify(port, PORTSC_PRC); } static void xhci_reset(DeviceState *dev) From 4f47f0f82eccbda44bac929df94fa244bf3452bd Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 26 Oct 2012 11:49:06 +0200 Subject: [PATCH 193/291] xhci: add port trace points Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci.c | 6 +++++- trace-events | 2 ++ 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 84d1b26bbb..325963882d 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2391,12 +2391,14 @@ static void xhci_port_update(XHCIPort *port, int is_detach) } } set_field(&port->portsc, pls, PORTSC_PLS); + trace_usb_xhci_port_link(port->portnr, pls); xhci_port_notify(port, PORTSC_CSC); } static void xhci_port_reset(XHCIPort *port) { - DPRINTF("xhci: port %d reset\n", port); + trace_usb_xhci_port_reset(port->portnr); + if (!xhci_port_have_device(port)) { return; } @@ -2408,6 +2410,7 @@ static void xhci_port_reset(XHCIPort *port) case USB_SPEED_FULL: case USB_SPEED_HIGH: set_field(&port->portsc, PLS_U0, PORTSC_PLS); + trace_usb_xhci_port_link(port->portnr, PLS_U0); port->portsc |= PORTSC_PED; break; } @@ -2574,6 +2577,7 @@ static void xhci_port_write(void *ptr, hwaddr reg, /* overwrite PLS only when LWS=1 */ uint32_t pls = get_field(val, PORTSC_PLS); set_field(&portsc, pls, PORTSC_PLS); + trace_usb_xhci_port_link(port->portnr, pls); } /* read/write bits */ portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); diff --git a/trace-events b/trace-events index 7ee21e58ea..0cb991e789 100644 --- a/trace-events +++ b/trace-events @@ -333,6 +333,8 @@ usb_xhci_irq_msix_use(uint32_t nr) "nr %d" usb_xhci_irq_msix_unuse(uint32_t nr) "nr %d" usb_xhci_queue_event(uint32_t vector, uint32_t idx, const char *trb, const char *evt, uint64_t param, uint32_t status, uint32_t control) "v %d, idx %d, %s, %s, p %016" PRIx64 ", s %08x, c 0x%08x" usb_xhci_fetch_trb(uint64_t addr, const char *name, uint64_t param, uint32_t status, uint32_t control) "addr %016" PRIx64 ", %s, p %016" PRIx64 ", s %08x, c 0x%08x" +usb_xhci_port_reset(uint32_t port) "port %d" +usb_xhci_port_link(uint32_t port, uint32_t pls) "port %d, pls %d" usb_xhci_slot_enable(uint32_t slotid) "slotid %d" usb_xhci_slot_disable(uint32_t slotid) "slotid %d" usb_xhci_slot_address(uint32_t slotid) "slotid %d" From 0bc85da69e01f25c27f575ef0d57d29be4154d71 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 26 Oct 2012 13:09:56 +0200 Subject: [PATCH 194/291] xhci: allow address slot being called multiple times win8 guests do that for some reason ... Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-xhci.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 325963882d..900abf5566 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -483,6 +483,8 @@ enum xhci_flags { static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid); +static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, + unsigned int epid); static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); @@ -1075,8 +1077,7 @@ static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, slot = &xhci->slots[slotid-1]; if (slot->eps[epid-1]) { - fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid); - return CC_TRB_ERROR; + xhci_disable_ep(xhci, slotid, epid); } epctx = g_malloc(sizeof(XHCIEPContext)); @@ -1919,6 +1920,9 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, } for (i = 0; i < xhci->numslots; i++) { + if (i == slotid-1) { + continue; + } if (xhci->slots[i].uport == uport) { fprintf(stderr, "xhci: port %s already assigned to slot %d\n", uport->path, i+1); @@ -1936,6 +1940,7 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, slot->devaddr = xhci->devaddr++; slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr; DPRINTF("xhci: device address is %d\n", slot->devaddr); + usb_device_reset(dev); usb_device_handle_control(dev, NULL, DeviceOutRequest | USB_REQ_SET_ADDRESS, slot->devaddr, 0, 0, NULL); From 27a11324e07f23587abfac3f0fd2fd6fb536aa74 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 29 Oct 2012 11:34:34 +1000 Subject: [PATCH 195/291] usb/ehci: parameterise the register region offsets The capabilities register and operational register offsets can vary from one EHCI implementation to the next. Parameterise accordingly. Signed-off-by: Peter Crosthwaite Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-ehci.c | 68 +++++++++++++++++++++++++---------------------- 1 file changed, 36 insertions(+), 32 deletions(-) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index f14f9d7018..7f04322485 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -48,20 +48,18 @@ #define USB_RET_PROCERR (-99) #define MMIO_SIZE 0x1000 +#define CAPA_SIZE 0x10 /* Capability Registers Base Address - section 2.2 */ -#define CAPREGBASE 0x0000 -#define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved -#define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version # -#define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params -#define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params +#define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */ +#define HCIVERSION 0x0002 /* 2-bytes, i/f version # */ +#define HCSPARAMS 0x0004 /* 4-bytes, structural params */ +#define HCCPARAMS 0x0008 /* 4-bytes, capability params */ #define EECP HCCPARAMS + 1 -#define HCSPPORTROUTE1 CAPREGBASE + 0x000c -#define HCSPPORTROUTE2 CAPREGBASE + 0x0010 +#define HCSPPORTROUTE1 0x000c +#define HCSPPORTROUTE2 0x0010 -#define OPREGBASE 0x0020 // Operational Registers Base Address - -#define USBCMD OPREGBASE + 0x0000 +#define USBCMD 0x0000 #define USBCMD_RUNSTOP (1 << 0) // run / Stop #define USBCMD_HCRESET (1 << 1) // HC Reset #define USBCMD_FLS (3 << 2) // Frame List Size @@ -75,7 +73,7 @@ #define USBCMD_ITC (0x7f << 16) // Int Threshold Control #define USBCMD_ITC_SH 16 // Int Threshold Control Shift -#define USBSTS OPREGBASE + 0x0004 +#define USBSTS 0x0004 #define USBSTS_RO_MASK 0x0000003f #define USBSTS_INT (1 << 0) // USB Interrupt #define USBSTS_ERRINT (1 << 1) // Error Interrupt @@ -92,18 +90,18 @@ * Interrupt enable bits correspond to the interrupt active bits in USBSTS * so no need to redefine here. */ -#define USBINTR OPREGBASE + 0x0008 +#define USBINTR 0x0008 #define USBINTR_MASK 0x0000003f -#define FRINDEX OPREGBASE + 0x000c -#define CTRLDSSEGMENT OPREGBASE + 0x0010 -#define PERIODICLISTBASE OPREGBASE + 0x0014 -#define ASYNCLISTADDR OPREGBASE + 0x0018 +#define FRINDEX 0x000c +#define CTRLDSSEGMENT 0x0010 +#define PERIODICLISTBASE 0x0014 +#define ASYNCLISTADDR 0x0018 #define ASYNCLISTADDR_MASK 0xffffffe0 -#define CONFIGFLAG OPREGBASE + 0x0040 +#define CONFIGFLAG 0x0040 -#define PORTSC (OPREGBASE + 0x0044) +#define PORTSC 0x0044 #define PORTSC_BEGIN PORTSC #define PORTSC_END (PORTSC + 4 * NB_PORTS) /* @@ -395,6 +393,8 @@ struct EHCIState { MemoryRegion mem_opreg; MemoryRegion mem_ports; int companion_count; + uint16_t capsbase; + uint16_t opregbase; /* properties */ uint32_t maxframes; @@ -403,9 +403,9 @@ struct EHCIState { * EHCI spec version 1.0 Section 2.3 * Host Controller Operational Registers */ - uint8_t caps[OPREGBASE]; + uint8_t caps[CAPA_SIZE]; union { - uint32_t opreg[(PORTSC_BEGIN-OPREGBASE)/sizeof(uint32_t)]; + uint32_t opreg[PORTSC_BEGIN/sizeof(uint32_t)]; struct { uint32_t usbcmd; uint32_t usbsts; @@ -506,8 +506,7 @@ static const char *state2str(uint32_t state) static const char *addr2str(hwaddr addr) { - return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), - addr + OPREGBASE); + return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr); } static void ehci_trace_usbsts(uint32_t mask, int state) @@ -1115,7 +1114,7 @@ static uint64_t ehci_opreg_read(void *ptr, hwaddr addr, uint32_t val; val = s->opreg[addr >> 2]; - trace_usb_ehci_opreg_read(addr + OPREGBASE, addr2str(addr), val); + trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val); return val; } @@ -1211,9 +1210,9 @@ static void ehci_opreg_write(void *ptr, hwaddr addr, uint32_t old = *mmio; int i; - trace_usb_ehci_opreg_write(addr + OPREGBASE, addr2str(addr), val); + trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val); - switch (addr + OPREGBASE) { + switch (addr) { case USBCMD: if (val & USBCMD_HCRESET) { ehci_reset(s); @@ -1291,7 +1290,8 @@ static void ehci_opreg_write(void *ptr, hwaddr addr, } *mmio = val; - trace_usb_ehci_opreg_change(addr + OPREGBASE, addr2str(addr), *mmio, old); + trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr), + *mmio, old); } @@ -2731,8 +2731,11 @@ static int usb_ehci_initfn(PCIDevice *dev) pci_conf[0x6e] = 0x00; pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS + s->capsbase = 0x00; + s->opregbase = 0x20; + /* 2.2 host controller interface version */ - s->caps[0x00] = (uint8_t) OPREGBASE; + s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase); s->caps[0x01] = 0x00; s->caps[0x02] = 0x00; s->caps[0x03] = 0x01; /* HC version */ @@ -2765,15 +2768,16 @@ static int usb_ehci_initfn(PCIDevice *dev) memory_region_init(&s->mem, "ehci", MMIO_SIZE); memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s, - "capabilities", OPREGBASE); + "capabilities", CAPA_SIZE); memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s, - "operational", PORTSC_BEGIN - OPREGBASE); + "operational", PORTSC_BEGIN); memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s, "ports", PORTSC_END - PORTSC_BEGIN); - memory_region_add_subregion(&s->mem, 0, &s->mem_caps); - memory_region_add_subregion(&s->mem, OPREGBASE, &s->mem_opreg); - memory_region_add_subregion(&s->mem, PORTSC_BEGIN, &s->mem_ports); + memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps); + memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); + memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN, + &s->mem_ports); pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); From 7ae6ce0258096d3ad974d274aafcf130d5a31bb7 Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 29 Oct 2012 11:34:35 +1000 Subject: [PATCH 196/291] usb/ehci: Abstract away PCI DMA API Pull the DMAContext for the PCI DMA out at device init time and put it into the device state. Use dma_memory_read/write() instead of pci specific versions. Signed-off-by: Peter Crosthwaite Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-ehci.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 7f04322485..28890b5f84 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -389,6 +389,7 @@ struct EHCIState { USBBus bus; qemu_irq irq; MemoryRegion mem; + DMAContext *dma; MemoryRegion mem_caps; MemoryRegion mem_opreg; MemoryRegion mem_ports; @@ -1304,7 +1305,7 @@ static inline int get_dwords(EHCIState *ehci, uint32_t addr, int i; for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { - pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf)); + dma_memory_read(ehci->dma, addr, buf, sizeof(*buf)); *buf = le32_to_cpu(*buf); } @@ -1319,7 +1320,7 @@ static inline int put_dwords(EHCIState *ehci, uint32_t addr, for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { uint32_t tmp = cpu_to_le32(*buf); - pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp)); + dma_memory_write(ehci->dma, addr, &tmp, sizeof(tmp)); } return 1; @@ -1402,7 +1403,7 @@ static int ehci_init_transfer(EHCIPacket *p) cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE); bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES); offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK; - pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5); + qemu_sglist_init(&p->sgl, 5, p->queue->ehci->dma); while (bytes > 0) { if (cpage > 4) { @@ -1647,7 +1648,7 @@ static int ehci_process_itd(EHCIState *ehci, return USB_RET_PROCERR; } - pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2); + qemu_sglist_init(&ehci->isgl, 2, ehci->dma); if (off + len > 4096) { /* transfer crosses page border */ uint32_t len2 = off + len - 4096; @@ -2402,7 +2403,7 @@ static void ehci_advance_periodic_state(EHCIState *ehci) } list |= ((ehci->frindex & 0x1ff8) >> 1); - pci_dma_read(&ehci->dev, list, &entry, sizeof entry); + dma_memory_read(ehci->dma, list, &entry, sizeof entry); entry = le32_to_cpu(entry); DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n", @@ -2750,6 +2751,8 @@ static int usb_ehci_initfn(PCIDevice *dev) s->irq = s->dev.irq[3]; + s->dma = pci_dma_context(dev); + usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); for(i = 0; i < NB_PORTS; i++) { usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, From 5010d4dc618b6b8e7c21129c487c06f6493f71fc Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 29 Oct 2012 11:34:36 +1000 Subject: [PATCH 197/291] usb/ehci: seperate out PCIisms Seperate the PCI stuff from the EHCI components. Extracted the PCIDevice out into a new wrapper struct to make EHCIState non-PCI-specific. Seperated tho non PCI init component out into a seperate "common" init function. Signed-off-by: Peter Crosthwaite Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-ehci.c | 124 +++++++++++++++++++++++++++------------------- 1 file changed, 72 insertions(+), 52 deletions(-) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 28890b5f84..59580fc80b 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -385,7 +385,6 @@ struct EHCIQueue { typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; struct EHCIState { - PCIDevice dev; USBBus bus; qemu_irq irq; MemoryRegion mem; @@ -447,6 +446,11 @@ struct EHCIState { bool int_req_by_async; }; +typedef struct EHCIPCIState { + PCIDevice pcidev; + EHCIState ehci; +} EHCIPCIState; + #define SET_LAST_RUN_CLOCK(s) \ (s)->last_run_ns = qemu_get_clock_ns(vm_clock); @@ -2553,7 +2557,7 @@ static const MemoryRegionOps ehci_mmio_port_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static int usb_ehci_initfn(PCIDevice *dev); +static int usb_ehci_pci_initfn(PCIDevice *dev); static USBPortOps ehci_port_ops = { .attach = ehci_attach, @@ -2614,12 +2618,11 @@ static void usb_ehci_vm_state_change(void *opaque, int running, RunState state) } static const VMStateDescription vmstate_ehci = { - .name = "ehci", + .name = "ehci-core", .version_id = 2, .minimum_version_id = 1, .post_load = usb_ehci_post_load, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(dev, EHCIState), /* mmio registers */ VMSTATE_UINT32(usbcmd, EHCIState), VMSTATE_UINT32(usbsts, EHCIState), @@ -2650,8 +2653,19 @@ static const VMStateDescription vmstate_ehci = { } }; -static Property ehci_properties[] = { - DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128), +static const VMStateDescription vmstate_ehci_pci = { + .name = "ehci", + .version_id = 2, + .minimum_version_id = 1, + .post_load = usb_ehci_post_load, + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(pcidev, EHCIPCIState), + VMSTATE_STRUCT(ehci, EHCIPCIState, 2, vmstate_ehci, EHCIState), + } +}; + +static Property ehci_pci_properties[] = { + DEFINE_PROP_UINT32("maxframes", EHCIPCIState, ehci.maxframes, 128), DEFINE_PROP_END_OF_LIST(), }; @@ -2660,13 +2674,13 @@ static void ehci_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - k->init = usb_ehci_initfn; + k->init = usb_ehci_pci_initfn; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ k->revision = 0x10; k->class_id = PCI_CLASS_SERIAL_USB; dc->vmsd = &vmstate_ehci; - dc->props = ehci_properties; + dc->props = ehci_pci_properties; } static TypeInfo ehci_info = { @@ -2681,13 +2695,13 @@ static void ich9_ehci_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - k->init = usb_ehci_initfn; + k->init = usb_ehci_pci_initfn; k->vendor_id = PCI_VENDOR_ID_INTEL; k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; k->revision = 0x03; k->class_id = PCI_CLASS_SERIAL_USB; dc->vmsd = &vmstate_ehci; - dc->props = ehci_properties; + dc->props = ehci_pci_properties; } static TypeInfo ich9_ehci_info = { @@ -2697,44 +2711,10 @@ static TypeInfo ich9_ehci_info = { .class_init = ich9_ehci_class_init, }; -static int usb_ehci_initfn(PCIDevice *dev) +static void usb_ehci_initfn(EHCIState *s, DeviceState *dev) { - EHCIState *s = DO_UPCAST(EHCIState, dev, dev); - uint8_t *pci_conf = s->dev.config; int i; - pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); - - /* capabilities pointer */ - pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); - //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); - - pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ - pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); - pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); - - // pci_conf[0x50] = 0x01; // power management caps - - pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4) - pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5) - pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6) - - pci_conf[0x64] = 0x00; - pci_conf[0x65] = 0x00; - pci_conf[0x66] = 0x00; - pci_conf[0x67] = 0x00; - pci_conf[0x68] = 0x01; - pci_conf[0x69] = 0x00; - pci_conf[0x6a] = 0x00; - pci_conf[0x6b] = 0x00; // USBLEGSUP - pci_conf[0x6c] = 0x00; - pci_conf[0x6d] = 0x00; - pci_conf[0x6e] = 0x00; - pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS - - s->capsbase = 0x00; - s->opregbase = 0x20; - /* 2.2 host controller interface version */ s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase); s->caps[0x01] = 0x00; @@ -2745,15 +2725,10 @@ static int usb_ehci_initfn(PCIDevice *dev) s->caps[0x06] = 0x00; s->caps[0x07] = 0x00; s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */ - s->caps[0x09] = 0x68; /* EECP */ s->caps[0x0a] = 0x00; s->caps[0x0b] = 0x00; - s->irq = s->dev.irq[3]; - - s->dma = pci_dma_context(dev); - - usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev); + usb_bus_new(&s->bus, &ehci_bus_ops, dev); for(i = 0; i < NB_PORTS; i++) { usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops, USB_SPEED_MASK_HIGH); @@ -2781,8 +2756,53 @@ static int usb_ehci_initfn(PCIDevice *dev) memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg); memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN, &s->mem_ports); +} - pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); +static int usb_ehci_pci_initfn(PCIDevice *dev) +{ + EHCIPCIState *i = DO_UPCAST(EHCIPCIState, pcidev, dev); + EHCIState *s = &i->ehci; + uint8_t *pci_conf = dev->config; + + pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); + + /* capabilities pointer */ + pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); + /* pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); */ + + pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ + pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); + pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); + + /* pci_conf[0x50] = 0x01; *//* power management caps */ + + pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); /* release # (2.1.4) */ + pci_set_byte(&pci_conf[0x61], 0x20); /* frame length adjustment (2.1.5) */ + pci_set_word(&pci_conf[0x62], 0x00); /* port wake up capability (2.1.6) */ + + pci_conf[0x64] = 0x00; + pci_conf[0x65] = 0x00; + pci_conf[0x66] = 0x00; + pci_conf[0x67] = 0x00; + pci_conf[0x68] = 0x01; + pci_conf[0x69] = 0x00; + pci_conf[0x6a] = 0x00; + pci_conf[0x6b] = 0x00; /* USBLEGSUP */ + pci_conf[0x6c] = 0x00; + pci_conf[0x6d] = 0x00; + pci_conf[0x6e] = 0x00; + pci_conf[0x6f] = 0xc0; /* USBLEFCTLSTS */ + + s->caps[0x09] = 0x68; /* EECP */ + + s->irq = dev->irq[3]; + s->dma = pci_dma_context(dev); + + s->capsbase = 0x00; + s->opregbase = 0x20; + + usb_ehci_initfn(s, DEVICE(dev)); + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); return 0; } From 569c7fc8400ea3a7b13589af889003208aaae2ed Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 29 Oct 2012 11:34:39 +1000 Subject: [PATCH 198/291] usb/ehci: Guard definition of EHCI_DEBUG Guard against re-definition of EHCI_DEBUG. Allows for turning on of debug info from configure (using --qemu-extra-cflags="-DEHCI_DEBUG=1") rather than source code hacking. Signed-off-by: Peter Crosthwaite Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-ehci.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index 59580fc80b..d3168c954d 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -36,7 +36,9 @@ #include "dma.h" #include "sysemu.h" +#ifndef EHCI_DEBUG #define EHCI_DEBUG 0 +#endif #if EHCI_DEBUG #define DPRINTF printf From 0bf96f9457cdaf620bb8195a971bbdcc732ba32b Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 30 Oct 2012 12:20:06 +0100 Subject: [PATCH 199/291] usb/ehci: split into multiple source files Signed-off-by: Gerd Hoffmann --- hw/usb/Makefile.objs | 2 +- hw/usb/hcd-ehci-pci.c | 138 ++++++++++++++ hw/usb/hcd-ehci.c | 426 +----------------------------------------- hw/usb/hcd-ehci.h | 320 +++++++++++++++++++++++++++++++ 4 files changed, 462 insertions(+), 424 deletions(-) create mode 100644 hw/usb/hcd-ehci-pci.c create mode 100644 hw/usb/hcd-ehci.h diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs index 6425c1ff73..5c7b024103 100644 --- a/hw/usb/Makefile.objs +++ b/hw/usb/Makefile.objs @@ -1,6 +1,6 @@ common-obj-$(CONFIG_USB_UHCI) += hcd-uhci.o common-obj-$(CONFIG_USB_OHCI) += hcd-ohci.o -common-obj-$(CONFIG_USB_EHCI) += hcd-ehci.o +common-obj-$(CONFIG_USB_EHCI) += hcd-ehci.o hcd-ehci-pci.o common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o common-obj-y += libhw.o diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c new file mode 100644 index 0000000000..daac41d7f8 --- /dev/null +++ b/hw/usb/hcd-ehci-pci.c @@ -0,0 +1,138 @@ +/* + * QEMU USB EHCI Emulation + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or(at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "hw/usb/hcd-ehci.h" +#include "hw/pci.h" + +typedef struct EHCIPCIState { + PCIDevice pcidev; + EHCIState ehci; +} EHCIPCIState; + +static int usb_ehci_pci_initfn(PCIDevice *dev) +{ + EHCIPCIState *i = DO_UPCAST(EHCIPCIState, pcidev, dev); + EHCIState *s = &i->ehci; + uint8_t *pci_conf = dev->config; + + pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); + + /* capabilities pointer */ + pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); + /* pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); */ + + pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ + pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); + pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); + + /* pci_conf[0x50] = 0x01; *//* power management caps */ + + pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); /* release # (2.1.4) */ + pci_set_byte(&pci_conf[0x61], 0x20); /* frame length adjustment (2.1.5) */ + pci_set_word(&pci_conf[0x62], 0x00); /* port wake up capability (2.1.6) */ + + pci_conf[0x64] = 0x00; + pci_conf[0x65] = 0x00; + pci_conf[0x66] = 0x00; + pci_conf[0x67] = 0x00; + pci_conf[0x68] = 0x01; + pci_conf[0x69] = 0x00; + pci_conf[0x6a] = 0x00; + pci_conf[0x6b] = 0x00; /* USBLEGSUP */ + pci_conf[0x6c] = 0x00; + pci_conf[0x6d] = 0x00; + pci_conf[0x6e] = 0x00; + pci_conf[0x6f] = 0xc0; /* USBLEFCTLSTS */ + + s->caps[0x09] = 0x68; /* EECP */ + + s->irq = dev->irq[3]; + s->dma = pci_dma_context(dev); + + s->capsbase = 0x00; + s->opregbase = 0x20; + + usb_ehci_initfn(s, DEVICE(dev)); + pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); + + return 0; +} + +static Property ehci_pci_properties[] = { + DEFINE_PROP_UINT32("maxframes", EHCIPCIState, ehci.maxframes, 128), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_ehci_pci = { + .name = "ehci", + .version_id = 2, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(pcidev, EHCIPCIState), + VMSTATE_STRUCT(ehci, EHCIPCIState, 2, vmstate_ehci, EHCIState), + } +}; + +static void ehci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->init = usb_ehci_pci_initfn; + k->vendor_id = PCI_VENDOR_ID_INTEL; + k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ + k->revision = 0x10; + k->class_id = PCI_CLASS_SERIAL_USB; + dc->vmsd = &vmstate_ehci; + dc->props = ehci_pci_properties; +} + +static TypeInfo ehci_info = { + .name = "usb-ehci", + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(EHCIState), + .class_init = ehci_class_init, +}; + +static void ich9_ehci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->init = usb_ehci_pci_initfn; + k->vendor_id = PCI_VENDOR_ID_INTEL; + k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; + k->revision = 0x03; + k->class_id = PCI_CLASS_SERIAL_USB; + dc->vmsd = &vmstate_ehci; + dc->props = ehci_pci_properties; +} + +static TypeInfo ich9_ehci_info = { + .name = "ich9-usb-ehci1", + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(EHCIState), + .class_init = ich9_ehci_class_init, +}; + +static void ehci_pci_register_types(void) +{ + type_register_static(&ehci_info); + type_register_static(&ich9_ehci_info); +} + +type_init(ehci_pci_register_types) diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index d3168c954d..d9dc576e7c 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -27,31 +27,11 @@ * along with this program; if not, see . */ -#include "hw/hw.h" -#include "qemu-timer.h" -#include "hw/usb.h" -#include "hw/pci.h" -#include "monitor.h" -#include "trace.h" -#include "dma.h" -#include "sysemu.h" - -#ifndef EHCI_DEBUG -#define EHCI_DEBUG 0 -#endif - -#if EHCI_DEBUG -#define DPRINTF printf -#else -#define DPRINTF(...) -#endif +#include "hw/usb/hcd-ehci.h" /* internal processing - reset HC to try and recover */ #define USB_RET_PROCERR (-99) -#define MMIO_SIZE 0x1000 -#define CAPA_SIZE 0x10 - /* Capability Registers Base Address - section 2.2 */ #define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */ #define HCIVERSION 0x0002 /* 2-bytes, i/f version # */ @@ -103,9 +83,6 @@ #define CONFIGFLAG 0x0040 -#define PORTSC 0x0044 -#define PORTSC_BEGIN PORTSC -#define PORTSC_END (PORTSC + 4 * NB_PORTS) /* * Bits that are reserved or are read-only are masked out of values * written to us by software @@ -137,7 +114,6 @@ #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ) #define NB_MAXINTRATE 8 // Max rate at which controller issues ints -#define NB_PORTS 6 // Number of downstream ports #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction #define MAX_QH 100 // Max allowable queue heads in a chain #define MIN_FR_PER_TICK 3 // Min frames to process when catching up @@ -174,285 +150,6 @@ typedef enum { #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor #define NLPTR_TYPE_FSTN 3 // frame span traversal node - -/* EHCI spec version 1.0 Section 3.3 - */ -typedef struct EHCIitd { - uint32_t next; - - uint32_t transact[8]; -#define ITD_XACT_ACTIVE (1 << 31) -#define ITD_XACT_DBERROR (1 << 30) -#define ITD_XACT_BABBLE (1 << 29) -#define ITD_XACT_XACTERR (1 << 28) -#define ITD_XACT_LENGTH_MASK 0x0fff0000 -#define ITD_XACT_LENGTH_SH 16 -#define ITD_XACT_IOC (1 << 15) -#define ITD_XACT_PGSEL_MASK 0x00007000 -#define ITD_XACT_PGSEL_SH 12 -#define ITD_XACT_OFFSET_MASK 0x00000fff - - uint32_t bufptr[7]; -#define ITD_BUFPTR_MASK 0xfffff000 -#define ITD_BUFPTR_SH 12 -#define ITD_BUFPTR_EP_MASK 0x00000f00 -#define ITD_BUFPTR_EP_SH 8 -#define ITD_BUFPTR_DEVADDR_MASK 0x0000007f -#define ITD_BUFPTR_DEVADDR_SH 0 -#define ITD_BUFPTR_DIRECTION (1 << 11) -#define ITD_BUFPTR_MAXPKT_MASK 0x000007ff -#define ITD_BUFPTR_MAXPKT_SH 0 -#define ITD_BUFPTR_MULT_MASK 0x00000003 -#define ITD_BUFPTR_MULT_SH 0 -} EHCIitd; - -/* EHCI spec version 1.0 Section 3.4 - */ -typedef struct EHCIsitd { - uint32_t next; // Standard next link pointer - uint32_t epchar; -#define SITD_EPCHAR_IO (1 << 31) -#define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 -#define SITD_EPCHAR_PORTNUM_SH 24 -#define SITD_EPCHAR_HUBADD_MASK 0x007f0000 -#define SITD_EPCHAR_HUBADDR_SH 16 -#define SITD_EPCHAR_EPNUM_MASK 0x00000f00 -#define SITD_EPCHAR_EPNUM_SH 8 -#define SITD_EPCHAR_DEVADDR_MASK 0x0000007f - - uint32_t uframe; -#define SITD_UFRAME_CMASK_MASK 0x0000ff00 -#define SITD_UFRAME_CMASK_SH 8 -#define SITD_UFRAME_SMASK_MASK 0x000000ff - - uint32_t results; -#define SITD_RESULTS_IOC (1 << 31) -#define SITD_RESULTS_PGSEL (1 << 30) -#define SITD_RESULTS_TBYTES_MASK 0x03ff0000 -#define SITD_RESULTS_TYBYTES_SH 16 -#define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 -#define SITD_RESULTS_CPROGMASK_SH 8 -#define SITD_RESULTS_ACTIVE (1 << 7) -#define SITD_RESULTS_ERR (1 << 6) -#define SITD_RESULTS_DBERR (1 << 5) -#define SITD_RESULTS_BABBLE (1 << 4) -#define SITD_RESULTS_XACTERR (1 << 3) -#define SITD_RESULTS_MISSEDUF (1 << 2) -#define SITD_RESULTS_SPLITXSTATE (1 << 1) - - uint32_t bufptr[2]; -#define SITD_BUFPTR_MASK 0xfffff000 -#define SITD_BUFPTR_CURROFF_MASK 0x00000fff -#define SITD_BUFPTR_TPOS_MASK 0x00000018 -#define SITD_BUFPTR_TPOS_SH 3 -#define SITD_BUFPTR_TCNT_MASK 0x00000007 - - uint32_t backptr; // Standard next link pointer -} EHCIsitd; - -/* EHCI spec version 1.0 Section 3.5 - */ -typedef struct EHCIqtd { - uint32_t next; // Standard next link pointer - uint32_t altnext; // Standard next link pointer - uint32_t token; -#define QTD_TOKEN_DTOGGLE (1 << 31) -#define QTD_TOKEN_TBYTES_MASK 0x7fff0000 -#define QTD_TOKEN_TBYTES_SH 16 -#define QTD_TOKEN_IOC (1 << 15) -#define QTD_TOKEN_CPAGE_MASK 0x00007000 -#define QTD_TOKEN_CPAGE_SH 12 -#define QTD_TOKEN_CERR_MASK 0x00000c00 -#define QTD_TOKEN_CERR_SH 10 -#define QTD_TOKEN_PID_MASK 0x00000300 -#define QTD_TOKEN_PID_SH 8 -#define QTD_TOKEN_ACTIVE (1 << 7) -#define QTD_TOKEN_HALT (1 << 6) -#define QTD_TOKEN_DBERR (1 << 5) -#define QTD_TOKEN_BABBLE (1 << 4) -#define QTD_TOKEN_XACTERR (1 << 3) -#define QTD_TOKEN_MISSEDUF (1 << 2) -#define QTD_TOKEN_SPLITXSTATE (1 << 1) -#define QTD_TOKEN_PING (1 << 0) - - uint32_t bufptr[5]; // Standard buffer pointer -#define QTD_BUFPTR_MASK 0xfffff000 -#define QTD_BUFPTR_SH 12 -} EHCIqtd; - -/* EHCI spec version 1.0 Section 3.6 - */ -typedef struct EHCIqh { - uint32_t next; // Standard next link pointer - - /* endpoint characteristics */ - uint32_t epchar; -#define QH_EPCHAR_RL_MASK 0xf0000000 -#define QH_EPCHAR_RL_SH 28 -#define QH_EPCHAR_C (1 << 27) -#define QH_EPCHAR_MPLEN_MASK 0x07FF0000 -#define QH_EPCHAR_MPLEN_SH 16 -#define QH_EPCHAR_H (1 << 15) -#define QH_EPCHAR_DTC (1 << 14) -#define QH_EPCHAR_EPS_MASK 0x00003000 -#define QH_EPCHAR_EPS_SH 12 -#define EHCI_QH_EPS_FULL 0 -#define EHCI_QH_EPS_LOW 1 -#define EHCI_QH_EPS_HIGH 2 -#define EHCI_QH_EPS_RESERVED 3 - -#define QH_EPCHAR_EP_MASK 0x00000f00 -#define QH_EPCHAR_EP_SH 8 -#define QH_EPCHAR_I (1 << 7) -#define QH_EPCHAR_DEVADDR_MASK 0x0000007f -#define QH_EPCHAR_DEVADDR_SH 0 - - /* endpoint capabilities */ - uint32_t epcap; -#define QH_EPCAP_MULT_MASK 0xc0000000 -#define QH_EPCAP_MULT_SH 30 -#define QH_EPCAP_PORTNUM_MASK 0x3f800000 -#define QH_EPCAP_PORTNUM_SH 23 -#define QH_EPCAP_HUBADDR_MASK 0x007f0000 -#define QH_EPCAP_HUBADDR_SH 16 -#define QH_EPCAP_CMASK_MASK 0x0000ff00 -#define QH_EPCAP_CMASK_SH 8 -#define QH_EPCAP_SMASK_MASK 0x000000ff -#define QH_EPCAP_SMASK_SH 0 - - uint32_t current_qtd; // Standard next link pointer - uint32_t next_qtd; // Standard next link pointer - uint32_t altnext_qtd; -#define QH_ALTNEXT_NAKCNT_MASK 0x0000001e -#define QH_ALTNEXT_NAKCNT_SH 1 - - uint32_t token; // Same as QTD token - uint32_t bufptr[5]; // Standard buffer pointer -#define BUFPTR_CPROGMASK_MASK 0x000000ff -#define BUFPTR_FRAMETAG_MASK 0x0000001f -#define BUFPTR_SBYTES_MASK 0x00000fe0 -#define BUFPTR_SBYTES_SH 5 -} EHCIqh; - -/* EHCI spec version 1.0 Section 3.7 - */ -typedef struct EHCIfstn { - uint32_t next; // Standard next link pointer - uint32_t backptr; // Standard next link pointer -} EHCIfstn; - -typedef struct EHCIPacket EHCIPacket; -typedef struct EHCIQueue EHCIQueue; -typedef struct EHCIState EHCIState; - -enum async_state { - EHCI_ASYNC_NONE = 0, - EHCI_ASYNC_INITIALIZED, - EHCI_ASYNC_INFLIGHT, - EHCI_ASYNC_FINISHED, -}; - -struct EHCIPacket { - EHCIQueue *queue; - QTAILQ_ENTRY(EHCIPacket) next; - - EHCIqtd qtd; /* copy of current QTD (being worked on) */ - uint32_t qtdaddr; /* address QTD read from */ - - USBPacket packet; - QEMUSGList sgl; - int pid; - enum async_state async; - int usb_status; -}; - -struct EHCIQueue { - EHCIState *ehci; - QTAILQ_ENTRY(EHCIQueue) next; - uint32_t seen; - uint64_t ts; - int async; - int transact_ctr; - - /* cached data from guest - needs to be flushed - * when guest removes an entry (doorbell, handshake sequence) - */ - EHCIqh qh; /* copy of current QH (being worked on) */ - uint32_t qhaddr; /* address QH read from */ - uint32_t qtdaddr; /* address QTD read from */ - USBDevice *dev; - QTAILQ_HEAD(pkts_head, EHCIPacket) packets; -}; - -typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; - -struct EHCIState { - USBBus bus; - qemu_irq irq; - MemoryRegion mem; - DMAContext *dma; - MemoryRegion mem_caps; - MemoryRegion mem_opreg; - MemoryRegion mem_ports; - int companion_count; - uint16_t capsbase; - uint16_t opregbase; - - /* properties */ - uint32_t maxframes; - - /* - * EHCI spec version 1.0 Section 2.3 - * Host Controller Operational Registers - */ - uint8_t caps[CAPA_SIZE]; - union { - uint32_t opreg[PORTSC_BEGIN/sizeof(uint32_t)]; - struct { - uint32_t usbcmd; - uint32_t usbsts; - uint32_t usbintr; - uint32_t frindex; - uint32_t ctrldssegment; - uint32_t periodiclistbase; - uint32_t asynclistaddr; - uint32_t notused[9]; - uint32_t configflag; - }; - }; - uint32_t portsc[NB_PORTS]; - - /* - * Internal states, shadow registers, etc - */ - QEMUTimer *frame_timer; - QEMUBH *async_bh; - uint32_t astate; /* Current state in asynchronous schedule */ - uint32_t pstate; /* Current state in periodic schedule */ - USBPort ports[NB_PORTS]; - USBPort *companion_ports[NB_PORTS]; - uint32_t usbsts_pending; - uint32_t usbsts_frindex; - EHCIQueueHead aqueues; - EHCIQueueHead pqueues; - - /* which address to look at next */ - uint32_t a_fetch_addr; - uint32_t p_fetch_addr; - - USBPacket ipacket; - QEMUSGList isgl; - - uint64_t last_run_ns; - uint32_t async_stepdown; - bool int_req_by_async; -}; - -typedef struct EHCIPCIState { - PCIDevice pcidev; - EHCIState ehci; -} EHCIPCIState; - #define SET_LAST_RUN_CLOCK(s) \ (s)->last_run_ns = qemu_get_clock_ns(vm_clock); @@ -2559,8 +2256,6 @@ static const MemoryRegionOps ehci_mmio_port_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static int usb_ehci_pci_initfn(PCIDevice *dev); - static USBPortOps ehci_port_ops = { .attach = ehci_attach, .detach = ehci_detach, @@ -2619,7 +2314,7 @@ static void usb_ehci_vm_state_change(void *opaque, int running, RunState state) } } -static const VMStateDescription vmstate_ehci = { +const VMStateDescription vmstate_ehci = { .name = "ehci-core", .version_id = 2, .minimum_version_id = 1, @@ -2655,65 +2350,7 @@ static const VMStateDescription vmstate_ehci = { } }; -static const VMStateDescription vmstate_ehci_pci = { - .name = "ehci", - .version_id = 2, - .minimum_version_id = 1, - .post_load = usb_ehci_post_load, - .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(pcidev, EHCIPCIState), - VMSTATE_STRUCT(ehci, EHCIPCIState, 2, vmstate_ehci, EHCIState), - } -}; - -static Property ehci_pci_properties[] = { - DEFINE_PROP_UINT32("maxframes", EHCIPCIState, ehci.maxframes, 128), - DEFINE_PROP_END_OF_LIST(), -}; - -static void ehci_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->init = usb_ehci_pci_initfn; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ - k->revision = 0x10; - k->class_id = PCI_CLASS_SERIAL_USB; - dc->vmsd = &vmstate_ehci; - dc->props = ehci_pci_properties; -} - -static TypeInfo ehci_info = { - .name = "usb-ehci", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(EHCIState), - .class_init = ehci_class_init, -}; - -static void ich9_ehci_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->init = usb_ehci_pci_initfn; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; - k->revision = 0x03; - k->class_id = PCI_CLASS_SERIAL_USB; - dc->vmsd = &vmstate_ehci; - dc->props = ehci_pci_properties; -} - -static TypeInfo ich9_ehci_info = { - .name = "ich9-usb-ehci1", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(EHCIState), - .class_init = ich9_ehci_class_init, -}; - -static void usb_ehci_initfn(EHCIState *s, DeviceState *dev) +void usb_ehci_initfn(EHCIState *s, DeviceState *dev) { int i; @@ -2760,63 +2397,6 @@ static void usb_ehci_initfn(EHCIState *s, DeviceState *dev) &s->mem_ports); } -static int usb_ehci_pci_initfn(PCIDevice *dev) -{ - EHCIPCIState *i = DO_UPCAST(EHCIPCIState, pcidev, dev); - EHCIState *s = &i->ehci; - uint8_t *pci_conf = dev->config; - - pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20); - - /* capabilities pointer */ - pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00); - /* pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50); */ - - pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */ - pci_set_byte(&pci_conf[PCI_MIN_GNT], 0); - pci_set_byte(&pci_conf[PCI_MAX_LAT], 0); - - /* pci_conf[0x50] = 0x01; *//* power management caps */ - - pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); /* release # (2.1.4) */ - pci_set_byte(&pci_conf[0x61], 0x20); /* frame length adjustment (2.1.5) */ - pci_set_word(&pci_conf[0x62], 0x00); /* port wake up capability (2.1.6) */ - - pci_conf[0x64] = 0x00; - pci_conf[0x65] = 0x00; - pci_conf[0x66] = 0x00; - pci_conf[0x67] = 0x00; - pci_conf[0x68] = 0x01; - pci_conf[0x69] = 0x00; - pci_conf[0x6a] = 0x00; - pci_conf[0x6b] = 0x00; /* USBLEGSUP */ - pci_conf[0x6c] = 0x00; - pci_conf[0x6d] = 0x00; - pci_conf[0x6e] = 0x00; - pci_conf[0x6f] = 0xc0; /* USBLEFCTLSTS */ - - s->caps[0x09] = 0x68; /* EECP */ - - s->irq = dev->irq[3]; - s->dma = pci_dma_context(dev); - - s->capsbase = 0x00; - s->opregbase = 0x20; - - usb_ehci_initfn(s, DEVICE(dev)); - pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem); - - return 0; -} - -static void ehci_register_types(void) -{ - type_register_static(&ehci_info); - type_register_static(&ich9_ehci_info); -} - -type_init(ehci_register_types) - /* * vim: expandtab ts=4 */ diff --git a/hw/usb/hcd-ehci.h b/hw/usb/hcd-ehci.h new file mode 100644 index 0000000000..0ec675c352 --- /dev/null +++ b/hw/usb/hcd-ehci.h @@ -0,0 +1,320 @@ +/* + * QEMU USB EHCI Emulation + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or(at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "hw/hw.h" +#include "qemu-timer.h" +#include "hw/usb.h" +#include "monitor.h" +#include "trace.h" +#include "dma.h" +#include "sysemu.h" + +#ifndef EHCI_DEBUG +#define EHCI_DEBUG 0 +#endif + +#if EHCI_DEBUG +#define DPRINTF printf +#else +#define DPRINTF(...) +#endif + +#define MMIO_SIZE 0x1000 +#define CAPA_SIZE 0x10 + +#define PORTSC 0x0044 +#define PORTSC_BEGIN PORTSC +#define PORTSC_END (PORTSC + 4 * NB_PORTS) + +#define NB_PORTS 6 /* Number of downstream ports */ + +typedef struct EHCIPacket EHCIPacket; +typedef struct EHCIQueue EHCIQueue; +typedef struct EHCIState EHCIState; + +/* EHCI spec version 1.0 Section 3.3 + */ +typedef struct EHCIitd { + uint32_t next; + + uint32_t transact[8]; +#define ITD_XACT_ACTIVE (1 << 31) +#define ITD_XACT_DBERROR (1 << 30) +#define ITD_XACT_BABBLE (1 << 29) +#define ITD_XACT_XACTERR (1 << 28) +#define ITD_XACT_LENGTH_MASK 0x0fff0000 +#define ITD_XACT_LENGTH_SH 16 +#define ITD_XACT_IOC (1 << 15) +#define ITD_XACT_PGSEL_MASK 0x00007000 +#define ITD_XACT_PGSEL_SH 12 +#define ITD_XACT_OFFSET_MASK 0x00000fff + + uint32_t bufptr[7]; +#define ITD_BUFPTR_MASK 0xfffff000 +#define ITD_BUFPTR_SH 12 +#define ITD_BUFPTR_EP_MASK 0x00000f00 +#define ITD_BUFPTR_EP_SH 8 +#define ITD_BUFPTR_DEVADDR_MASK 0x0000007f +#define ITD_BUFPTR_DEVADDR_SH 0 +#define ITD_BUFPTR_DIRECTION (1 << 11) +#define ITD_BUFPTR_MAXPKT_MASK 0x000007ff +#define ITD_BUFPTR_MAXPKT_SH 0 +#define ITD_BUFPTR_MULT_MASK 0x00000003 +#define ITD_BUFPTR_MULT_SH 0 +} EHCIitd; + +/* EHCI spec version 1.0 Section 3.4 + */ +typedef struct EHCIsitd { + uint32_t next; /* Standard next link pointer */ + uint32_t epchar; +#define SITD_EPCHAR_IO (1 << 31) +#define SITD_EPCHAR_PORTNUM_MASK 0x7f000000 +#define SITD_EPCHAR_PORTNUM_SH 24 +#define SITD_EPCHAR_HUBADD_MASK 0x007f0000 +#define SITD_EPCHAR_HUBADDR_SH 16 +#define SITD_EPCHAR_EPNUM_MASK 0x00000f00 +#define SITD_EPCHAR_EPNUM_SH 8 +#define SITD_EPCHAR_DEVADDR_MASK 0x0000007f + + uint32_t uframe; +#define SITD_UFRAME_CMASK_MASK 0x0000ff00 +#define SITD_UFRAME_CMASK_SH 8 +#define SITD_UFRAME_SMASK_MASK 0x000000ff + + uint32_t results; +#define SITD_RESULTS_IOC (1 << 31) +#define SITD_RESULTS_PGSEL (1 << 30) +#define SITD_RESULTS_TBYTES_MASK 0x03ff0000 +#define SITD_RESULTS_TYBYTES_SH 16 +#define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00 +#define SITD_RESULTS_CPROGMASK_SH 8 +#define SITD_RESULTS_ACTIVE (1 << 7) +#define SITD_RESULTS_ERR (1 << 6) +#define SITD_RESULTS_DBERR (1 << 5) +#define SITD_RESULTS_BABBLE (1 << 4) +#define SITD_RESULTS_XACTERR (1 << 3) +#define SITD_RESULTS_MISSEDUF (1 << 2) +#define SITD_RESULTS_SPLITXSTATE (1 << 1) + + uint32_t bufptr[2]; +#define SITD_BUFPTR_MASK 0xfffff000 +#define SITD_BUFPTR_CURROFF_MASK 0x00000fff +#define SITD_BUFPTR_TPOS_MASK 0x00000018 +#define SITD_BUFPTR_TPOS_SH 3 +#define SITD_BUFPTR_TCNT_MASK 0x00000007 + + uint32_t backptr; /* Standard next link pointer */ +} EHCIsitd; + +/* EHCI spec version 1.0 Section 3.5 + */ +typedef struct EHCIqtd { + uint32_t next; /* Standard next link pointer */ + uint32_t altnext; /* Standard next link pointer */ + uint32_t token; +#define QTD_TOKEN_DTOGGLE (1 << 31) +#define QTD_TOKEN_TBYTES_MASK 0x7fff0000 +#define QTD_TOKEN_TBYTES_SH 16 +#define QTD_TOKEN_IOC (1 << 15) +#define QTD_TOKEN_CPAGE_MASK 0x00007000 +#define QTD_TOKEN_CPAGE_SH 12 +#define QTD_TOKEN_CERR_MASK 0x00000c00 +#define QTD_TOKEN_CERR_SH 10 +#define QTD_TOKEN_PID_MASK 0x00000300 +#define QTD_TOKEN_PID_SH 8 +#define QTD_TOKEN_ACTIVE (1 << 7) +#define QTD_TOKEN_HALT (1 << 6) +#define QTD_TOKEN_DBERR (1 << 5) +#define QTD_TOKEN_BABBLE (1 << 4) +#define QTD_TOKEN_XACTERR (1 << 3) +#define QTD_TOKEN_MISSEDUF (1 << 2) +#define QTD_TOKEN_SPLITXSTATE (1 << 1) +#define QTD_TOKEN_PING (1 << 0) + + uint32_t bufptr[5]; /* Standard buffer pointer */ +#define QTD_BUFPTR_MASK 0xfffff000 +#define QTD_BUFPTR_SH 12 +} EHCIqtd; + +/* EHCI spec version 1.0 Section 3.6 + */ +typedef struct EHCIqh { + uint32_t next; /* Standard next link pointer */ + + /* endpoint characteristics */ + uint32_t epchar; +#define QH_EPCHAR_RL_MASK 0xf0000000 +#define QH_EPCHAR_RL_SH 28 +#define QH_EPCHAR_C (1 << 27) +#define QH_EPCHAR_MPLEN_MASK 0x07FF0000 +#define QH_EPCHAR_MPLEN_SH 16 +#define QH_EPCHAR_H (1 << 15) +#define QH_EPCHAR_DTC (1 << 14) +#define QH_EPCHAR_EPS_MASK 0x00003000 +#define QH_EPCHAR_EPS_SH 12 +#define EHCI_QH_EPS_FULL 0 +#define EHCI_QH_EPS_LOW 1 +#define EHCI_QH_EPS_HIGH 2 +#define EHCI_QH_EPS_RESERVED 3 + +#define QH_EPCHAR_EP_MASK 0x00000f00 +#define QH_EPCHAR_EP_SH 8 +#define QH_EPCHAR_I (1 << 7) +#define QH_EPCHAR_DEVADDR_MASK 0x0000007f +#define QH_EPCHAR_DEVADDR_SH 0 + + /* endpoint capabilities */ + uint32_t epcap; +#define QH_EPCAP_MULT_MASK 0xc0000000 +#define QH_EPCAP_MULT_SH 30 +#define QH_EPCAP_PORTNUM_MASK 0x3f800000 +#define QH_EPCAP_PORTNUM_SH 23 +#define QH_EPCAP_HUBADDR_MASK 0x007f0000 +#define QH_EPCAP_HUBADDR_SH 16 +#define QH_EPCAP_CMASK_MASK 0x0000ff00 +#define QH_EPCAP_CMASK_SH 8 +#define QH_EPCAP_SMASK_MASK 0x000000ff +#define QH_EPCAP_SMASK_SH 0 + + uint32_t current_qtd; /* Standard next link pointer */ + uint32_t next_qtd; /* Standard next link pointer */ + uint32_t altnext_qtd; +#define QH_ALTNEXT_NAKCNT_MASK 0x0000001e +#define QH_ALTNEXT_NAKCNT_SH 1 + + uint32_t token; /* Same as QTD token */ + uint32_t bufptr[5]; /* Standard buffer pointer */ +#define BUFPTR_CPROGMASK_MASK 0x000000ff +#define BUFPTR_FRAMETAG_MASK 0x0000001f +#define BUFPTR_SBYTES_MASK 0x00000fe0 +#define BUFPTR_SBYTES_SH 5 +} EHCIqh; + +/* EHCI spec version 1.0 Section 3.7 + */ +typedef struct EHCIfstn { + uint32_t next; /* Standard next link pointer */ + uint32_t backptr; /* Standard next link pointer */ +} EHCIfstn; + +enum async_state { + EHCI_ASYNC_NONE = 0, + EHCI_ASYNC_INITIALIZED, + EHCI_ASYNC_INFLIGHT, + EHCI_ASYNC_FINISHED, +}; + +struct EHCIPacket { + EHCIQueue *queue; + QTAILQ_ENTRY(EHCIPacket) next; + + EHCIqtd qtd; /* copy of current QTD (being worked on) */ + uint32_t qtdaddr; /* address QTD read from */ + + USBPacket packet; + QEMUSGList sgl; + int pid; + enum async_state async; + int usb_status; +}; + +struct EHCIQueue { + EHCIState *ehci; + QTAILQ_ENTRY(EHCIQueue) next; + uint32_t seen; + uint64_t ts; + int async; + int transact_ctr; + + /* cached data from guest - needs to be flushed + * when guest removes an entry (doorbell, handshake sequence) + */ + EHCIqh qh; /* copy of current QH (being worked on) */ + uint32_t qhaddr; /* address QH read from */ + uint32_t qtdaddr; /* address QTD read from */ + USBDevice *dev; + QTAILQ_HEAD(pkts_head, EHCIPacket) packets; +}; + +typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead; + +struct EHCIState { + USBBus bus; + qemu_irq irq; + MemoryRegion mem; + DMAContext *dma; + MemoryRegion mem_caps; + MemoryRegion mem_opreg; + MemoryRegion mem_ports; + int companion_count; + uint16_t capsbase; + uint16_t opregbase; + + /* properties */ + uint32_t maxframes; + + /* + * EHCI spec version 1.0 Section 2.3 + * Host Controller Operational Registers + */ + uint8_t caps[CAPA_SIZE]; + union { + uint32_t opreg[PORTSC_BEGIN/sizeof(uint32_t)]; + struct { + uint32_t usbcmd; + uint32_t usbsts; + uint32_t usbintr; + uint32_t frindex; + uint32_t ctrldssegment; + uint32_t periodiclistbase; + uint32_t asynclistaddr; + uint32_t notused[9]; + uint32_t configflag; + }; + }; + uint32_t portsc[NB_PORTS]; + + /* + * Internal states, shadow registers, etc + */ + QEMUTimer *frame_timer; + QEMUBH *async_bh; + uint32_t astate; /* Current state in asynchronous schedule */ + uint32_t pstate; /* Current state in periodic schedule */ + USBPort ports[NB_PORTS]; + USBPort *companion_ports[NB_PORTS]; + uint32_t usbsts_pending; + uint32_t usbsts_frindex; + EHCIQueueHead aqueues; + EHCIQueueHead pqueues; + + /* which address to look at next */ + uint32_t a_fetch_addr; + uint32_t p_fetch_addr; + + USBPacket ipacket; + QEMUSGList isgl; + + uint64_t last_run_ns; + uint32_t async_stepdown; + bool int_req_by_async; +}; + +extern const VMStateDescription vmstate_ehci; + +void usb_ehci_initfn(EHCIState *s, DeviceState *dev); From e433785a768391795e88fbbdd75bbd34859666d3 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 30 Oct 2012 15:08:37 +0100 Subject: [PATCH 200/291] usb/ehci: add sysbus variant Signed-off-by: Gerd Hoffmann --- hw/usb/Makefile.objs | 2 +- hw/usb/hcd-ehci-sysbus.c | 77 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 hw/usb/hcd-ehci-sysbus.c diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs index 5c7b024103..7669938abd 100644 --- a/hw/usb/Makefile.objs +++ b/hw/usb/Makefile.objs @@ -1,6 +1,6 @@ common-obj-$(CONFIG_USB_UHCI) += hcd-uhci.o common-obj-$(CONFIG_USB_OHCI) += hcd-ohci.o -common-obj-$(CONFIG_USB_EHCI) += hcd-ehci.o hcd-ehci-pci.o +common-obj-$(CONFIG_USB_EHCI) += hcd-ehci.o hcd-ehci-pci.o hcd-ehci-sysbus.o common-obj-$(CONFIG_USB_XHCI) += hcd-xhci.o common-obj-y += libhw.o diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c new file mode 100644 index 0000000000..1584079796 --- /dev/null +++ b/hw/usb/hcd-ehci-sysbus.c @@ -0,0 +1,77 @@ +/* + * QEMU USB EHCI Emulation + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or(at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ + +#include "hw/usb/hcd-ehci.h" +#include "hw/sysbus.h" + +typedef struct EHCISysBusState { + SysBusDevice busdev; + EHCIState ehci; +} EHCISysBusState; + +static const VMStateDescription vmstate_ehci_sysbus = { + .name = "ehci-sysbus", + .version_id = 2, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_STRUCT(ehci, EHCISysBusState, 2, vmstate_ehci, EHCIState), + VMSTATE_END_OF_LIST() + } +}; + +static Property ehci_sysbus_properties[] = { + DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128), + DEFINE_PROP_END_OF_LIST(), +}; + +static int usb_ehci_sysbus_initfn(SysBusDevice *dev) +{ + EHCISysBusState *i = FROM_SYSBUS(EHCISysBusState, dev); + EHCIState *s = &i->ehci; + + s->capsbase = 0x100; + s->opregbase = 0x140; + + usb_ehci_initfn(s, DEVICE(dev)); + sysbus_init_irq(dev, &s->irq); + sysbus_init_mmio(dev, &s->mem); + return 0; +} + +static void ehci_sysbus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); + + k->init = usb_ehci_sysbus_initfn; + dc->vmsd = &vmstate_ehci_sysbus; + dc->props = ehci_sysbus_properties; +} + +TypeInfo ehci_xlnx_type_info = { + .name = "xlnx,ps7-usb", + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(EHCISysBusState), + .class_init = ehci_sysbus_class_init, +}; + +static void ehci_sysbus_register_types(void) +{ + type_register_static(&ehci_xlnx_type_info); +} + +type_init(ehci_sysbus_register_types) From e2134eb9223edac82cc7aa2281779c92c920d579 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 25 Sep 2012 16:04:58 +0200 Subject: [PATCH 201/291] pixman: windup in configure & makefiles Signed-off-by: Gerd Hoffmann --- Makefile | 9 +++++++++ configure | 38 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/Makefile b/Makefile index b522b10195..e4866d9bd3 100644 --- a/Makefile +++ b/Makefile @@ -118,6 +118,15 @@ endif subdir-libcacard: $(oslib-obj-y) $(trace-obj-y) qemu-timer-common.o +subdir-pixman: pixman/Makefile + $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C pixman V="$(V)" all,) + +pixman/Makefile: $(SRC_PATH)/pixman/configure + (cd pixman; $(SRC_PATH)/pixman/configure --disable-shared --enable-static) + +$(SRC_PATH)/pixman/configure: + (cd $(SRC_PATH)/pixman; autoreconf -v --install) + $(filter %-softmmu,$(SUBDIR_RULES)): $(universal-obj-y) $(trace-obj-y) $(common-obj-y) $(extra-obj-y) subdir-libdis $(filter %-user,$(SUBDIR_RULES)): $(universal-obj-y) $(trace-obj-y) subdir-libdis-user subdir-libuser diff --git a/configure b/configure index 9c6ac875a5..79701ea27b 100755 --- a/configure +++ b/configure @@ -147,6 +147,7 @@ curses="" docs="" fdt="" nptl="" +pixman="" sdl="" virtfs="" vnc="yes" @@ -642,6 +643,10 @@ for opt do # configure to be used by RPM and similar macros that set # lots of directory switches by default. ;; + --with-system-pixman) pixman="system" + ;; + --without-system-pixman) pixman="internal" + ;; --disable-sdl) sdl="no" ;; --enable-sdl) sdl="yes" @@ -2094,6 +2099,34 @@ else exit 1 fi +########################################## +# pixman support probe + +if test "$pixman" = ""; then + if $pkg_config pixman-1 > /dev/null 2>&1; then + pixman="system" + else + pixman="internal" + fi +fi +if test "$pixman" = "system"; then + pixman_cflags=`$pkg_config --cflags pixman-1 2>/dev/null` + pixman_libs=`$pkg_config --libs pixman-1 2>/dev/null` +else + if test ! -d ${source_path}/pixman/pixman; then + echo "ERROR: pixman not present. Your options:" + echo " (1) Prefered: Install the pixman devel package (any recent" + echo " distro should have packages as Xorg needs pixman too)." + echo " (2) Fetch the pixman submodule, using:" + echo " git submodule update --init pixman" + exit 1 + fi + pixman_cflags="-I${source_path}/pixman/pixman" + pixman_libs="-Lpixman/pixman/.libs -lpixman-1" +fi +QEMU_CFLAGS="$QEMU_CFLAGS $pixman_cflags" +libs_softmmu="$libs_softmmu $pixman_libs" + ########################################## # libcap probe @@ -3142,6 +3175,7 @@ echo "-Werror enabled $werror" if test "$darwin" = "yes" ; then echo "Cocoa support $cocoa" fi +echo "pixman $pixman" echo "SDL support $sdl" echo "curses support $curses" echo "curl support $curl" @@ -3908,6 +3942,9 @@ if test "$target_softmmu" = "yes" ; then if test "$smartcard_nss" = "yes" ; then echo "subdir-$target: subdir-libcacard" >> $config_host_mak fi + if test "$pixman" = "internal" ; then + echo "subdir-$target: subdir-pixman" >> $config_host_mak + fi case "$target_arch2" in i386|x86_64) echo "CONFIG_HAVE_CORE_DUMP=y" >> $config_target_mak @@ -4111,6 +4148,7 @@ DIRS="$DIRS pc-bios/optionrom pc-bios/spapr-rtas" DIRS="$DIRS roms/seabios roms/vgabios" DIRS="$DIRS qapi-generated" DIRS="$DIRS libcacard libcacard/libcacard libcacard/trace" +DIRS="$DIRS pixman" FILES="Makefile tests/tcg/Makefile qdict-test-data.txt" FILES="$FILES tests/tcg/cris/Makefile tests/tcg/cris/.gdbinit" FILES="$FILES tests/tcg/lm32/Makefile libcacard/Makefile" From d2ec7e24a270ba72a151b506ac57c6cd21e3c587 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 25 Sep 2012 16:23:24 +0200 Subject: [PATCH 202/291] pixman: helper functions Add some helper functions which will be put into use by following patches. Signed-off-by: Gerd Hoffmann --- Makefile.objs | 1 + qemu-pixman.c | 60 +++++++++++++++++++++++++++++++++++++++++++++++++++ qemu-pixman.h | 32 +++++++++++++++++++++++++++ 3 files changed, 93 insertions(+) create mode 100644 qemu-pixman.c create mode 100644 qemu-pixman.h diff --git a/Makefile.objs b/Makefile.objs index 9eca179903..acca2854d1 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -65,6 +65,7 @@ common-obj-y = $(block-obj-y) blockdev.o blockdev-nbd.o block/ common-obj-y += net.o net/ common-obj-y += qom/ common-obj-y += readline.o console.o cursor.o +common-obj-y += qemu-pixman.o common-obj-y += $(oslib-obj-y) common-obj-$(CONFIG_WIN32) += os-win32.o common-obj-$(CONFIG_POSIX) += os-posix.o diff --git a/qemu-pixman.c b/qemu-pixman.c new file mode 100644 index 0000000000..7547ed74c1 --- /dev/null +++ b/qemu-pixman.c @@ -0,0 +1,60 @@ +#include "qemu-pixman.h" + +int qemu_pixman_get_type(int rshift, int gshift, int bshift) +{ + int type = PIXMAN_TYPE_OTHER; + + if (rshift > gshift && gshift > bshift) { + if (bshift == 0) { + type = PIXMAN_TYPE_ARGB; + } else { +#if PIXMAN_VERSION >= PIXMAN_VERSION_ENCODE(0, 21, 8) + type = PIXMAN_TYPE_RGBA; +#endif + } + } else if (rshift < gshift && gshift < bshift) { + if (rshift == 0) { + type = PIXMAN_TYPE_ABGR; + } else { + type = PIXMAN_TYPE_BGRA; + } + } + return type; +} + +pixman_format_code_t qemu_pixman_get_format(PixelFormat *pf) +{ + pixman_format_code_t format; + int type; + + type = qemu_pixman_get_type(pf->rshift, pf->gshift, pf->bshift); + format = PIXMAN_FORMAT(pf->bits_per_pixel, type, + pf->abits, pf->rbits, pf->gbits, pf->bbits); + if (!pixman_format_supported_source(format)) { + return 0; + } + return format; +} + +pixman_image_t *qemu_pixman_linebuf_create(pixman_format_code_t format, + int width) +{ + pixman_image_t *image = pixman_image_create_bits(format, width, 1, NULL, 0); + assert(image != NULL); + return image; +} + +void qemu_pixman_linebuf_fill(pixman_image_t *linebuf, pixman_image_t *fb, + int width, int y) +{ + pixman_image_composite(PIXMAN_OP_SRC, fb, NULL, linebuf, + 0, y, 0, 0, 0, 0, width, 1); +} + +void qemu_pixman_image_unref(pixman_image_t *image) +{ + if (image == NULL) { + return; + } + pixman_image_unref(image); +} diff --git a/qemu-pixman.h b/qemu-pixman.h new file mode 100644 index 0000000000..7652c41277 --- /dev/null +++ b/qemu-pixman.h @@ -0,0 +1,32 @@ +#ifndef QEMU_PIXMAN_H +#define QEMU_PIXMAN_H + +#include + +#include "console.h" + +/* + * pixman image formats are defined to be native endian, + * that means host byte order on qemu. So we go define + * fixed formats here for cases where it is needed, like + * feeding libjpeg / libpng and writing screenshots. + */ + +#ifdef HOST_WORDS_BIGENDIAN +# define PIXMAN_BE_r8g8b8 PIXMAN_r8g8b8 +#else +# define PIXMAN_BE_r8g8b8 PIXMAN_b8g8r8 +#endif + +/* -------------------------------------------------------------------- */ + +int qemu_pixman_get_type(int rshift, int gshift, int bshift); +pixman_format_code_t qemu_pixman_get_format(PixelFormat *pf); + +pixman_image_t *qemu_pixman_linebuf_create(pixman_format_code_t format, + int width); +void qemu_pixman_linebuf_fill(pixman_image_t *linebuf, pixman_image_t *fb, + int width, int y); +void qemu_pixman_image_unref(pixman_image_t *image); + +#endif /* QEMU_PIXMAN_H */ From 69c7777720c18d8afca7d9685c6dced1aae3a056 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 26 Sep 2012 15:20:05 +0200 Subject: [PATCH 203/291] pixman: add pixman image to DisplaySurface Surfaces are now allocated using pixman. DisplaySurface gets new struct fields with pixman image and data. DisplayChangeListeners can easily start using pixman now. Signed-off-by: Gerd Hoffmann --- console.c | 37 ++++++++++++++++++++++++------------- console.h | 3 +++ 2 files changed, 27 insertions(+), 13 deletions(-) diff --git a/console.c b/console.c index 71cc543b7b..5e1c5f560d 100644 --- a/console.c +++ b/console.c @@ -1319,18 +1319,23 @@ DisplaySurface *qemu_resize_displaysurface(DisplayState *ds, void qemu_alloc_display(DisplaySurface *surface, int width, int height, int linesize, PixelFormat pf, int newflags) { - void *data; surface->width = width; surface->height = height; surface->linesize = linesize; surface->pf = pf; - if (surface->flags & QEMU_ALLOCATED_FLAG) { - data = g_realloc(surface->data, - surface->linesize * surface->height); - } else { - data = g_malloc(surface->linesize * surface->height); - } - surface->data = (uint8_t *)data; + + qemu_pixman_image_unref(surface->image); + surface->image = NULL; + surface->data = NULL; + + surface->format = qemu_pixman_get_format(&pf); + assert(surface->format != 0); + surface->image = pixman_image_create_bits(surface->format, + width, height, + NULL, linesize); + assert(surface->image != NULL); + + surface->data = (uint8_t *)pixman_image_get_data(surface->image); surface->flags = newflags | QEMU_ALLOCATED_FLAG; #ifdef HOST_WORDS_BIGENDIAN surface->flags |= QEMU_BIG_ENDIAN_FLAG; @@ -1338,14 +1343,22 @@ void qemu_alloc_display(DisplaySurface *surface, int width, int height, } DisplaySurface *qemu_create_displaysurface_from(int width, int height, int bpp, - int linesize, uint8_t *data) + int linesize, uint8_t *data) { - DisplaySurface *surface = (DisplaySurface*) g_malloc0(sizeof(DisplaySurface)); + DisplaySurface *surface = g_new0(DisplaySurface, 1); surface->width = width; surface->height = height; surface->linesize = linesize; surface->pf = qemu_default_pixelformat(bpp); + + surface->format = qemu_pixman_get_format(&surface->pf); + assert(surface->format != 0); + surface->image = pixman_image_create_bits(surface->format, + width, height, + (void *)data, linesize); + assert(surface->image != NULL); + #ifdef HOST_WORDS_BIGENDIAN surface->flags = QEMU_BIG_ENDIAN_FLAG; #endif @@ -1360,9 +1373,7 @@ void qemu_free_displaysurface(DisplayState *ds) if (ds->surface == NULL) { return; } - if (ds->surface->flags & QEMU_ALLOCATED_FLAG) { - g_free(ds->surface->data); - } + qemu_pixman_image_unref(ds->surface->image); g_free(ds->surface); } diff --git a/console.h b/console.h index 6be880a554..f19e6a443b 100644 --- a/console.h +++ b/console.h @@ -2,6 +2,7 @@ #define CONSOLE_H #include "qemu-char.h" +#include "qemu-pixman.h" #include "qdict.h" #include "notify.h" #include "monitor.h" @@ -119,6 +120,8 @@ struct PixelFormat { }; struct DisplaySurface { + pixman_format_code_t format; + pixman_image_t *image; uint8_t flags; int width; int height; From 537a43913c19973adc4153d30498591f92a90359 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Thu, 27 Sep 2012 11:06:36 +0200 Subject: [PATCH 204/291] console: make qemu_alloc_display static Signed-off-by: Gerd Hoffmann --- console.c | 48 ++++++++++++++++++++++++------------------------ console.h | 2 -- 2 files changed, 24 insertions(+), 26 deletions(-) diff --git a/console.c b/console.c index 5e1c5f560d..48d88e43ce 100644 --- a/console.c +++ b/console.c @@ -1294,30 +1294,8 @@ static QemuConsole *new_console(DisplayState *ds, console_type_t console_type) return s; } -DisplaySurface *qemu_create_displaysurface(DisplayState *ds, - int width, int height) -{ - DisplaySurface *surface = g_new0(DisplaySurface, 1); - - int linesize = width * 4; - qemu_alloc_display(surface, width, height, linesize, - qemu_default_pixelformat(32), 0); - return surface; -} - -DisplaySurface *qemu_resize_displaysurface(DisplayState *ds, - int width, int height) -{ - int linesize = width * 4; - - trace_displaysurface_resize(ds, ds->surface, width, height); - qemu_alloc_display(ds->surface, width, height, linesize, - qemu_default_pixelformat(32), 0); - return ds->surface; -} - -void qemu_alloc_display(DisplaySurface *surface, int width, int height, - int linesize, PixelFormat pf, int newflags) +static void qemu_alloc_display(DisplaySurface *surface, int width, int height, + int linesize, PixelFormat pf, int newflags) { surface->width = width; surface->height = height; @@ -1342,6 +1320,28 @@ void qemu_alloc_display(DisplaySurface *surface, int width, int height, #endif } +DisplaySurface *qemu_create_displaysurface(DisplayState *ds, + int width, int height) +{ + DisplaySurface *surface = g_new0(DisplaySurface, 1); + + int linesize = width * 4; + qemu_alloc_display(surface, width, height, linesize, + qemu_default_pixelformat(32), 0); + return surface; +} + +DisplaySurface *qemu_resize_displaysurface(DisplayState *ds, + int width, int height) +{ + int linesize = width * 4; + + trace_displaysurface_resize(ds, ds->surface, width, height); + qemu_alloc_display(ds->surface, width, height, linesize, + qemu_default_pixelformat(32), 0); + return ds->surface; +} + DisplaySurface *qemu_create_displaysurface_from(int width, int height, int bpp, int linesize, uint8_t *data) { diff --git a/console.h b/console.h index f19e6a443b..21bd957d95 100644 --- a/console.h +++ b/console.h @@ -190,8 +190,6 @@ void register_displaystate(DisplayState *ds); DisplayState *get_displaystate(void); DisplaySurface* qemu_create_displaysurface_from(int width, int height, int bpp, int linesize, uint8_t *data); -void qemu_alloc_display(DisplaySurface *surface, int width, int height, - int linesize, PixelFormat pf, int newflags); PixelFormat qemu_different_endianness_pixelformat(int bpp); PixelFormat qemu_default_pixelformat(int bpp); From 09bbb0ae8226c71aba440bdfa6fca300acd9e5d4 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 10 Oct 2012 11:16:26 +0200 Subject: [PATCH 205/291] console: don't set PixelFormat alpha fields for 32bpp Currently it is inconstent, PixelFormat->amask is left unset whereas abits and amax and ashift are filled. As an alpha channel doesn't make sense for the vga framebuffer leave all alpha fields clear. Signed-off-by: Gerd Hoffmann --- console.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/console.c b/console.c index 48d88e43ce..d28b75ec7d 100644 --- a/console.c +++ b/console.c @@ -1715,18 +1715,15 @@ PixelFormat qemu_default_pixelformat(int bpp) pf.rmask = 0x00FF0000; pf.gmask = 0x0000FF00; pf.bmask = 0x000000FF; - pf.amax = 255; pf.rmax = 255; pf.gmax = 255; pf.bmax = 255; - pf.ashift = 24; pf.rshift = 16; pf.gshift = 8; pf.bshift = 0; pf.rbits = 8; pf.gbits = 8; pf.bbits = 8; - pf.abits = 8; break; default: break; From b6e9f63711ea19b110574e384477bad4ea74f4a2 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 10 Oct 2012 13:02:14 +0200 Subject: [PATCH 206/291] qxl: stop direct access to DisplaySurface fields. Signed-off-by: Gerd Hoffmann --- hw/qxl-render.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/qxl-render.c b/hw/qxl-render.c index 47eb8b4154..98ecb21405 100644 --- a/hw/qxl-render.c +++ b/hw/qxl-render.c @@ -24,7 +24,7 @@ static void qxl_blit(PCIQXLDevice *qxl, QXLRect *rect) { uint8_t *src; - uint8_t *dst = qxl->vga.ds->surface->data; + uint8_t *dst = ds_get_data(qxl->vga.ds); int len, i; if (is_buffer_shared(qxl->vga.ds->surface)) { From 1fd2510a3786fb557919cdd71e8e65c504439ddc Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 10 Oct 2012 13:05:05 +0200 Subject: [PATCH 207/291] vga: stop direct access to DisplaySurface fields. Signed-off-by: Gerd Hoffmann --- hw/vga.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/vga.c b/hw/vga.c index f31dbdd652..1188463208 100644 --- a/hw/vga.c +++ b/hw/vga.c @@ -1709,8 +1709,13 @@ static void vga_draw_graphic(VGACommonState *s, int full_update) s->last_depth = depth; full_update = 1; } else if (is_buffer_shared(s->ds->surface) && - (full_update || s->ds->surface->data != s->vram_ptr + (s->start_addr * 4))) { - s->ds->surface->data = s->vram_ptr + (s->start_addr * 4); + (full_update || ds_get_data(s->ds) != s->vram_ptr + + (s->start_addr * 4))) { + qemu_free_displaysurface(s->ds); + s->ds->surface = qemu_create_displaysurface_from(disp_width, + height, depth, + s->line_offset, + s->vram_ptr + (s->start_addr * 4)); dpy_gfx_setdata(s->ds); } From b12f32c408ef8cb9b3a4dfcb3710b382fd24a3ee Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 10 Oct 2012 13:12:58 +0200 Subject: [PATCH 208/291] pixman: switch screendump function. Signed-off-by: Gerd Hoffmann --- hw/vga.c | 39 +++++++++++---------------------------- 1 file changed, 11 insertions(+), 28 deletions(-) diff --git a/hw/vga.c b/hw/vga.c index 1188463208..023134ef68 100644 --- a/hw/vga.c +++ b/hw/vga.c @@ -2393,13 +2393,12 @@ void vga_init_vbe(VGACommonState *s, MemoryRegion *system_memory) void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp) { + int width = pixman_image_get_width(ds->image); + int height = pixman_image_get_height(ds->image); FILE *f; - uint8_t *d, *d1; - uint32_t v; - int y, x; - uint8_t r, g, b; + int y; int ret; - char *linebuf, *pbuf; + pixman_image_t *linebuf; trace_ppm_save(filename, ds); f = fopen(filename, "wb"); @@ -2408,33 +2407,17 @@ void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp) strerror(errno)); return; } - ret = fprintf(f, "P6\n%d %d\n%d\n", ds->width, ds->height, 255); + ret = fprintf(f, "P6\n%d %d\n%d\n", width, height, 255); if (ret < 0) { linebuf = NULL; goto write_err; } - linebuf = g_malloc(ds->width * 3); - d1 = ds->data; - for(y = 0; y < ds->height; y++) { - d = d1; - pbuf = linebuf; - for(x = 0; x < ds->width; x++) { - if (ds->pf.bits_per_pixel == 32) - v = *(uint32_t *)d; - else - v = (uint32_t) (*(uint16_t *)d); - /* Limited to 8 or fewer bits per channel: */ - r = ((v >> ds->pf.rshift) & ds->pf.rmax) << (8 - ds->pf.rbits); - g = ((v >> ds->pf.gshift) & ds->pf.gmax) << (8 - ds->pf.gbits); - b = ((v >> ds->pf.bshift) & ds->pf.bmax) << (8 - ds->pf.bbits); - *pbuf++ = r; - *pbuf++ = g; - *pbuf++ = b; - d += ds->pf.bytes_per_pixel; - } - d1 += ds->linesize; + linebuf = qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width); + for (y = 0; y < height; y++) { + qemu_pixman_linebuf_fill(linebuf, ds->image, width, y); clearerr(f); - ret = fwrite(linebuf, 1, pbuf - linebuf, f); + ret = fwrite(pixman_image_get_data(linebuf), 1, + pixman_image_get_stride(linebuf), f); (void)ret; if (ferror(f)) { goto write_err; @@ -2442,7 +2425,7 @@ void ppm_save(const char *filename, struct DisplaySurface *ds, Error **errp) } out: - g_free(linebuf); + qemu_pixman_image_unref(linebuf); fclose(f); return; From 9f64916da20eea67121d544698676295bbb105a7 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 10 Oct 2012 13:29:43 +0200 Subject: [PATCH 209/291] pixman/vnc: use pixman images in vnc. The vnc code uses *three* DisplaySurfaces: First is the surface of the actual QemuConsole, usually the guest screen, but could also be a text console (monitor/serial reachable via Ctrl-Alt- keys). This is left as-is. Second is the current server's view of the screen content. The vnc code uses this to figure which parts of the guest screen did _really_ change to reduce the amount of updates sent to the vnc clients. It is also used as data source when sending out the updates to the clients. This surface gets replaced by a pixman image. The format changes too, instead of using the guest screen format we'll use fixed 32bit rgb framebuffer and convert the pixels on the fly when comparing and updating the server framebuffer. Third surface carries the format expected by the vnc client. That isn't used to store image data. This surface is switched to PixelFormat and a boolean for bigendian byte order. Signed-off-by: Gerd Hoffmann --- ui/vnc-enc-hextile-template.h | 23 ++-- ui/vnc-enc-hextile.c | 45 ++++--- ui/vnc-enc-tight.c | 144 ++++++++++----------- ui/vnc-enc-zrle.c | 18 +-- ui/vnc-jobs.c | 3 +- ui/vnc.c | 235 +++++++++++++++++++--------------- ui/vnc.h | 19 ++- 7 files changed, 259 insertions(+), 228 deletions(-) diff --git a/ui/vnc-enc-hextile-template.h b/ui/vnc-enc-hextile-template.h index a7310e1947..d868d75720 100644 --- a/ui/vnc-enc-hextile-template.h +++ b/ui/vnc-enc-hextile-template.h @@ -14,7 +14,7 @@ static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, int *has_bg, int *has_fg) { VncDisplay *vd = vs->vd; - uint8_t *row = vd->server->data + y * ds_get_linesize(vs->ds) + x * ds_get_bytes_per_pixel(vs->ds); + uint8_t *row = vnc_server_fb_ptr(vd, x, y); pixel_t *irow = (pixel_t *)row; int j, i; pixel_t *last_bg = (pixel_t *)last_bg_; @@ -25,7 +25,7 @@ static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, int bg_count = 0; int fg_count = 0; int flags = 0; - uint8_t data[(vs->clientds.pf.bytes_per_pixel + 2) * 16 * 16]; + uint8_t data[(vs->client_pf.bytes_per_pixel + 2) * 16 * 16]; int n_data = 0; int n_subtiles = 0; @@ -58,7 +58,7 @@ static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, } if (n_colors > 2) break; - irow += ds_get_linesize(vs->ds) / sizeof(pixel_t); + irow += vnc_server_fb_stride(vd) / sizeof(pixel_t); } if (n_colors > 1 && fg_count > bg_count) { @@ -106,7 +106,7 @@ static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, n_data += 2; n_subtiles++; } - irow += ds_get_linesize(vs->ds) / sizeof(pixel_t); + irow += vnc_server_fb_stride(vd) / sizeof(pixel_t); } break; case 3: @@ -133,7 +133,7 @@ static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, has_color = 0; #ifdef GENERIC vnc_convert_pixel(vs, data + n_data, color); - n_data += vs->clientds.pf.bytes_per_pixel; + n_data += vs->client_pf.bytes_per_pixel; #else memcpy(data + n_data, &color, sizeof(color)); n_data += sizeof(pixel_t); @@ -153,7 +153,7 @@ static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, if (has_color) { #ifdef GENERIC vnc_convert_pixel(vs, data + n_data, color); - n_data += vs->clientds.pf.bytes_per_pixel; + n_data += vs->client_pf.bytes_per_pixel; #else memcpy(data + n_data, &color, sizeof(color)); n_data += sizeof(pixel_t); @@ -162,7 +162,7 @@ static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, n_data += 2; n_subtiles++; } - irow += ds_get_linesize(vs->ds) / sizeof(pixel_t); + irow += vnc_server_fb_stride(vd) / sizeof(pixel_t); } /* A SubrectsColoured subtile invalidates the foreground color */ @@ -190,18 +190,17 @@ static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, vnc_write_u8(vs, flags); if (n_colors < 4) { if (flags & 0x02) - vs->write_pixels(vs, &vd->server->pf, last_bg, sizeof(pixel_t)); + vs->write_pixels(vs, last_bg, sizeof(pixel_t)); if (flags & 0x04) - vs->write_pixels(vs, &vd->server->pf, last_fg, sizeof(pixel_t)); + vs->write_pixels(vs, last_fg, sizeof(pixel_t)); if (n_subtiles) { vnc_write_u8(vs, n_subtiles); vnc_write(vs, data, n_data); } } else { for (j = 0; j < h; j++) { - vs->write_pixels(vs, &vd->server->pf, row, - w * ds_get_bytes_per_pixel(vs->ds)); - row += ds_get_linesize(vs->ds); + vs->write_pixels(vs, row, w * 4); + row += vnc_server_fb_stride(vd); } } } diff --git a/ui/vnc-enc-hextile.c b/ui/vnc-enc-hextile.c index c860dbb2e5..263a0ce9d2 100644 --- a/ui/vnc-enc-hextile.c +++ b/ui/vnc-enc-hextile.c @@ -68,10 +68,9 @@ int vnc_hextile_send_framebuffer_update(VncState *vs, int x, int i, j; int has_fg, has_bg; uint8_t *last_fg, *last_bg; - VncDisplay *vd = vs->vd; - last_fg = (uint8_t *) g_malloc(vd->server->pf.bytes_per_pixel); - last_bg = (uint8_t *) g_malloc(vd->server->pf.bytes_per_pixel); + last_fg = (uint8_t *) g_malloc(VNC_SERVER_FB_BYTES); + last_bg = (uint8_t *) g_malloc(VNC_SERVER_FB_BYTES); has_fg = has_bg = 0; for (j = y; j < (y + h); j += 16) { for (i = x; i < (x + w); i += 16) { @@ -89,28 +88,28 @@ int vnc_hextile_send_framebuffer_update(VncState *vs, int x, void vnc_hextile_set_pixel_conversion(VncState *vs, int generic) { if (!generic) { - switch (vs->ds->surface->pf.bits_per_pixel) { - case 8: - vs->hextile.send_tile = send_hextile_tile_8; - break; - case 16: - vs->hextile.send_tile = send_hextile_tile_16; - break; - case 32: - vs->hextile.send_tile = send_hextile_tile_32; - break; + switch (VNC_SERVER_FB_BITS) { + case 8: + vs->hextile.send_tile = send_hextile_tile_8; + break; + case 16: + vs->hextile.send_tile = send_hextile_tile_16; + break; + case 32: + vs->hextile.send_tile = send_hextile_tile_32; + break; } } else { - switch (vs->ds->surface->pf.bits_per_pixel) { - case 8: - vs->hextile.send_tile = send_hextile_tile_generic_8; - break; - case 16: - vs->hextile.send_tile = send_hextile_tile_generic_16; - break; - case 32: - vs->hextile.send_tile = send_hextile_tile_generic_32; - break; + switch (VNC_SERVER_FB_BITS) { + case 8: + vs->hextile.send_tile = send_hextile_tile_generic_8; + break; + case 16: + vs->hextile.send_tile = send_hextile_tile_generic_16; + break; + case 32: + vs->hextile.send_tile = send_hextile_tile_generic_32; + break; } } } diff --git a/ui/vnc-enc-tight.c b/ui/vnc-enc-tight.c index 5d492abe92..8013c5c6dd 100644 --- a/ui/vnc-enc-tight.c +++ b/ui/vnc-enc-tight.c @@ -124,7 +124,7 @@ static bool tight_can_send_png_rect(VncState *vs, int w, int h) } if (ds_get_bytes_per_pixel(vs->ds) == 1 || - vs->clientds.pf.bytes_per_pixel == 1) { + vs->client_pf.bytes_per_pixel == 1) { return false; } @@ -153,7 +153,7 @@ tight_detect_smooth_image24(VncState *vs, int w, int h) * If client is big-endian, color samples begin from the second * byte (offset 1) of a 32-bit pixel value. */ - off = !!(vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG); + off = vs->client_be; memset(stats, 0, sizeof (stats)); @@ -216,16 +216,16 @@ tight_detect_smooth_image24(VncState *vs, int w, int h) unsigned int errors; \ unsigned char *buf = vs->tight.tight.buffer; \ \ - endian = ((vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) != \ - (vs->ds->surface->flags & QEMU_BIG_ENDIAN_FLAG)); \ + endian = 0; /* FIXME: ((vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) != \ + (vs->ds->surface->flags & QEMU_BIG_ENDIAN_FLAG)); */ \ \ \ - max[0] = vs->clientds.pf.rmax; \ - max[1] = vs->clientds.pf.gmax; \ - max[2] = vs->clientds.pf.bmax; \ - shift[0] = vs->clientds.pf.rshift; \ - shift[1] = vs->clientds.pf.gshift; \ - shift[2] = vs->clientds.pf.bshift; \ + max[0] = vs->client_pf.rmax; \ + max[1] = vs->client_pf.gmax; \ + max[2] = vs->client_pf.bmax; \ + shift[0] = vs->client_pf.rshift; \ + shift[1] = vs->client_pf.gshift; \ + shift[2] = vs->client_pf.bshift; \ \ memset(stats, 0, sizeof(stats)); \ \ @@ -302,7 +302,7 @@ tight_detect_smooth_image(VncState *vs, int w, int h) } if (ds_get_bytes_per_pixel(vs->ds) == 1 || - vs->clientds.pf.bytes_per_pixel == 1 || + vs->client_pf.bytes_per_pixel == 1 || w < VNC_TIGHT_DETECT_MIN_WIDTH || h < VNC_TIGHT_DETECT_MIN_HEIGHT) { return 0; } @@ -317,7 +317,7 @@ tight_detect_smooth_image(VncState *vs, int w, int h) } } - if (vs->clientds.pf.bytes_per_pixel == 4) { + if (vs->client_pf.bytes_per_pixel == 4) { if (vs->tight.pixel24) { errors = tight_detect_smooth_image24(vs, w, h); if (vs->tight.quality != (uint8_t)-1) { @@ -430,7 +430,7 @@ static int tight_fill_palette(VncState *vs, int x, int y, max = 256; } - switch(vs->clientds.pf.bytes_per_pixel) { + switch (vs->client_pf.bytes_per_pixel) { case 4: return tight_fill_palette32(vs, x, y, max, count, bg, fg, palette); case 2: @@ -557,15 +557,15 @@ tight_filter_gradient24(VncState *vs, uint8_t *buf, int w, int h) buf32 = (uint32_t *)buf; memset(vs->tight.gradient.buffer, 0, w * 3 * sizeof(int)); - if ((vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) == - (vs->ds->surface->flags & QEMU_BIG_ENDIAN_FLAG)) { - shift[0] = vs->clientds.pf.rshift; - shift[1] = vs->clientds.pf.gshift; - shift[2] = vs->clientds.pf.bshift; + if (1 /* FIXME: (vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) == + (vs->ds->surface->flags & QEMU_BIG_ENDIAN_FLAG) */) { + shift[0] = vs->client_pf.rshift; + shift[1] = vs->client_pf.gshift; + shift[2] = vs->client_pf.bshift; } else { - shift[0] = 24 - vs->clientds.pf.rshift; - shift[1] = 24 - vs->clientds.pf.gshift; - shift[2] = 24 - vs->clientds.pf.bshift; + shift[0] = 24 - vs->client_pf.rshift; + shift[1] = 24 - vs->client_pf.gshift; + shift[2] = 24 - vs->client_pf.bshift; } for (y = 0; y < h; y++) { @@ -615,15 +615,15 @@ tight_filter_gradient24(VncState *vs, uint8_t *buf, int w, int h) \ memset (vs->tight.gradient.buffer, 0, w * 3 * sizeof(int)); \ \ - endian = ((vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) != \ - (vs->ds->surface->flags & QEMU_BIG_ENDIAN_FLAG)); \ + endian = 0; /* FIXME: ((vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) != \ + (vs->ds->surface->flags & QEMU_BIG_ENDIAN_FLAG)); */ \ \ - max[0] = vs->clientds.pf.rmax; \ - max[1] = vs->clientds.pf.gmax; \ - max[2] = vs->clientds.pf.bmax; \ - shift[0] = vs->clientds.pf.rshift; \ - shift[1] = vs->clientds.pf.gshift; \ - shift[2] = vs->clientds.pf.bshift; \ + max[0] = vs->client_pf.rmax; \ + max[1] = vs->client_pf.gmax; \ + max[2] = vs->client_pf.bmax; \ + shift[0] = vs->client_pf.rshift; \ + shift[1] = vs->client_pf.gshift; \ + shift[2] = vs->client_pf.bshift; \ \ for (y = 0; y < h; y++) { \ for (c = 0; c < 3; c++) { \ @@ -682,9 +682,7 @@ DEFINE_GRADIENT_FILTER_FUNCTION(32) uint##bpp##_t c; \ int dx, dy; \ \ - fbptr = (uint##bpp##_t *) \ - (vd->server->data + y * ds_get_linesize(vs->ds) + \ - x * ds_get_bytes_per_pixel(vs->ds)); \ + fbptr = vnc_server_fb_ptr(vd, x, y); \ \ c = *fbptr; \ if (samecolor && (uint32_t)c != *color) { \ @@ -698,7 +696,7 @@ DEFINE_GRADIENT_FILTER_FUNCTION(32) } \ } \ fbptr = (uint##bpp##_t *) \ - ((uint8_t *)fbptr + ds_get_linesize(vs->ds)); \ + ((uint8_t *)fbptr + vnc_server_fb_stride(vd)); \ } \ \ *color = (uint32_t)c; \ @@ -712,9 +710,7 @@ DEFINE_CHECK_SOLID_FUNCTION(8) static bool check_solid_tile(VncState *vs, int x, int y, int w, int h, uint32_t* color, bool samecolor) { - VncDisplay *vd = vs->vd; - - switch(vd->server->pf.bytes_per_pixel) { + switch (VNC_SERVER_FB_BYTES) { case 4: return check_solid_tile32(vs, x, y, w, h, color, samecolor); case 2: @@ -906,15 +902,15 @@ static void tight_pack24(VncState *vs, uint8_t *buf, size_t count, size_t *ret) buf32 = (uint32_t *)buf; - if ((vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) == - (vs->ds->surface->flags & QEMU_BIG_ENDIAN_FLAG)) { - rshift = vs->clientds.pf.rshift; - gshift = vs->clientds.pf.gshift; - bshift = vs->clientds.pf.bshift; + if (1 /* FIXME: (vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) == + (vs->ds->surface->flags & QEMU_BIG_ENDIAN_FLAG) */) { + rshift = vs->client_pf.rshift; + gshift = vs->client_pf.gshift; + bshift = vs->client_pf.bshift; } else { - rshift = 24 - vs->clientds.pf.rshift; - gshift = 24 - vs->clientds.pf.gshift; - bshift = 24 - vs->clientds.pf.bshift; + rshift = 24 - vs->client_pf.rshift; + gshift = 24 - vs->client_pf.gshift; + bshift = 24 - vs->client_pf.bshift; } if (ret) { @@ -946,7 +942,7 @@ static int send_full_color_rect(VncState *vs, int x, int y, int w, int h) tight_pack24(vs, vs->tight.tight.buffer, w * h, &vs->tight.tight.offset); bytes = 3; } else { - bytes = vs->clientds.pf.bytes_per_pixel; + bytes = vs->client_pf.bytes_per_pixel; } bytes = tight_compress_data(vs, stream, w * h * bytes, @@ -966,7 +962,7 @@ static int send_solid_rect(VncState *vs) tight_pack24(vs, vs->tight.tight.buffer, 1, &vs->tight.tight.offset); bytes = 3; } else { - bytes = vs->clientds.pf.bytes_per_pixel; + bytes = vs->client_pf.bytes_per_pixel; } vnc_write(vs, vs->tight.tight.buffer, bytes); @@ -983,7 +979,7 @@ static int send_mono_rect(VncState *vs, int x, int y, #ifdef CONFIG_VNC_PNG if (tight_can_send_png_rect(vs, w, h)) { int ret; - int bpp = vs->clientds.pf.bytes_per_pixel * 8; + int bpp = vs->client_pf.bytes_per_pixel * 8; VncPalette *palette = palette_new(2, bpp); palette_put(palette, bg); @@ -1000,7 +996,7 @@ static int send_mono_rect(VncState *vs, int x, int y, vnc_write_u8(vs, VNC_TIGHT_FILTER_PALETTE); vnc_write_u8(vs, 1); - switch(vs->clientds.pf.bytes_per_pixel) { + switch (vs->client_pf.bytes_per_pixel) { case 4: { uint32_t buf[2] = {bg, fg}; @@ -1043,7 +1039,7 @@ static void write_palette(int idx, uint32_t color, void *opaque) { struct palette_cb_priv *priv = opaque; VncState *vs = priv->vs; - uint32_t bytes = vs->clientds.pf.bytes_per_pixel; + uint32_t bytes = vs->client_pf.bytes_per_pixel; if (bytes == 4) { ((uint32_t*)priv->header)[idx] = color; @@ -1058,8 +1054,9 @@ static bool send_gradient_rect(VncState *vs, int x, int y, int w, int h) int level = tight_conf[vs->tight.compression].gradient_zlib_level; ssize_t bytes; - if (vs->clientds.pf.bytes_per_pixel == 1) + if (vs->client_pf.bytes_per_pixel == 1) { return send_full_color_rect(vs, x, y, w, h); + } vnc_write_u8(vs, (stream | VNC_TIGHT_EXPLICIT_FILTER) << 4); vnc_write_u8(vs, VNC_TIGHT_FILTER_GRADIENT); @@ -1069,7 +1066,7 @@ static bool send_gradient_rect(VncState *vs, int x, int y, int w, int h) if (vs->tight.pixel24) { tight_filter_gradient24(vs, vs->tight.tight.buffer, w, h); bytes = 3; - } else if (vs->clientds.pf.bytes_per_pixel == 4) { + } else if (vs->client_pf.bytes_per_pixel == 4) { tight_filter_gradient32(vs, (uint32_t *)vs->tight.tight.buffer, w, h); bytes = 4; } else { @@ -1107,7 +1104,7 @@ static int send_palette_rect(VncState *vs, int x, int y, vnc_write_u8(vs, VNC_TIGHT_FILTER_PALETTE); vnc_write_u8(vs, colors - 1); - switch(vs->clientds.pf.bytes_per_pixel) { + switch (vs->client_pf.bytes_per_pixel) { case 4: { size_t old_offset, offset; @@ -1156,8 +1153,7 @@ static void rgb_prepare_row24(VncState *vs, uint8_t *dst, int x, int y, uint32_t *fbptr; uint32_t pix; - fbptr = (uint32_t *)(vd->server->data + y * ds_get_linesize(vs->ds) + - x * ds_get_bytes_per_pixel(vs->ds)); + fbptr = vnc_server_fb_ptr(vd, x, y); while (count--) { pix = *fbptr++; @@ -1178,9 +1174,7 @@ static void rgb_prepare_row24(VncState *vs, uint8_t *dst, int x, int y, uint##bpp##_t pix; \ int r, g, b; \ \ - fbptr = (uint##bpp##_t *) \ - (vd->server->data + y * ds_get_linesize(vs->ds) + \ - x * ds_get_bytes_per_pixel(vs->ds)); \ + fbptr = vnc_server_fb_ptr(vd, x, y); \ \ while (count--) { \ pix = *fbptr++; \ @@ -1207,10 +1201,8 @@ DEFINE_RGB_GET_ROW_FUNCTION(32) static void rgb_prepare_row(VncState *vs, uint8_t *dst, int x, int y, int count) { - if (ds_get_bytes_per_pixel(vs->ds) == 4) { - if (vs->ds->surface->pf.rmax == 0xFF && - vs->ds->surface->pf.gmax == 0xFF && - vs->ds->surface->pf.bmax == 0xFF) { + if (VNC_SERVER_FB_BYTES == 4) { + if (1) { rgb_prepare_row24(vs, dst, x, y, count); } else { rgb_prepare_row32(vs, dst, x, y, count); @@ -1326,23 +1318,23 @@ static void write_png_palette(int idx, uint32_t pix, void *opaque) if (vs->tight.pixel24) { - color->red = (pix >> vs->clientds.pf.rshift) & vs->clientds.pf.rmax; - color->green = (pix >> vs->clientds.pf.gshift) & vs->clientds.pf.gmax; - color->blue = (pix >> vs->clientds.pf.bshift) & vs->clientds.pf.bmax; + color->red = (pix >> vs->client_pf.rshift) & vs->client_pf.rmax; + color->green = (pix >> vs->client_pf.gshift) & vs->client_pf.gmax; + color->blue = (pix >> vs->client_pf.bshift) & vs->client_pf.bmax; } else { int red, green, blue; - red = (pix >> vs->clientds.pf.rshift) & vs->clientds.pf.rmax; - green = (pix >> vs->clientds.pf.gshift) & vs->clientds.pf.gmax; - blue = (pix >> vs->clientds.pf.bshift) & vs->clientds.pf.bmax; - color->red = ((red * 255 + vs->clientds.pf.rmax / 2) / - vs->clientds.pf.rmax); - color->green = ((green * 255 + vs->clientds.pf.gmax / 2) / - vs->clientds.pf.gmax); - color->blue = ((blue * 255 + vs->clientds.pf.bmax / 2) / - vs->clientds.pf.bmax); + red = (pix >> vs->client_pf.rshift) & vs->client_pf.rmax; + green = (pix >> vs->client_pf.gshift) & vs->client_pf.gmax; + blue = (pix >> vs->client_pf.bshift) & vs->client_pf.bmax; + color->red = ((red * 255 + vs->client_pf.rmax / 2) / + vs->client_pf.rmax); + color->green = ((green * 255 + vs->client_pf.gmax / 2) / + vs->client_pf.gmax); + color->blue = ((blue * 255 + vs->client_pf.bmax / 2) / + vs->client_pf.bmax); } } @@ -1422,7 +1414,7 @@ static int send_png_rect(VncState *vs, int x, int y, int w, int h, png_set_PLTE(png_ptr, info_ptr, png_palette, palette_size(palette)); - if (vs->clientds.pf.bytes_per_pixel == 4) { + if (vs->client_pf.bytes_per_pixel == 4) { tight_encode_indexed_rect32(vs->tight.tight.buffer, w * h, palette); } else { tight_encode_indexed_rect16(vs->tight.tight.buffer, w * h, palette); @@ -1713,8 +1705,8 @@ static int tight_send_framebuffer_update(VncState *vs, int x, int y, { int max_rows; - if (vs->clientds.pf.bytes_per_pixel == 4 && vs->clientds.pf.rmax == 0xFF && - vs->clientds.pf.bmax == 0xFF && vs->clientds.pf.gmax == 0xFF) { + if (vs->client_pf.bytes_per_pixel == 4 && vs->client_pf.rmax == 0xFF && + vs->client_pf.bmax == 0xFF && vs->client_pf.gmax == 0xFF) { vs->tight.pixel24 = true; } else { vs->tight.pixel24 = false; diff --git a/ui/vnc-enc-zrle.c b/ui/vnc-enc-zrle.c index 917d384f57..ed3b48465d 100644 --- a/ui/vnc-enc-zrle.c +++ b/ui/vnc-enc-zrle.c @@ -255,7 +255,7 @@ static void zrle_write_u8(VncState *vs, uint8_t value) static int zrle_send_framebuffer_update(VncState *vs, int x, int y, int w, int h) { - bool be = !!(vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG); + bool be = vs->client_be; size_t bytes; int zywrle_level; @@ -277,13 +277,13 @@ static int zrle_send_framebuffer_update(VncState *vs, int x, int y, vnc_zrle_start(vs); - switch(vs->clientds.pf.bytes_per_pixel) { + switch (vs->client_pf.bytes_per_pixel) { case 1: zrle_encode_8ne(vs, x, y, w, h, zywrle_level); break; case 2: - if (vs->clientds.pf.gmax > 0x1F) { + if (vs->client_pf.gmax > 0x1F) { if (be) { zrle_encode_16be(vs, x, y, w, h, zywrle_level); } else { @@ -304,13 +304,13 @@ static int zrle_send_framebuffer_update(VncState *vs, int x, int y, bool fits_in_ms3bytes; fits_in_ls3bytes = - ((vs->clientds.pf.rmax << vs->clientds.pf.rshift) < (1 << 24) && - (vs->clientds.pf.gmax << vs->clientds.pf.gshift) < (1 << 24) && - (vs->clientds.pf.bmax << vs->clientds.pf.bshift) < (1 << 24)); + ((vs->client_pf.rmax << vs->client_pf.rshift) < (1 << 24) && + (vs->client_pf.gmax << vs->client_pf.gshift) < (1 << 24) && + (vs->client_pf.bmax << vs->client_pf.bshift) < (1 << 24)); - fits_in_ms3bytes = (vs->clientds.pf.rshift > 7 && - vs->clientds.pf.gshift > 7 && - vs->clientds.pf.bshift > 7); + fits_in_ms3bytes = (vs->client_pf.rshift > 7 && + vs->client_pf.gshift > 7 && + vs->client_pf.bshift > 7); if ((fits_in_ls3bytes && !be) || (fits_in_ms3bytes && be)) { if (be) { diff --git a/ui/vnc-jobs.c b/ui/vnc-jobs.c index 3c592b3f3d..04f139b56f 100644 --- a/ui/vnc-jobs.c +++ b/ui/vnc-jobs.c @@ -187,7 +187,8 @@ static void vnc_async_encoding_start(VncState *orig, VncState *local) local->vd = orig->vd; local->lossy_rect = orig->lossy_rect; local->write_pixels = orig->write_pixels; - local->clientds = orig->clientds; + local->client_pf = orig->client_pf; + local->client_be = orig->client_be; local->tight = orig->tight; local->zlib = orig->zlib; local->hextile = orig->hextile; diff --git a/ui/vnc.c b/ui/vnc.c index 0ae1c74984..15aef86047 100644 --- a/ui/vnc.c +++ b/ui/vnc.c @@ -436,6 +436,8 @@ static void vnc_dpy_update(DisplayState *ds, int x, int y, int w, int h) int i; VncDisplay *vd = ds->opaque; struct VncSurface *s = &vd->guest; + int width = ds_get_width(ds); + int height = ds_get_height(ds); h += y; @@ -446,10 +448,10 @@ static void vnc_dpy_update(DisplayState *ds, int x, int y, int w, int h) w += (x % 16); x -= (x % 16); - x = MIN(x, s->ds->width); - y = MIN(y, s->ds->height); - w = MIN(x + w, s->ds->width) - x; - h = MIN(h, s->ds->height); + x = MIN(x, width); + y = MIN(y, height); + w = MIN(x + w, width) - x; + h = MIN(h, height); for (; y < h; y++) for (i = 0; i < w; i += 16) @@ -550,6 +552,21 @@ static void vnc_abort_display_jobs(VncDisplay *vd) } } +int vnc_server_fb_stride(VncDisplay *vd) +{ + return pixman_image_get_stride(vd->server); +} + +void *vnc_server_fb_ptr(VncDisplay *vd, int x, int y) +{ + uint8_t *ptr; + + ptr = (uint8_t *)pixman_image_get_data(vd->server); + ptr += y * vnc_server_fb_stride(vd); + ptr += x * VNC_SERVER_FB_BYTES; + return ptr; +} + static void vnc_dpy_resize(DisplayState *ds) { VncDisplay *vd = ds->opaque; @@ -558,20 +575,20 @@ static void vnc_dpy_resize(DisplayState *ds) vnc_abort_display_jobs(vd); /* server surface */ - if (!vd->server) - vd->server = g_malloc0(sizeof(*vd->server)); - if (vd->server->data) - g_free(vd->server->data); - *(vd->server) = *(ds->surface); - vd->server->data = g_malloc0(vd->server->linesize * - vd->server->height); + qemu_pixman_image_unref(vd->server); + vd->server = pixman_image_create_bits(VNC_SERVER_FB_FORMAT, + ds_get_width(ds), + ds_get_height(ds), + NULL, 0); /* guest surface */ - if (!vd->guest.ds) - vd->guest.ds = g_malloc0(sizeof(*vd->guest.ds)); +#if 0 /* FIXME */ if (ds_get_bytes_per_pixel(ds) != vd->guest.ds->pf.bytes_per_pixel) console_color_init(ds); - *(vd->guest.ds) = *(ds->surface); +#endif + qemu_pixman_image_unref(vd->guest.fb); + vd->guest.fb = pixman_image_ref(ds->surface->image); + vd->guest.format = ds->surface->format; memset(vd->guest.dirty, 0xFF, sizeof(vd->guest.dirty)); QTAILQ_FOREACH(vs, &vd->clients, next) { @@ -585,7 +602,7 @@ static void vnc_dpy_resize(DisplayState *ds) } /* fastest code */ -static void vnc_write_pixels_copy(VncState *vs, struct PixelFormat *pf, +static void vnc_write_pixels_copy(VncState *vs, void *pixels, int size) { vnc_write(vs, pixels, size); @@ -595,23 +612,23 @@ static void vnc_write_pixels_copy(VncState *vs, struct PixelFormat *pf, void vnc_convert_pixel(VncState *vs, uint8_t *buf, uint32_t v) { uint8_t r, g, b; - VncDisplay *vd = vs->vd; - r = ((((v & vd->server->pf.rmask) >> vd->server->pf.rshift) << vs->clientds.pf.rbits) >> - vd->server->pf.rbits); - g = ((((v & vd->server->pf.gmask) >> vd->server->pf.gshift) << vs->clientds.pf.gbits) >> - vd->server->pf.gbits); - b = ((((v & vd->server->pf.bmask) >> vd->server->pf.bshift) << vs->clientds.pf.bbits) >> - vd->server->pf.bbits); - v = (r << vs->clientds.pf.rshift) | - (g << vs->clientds.pf.gshift) | - (b << vs->clientds.pf.bshift); - switch(vs->clientds.pf.bytes_per_pixel) { +#if VNC_SERVER_FB_FORMAT == PIXMAN_FORMAT(32, PIXMAN_TYPE_ARGB, 0, 8, 8, 8) + r = (((v & 0x00ff0000) >> 16) << vs->client_pf.rbits) >> 8; + g = (((v & 0x0000ff00) >> 8) << vs->client_pf.gbits) >> 8; + b = (((v & 0x000000ff) >> 0) << vs->client_pf.bbits) >> 8; +#else +# error need some bits here if you change VNC_SERVER_FB_FORMAT +#endif + v = (r << vs->client_pf.rshift) | + (g << vs->client_pf.gshift) | + (b << vs->client_pf.bshift); + switch (vs->client_pf.bytes_per_pixel) { case 1: buf[0] = v; break; case 2: - if (vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) { + if (vs->client_be) { buf[0] = v >> 8; buf[1] = v; } else { @@ -621,7 +638,7 @@ void vnc_convert_pixel(VncState *vs, uint8_t *buf, uint32_t v) break; default: case 4: - if (vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) { + if (vs->client_be) { buf[0] = v >> 24; buf[1] = v >> 16; buf[2] = v >> 8; @@ -636,37 +653,37 @@ void vnc_convert_pixel(VncState *vs, uint8_t *buf, uint32_t v) } } -static void vnc_write_pixels_generic(VncState *vs, struct PixelFormat *pf, +static void vnc_write_pixels_generic(VncState *vs, void *pixels1, int size) { uint8_t buf[4]; - if (pf->bytes_per_pixel == 4) { + if (VNC_SERVER_FB_BYTES == 4) { uint32_t *pixels = pixels1; int n, i; n = size >> 2; - for(i = 0; i < n; i++) { + for (i = 0; i < n; i++) { vnc_convert_pixel(vs, buf, pixels[i]); - vnc_write(vs, buf, vs->clientds.pf.bytes_per_pixel); + vnc_write(vs, buf, vs->client_pf.bytes_per_pixel); } - } else if (pf->bytes_per_pixel == 2) { + } else if (VNC_SERVER_FB_BYTES == 2) { uint16_t *pixels = pixels1; int n, i; n = size >> 1; - for(i = 0; i < n; i++) { + for (i = 0; i < n; i++) { vnc_convert_pixel(vs, buf, pixels[i]); - vnc_write(vs, buf, vs->clientds.pf.bytes_per_pixel); + vnc_write(vs, buf, vs->client_pf.bytes_per_pixel); } - } else if (pf->bytes_per_pixel == 1) { + } else if (VNC_SERVER_FB_BYTES == 1) { uint8_t *pixels = pixels1; int n, i; n = size; - for(i = 0; i < n; i++) { + for (i = 0; i < n; i++) { vnc_convert_pixel(vs, buf, pixels[i]); - vnc_write(vs, buf, vs->clientds.pf.bytes_per_pixel); + vnc_write(vs, buf, vs->client_pf.bytes_per_pixel); } } else { - fprintf(stderr, "vnc_write_pixels_generic: VncState color depth not supported\n"); + fprintf(stderr, "%s: VncState color depth not supported\n", __func__); } } @@ -676,10 +693,10 @@ int vnc_raw_send_framebuffer_update(VncState *vs, int x, int y, int w, int h) uint8_t *row; VncDisplay *vd = vs->vd; - row = vd->server->data + y * ds_get_linesize(vs->ds) + x * ds_get_bytes_per_pixel(vs->ds); + row = vnc_server_fb_ptr(vd, x, y); for (i = 0; i < h; i++) { - vs->write_pixels(vs, &vd->server->pf, row, w * ds_get_bytes_per_pixel(vs->ds)); - row += ds_get_linesize(vs->ds); + vs->write_pixels(vs, row, w * VNC_SERVER_FB_BYTES); + row += vnc_server_fb_stride(vd); } return 1; } @@ -736,7 +753,7 @@ static void vnc_dpy_copy(DisplayState *ds, int src_x, int src_y, int dst_x, int VncState *vs, *vn; uint8_t *src_row; uint8_t *dst_row; - int i,x,y,pitch,depth,inc,w_lim,s; + int i, x, y, pitch, inc, w_lim, s; int cmp_bytes; vnc_refresh_server_surface(vd); @@ -749,10 +766,9 @@ static void vnc_dpy_copy(DisplayState *ds, int src_x, int src_y, int dst_x, int } /* do bitblit op on the local surface too */ - pitch = ds_get_linesize(vd->ds); - depth = ds_get_bytes_per_pixel(vd->ds); - src_row = vd->server->data + pitch * src_y + depth * src_x; - dst_row = vd->server->data + pitch * dst_y + depth * dst_x; + pitch = vnc_server_fb_stride(vd); + src_row = vnc_server_fb_ptr(vd, src_x, src_y); + dst_row = vnc_server_fb_ptr(vd, dst_x, dst_y); y = dst_y; inc = 1; if (dst_y > src_y) { @@ -780,7 +796,7 @@ static void vnc_dpy_copy(DisplayState *ds, int src_x, int src_y, int dst_x, int } else { s = 16; } - cmp_bytes = s * depth; + cmp_bytes = s * VNC_SERVER_FB_BYTES; if (memcmp(src_row, dst_row, cmp_bytes) == 0) continue; memmove(dst_row, src_row, cmp_bytes); @@ -790,8 +806,8 @@ static void vnc_dpy_copy(DisplayState *ds, int src_x, int src_y, int dst_x, int } } } - src_row += pitch - w * depth; - dst_row += pitch - w * depth; + src_row += pitch - w * VNC_SERVER_FB_BYTES; + dst_row += pitch - w * VNC_SERVER_FB_BYTES; y += inc; } @@ -810,7 +826,6 @@ static void vnc_mouse_set(DisplayState *ds, int x, int y, int visible) static int vnc_cursor_define(VncState *vs) { QEMUCursor *c = vs->vd->cursor; - PixelFormat pf = qemu_default_pixelformat(32); int isize; if (vnc_has_feature(vs, VNC_FEATURE_RICH_CURSOR)) { @@ -820,8 +835,8 @@ static int vnc_cursor_define(VncState *vs) vnc_write_u16(vs, 1); /* # of rects */ vnc_framebuffer_update(vs, c->hot_x, c->hot_y, c->width, c->height, VNC_ENCODING_RICH_CURSOR); - isize = c->width * c->height * vs->clientds.pf.bytes_per_pixel; - vnc_write_pixels_generic(vs, &pf, c->data, isize); + isize = c->width * c->height * vs->client_pf.bytes_per_pixel; + vnc_write_pixels_generic(vs, c->data, isize); vnc_write(vs, vs->vd->cursor_mask, vs->vd->cursor_msize); vnc_unlock_output(vs); return 0; @@ -898,8 +913,8 @@ static int vnc_update_client(VncState *vs, int has_dirty) */ job = vnc_job_new(vs); - width = MIN(vd->server->width, vs->client_width); - height = MIN(vd->server->height, vs->client_height); + width = MIN(pixman_image_get_width(vd->server), vs->client_width); + height = MIN(pixman_image_get_height(vd->server), vs->client_height); for (y = 0; y < height; y++) { int x; @@ -1861,9 +1876,9 @@ static void set_encodings(VncState *vs, int32_t *encodings, size_t n_encodings) static void set_pixel_conversion(VncState *vs) { - if ((vs->clientds.flags & QEMU_BIG_ENDIAN_FLAG) == - (vs->ds->surface->flags & QEMU_BIG_ENDIAN_FLAG) && - !memcmp(&(vs->clientds.pf), &(vs->ds->surface->pf), sizeof(PixelFormat))) { + pixman_format_code_t fmt = qemu_pixman_get_format(&vs->client_pf); + + if (fmt == VNC_SERVER_FB_FORMAT) { vs->write_pixels = vnc_write_pixels_copy; vnc_hextile_set_pixel_conversion(vs, 0); } else { @@ -1883,23 +1898,22 @@ static void set_pixel_format(VncState *vs, return; } - vs->clientds = *(vs->vd->guest.ds); - vs->clientds.pf.rmax = red_max; - vs->clientds.pf.rbits = hweight_long(red_max); - vs->clientds.pf.rshift = red_shift; - vs->clientds.pf.rmask = red_max << red_shift; - vs->clientds.pf.gmax = green_max; - vs->clientds.pf.gbits = hweight_long(green_max); - vs->clientds.pf.gshift = green_shift; - vs->clientds.pf.gmask = green_max << green_shift; - vs->clientds.pf.bmax = blue_max; - vs->clientds.pf.bbits = hweight_long(blue_max); - vs->clientds.pf.bshift = blue_shift; - vs->clientds.pf.bmask = blue_max << blue_shift; - vs->clientds.pf.bits_per_pixel = bits_per_pixel; - vs->clientds.pf.bytes_per_pixel = bits_per_pixel / 8; - vs->clientds.pf.depth = bits_per_pixel == 32 ? 24 : bits_per_pixel; - vs->clientds.flags = big_endian_flag ? QEMU_BIG_ENDIAN_FLAG : 0x00; + vs->client_pf.rmax = red_max; + vs->client_pf.rbits = hweight_long(red_max); + vs->client_pf.rshift = red_shift; + vs->client_pf.rmask = red_max << red_shift; + vs->client_pf.gmax = green_max; + vs->client_pf.gbits = hweight_long(green_max); + vs->client_pf.gshift = green_shift; + vs->client_pf.gmask = green_max << green_shift; + vs->client_pf.bmax = blue_max; + vs->client_pf.bbits = hweight_long(blue_max); + vs->client_pf.bshift = blue_shift; + vs->client_pf.bmask = blue_max << blue_shift; + vs->client_pf.bits_per_pixel = bits_per_pixel; + vs->client_pf.bytes_per_pixel = bits_per_pixel / 8; + vs->client_pf.depth = bits_per_pixel == 32 ? 24 : bits_per_pixel; + vs->client_be = big_endian_flag; set_pixel_conversion(vs); @@ -1910,8 +1924,10 @@ static void set_pixel_format(VncState *vs, static void pixel_format_message (VncState *vs) { char pad[3] = { 0, 0, 0 }; - vnc_write_u8(vs, vs->ds->surface->pf.bits_per_pixel); /* bits-per-pixel */ - vnc_write_u8(vs, vs->ds->surface->pf.depth); /* depth */ + vs->client_pf = qemu_default_pixelformat(32); + + vnc_write_u8(vs, vs->client_pf.bits_per_pixel); /* bits-per-pixel */ + vnc_write_u8(vs, vs->client_pf.depth); /* depth */ #ifdef HOST_WORDS_BIGENDIAN vnc_write_u8(vs, 1); /* big-endian-flag */ @@ -1919,27 +1935,25 @@ static void pixel_format_message (VncState *vs) { vnc_write_u8(vs, 0); /* big-endian-flag */ #endif vnc_write_u8(vs, 1); /* true-color-flag */ - vnc_write_u16(vs, vs->ds->surface->pf.rmax); /* red-max */ - vnc_write_u16(vs, vs->ds->surface->pf.gmax); /* green-max */ - vnc_write_u16(vs, vs->ds->surface->pf.bmax); /* blue-max */ - vnc_write_u8(vs, vs->ds->surface->pf.rshift); /* red-shift */ - vnc_write_u8(vs, vs->ds->surface->pf.gshift); /* green-shift */ - vnc_write_u8(vs, vs->ds->surface->pf.bshift); /* blue-shift */ + vnc_write_u16(vs, vs->client_pf.rmax); /* red-max */ + vnc_write_u16(vs, vs->client_pf.gmax); /* green-max */ + vnc_write_u16(vs, vs->client_pf.bmax); /* blue-max */ + vnc_write_u8(vs, vs->client_pf.rshift); /* red-shift */ + vnc_write_u8(vs, vs->client_pf.gshift); /* green-shift */ + vnc_write_u8(vs, vs->client_pf.bshift); /* blue-shift */ + vnc_write(vs, pad, 3); /* padding */ vnc_hextile_set_pixel_conversion(vs, 0); - - vs->clientds = *(vs->ds->surface); - vs->clientds.flags &= ~QEMU_ALLOCATED_FLAG; vs->write_pixels = vnc_write_pixels_copy; - - vnc_write(vs, pad, 3); /* padding */ } static void vnc_dpy_setdata(DisplayState *ds) { VncDisplay *vd = ds->opaque; - *(vd->guest.ds) = *(ds->surface); + qemu_pixman_image_unref(vd->guest.fb); + vd->guest.fb = pixman_image_ref(ds->surface->image); + vd->guest.format = ds->surface->format; vnc_dpy_update(ds, 0, 0, ds_get_width(ds), ds_get_height(ds)); } @@ -2443,12 +2457,14 @@ static int vnc_refresh_lossy_rect(VncDisplay *vd, int x, int y) static int vnc_update_stats(VncDisplay *vd, struct timeval * tv) { + int width = pixman_image_get_width(vd->guest.fb); + int height = pixman_image_get_height(vd->guest.fb); int x, y; struct timeval res; int has_dirty = 0; - for (y = 0; y < vd->guest.ds->height; y += VNC_STAT_RECT) { - for (x = 0; x < vd->guest.ds->width; x += VNC_STAT_RECT) { + for (y = 0; y < height; y += VNC_STAT_RECT) { + for (x = 0; x < width; x += VNC_STAT_RECT) { VncRectStat *rect = vnc_stat_rect(vd, x, y); rect->updated = false; @@ -2462,8 +2478,8 @@ static int vnc_update_stats(VncDisplay *vd, struct timeval * tv) } vd->guest.last_freq_check = *tv; - for (y = 0; y < vd->guest.ds->height; y += VNC_STAT_RECT) { - for (x = 0; x < vd->guest.ds->width; x += VNC_STAT_RECT) { + for (y = 0; y < height; y += VNC_STAT_RECT) { + for (x = 0; x < width; x += VNC_STAT_RECT) { VncRectStat *rect= vnc_stat_rect(vd, x, y); int count = ARRAY_SIZE(rect->times); struct timeval min, max; @@ -2532,12 +2548,15 @@ static void vnc_rect_updated(VncDisplay *vd, int x, int y, struct timeval * tv) static int vnc_refresh_server_surface(VncDisplay *vd) { + int width = pixman_image_get_width(vd->guest.fb); + int height = pixman_image_get_height(vd->guest.fb); int y; uint8_t *guest_row; uint8_t *server_row; int cmp_bytes; VncState *vs; int has_dirty = 0; + pixman_image_t *tmpbuf = NULL; struct timeval tv = { 0, 0 }; @@ -2551,22 +2570,31 @@ static int vnc_refresh_server_surface(VncDisplay *vd) * Check and copy modified bits from guest to server surface. * Update server dirty map. */ - cmp_bytes = 16 * ds_get_bytes_per_pixel(vd->ds); - if (cmp_bytes > vd->ds->surface->linesize) { - cmp_bytes = vd->ds->surface->linesize; + cmp_bytes = 64; + if (cmp_bytes > vnc_server_fb_stride(vd)) { + cmp_bytes = vnc_server_fb_stride(vd); } - guest_row = vd->guest.ds->data; - server_row = vd->server->data; - for (y = 0; y < vd->guest.ds->height; y++) { + if (vd->guest.format != VNC_SERVER_FB_FORMAT) { + int width = pixman_image_get_width(vd->server); + tmpbuf = qemu_pixman_linebuf_create(VNC_SERVER_FB_FORMAT, width); + } + guest_row = (uint8_t *)pixman_image_get_data(vd->guest.fb); + server_row = (uint8_t *)pixman_image_get_data(vd->server); + for (y = 0; y < height; y++) { if (!bitmap_empty(vd->guest.dirty[y], VNC_DIRTY_BITS)) { int x; uint8_t *guest_ptr; uint8_t *server_ptr; - guest_ptr = guest_row; + if (vd->guest.format != VNC_SERVER_FB_FORMAT) { + qemu_pixman_linebuf_fill(tmpbuf, vd->guest.fb, width, y); + guest_ptr = (uint8_t *)pixman_image_get_data(tmpbuf); + } else { + guest_ptr = guest_row; + } server_ptr = server_row; - for (x = 0; x + 15 < vd->guest.ds->width; + for (x = 0; x + 15 < width; x += 16, guest_ptr += cmp_bytes, server_ptr += cmp_bytes) { if (!test_and_clear_bit((x / 16), vd->guest.dirty[y])) continue; @@ -2581,9 +2609,10 @@ static int vnc_refresh_server_surface(VncDisplay *vd) has_dirty++; } } - guest_row += ds_get_linesize(vd->ds); - server_row += ds_get_linesize(vd->ds); + guest_row += pixman_image_get_stride(vd->guest.fb); + server_row += pixman_image_get_stride(vd->server); } + qemu_pixman_image_unref(tmpbuf); return has_dirty; } diff --git a/ui/vnc.h b/ui/vnc.h index 068c2fcda5..d003afbbfd 100644 --- a/ui/vnc.h +++ b/ui/vnc.h @@ -69,7 +69,7 @@ typedef struct VncRectEntry VncRectEntry; typedef int VncReadEvent(VncState *vs, uint8_t *data, size_t len); -typedef void VncWritePixels(VncState *vs, struct PixelFormat *pf, void *data, int size); +typedef void VncWritePixels(VncState *vs, void *data, int size); typedef void VncSendHextileTile(VncState *vs, int x, int y, int w, int h, @@ -117,7 +117,8 @@ struct VncSurface struct timeval last_freq_check; DECLARE_BITMAP(dirty[VNC_MAX_HEIGHT], VNC_MAX_WIDTH / 16); VncRectStat stats[VNC_STAT_ROWS][VNC_STAT_COLS]; - DisplaySurface *ds; + pixman_image_t *fb; + pixman_format_code_t format; }; typedef enum VncShareMode { @@ -151,7 +152,7 @@ struct VncDisplay uint8_t *cursor_mask; struct VncSurface guest; /* guest visible surface (aka ds->surface) */ - DisplaySurface *server; /* vnc server surface */ + pixman_image_t *server; /* vnc server surface */ char *display; char *password; @@ -275,7 +276,9 @@ struct VncState Buffer input; /* current output mode information */ VncWritePixels *write_pixels; - DisplaySurface clientds; + PixelFormat client_pf; + pixman_format_code_t client_format; + bool client_be; CaptureVoiceOut *audio_cap; struct audsettings as; @@ -527,6 +530,14 @@ static inline uint32_t vnc_has_feature(VncState *vs, int feature) { void vnc_framebuffer_update(VncState *vs, int x, int y, int w, int h, int32_t encoding); +/* server fb is in PIXMAN_x8r8g8b8 */ +#define VNC_SERVER_FB_FORMAT PIXMAN_FORMAT(32, PIXMAN_TYPE_ARGB, 0, 8, 8, 8) +#define VNC_SERVER_FB_BITS (PIXMAN_FORMAT_BPP(VNC_SERVER_FB_FORMAT)) +#define VNC_SERVER_FB_BYTES ((VNC_SERVER_FB_BITS+7)/8) + +void *vnc_server_fb_ptr(VncDisplay *vd, int x, int y); +int vnc_server_fb_stride(VncDisplay *vd); + void vnc_convert_pixel(VncState *vs, uint8_t *buf, uint32_t v); double vnc_update_freq(VncState *vs, int x, int y, int w, int h); void vnc_sent_lossy_rect(VncState *vs, int x, int y, int w, int h); From 47683d669f993308c2b84bed4ce64aafb5d7ced4 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Thu, 11 Oct 2012 12:04:33 +0200 Subject: [PATCH 210/291] pixman/vnc: remove rgb_prepare_row* functions Let pixman do it instead. Signed-off-by: Gerd Hoffmann --- ui/vnc-enc-tight.c | 84 ++++++---------------------------------------- 1 file changed, 10 insertions(+), 74 deletions(-) diff --git a/ui/vnc-enc-tight.c b/ui/vnc-enc-tight.c index 8013c5c6dd..9fd255650e 100644 --- a/ui/vnc-enc-tight.c +++ b/ui/vnc-enc-tight.c @@ -1145,74 +1145,6 @@ static int send_palette_rect(VncState *vs, int x, int y, return (bytes >= 0); } -#if defined(CONFIG_VNC_JPEG) || defined(CONFIG_VNC_PNG) -static void rgb_prepare_row24(VncState *vs, uint8_t *dst, int x, int y, - int count) -{ - VncDisplay *vd = vs->vd; - uint32_t *fbptr; - uint32_t pix; - - fbptr = vnc_server_fb_ptr(vd, x, y); - - while (count--) { - pix = *fbptr++; - *dst++ = (uint8_t)(pix >> vs->ds->surface->pf.rshift); - *dst++ = (uint8_t)(pix >> vs->ds->surface->pf.gshift); - *dst++ = (uint8_t)(pix >> vs->ds->surface->pf.bshift); - } -} - -#define DEFINE_RGB_GET_ROW_FUNCTION(bpp) \ - \ - static void \ - rgb_prepare_row##bpp(VncState *vs, uint8_t *dst, \ - int x, int y, int count) \ - { \ - VncDisplay *vd = vs->vd; \ - uint##bpp##_t *fbptr; \ - uint##bpp##_t pix; \ - int r, g, b; \ - \ - fbptr = vnc_server_fb_ptr(vd, x, y); \ - \ - while (count--) { \ - pix = *fbptr++; \ - \ - r = (int)((pix >> vs->ds->surface->pf.rshift) \ - & vs->ds->surface->pf.rmax); \ - g = (int)((pix >> vs->ds->surface->pf.gshift) \ - & vs->ds->surface->pf.gmax); \ - b = (int)((pix >> vs->ds->surface->pf.bshift) \ - & vs->ds->surface->pf.bmax); \ - \ - *dst++ = (uint8_t)((r * 255 + vs->ds->surface->pf.rmax / 2) \ - / vs->ds->surface->pf.rmax); \ - *dst++ = (uint8_t)((g * 255 + vs->ds->surface->pf.gmax / 2) \ - / vs->ds->surface->pf.gmax); \ - *dst++ = (uint8_t)((b * 255 + vs->ds->surface->pf.bmax / 2) \ - / vs->ds->surface->pf.bmax); \ - } \ - } - -DEFINE_RGB_GET_ROW_FUNCTION(16) -DEFINE_RGB_GET_ROW_FUNCTION(32) - -static void rgb_prepare_row(VncState *vs, uint8_t *dst, int x, int y, - int count) -{ - if (VNC_SERVER_FB_BYTES == 4) { - if (1) { - rgb_prepare_row24(vs, dst, x, y, count); - } else { - rgb_prepare_row32(vs, dst, x, y, count); - } - } else { - rgb_prepare_row16(vs, dst, x, y, count); - } -} -#endif /* CONFIG_VNC_JPEG or CONFIG_VNC_PNG */ - /* * JPEG compression stuff. */ @@ -1257,6 +1189,7 @@ static int send_jpeg_rect(VncState *vs, int x, int y, int w, int h, int quality) struct jpeg_compress_struct cinfo; struct jpeg_error_mgr jerr; struct jpeg_destination_mgr manager; + pixman_image_t *linebuf; JSAMPROW row[1]; uint8_t *buf; int dy; @@ -1285,13 +1218,14 @@ static int send_jpeg_rect(VncState *vs, int x, int y, int w, int h, int quality) jpeg_start_compress(&cinfo, true); - buf = g_malloc(w * 3); + linebuf = qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, w); + buf = (uint8_t *)pixman_image_get_data(linebuf); row[0] = buf; for (dy = 0; dy < h; dy++) { - rgb_prepare_row(vs, buf, x, y + dy, w); + qemu_pixman_linebuf_fill(linebuf, vs->vd->server, w, dy); jpeg_write_scanlines(&cinfo, row, 1); } - g_free(buf); + qemu_pixman_image_unref(linebuf); jpeg_finish_compress(&cinfo); jpeg_destroy_compress(&cinfo); @@ -1370,6 +1304,7 @@ static int send_png_rect(VncState *vs, int x, int y, int w, int h, png_structp png_ptr; png_infop info_ptr; png_colorp png_palette = NULL; + pixman_image_t *linebuf; int level = tight_png_conf[vs->tight.compression].png_zlib_level; int filters = tight_png_conf[vs->tight.compression].png_filters; uint8_t *buf; @@ -1424,17 +1359,18 @@ static int send_png_rect(VncState *vs, int x, int y, int w, int h, png_write_info(png_ptr, info_ptr); buffer_reserve(&vs->tight.png, 2048); - buf = g_malloc(w * 3); + linebuf = qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, w); + buf = (uint8_t *)pixman_image_get_data(linebuf); for (dy = 0; dy < h; dy++) { if (color_type == PNG_COLOR_TYPE_PALETTE) { memcpy(buf, vs->tight.tight.buffer + (dy * w), w); } else { - rgb_prepare_row(vs, buf, x, y + dy, w); + qemu_pixman_linebuf_fill(linebuf, vs->vd->server, w, dy); } png_write_row(png_ptr, buf); } - g_free(buf); + qemu_pixman_image_unref(linebuf); png_write_end(png_ptr, NULL); From 94362682d31eb7c9bfd6bf74cd615d0616a09361 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Thu, 11 Oct 2012 12:11:27 +0200 Subject: [PATCH 211/291] pixman/vnc: remove dead code. Switching the vnc server framebuffer to use 32bpp unconditionally turns the code bits which handle 8 and 16 bpp into dead code. Remove them. Signed-off-by: Gerd Hoffmann --- ui/vnc-enc-hextile.c | 32 ---------------------- ui/vnc-enc-tight.c | 64 +++++++++++++++++++------------------------- ui/vnc.c | 18 ------------- 3 files changed, 27 insertions(+), 87 deletions(-) diff --git a/ui/vnc-enc-hextile.c b/ui/vnc-enc-hextile.c index 263a0ce9d2..2e768fd899 100644 --- a/ui/vnc-enc-hextile.c +++ b/ui/vnc-enc-hextile.c @@ -32,30 +32,10 @@ static void hextile_enc_cord(uint8_t *ptr, int x, int y, int w, int h) ptr[1] = (((w - 1) & 0x0F) << 4) | ((h - 1) & 0x0F); } -#define BPP 8 -#include "vnc-enc-hextile-template.h" -#undef BPP - -#define BPP 16 -#include "vnc-enc-hextile-template.h" -#undef BPP - #define BPP 32 #include "vnc-enc-hextile-template.h" #undef BPP -#define GENERIC -#define BPP 8 -#include "vnc-enc-hextile-template.h" -#undef BPP -#undef GENERIC - -#define GENERIC -#define BPP 16 -#include "vnc-enc-hextile-template.h" -#undef BPP -#undef GENERIC - #define GENERIC #define BPP 32 #include "vnc-enc-hextile-template.h" @@ -89,24 +69,12 @@ void vnc_hextile_set_pixel_conversion(VncState *vs, int generic) { if (!generic) { switch (VNC_SERVER_FB_BITS) { - case 8: - vs->hextile.send_tile = send_hextile_tile_8; - break; - case 16: - vs->hextile.send_tile = send_hextile_tile_16; - break; case 32: vs->hextile.send_tile = send_hextile_tile_32; break; } } else { switch (VNC_SERVER_FB_BITS) { - case 8: - vs->hextile.send_tile = send_hextile_tile_generic_8; - break; - case 16: - vs->hextile.send_tile = send_hextile_tile_generic_16; - break; case 32: vs->hextile.send_tile = send_hextile_tile_generic_32; break; diff --git a/ui/vnc-enc-tight.c b/ui/vnc-enc-tight.c index 9fd255650e..9ae4cabffc 100644 --- a/ui/vnc-enc-tight.c +++ b/ui/vnc-enc-tight.c @@ -671,41 +671,35 @@ DEFINE_GRADIENT_FILTER_FUNCTION(32) * that case new color will be stored in *colorPtr. */ -#define DEFINE_CHECK_SOLID_FUNCTION(bpp) \ - \ - static bool \ - check_solid_tile##bpp(VncState *vs, int x, int y, int w, int h, \ - uint32_t* color, bool samecolor) \ - { \ - VncDisplay *vd = vs->vd; \ - uint##bpp##_t *fbptr; \ - uint##bpp##_t c; \ - int dx, dy; \ - \ - fbptr = vnc_server_fb_ptr(vd, x, y); \ - \ - c = *fbptr; \ - if (samecolor && (uint32_t)c != *color) { \ - return false; \ - } \ - \ - for (dy = 0; dy < h; dy++) { \ - for (dx = 0; dx < w; dx++) { \ - if (c != fbptr[dx]) { \ - return false; \ - } \ - } \ - fbptr = (uint##bpp##_t *) \ - ((uint8_t *)fbptr + vnc_server_fb_stride(vd)); \ - } \ - \ - *color = (uint32_t)c; \ - return true; \ +static bool +check_solid_tile32(VncState *vs, int x, int y, int w, int h, + uint32_t *color, bool samecolor) +{ + VncDisplay *vd = vs->vd; + uint32_t *fbptr; + uint32_t c; + int dx, dy; + + fbptr = vnc_server_fb_ptr(vd, x, y); + + c = *fbptr; + if (samecolor && (uint32_t)c != *color) { + return false; } -DEFINE_CHECK_SOLID_FUNCTION(32) -DEFINE_CHECK_SOLID_FUNCTION(16) -DEFINE_CHECK_SOLID_FUNCTION(8) + for (dy = 0; dy < h; dy++) { + for (dx = 0; dx < w; dx++) { + if (c != fbptr[dx]) { + return false; + } + } + fbptr = (uint32_t *) + ((uint8_t *)fbptr + vnc_server_fb_stride(vd)); + } + + *color = (uint32_t)c; + return true; +} static bool check_solid_tile(VncState *vs, int x, int y, int w, int h, uint32_t* color, bool samecolor) @@ -713,10 +707,6 @@ static bool check_solid_tile(VncState *vs, int x, int y, int w, int h, switch (VNC_SERVER_FB_BYTES) { case 4: return check_solid_tile32(vs, x, y, w, h, color, samecolor); - case 2: - return check_solid_tile16(vs, x, y, w, h, color, samecolor); - default: - return check_solid_tile8(vs, x, y, w, h, color, samecolor); } } diff --git a/ui/vnc.c b/ui/vnc.c index 15aef86047..7c120e6f06 100644 --- a/ui/vnc.c +++ b/ui/vnc.c @@ -666,24 +666,6 @@ static void vnc_write_pixels_generic(VncState *vs, vnc_convert_pixel(vs, buf, pixels[i]); vnc_write(vs, buf, vs->client_pf.bytes_per_pixel); } - } else if (VNC_SERVER_FB_BYTES == 2) { - uint16_t *pixels = pixels1; - int n, i; - n = size >> 1; - for (i = 0; i < n; i++) { - vnc_convert_pixel(vs, buf, pixels[i]); - vnc_write(vs, buf, vs->client_pf.bytes_per_pixel); - } - } else if (VNC_SERVER_FB_BYTES == 1) { - uint8_t *pixels = pixels1; - int n, i; - n = size; - for (i = 0; i < n; i++) { - vnc_convert_pixel(vs, buf, pixels[i]); - vnc_write(vs, buf, vs->client_pf.bytes_per_pixel); - } - } else { - fprintf(stderr, "%s: VncState color depth not supported\n", __func__); } } From 64f735920ad319aee860e56bb9bad6cfccf4ad40 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Wed, 10 Oct 2012 11:15:52 +0200 Subject: [PATCH 212/291] pixman: drop obsolete fields from DisplaySurface Signed-off-by: Gerd Hoffmann --- console.c | 9 --------- console.h | 23 +++++++++++++---------- 2 files changed, 13 insertions(+), 19 deletions(-) diff --git a/console.c b/console.c index d28b75ec7d..048b48e721 100644 --- a/console.c +++ b/console.c @@ -1297,14 +1297,10 @@ static QemuConsole *new_console(DisplayState *ds, console_type_t console_type) static void qemu_alloc_display(DisplaySurface *surface, int width, int height, int linesize, PixelFormat pf, int newflags) { - surface->width = width; - surface->height = height; - surface->linesize = linesize; surface->pf = pf; qemu_pixman_image_unref(surface->image); surface->image = NULL; - surface->data = NULL; surface->format = qemu_pixman_get_format(&pf); assert(surface->format != 0); @@ -1313,7 +1309,6 @@ static void qemu_alloc_display(DisplaySurface *surface, int width, int height, NULL, linesize); assert(surface->image != NULL); - surface->data = (uint8_t *)pixman_image_get_data(surface->image); surface->flags = newflags | QEMU_ALLOCATED_FLAG; #ifdef HOST_WORDS_BIGENDIAN surface->flags |= QEMU_BIG_ENDIAN_FLAG; @@ -1347,9 +1342,6 @@ DisplaySurface *qemu_create_displaysurface_from(int width, int height, int bpp, { DisplaySurface *surface = g_new0(DisplaySurface, 1); - surface->width = width; - surface->height = height; - surface->linesize = linesize; surface->pf = qemu_default_pixelformat(bpp); surface->format = qemu_pixman_get_format(&surface->pf); @@ -1362,7 +1354,6 @@ DisplaySurface *qemu_create_displaysurface_from(int width, int height, int bpp, #ifdef HOST_WORDS_BIGENDIAN surface->flags = QEMU_BIG_ENDIAN_FLAG; #endif - surface->data = data; return surface; } diff --git a/console.h b/console.h index 21bd957d95..33ad69b48c 100644 --- a/console.h +++ b/console.h @@ -123,10 +123,6 @@ struct DisplaySurface { pixman_format_code_t format; pixman_image_t *image; uint8_t flags; - int width; - int height; - int linesize; /* bytes per line */ - uint8_t *data; struct PixelFormat pf; }; @@ -346,32 +342,39 @@ static inline bool dpy_cursor_define_supported(struct DisplayState *s) static inline int ds_get_linesize(DisplayState *ds) { - return ds->surface->linesize; + return pixman_image_get_stride(ds->surface->image); } static inline uint8_t* ds_get_data(DisplayState *ds) { - return ds->surface->data; + return (void *)pixman_image_get_data(ds->surface->image); } static inline int ds_get_width(DisplayState *ds) { - return ds->surface->width; + return pixman_image_get_width(ds->surface->image); } static inline int ds_get_height(DisplayState *ds) { - return ds->surface->height; + return pixman_image_get_height(ds->surface->image); } static inline int ds_get_bits_per_pixel(DisplayState *ds) { - return ds->surface->pf.bits_per_pixel; + int bits = PIXMAN_FORMAT_BPP(ds->surface->format); + return bits; } static inline int ds_get_bytes_per_pixel(DisplayState *ds) { - return ds->surface->pf.bytes_per_pixel; + int bits = PIXMAN_FORMAT_BPP(ds->surface->format); + return (bits + 7) / 8; +} + +static inline pixman_format_code_t ds_get_format(DisplayState *ds) +{ + return ds->surface->format; } #ifdef CONFIG_CURSES From 892776ce02e3915b8db9d85935ea144ee5a1a41a Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Mon, 29 Oct 2012 11:34:38 +1000 Subject: [PATCH 213/291] xilinx_zynq: add USB controllers Add the two usb controllers in Zynq. Signed-off-by: Peter Crosthwaite Signed-off-by: Gerd Hoffmann --- hw/xilinx_zynq.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/hw/xilinx_zynq.c b/hw/xilinx_zynq.c index 00262350b6..1f12a3d1ad 100644 --- a/hw/xilinx_zynq.c +++ b/hw/xilinx_zynq.c @@ -166,6 +166,9 @@ static void zynq_init(QEMUMachineInitArgs *args) zynq_init_spi_flashes(0xE0007000, pic[81-IRQ_OFFSET], false); zynq_init_spi_flashes(0xE000D000, pic[51-IRQ_OFFSET], true); + sysbus_create_simple("xlnx,ps7-usb", 0xE0002000, pic[53-IRQ_OFFSET]); + sysbus_create_simple("xlnx,ps7-usb", 0xE0003000, pic[75-IRQ_OFFSET]); + sysbus_create_simple("cadence_uart", 0xE0000000, pic[59-IRQ_OFFSET]); sysbus_create_simple("cadence_uart", 0xE0001000, pic[82-IRQ_OFFSET]); From 2c2e852509de3fecf606e8f2dcbca0ebd1eddc10 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Thu, 25 Oct 2012 16:22:57 +0200 Subject: [PATCH 214/291] uhci: dynamic type generation Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-uhci.c | 194 +++++++++++++++++----------------------------- 1 file changed, 69 insertions(+), 125 deletions(-) diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index b6b972fa92..925c738e7d 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -88,6 +88,16 @@ enum { typedef struct UHCIState UHCIState; typedef struct UHCIAsync UHCIAsync; typedef struct UHCIQueue UHCIQueue; +typedef struct UHCIInfo UHCIInfo; + +struct UHCIInfo { + const char *name; + uint16_t vendor_id; + uint16_t device_id; + uint8_t revision; + int (*initfn)(PCIDevice *dev); + bool unplug; +}; /* * Pending async transaction. @@ -1293,143 +1303,77 @@ static Property uhci_properties[] = { DEFINE_PROP_END_OF_LIST(), }; -static void piix3_uhci_class_init(ObjectClass *klass, void *data) +static void uhci_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + UHCIInfo *info = data; - k->init = usb_uhci_common_initfn; - k->exit = usb_uhci_exit; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82371SB_2; - k->revision = 0x01; - k->class_id = PCI_CLASS_SERIAL_USB; + k->init = info->initfn ? info->initfn : usb_uhci_common_initfn; + k->exit = info->unplug ? usb_uhci_exit : NULL; + k->vendor_id = info->vendor_id; + k->device_id = info->device_id; + k->revision = info->revision; + k->class_id = PCI_CLASS_SERIAL_USB; dc->vmsd = &vmstate_uhci; dc->props = uhci_properties; } -static TypeInfo piix3_uhci_info = { - .name = "piix3-usb-uhci", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(UHCIState), - .class_init = piix3_uhci_class_init, -}; - -static void piix4_uhci_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->init = usb_uhci_common_initfn; - k->exit = usb_uhci_exit; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82371AB_2; - k->revision = 0x01; - k->class_id = PCI_CLASS_SERIAL_USB; - dc->vmsd = &vmstate_uhci; - dc->props = uhci_properties; -} - -static TypeInfo piix4_uhci_info = { - .name = "piix4-usb-uhci", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(UHCIState), - .class_init = piix4_uhci_class_init, -}; - -static void vt82c686b_uhci_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->init = usb_uhci_vt82c686b_initfn; - k->exit = usb_uhci_exit; - k->vendor_id = PCI_VENDOR_ID_VIA; - k->device_id = PCI_DEVICE_ID_VIA_UHCI; - k->revision = 0x01; - k->class_id = PCI_CLASS_SERIAL_USB; - dc->vmsd = &vmstate_uhci; - dc->props = uhci_properties; -} - -static TypeInfo vt82c686b_uhci_info = { - .name = "vt82c686b-usb-uhci", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(UHCIState), - .class_init = vt82c686b_uhci_class_init, -}; - -static void ich9_uhci1_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->init = usb_uhci_common_initfn; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1; - k->revision = 0x03; - k->class_id = PCI_CLASS_SERIAL_USB; - dc->vmsd = &vmstate_uhci; - dc->props = uhci_properties; -} - -static TypeInfo ich9_uhci1_info = { - .name = "ich9-usb-uhci1", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(UHCIState), - .class_init = ich9_uhci1_class_init, -}; - -static void ich9_uhci2_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->init = usb_uhci_common_initfn; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2; - k->revision = 0x03; - k->class_id = PCI_CLASS_SERIAL_USB; - dc->vmsd = &vmstate_uhci; - dc->props = uhci_properties; -} - -static TypeInfo ich9_uhci2_info = { - .name = "ich9-usb-uhci2", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(UHCIState), - .class_init = ich9_uhci2_class_init, -}; - -static void ich9_uhci3_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->init = usb_uhci_common_initfn; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3; - k->revision = 0x03; - k->class_id = PCI_CLASS_SERIAL_USB; - dc->vmsd = &vmstate_uhci; - dc->props = uhci_properties; -} - -static TypeInfo ich9_uhci3_info = { - .name = "ich9-usb-uhci3", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(UHCIState), - .class_init = ich9_uhci3_class_init, +static UHCIInfo uhci_info[] = { + { + .name = "piix3-usb-uhci", + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, + .revision = 0x01, + .unplug = true, + },{ + .name = "piix4-usb-uhci", + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, + .revision = 0x01, + .unplug = true, + },{ + .name = "vt82c686b-usb-uhci", + .vendor_id = PCI_VENDOR_ID_VIA, + .device_id = PCI_DEVICE_ID_VIA_UHCI, + .revision = 0x01, + .initfn = usb_uhci_vt82c686b_initfn, + .unplug = true, + },{ + .name = "ich9-usb-uhci1", + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, + .revision = 0x03, + .unplug = false, + },{ + .name = "ich9-usb-uhci2", + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, + .revision = 0x03, + .unplug = false, + },{ + .name = "ich9-usb-uhci3", + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, + .revision = 0x03, + .unplug = false, + } }; static void uhci_register_types(void) { - type_register_static(&piix3_uhci_info); - type_register_static(&piix4_uhci_info); - type_register_static(&vt82c686b_uhci_info); - type_register_static(&ich9_uhci1_info); - type_register_static(&ich9_uhci2_info); - type_register_static(&ich9_uhci3_info); + TypeInfo uhci_type_info = { + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(UHCIState), + .class_init = uhci_class_init, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(uhci_info); i++) { + uhci_type_info.name = uhci_info[i].name; + uhci_type_info.class_data = uhci_info + i; + type_register(&uhci_type_info); + } } type_init(uhci_register_types) From 8f3f90b0c7d095ba11b1ad558a0b7c2eeb36c8dc Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 26 Oct 2012 14:56:19 +0200 Subject: [PATCH 215/291] uhci: stick irq routing info into UHCIInfo too. Kills the ugly "switch (device_id) { ... }" struct and makes it easier to figure what the differences between the uhci variants are. Need our own DeviceClass struct for that so we can allocate some space to store UHCIInfo. Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-uhci.c | 32 ++++++++++++++++++-------------- 1 file changed, 18 insertions(+), 14 deletions(-) diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index 925c738e7d..27046b65c8 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -89,16 +89,23 @@ typedef struct UHCIState UHCIState; typedef struct UHCIAsync UHCIAsync; typedef struct UHCIQueue UHCIQueue; typedef struct UHCIInfo UHCIInfo; +typedef struct UHCIPCIDeviceClass UHCIPCIDeviceClass; struct UHCIInfo { const char *name; uint16_t vendor_id; uint16_t device_id; uint8_t revision; + uint8_t irq_pin; int (*initfn)(PCIDevice *dev); bool unplug; }; +struct UHCIPCIDeviceClass { + PCIDeviceClass parent_class; + UHCIInfo info; +}; + /* * Pending async transaction. * 'packet' must be the first field because completion @@ -1218,6 +1225,7 @@ static USBBusOps uhci_bus_ops = { static int usb_uhci_common_initfn(PCIDevice *dev) { PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev); + UHCIPCIDeviceClass *u = container_of(pc, UHCIPCIDeviceClass, parent_class); UHCIState *s = DO_UPCAST(UHCIState, dev, dev); uint8_t *pci_conf = s->dev.config; int i; @@ -1226,20 +1234,7 @@ static int usb_uhci_common_initfn(PCIDevice *dev) /* TODO: reset value should be 0. */ pci_conf[USB_SBRN] = USB_RELEASE_1; // release number - switch (pc->device_id) { - case PCI_DEVICE_ID_INTEL_82801I_UHCI1: - s->irq_pin = 0; /* A */ - break; - case PCI_DEVICE_ID_INTEL_82801I_UHCI2: - s->irq_pin = 1; /* B */ - break; - case PCI_DEVICE_ID_INTEL_82801I_UHCI3: - s->irq_pin = 2; /* C */ - break; - default: - s->irq_pin = 3; /* D */ - break; - } + s->irq_pin = u->info.irq_pin; pci_config_set_interrupt_pin(pci_conf, s->irq_pin + 1); if (s->masterbus) { @@ -1307,6 +1302,7 @@ static void uhci_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + UHCIPCIDeviceClass *u = container_of(k, UHCIPCIDeviceClass, parent_class); UHCIInfo *info = data; k->init = info->initfn ? info->initfn : usb_uhci_common_initfn; @@ -1317,6 +1313,7 @@ static void uhci_class_init(ObjectClass *klass, void *data) k->class_id = PCI_CLASS_SERIAL_USB; dc->vmsd = &vmstate_uhci; dc->props = uhci_properties; + u->info = *info; } static UHCIInfo uhci_info[] = { @@ -1325,18 +1322,21 @@ static UHCIInfo uhci_info[] = { .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82371SB_2, .revision = 0x01, + .irq_pin = 3, .unplug = true, },{ .name = "piix4-usb-uhci", .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82371AB_2, .revision = 0x01, + .irq_pin = 3, .unplug = true, },{ .name = "vt82c686b-usb-uhci", .vendor_id = PCI_VENDOR_ID_VIA, .device_id = PCI_DEVICE_ID_VIA_UHCI, .revision = 0x01, + .irq_pin = 3, .initfn = usb_uhci_vt82c686b_initfn, .unplug = true, },{ @@ -1344,18 +1344,21 @@ static UHCIInfo uhci_info[] = { .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, .revision = 0x03, + .irq_pin = 0, .unplug = false, },{ .name = "ich9-usb-uhci2", .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, .revision = 0x03, + .irq_pin = 1, .unplug = false, },{ .name = "ich9-usb-uhci3", .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, .revision = 0x03, + .irq_pin = 2, .unplug = false, } }; @@ -1365,6 +1368,7 @@ static void uhci_register_types(void) TypeInfo uhci_type_info = { .parent = TYPE_PCI_DEVICE, .instance_size = sizeof(UHCIState), + .class_size = sizeof(UHCIPCIDeviceClass), .class_init = uhci_class_init, }; int i; From 74625ea27c39df7047ebefb11c4a04c3a3513f16 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 30 Oct 2012 09:57:28 +0100 Subject: [PATCH 216/291] uhci: add ich9 00:1a.* variants Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-uhci.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index 27046b65c8..71263fe143 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -1340,26 +1340,47 @@ static UHCIInfo uhci_info[] = { .initfn = usb_uhci_vt82c686b_initfn, .unplug = true, },{ - .name = "ich9-usb-uhci1", + .name = "ich9-usb-uhci1", /* 00:1d.0 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI1, .revision = 0x03, .irq_pin = 0, .unplug = false, },{ - .name = "ich9-usb-uhci2", + .name = "ich9-usb-uhci2", /* 00:1d.1 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI2, .revision = 0x03, .irq_pin = 1, .unplug = false, },{ - .name = "ich9-usb-uhci3", + .name = "ich9-usb-uhci3", /* 00:1d.2 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI3, .revision = 0x03, .irq_pin = 2, .unplug = false, + },{ + .name = "ich9-usb-uhci4", /* 00:1a.0 */ + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI4, + .revision = 0x03, + .irq_pin = 0, + .unplug = false, + },{ + .name = "ich9-usb-uhci5", /* 00:1a.1 */ + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI5, + .revision = 0x03, + .irq_pin = 1, + .unplug = false, + },{ + .name = "ich9-usb-uhci6", /* 00:1a.2 */ + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82801I_UHCI6, + .revision = 0x03, + .irq_pin = 2, + .unplug = false, } }; From df013187777efc62faeea979cfec2ca4470cc34b Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 30 Oct 2012 12:53:17 +0100 Subject: [PATCH 217/291] usb/ehci-pci: dynamic type generation Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-ehci-pci.c | 66 +++++++++++++++++++++++-------------------- 1 file changed, 35 insertions(+), 31 deletions(-) diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c index daac41d7f8..df137cccc9 100644 --- a/hw/usb/hcd-ehci-pci.c +++ b/hw/usb/hcd-ehci-pci.c @@ -23,6 +23,13 @@ typedef struct EHCIPCIState { EHCIState ehci; } EHCIPCIState; +typedef struct EHCIPCIInfo { + const char *name; + uint16_t vendor_id; + uint16_t device_id; + uint8_t revision; +} EHCIPCIInfo; + static int usb_ehci_pci_initfn(PCIDevice *dev) { EHCIPCIState *i = DO_UPCAST(EHCIPCIState, pcidev, dev); @@ -91,48 +98,45 @@ static void ehci_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + EHCIPCIInfo *i = data; k->init = usb_ehci_pci_initfn; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */ - k->revision = 0x10; + k->vendor_id = i->vendor_id; + k->device_id = i->device_id; + k->revision = i->revision; k->class_id = PCI_CLASS_SERIAL_USB; dc->vmsd = &vmstate_ehci; dc->props = ehci_pci_properties; } -static TypeInfo ehci_info = { - .name = "usb-ehci", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(EHCIState), - .class_init = ehci_class_init, -}; - -static void ich9_ehci_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->init = usb_ehci_pci_initfn; - k->vendor_id = PCI_VENDOR_ID_INTEL; - k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1; - k->revision = 0x03; - k->class_id = PCI_CLASS_SERIAL_USB; - dc->vmsd = &vmstate_ehci; - dc->props = ehci_pci_properties; -} - -static TypeInfo ich9_ehci_info = { - .name = "ich9-usb-ehci1", - .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(EHCIState), - .class_init = ich9_ehci_class_init, +static struct EHCIPCIInfo ehci_pci_info[] = { + { + .name = "usb-ehci", + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82801D, /* ich4 */ + .revision = 0x10, + },{ + .name = "ich9-usb-ehci1", + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1, + .revision = 0x03, + } }; static void ehci_pci_register_types(void) { - type_register_static(&ehci_info); - type_register_static(&ich9_ehci_info); + TypeInfo ehci_type_info = { + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(EHCIPCIState), + .class_init = ehci_class_init, + }; + int i; + + for (i = 0; i < ARRAY_SIZE(ehci_pci_info); i++) { + ehci_type_info.name = ehci_pci_info[i].name; + ehci_type_info.class_data = ehci_pci_info + i; + type_register(&ehci_type_info); + } } type_init(ehci_pci_register_types) From ba07630c79807147786d3fd033e2762ae84eb132 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 30 Oct 2012 13:17:46 +0100 Subject: [PATCH 218/291] usb/ehci-pci: add ich9 00:1a.* variant Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-ehci-pci.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c index df137cccc9..79bc276a44 100644 --- a/hw/usb/hcd-ehci-pci.c +++ b/hw/usb/hcd-ehci-pci.c @@ -116,10 +116,15 @@ static struct EHCIPCIInfo ehci_pci_info[] = { .device_id = PCI_DEVICE_ID_INTEL_82801D, /* ich4 */ .revision = 0x10, },{ - .name = "ich9-usb-ehci1", + .name = "ich9-usb-ehci1", /* 00:1d.7 */ .vendor_id = PCI_VENDOR_ID_INTEL, .device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1, .revision = 0x03, + },{ + .name = "ich9-usb-ehci2", /* 00:1a.7 */ + .vendor_id = PCI_VENDOR_ID_INTEL, + .device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI2, + .revision = 0x03, } }; From bb4d2b2f0aad4a940db86eb469de0bf91c1c6837 Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Tue, 30 Oct 2012 13:18:36 +0100 Subject: [PATCH 219/291] usb/ehci-pci: add helper to create ich9 usb controllers Signed-off-by: Gerd Hoffmann --- hw/usb.h | 2 ++ hw/usb/hcd-ehci-pci.c | 53 +++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/hw/usb.h b/hw/usb.h index 3a6cc8444a..1837bf780f 100644 --- a/hw/usb.h +++ b/hw/usb.h @@ -524,5 +524,7 @@ const char *usb_device_get_product_desc(USBDevice *dev); const USBDesc *usb_device_get_usb_desc(USBDevice *dev); +int ehci_create_ich9_with_companions(PCIBus *bus, int slot); + #endif diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c index 79bc276a44..d5c7d462d0 100644 --- a/hw/usb/hcd-ehci-pci.c +++ b/hw/usb/hcd-ehci-pci.c @@ -145,3 +145,56 @@ static void ehci_pci_register_types(void) } type_init(ehci_pci_register_types) + +struct ehci_companions { + const char *name; + int func; + int port; +}; + +static const struct ehci_companions ich9_1d[] = { + { .name = "ich9-usb-uhci1", .func = 0, .port = 0 }, + { .name = "ich9-usb-uhci2", .func = 1, .port = 2 }, + { .name = "ich9-usb-uhci3", .func = 2, .port = 4 }, +}; + +static const struct ehci_companions ich9_1a[] = { + { .name = "ich9-usb-uhci4", .func = 0, .port = 0 }, + { .name = "ich9-usb-uhci5", .func = 1, .port = 2 }, + { .name = "ich9-usb-uhci6", .func = 2, .port = 4 }, +}; + +int ehci_create_ich9_with_companions(PCIBus *bus, int slot) +{ + const struct ehci_companions *comp; + PCIDevice *ehci, *uhci; + BusState *usbbus; + const char *name; + int i; + + switch (slot) { + case 0x1d: + name = "ich9-usb-ehci1"; + comp = ich9_1d; + break; + case 0x1a: + name = "ich9-usb-ehci2"; + comp = ich9_1a; + break; + default: + return -1; + } + + ehci = pci_create_multifunction(bus, PCI_DEVFN(slot, 7), true, name); + qdev_init_nofail(&ehci->qdev); + usbbus = QLIST_FIRST(&ehci->qdev.child_bus); + + for (i = 0; i < 3; i++) { + uhci = pci_create_multifunction(bus, PCI_DEVFN(slot, comp[i].func), + true, comp[i].name); + qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name); + qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port); + qdev_init_nofail(&uhci->qdev); + } + return 0; +} From faccca000f27bb63fce0c71dc4ca68be1c23a8b0 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 31 Oct 2012 12:54:36 +0100 Subject: [PATCH 220/291] uhci: Add a uhci_handle_td_error() helper function Signed-off-by: Hans de Goede Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-uhci.c | 90 +++++++++++++++++++++++++---------------------- 1 file changed, 47 insertions(+), 43 deletions(-) diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index 71263fe143..a06372b461 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -735,9 +735,52 @@ static void uhci_read_td(UHCIState *s, UHCI_TD *td, uint32_t link) le32_to_cpus(&td->buffer); } +static int uhci_handle_td_error(UHCIState *s, UHCI_TD *td, uint32_t td_addr, + int status, uint32_t *int_mask) +{ + uint32_t queue_token = uhci_queue_token(td); + int ret; + + switch (status) { + case USB_RET_NAK: + td->ctrl |= TD_CTRL_NAK; + return TD_RESULT_NEXT_QH; + + case USB_RET_STALL: + td->ctrl |= TD_CTRL_STALL; + trace_usb_uhci_packet_complete_stall(queue_token, td_addr); + ret = TD_RESULT_NEXT_QH; + break; + + case USB_RET_BABBLE: + td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; + /* frame interrupted */ + trace_usb_uhci_packet_complete_babble(queue_token, td_addr); + ret = TD_RESULT_STOP_FRAME; + break; + + case USB_RET_IOERROR: + case USB_RET_NODEV: + default: + td->ctrl |= TD_CTRL_TIMEOUT; + td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); + trace_usb_uhci_packet_complete_error(queue_token, td_addr); + ret = TD_RESULT_NEXT_QH; + break; + } + + td->ctrl &= ~TD_CTRL_ACTIVE; + s->status |= UHCI_STS_USBERR; + if (td->ctrl & TD_CTRL_IOC) { + *int_mask |= 0x01; + } + uhci_update_irq(s); + return ret; +} + static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_t *int_mask) { - int len = 0, max_len, err, ret; + int len = 0, max_len, ret; uint8_t pid; max_len = ((td->token >> 21) + 1) & 0x7ff; @@ -748,8 +791,9 @@ static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_ if (td->ctrl & TD_CTRL_IOS) td->ctrl &= ~TD_CTRL_ACTIVE; - if (ret < 0) - goto out; + if (ret < 0) { + return uhci_handle_td_error(s, td, async->td_addr, ret, int_mask); + } len = async->packet.result; td->ctrl = (td->ctrl & ~0x7ff) | ((len - 1) & 0x7ff); @@ -775,46 +819,6 @@ static int uhci_complete_td(UHCIState *s, UHCI_TD *td, UHCIAsync *async, uint32_ trace_usb_uhci_packet_complete_success(async->queue->token, async->td_addr); return TD_RESULT_COMPLETE; - -out: - switch(ret) { - case USB_RET_NAK: - td->ctrl |= TD_CTRL_NAK; - return TD_RESULT_NEXT_QH; - - case USB_RET_STALL: - td->ctrl |= TD_CTRL_STALL; - trace_usb_uhci_packet_complete_stall(async->queue->token, - async->td_addr); - err = TD_RESULT_NEXT_QH; - break; - - case USB_RET_BABBLE: - td->ctrl |= TD_CTRL_BABBLE | TD_CTRL_STALL; - /* frame interrupted */ - trace_usb_uhci_packet_complete_babble(async->queue->token, - async->td_addr); - err = TD_RESULT_STOP_FRAME; - break; - - case USB_RET_IOERROR: - case USB_RET_NODEV: - default: - td->ctrl |= TD_CTRL_TIMEOUT; - td->ctrl &= ~(3 << TD_CTRL_ERROR_SHIFT); - trace_usb_uhci_packet_complete_error(async->queue->token, - async->td_addr); - err = TD_RESULT_NEXT_QH; - break; - } - - td->ctrl &= ~TD_CTRL_ACTIVE; - s->status |= UHCI_STS_USBERR; - if (td->ctrl & TD_CTRL_IOC) { - *int_mask |= 0x01; - } - uhci_update_irq(s); - return err; } static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, From 7f102ebeb5bad7b723a25557234b0feb493f6134 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 31 Oct 2012 12:54:37 +0100 Subject: [PATCH 221/291] uhci: Don't crash on device disconnect My recent uhci cleanup series has introduced a regression, where qemu sometimes crashes on a device disconnect. The problem is that the uhci code never checked for a device not / no longer existing, instead it was relying on usb_handle_packet accepting a NULL device. But since we now pass usb_handle_packet q->ep->dev, rather then just a local dev variable, we crash as q->ep == NULL due to the device no longer existing. This patch fixes this. Note that this patch also improves over the old behavior were we would: 1) create a queue for the device 2) create an async for the packet 3) have usb_handle_packet fail 4) destroy the async 5) wait for the queue to be idle for 32 frames 6) destroy the queue Which was rather sub-optimal. Signed-off-by: Hans de Goede Signed-off-by: Gerd Hoffmann --- hw/usb/hcd-uhci.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index a06372b461..f4b555addc 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -896,6 +896,11 @@ static int uhci_handle_td(UHCIState *s, UHCIQueue *q, uint32_t qh_addr, if (q == NULL) { USBDevice *dev = uhci_find_device(s, (td->token >> 8) & 0x7f); USBEndpoint *ep = usb_ep_get(dev, pid, (td->token >> 15) & 0xf); + + if (ep == NULL) { + return uhci_handle_td_error(s, td, td_addr, USB_RET_NODEV, + int_mask); + } q = uhci_queue_new(s, qh_addr, td, ep); } async = uhci_async_alloc(q, td_addr); From a552a966f16b7b39c5df16fc17e12d02c4fa5954 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 31 Oct 2012 13:47:09 +0100 Subject: [PATCH 222/291] usb: Add packet combining functions Currently we only do pipelining for output endpoints, since to properly support short-not-ok semantics we can only have one outstanding input packet. Since the ehci and uhci controllers have a limited per td packet size guests will split large input transfers to into multiple packets, and since we don't pipeline these, this comes with a serious performance penalty. This patch adds helper functions to (re-)combine packets which belong to 1 transfer at the guest device-driver level into 1 large transger. This can be used by (redirection) usb-devices to enable pipelining for input endpoints. This patch will combine packets together until a transfer terminating packet is encountered. A terminating packet is a packet which meets one or more of the following conditions: 1) The packet size is *not* a multiple of the endpoint max packet size 2) The packet does *not* have its short-not-ok flag set 3) The packet has its interrupt-on-complete flag set The short-not-ok flag of the combined packet is that of the terminating packet. Multiple combined packets may be submitted to the device, if the combined packets do not have their short-not-ok flag set, enabling true pipelining. If a combined packet does have its short-not-ok flag set the queue will wait with submitting further packets to the device until that packet has completed. Once enabled in the usb-redir and ehci code, this improves the speed (MB/s) of a Linux guest reading from a USB mass storage device by a factor of 1.2 - 1.5. And the main reason why I started working on this, when reading from a pl2303 USB<->serial converter, it combines the previous 4 packets submitted per device-driver level read into 1 big read, reducing the number of packets / sec by a factor 4, and it allows to have multiple reads outstanding. This allows for much better latency tolerance without the pl2303's internal buffer overflowing (which was happening at 115200 bps, without serial flow control). Signed-off-by: Hans de Goede Signed-off-by: Gerd Hoffmann --- hw/usb.h | 13 +++ hw/usb/Makefile.objs | 2 +- hw/usb/combined-packet.c | 179 +++++++++++++++++++++++++++++++++++++++ hw/usb/core.c | 1 + 4 files changed, 194 insertions(+), 1 deletion(-) create mode 100644 hw/usb/combined-packet.c diff --git a/hw/usb.h b/hw/usb.h index 1837bf780f..aef07f4a07 100644 --- a/hw/usb.h +++ b/hw/usb.h @@ -160,6 +160,7 @@ typedef struct USBBusOps USBBusOps; typedef struct USBPort USBPort; typedef struct USBDevice USBDevice; typedef struct USBPacket USBPacket; +typedef struct USBCombinedPacket USBCombinedPacket; typedef struct USBEndpoint USBEndpoint; typedef struct USBDesc USBDesc; @@ -356,7 +357,15 @@ struct USBPacket { int result; /* transfer length or USB_RET_* status code */ /* Internal use by the USB layer. */ USBPacketState state; + USBCombinedPacket *combined; QTAILQ_ENTRY(USBPacket) queue; + QTAILQ_ENTRY(USBPacket) combined_entry; +}; + +struct USBCombinedPacket { + USBPacket *first; + QTAILQ_HEAD(packets_head, USBPacket) packets; + QEMUIOVector iov; }; void usb_packet_init(USBPacket *p); @@ -399,6 +408,10 @@ void usb_ep_set_pipeline(USBDevice *dev, int pid, int ep, bool enabled); USBPacket *usb_ep_find_packet_by_id(USBDevice *dev, int pid, int ep, uint64_t id); +void usb_ep_combine_input_packets(USBEndpoint *ep); +void usb_combined_input_packet_complete(USBDevice *dev, USBPacket *p); +void usb_combined_packet_cancel(USBDevice *dev, USBPacket *p); + void usb_attach(USBPort *port); void usb_detach(USBPort *port); void usb_port_reset(USBPort *port); diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs index 7669938abd..5a4eeb6d13 100644 --- a/hw/usb/Makefile.objs +++ b/hw/usb/Makefile.objs @@ -7,7 +7,7 @@ common-obj-y += libhw.o common-obj-$(CONFIG_SMARTCARD) += dev-smartcard-reader.o common-obj-$(CONFIG_USB_REDIR) += redirect.o -common-obj-y += core.o bus.o desc.o dev-hub.o +common-obj-y += core.o combined-packet.o bus.o desc.o dev-hub.o common-obj-y += host-$(HOST_USB).o dev-bluetooth.o common-obj-y += dev-hid.o dev-storage.o dev-wacom.o common-obj-y += dev-serial.o dev-network.o dev-audio.o diff --git a/hw/usb/combined-packet.c b/hw/usb/combined-packet.c new file mode 100644 index 0000000000..652bf02628 --- /dev/null +++ b/hw/usb/combined-packet.c @@ -0,0 +1,179 @@ +/* + * QEMU USB packet combining code (for input pipelining) + * + * Copyright(c) 2012 Red Hat, Inc. + * + * Red Hat Authors: + * Hans de Goede + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or(at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see . + */ +#include "qemu-common.h" +#include "hw/usb.h" +#include "iov.h" +#include "trace.h" + +static void usb_combined_packet_add(USBCombinedPacket *combined, USBPacket *p) +{ + qemu_iovec_concat(&combined->iov, &p->iov, 0, p->iov.size); + QTAILQ_INSERT_TAIL(&combined->packets, p, combined_entry); + p->combined = combined; +} + +static void usb_combined_packet_remove(USBCombinedPacket *combined, + USBPacket *p) +{ + assert(p->combined == combined); + p->combined = NULL; + QTAILQ_REMOVE(&combined->packets, p, combined_entry); +} + +/* Also handles completion of non combined packets for pipelined input eps */ +void usb_combined_input_packet_complete(USBDevice *dev, USBPacket *p) +{ + USBCombinedPacket *combined = p->combined; + USBEndpoint *ep = p->ep; + USBPacket *next; + enum { completing, complete, leftover }; + int result, state = completing; + bool short_not_ok; + + if (combined == NULL) { + usb_packet_complete_one(dev, p); + goto leave; + } + + assert(combined->first == p && p == QTAILQ_FIRST(&combined->packets)); + + result = combined->first->result; + short_not_ok = QTAILQ_LAST(&combined->packets, packets_head)->short_not_ok; + + QTAILQ_FOREACH_SAFE(p, &combined->packets, combined_entry, next) { + if (state == completing) { + /* Distribute data over uncombined packets */ + if (result >= p->iov.size) { + p->result = p->iov.size; + } else { + /* Send short or error packet to complete the transfer */ + p->result = result; + state = complete; + } + p->short_not_ok = short_not_ok; + usb_combined_packet_remove(combined, p); + usb_packet_complete_one(dev, p); + result -= p->result; + } else { + /* Remove any leftover packets from the queue */ + state = leftover; + p->result = USB_RET_REMOVE_FROM_QUEUE; + dev->port->ops->complete(dev->port, p); + } + } + /* + * If we had leftover packets the hcd driver will have cancelled them + * and usb_combined_packet_cancel has already freed combined! + */ + if (state != leftover) { + g_free(combined); + } +leave: + /* Check if there are packets in the queue waiting for our completion */ + usb_ep_combine_input_packets(ep); +} + +/* May only be called for combined packets! */ +void usb_combined_packet_cancel(USBDevice *dev, USBPacket *p) +{ + USBCombinedPacket *combined = p->combined; + assert(combined != NULL); + + usb_combined_packet_remove(combined, p); + if (p == combined->first) { + usb_device_cancel_packet(dev, p); + } + if (QTAILQ_EMPTY(&combined->packets)) { + g_free(combined); + } +} + +/* + * Large input transfers can get split into multiple input packets, this + * function recombines them, removing the short_not_ok checks which all but + * the last packet of such splits transfers have, thereby allowing input + * transfer pipelining (which we cannot do on short_not_ok transfers) + */ +void usb_ep_combine_input_packets(USBEndpoint *ep) +{ + USBPacket *p, *u, *next, *prev = NULL, *first = NULL; + USBPort *port = ep->dev->port; + int ret; + + assert(ep->pipeline); + assert(ep->pid == USB_TOKEN_IN); + + QTAILQ_FOREACH_SAFE(p, &ep->queue, queue, next) { + /* Empty the queue on a halt */ + if (ep->halted) { + p->result = USB_RET_REMOVE_FROM_QUEUE; + port->ops->complete(port, p); + continue; + } + + /* Skip packets already submitted to the device */ + if (p->state == USB_PACKET_ASYNC) { + prev = p; + continue; + } + usb_packet_check_state(p, USB_PACKET_QUEUED); + + /* + * If the previous (combined) packet has the short_not_ok flag set + * stop, as we must not submit packets to the device after a transfer + * ending with short_not_ok packet. + */ + if (prev && prev->short_not_ok) { + break; + } + + if (first) { + if (first->combined == NULL) { + USBCombinedPacket *combined = g_new0(USBCombinedPacket, 1); + + combined->first = first; + QTAILQ_INIT(&combined->packets); + qemu_iovec_init(&combined->iov, 2); + usb_combined_packet_add(combined, first); + } + usb_combined_packet_add(first->combined, p); + } else { + first = p; + } + + /* Is this packet the last one of a (combined) transfer? */ + if ((p->iov.size % ep->max_packet_size) != 0 || !p->short_not_ok || + next == NULL) { + ret = usb_device_handle_data(ep->dev, first); + assert(ret == USB_RET_ASYNC); + if (first->combined) { + QTAILQ_FOREACH(u, &first->combined->packets, combined_entry) { + usb_packet_set_state(u, USB_PACKET_ASYNC); + } + } else { + usb_packet_set_state(first, USB_PACKET_ASYNC); + } + first = NULL; + prev = p; + } + } +} diff --git a/hw/usb/core.c b/hw/usb/core.c index 632a8efe47..ab37f6f7b8 100644 --- a/hw/usb/core.c +++ b/hw/usb/core.c @@ -545,6 +545,7 @@ void usb_packet_setup(USBPacket *p, int pid, USBEndpoint *ep, uint64_t id, p->parameter = 0; p->short_not_ok = short_not_ok; p->int_req = int_req; + p->combined = NULL; qemu_iovec_reset(&p->iov); usb_packet_set_state(p, USB_PACKET_SETUP); } From 579967bea69bf1b32faee13ff76b19ba641a2618 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 31 Oct 2012 13:47:10 +0100 Subject: [PATCH 223/291] combined-packet: Add a workaround for Linux usbfs + live migration Older versions (anything but the latest) of Linux usbfs + libusb(x), will submit larger (bulk) transfers split into multiple 16k submissions, which means that rather then all tds getting linked into the queue in one atomic operarion they get linked in a bunch at a time, which could cause problems if: 1) We scan the queue while libusb is in the middle of submitting a split bulk transfer 2) While this bulk transfer is pending we migrate to another host. The problem is that after 2, the new host will rescan the queue and combine the packets in one large transfer, where as 1) has caused the original host to see them as 2 transfers. This patch fixes this by stopping combinging if we detect a 16k transfer with its int_req flag set. This should not adversely effect performance for other cases as: 1) Linux never sets the interrupt flag on packets other then the last 2) Windows does set the in_req flag on each td, but will submit large transfers in 20k tds thus never triggering the check Signed-off-by: Hans de Goede Signed-off-by: Gerd Hoffmann --- hw/usb/combined-packet.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/hw/usb/combined-packet.c b/hw/usb/combined-packet.c index 652bf02628..3904e71634 100644 --- a/hw/usb/combined-packet.c +++ b/hw/usb/combined-packet.c @@ -117,7 +117,7 @@ void usb_ep_combine_input_packets(USBEndpoint *ep) { USBPacket *p, *u, *next, *prev = NULL, *first = NULL; USBPort *port = ep->dev->port; - int ret; + int ret, totalsize; assert(ep->pipeline); assert(ep->pid == USB_TOKEN_IN); @@ -161,8 +161,11 @@ void usb_ep_combine_input_packets(USBEndpoint *ep) } /* Is this packet the last one of a (combined) transfer? */ + totalsize = (p->combined) ? p->combined->iov.size : p->iov.size; if ((p->iov.size % ep->max_packet_size) != 0 || !p->short_not_ok || - next == NULL) { + next == NULL || + /* Work around for Linux usbfs bulk splitting + migration */ + (totalsize == 16348 && p->int_req)) { ret = usb_device_handle_data(ep->dev, first); assert(ret == USB_RET_ASYNC); if (first->combined) { From c19a798133e936a15ee0175ebc973d777c4c62ed Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 31 Oct 2012 13:47:11 +0100 Subject: [PATCH 224/291] usb-redir: Add support for 32 bits bulk packet length Signed-off-by: Hans de Goede Signed-off-by: Gerd Hoffmann --- configure | 2 +- hw/usb/redirect.c | 7 ++++++- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 9c6ac875a5..fbebf0f448 100755 --- a/configure +++ b/configure @@ -2755,7 +2755,7 @@ fi # check for usbredirparser for usb network redirection support if test "$usb_redir" != "no" ; then - if $pkg_config --atleast-version=0.5 libusbredirparser-0.5 >/dev/null 2>&1 ; then + if $pkg_config --atleast-version=0.5.3 libusbredirparser-0.5 >/dev/null 2>&1 ; then usb_redir="yes" usb_redir_cflags=$($pkg_config --cflags libusbredirparser-0.5 2>/dev/null) usb_redir_libs=$($pkg_config --libs libusbredirparser-0.5 2>/dev/null) diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index 22f671b3b1..6008620241 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -575,6 +575,10 @@ static int usbredir_handle_bulk_data(USBRedirDevice *dev, USBPacket *p, bulk_packet.endpoint = ep; bulk_packet.length = p->iov.size; bulk_packet.stream_id = 0; + bulk_packet.length_high = p->iov.size >> 16; + assert(bulk_packet.length_high == 0 || + usbredirparser_peer_has_cap(dev->parser, + usb_redir_cap_32bits_bulk_length)); if (ep & USB_DIR_IN) { usbredirparser_send_bulk_packet(dev->parser, p->id, @@ -896,6 +900,7 @@ static void usbredir_create_parser(USBRedirDevice *dev) usbredirparser_caps_set_cap(caps, usb_redir_cap_filter); usbredirparser_caps_set_cap(caps, usb_redir_cap_ep_info_max_packet_size); usbredirparser_caps_set_cap(caps, usb_redir_cap_64bits_ids); + usbredirparser_caps_set_cap(caps, usb_redir_cap_32bits_bulk_length); if (runstate_check(RUN_STATE_INMIGRATE)) { flags |= usbredirparser_fl_no_hello; @@ -1452,7 +1457,7 @@ static void usbredir_bulk_packet(void *priv, uint64_t id, { USBRedirDevice *dev = priv; uint8_t ep = bulk_packet->endpoint; - int len = bulk_packet->length; + int len = (bulk_packet->length_high << 16) | bulk_packet->length; USBPacket *p; DPRINTF("bulk-in status %d ep %02X len %d id %"PRIu64"\n", From 1b36c4d826b586de40efd0c2d3c269b14ca8e150 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 31 Oct 2012 13:47:12 +0100 Subject: [PATCH 225/291] usb-redir: Add support for input pipelining Signed-off-by: Hans de Goede Signed-off-by: Gerd Hoffmann --- hw/usb/redirect.c | 63 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 53 insertions(+), 10 deletions(-) diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index 6008620241..448cfabb17 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -29,6 +29,7 @@ #include "qemu-timer.h" #include "monitor.h" #include "sysemu.h" +#include "iov.h" #include #include @@ -312,6 +313,11 @@ static void usbredir_cancel_packet(USBDevice *udev, USBPacket *p) { USBRedirDevice *dev = DO_UPCAST(USBRedirDevice, dev, udev); + if (p->combined) { + usb_combined_packet_cancel(udev, p); + return; + } + packet_id_queue_add(&dev->cancelled, p->id); usbredirparser_send_cancel_data_packet(dev->parser, p->id); usbredirparser_do_write(dev->parser); @@ -331,6 +337,10 @@ static void usbredir_fill_already_in_flight_from_ep(USBRedirDevice *dev, static USBPacket *p; QTAILQ_FOREACH(p, &ep->queue, queue) { + /* Skip combined packets, except for the first */ + if (p->combined && p != p->combined->first) { + continue; + } packet_id_queue_add(&dev->already_in_flight, p->id); } } @@ -565,17 +575,18 @@ static int usbredir_handle_bulk_data(USBRedirDevice *dev, USBPacket *p, uint8_t ep) { struct usb_redir_bulk_packet_header bulk_packet; + size_t size = (p->combined) ? p->combined->iov.size : p->iov.size; - DPRINTF("bulk-out ep %02X len %zd id %"PRIu64"\n", ep, p->iov.size, p->id); + DPRINTF("bulk-out ep %02X len %zd id %"PRIu64"\n", ep, size, p->id); if (usbredir_already_in_flight(dev, p->id)) { return USB_RET_ASYNC; } bulk_packet.endpoint = ep; - bulk_packet.length = p->iov.size; + bulk_packet.length = size; bulk_packet.stream_id = 0; - bulk_packet.length_high = p->iov.size >> 16; + bulk_packet.length_high = size >> 16; assert(bulk_packet.length_high == 0 || usbredirparser_peer_has_cap(dev->parser, usb_redir_cap_32bits_bulk_length)); @@ -584,11 +595,16 @@ static int usbredir_handle_bulk_data(USBRedirDevice *dev, USBPacket *p, usbredirparser_send_bulk_packet(dev->parser, p->id, &bulk_packet, NULL, 0); } else { - uint8_t buf[p->iov.size]; - usb_packet_copy(p, buf, p->iov.size); - usbredir_log_data(dev, "bulk data out:", buf, p->iov.size); + uint8_t buf[size]; + if (p->combined) { + iov_to_buf(p->combined->iov.iov, p->combined->iov.niov, + 0, buf, size); + } else { + usb_packet_copy(p, buf, size); + } + usbredir_log_data(dev, "bulk data out:", buf, size); usbredirparser_send_bulk_packet(dev->parser, p->id, - &bulk_packet, buf, p->iov.size); + &bulk_packet, buf, size); } usbredirparser_do_write(dev->parser); return USB_RET_ASYNC; @@ -705,6 +721,10 @@ static int usbredir_handle_data(USBDevice *udev, USBPacket *p) case USB_ENDPOINT_XFER_ISOC: return usbredir_handle_iso_data(dev, p, ep); case USB_ENDPOINT_XFER_BULK: + if (p->state == USB_PACKET_SETUP && p->pid == USB_TOKEN_IN && + p->ep->pipeline) { + return USB_RET_ADD_TO_QUEUE; + } return usbredir_handle_bulk_data(dev, p, ep); case USB_ENDPOINT_XFER_INT: return usbredir_handle_interrupt_data(dev, p, ep); @@ -715,6 +735,13 @@ static int usbredir_handle_data(USBDevice *udev, USBPacket *p) } } +static void usbredir_flush_ep_queue(USBDevice *dev, USBEndpoint *ep) +{ + if (ep->pid == USB_TOKEN_IN && ep->pipeline) { + usb_ep_combine_input_packets(ep); + } +} + static int usbredir_set_config(USBRedirDevice *dev, USBPacket *p, int config) { @@ -1283,6 +1310,11 @@ static void usbredir_set_pipeline(USBRedirDevice *dev, struct USBEndpoint *uep) if (uep->pid == USB_TOKEN_OUT) { uep->pipeline = true; } + if (uep->pid == USB_TOKEN_IN && uep->max_packet_size != 0 && + usbredirparser_peer_has_cap(dev->parser, + usb_redir_cap_32bits_bulk_length)) { + uep->pipeline = true; + } } static void usbredir_ep_info(void *priv, @@ -1465,11 +1497,17 @@ static void usbredir_bulk_packet(void *priv, uint64_t id, p = usbredir_find_packet_by_id(dev, ep, id); if (p) { + size_t size = (p->combined) ? p->combined->iov.size : p->iov.size; len = usbredir_handle_status(dev, bulk_packet->status, len); if (len > 0) { usbredir_log_data(dev, "bulk data in:", data, data_len); - if (data_len <= p->iov.size) { - usb_packet_copy(p, data, data_len); + if (data_len <= size) { + if (p->combined) { + iov_from_buf(p->combined->iov.iov, p->combined->iov.niov, + 0, data, data_len); + } else { + usb_packet_copy(p, data, data_len); + } } else { ERROR("bulk got more data then requested (%d > %zd)\n", data_len, p->iov.size); @@ -1477,7 +1515,11 @@ static void usbredir_bulk_packet(void *priv, uint64_t id, } } p->result = len; - usb_packet_complete(&dev->dev, p); + if (p->pid == USB_TOKEN_IN && p->ep->pipeline) { + usb_combined_input_packet_complete(&dev->dev, p); + } else { + usb_packet_complete(&dev->dev, p); + } } free(data); } @@ -1884,6 +1926,7 @@ static void usbredir_class_initfn(ObjectClass *klass, void *data) uc->handle_reset = usbredir_handle_reset; uc->handle_data = usbredir_handle_data; uc->handle_control = usbredir_handle_control; + uc->flush_ep_queue = usbredir_flush_ep_queue; dc->vmsd = &usbredir_vmstate; dc->props = usbredir_properties; } From 7e03d1781690c9e9ad67a671237dbcc0d159f528 Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 31 Oct 2012 13:47:13 +0100 Subject: [PATCH 226/291] usb-redir: Add an usbredir_setup_usb_eps() helper function Signed-off-by: Hans de Goede Signed-off-by: Gerd Hoffmann --- hw/usb/redirect.c | 45 ++++++++++++++++++++++----------------------- 1 file changed, 22 insertions(+), 23 deletions(-) diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index 448cfabb17..a3df757c43 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -1317,17 +1317,35 @@ static void usbredir_set_pipeline(USBRedirDevice *dev, struct USBEndpoint *uep) } } +static void usbredir_setup_usb_eps(USBRedirDevice *dev) +{ + struct USBEndpoint *usb_ep; + int i, pid; + + for (i = 0; i < MAX_ENDPOINTS; i++) { + pid = (i & 0x10) ? USB_TOKEN_IN : USB_TOKEN_OUT; + usb_ep = usb_ep_get(&dev->dev, pid, i & 0x0f); + usb_ep->type = dev->endpoint[i].type; + usb_ep->ifnum = dev->endpoint[i].interface; + usb_ep->max_packet_size = dev->endpoint[i].max_packet_size; + usbredir_set_pipeline(dev, usb_ep); + } +} + static void usbredir_ep_info(void *priv, struct usb_redir_ep_info_header *ep_info) { USBRedirDevice *dev = priv; - struct USBEndpoint *usb_ep; int i; for (i = 0; i < MAX_ENDPOINTS; i++) { dev->endpoint[i].type = ep_info->type[i]; dev->endpoint[i].interval = ep_info->interval[i]; dev->endpoint[i].interface = ep_info->interface[i]; + if (usbredirparser_peer_has_cap(dev->parser, + usb_redir_cap_ep_info_max_packet_size)) { + dev->endpoint[i].max_packet_size = ep_info->max_packet_size[i]; + } switch (dev->endpoint[i].type) { case usb_redir_type_invalid: break; @@ -1348,18 +1366,8 @@ static void usbredir_ep_info(void *priv, usbredir_device_disconnect(dev); return; } - usb_ep = usb_ep_get(&dev->dev, - (i & 0x10) ? USB_TOKEN_IN : USB_TOKEN_OUT, - i & 0x0f); - usb_ep->type = dev->endpoint[i].type; - usb_ep->ifnum = dev->endpoint[i].interface; - if (usbredirparser_peer_has_cap(dev->parser, - usb_redir_cap_ep_info_max_packet_size)) { - dev->endpoint[i].max_packet_size = - usb_ep->max_packet_size = ep_info->max_packet_size[i]; - } - usbredir_set_pipeline(dev, usb_ep); } + usbredir_setup_usb_eps(dev); } static void usbredir_configuration_status(void *priv, uint64_t id, @@ -1601,8 +1609,6 @@ static void usbredir_pre_save(void *priv) static int usbredir_post_load(void *priv, int version_id) { USBRedirDevice *dev = priv; - struct USBEndpoint *usb_ep; - int i; switch (dev->device_info.speed) { case usb_redir_speed_low: @@ -1622,15 +1628,8 @@ static int usbredir_post_load(void *priv, int version_id) } dev->dev.speedmask = (1 << dev->dev.speed); - for (i = 0; i < MAX_ENDPOINTS; i++) { - usb_ep = usb_ep_get(&dev->dev, - (i & 0x10) ? USB_TOKEN_IN : USB_TOKEN_OUT, - i & 0x0f); - usb_ep->type = dev->endpoint[i].type; - usb_ep->ifnum = dev->endpoint[i].interface; - usb_ep->max_packet_size = dev->endpoint[i].max_packet_size; - usbredir_set_pipeline(dev, usb_ep); - } + usbredir_setup_usb_eps(dev); + return 0; } From 24ac283aa293f9bd8ca4137775506edf33e45eae Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 31 Oct 2012 13:47:14 +0100 Subject: [PATCH 227/291] usb-redir: Use reject rather the disconnect on bad ep info So that the client gets a notification about us disconnecting the device. Signed-off-by: Hans de Goede Signed-off-by: Gerd Hoffmann --- hw/usb/redirect.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index a3df757c43..5c2d185550 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -1353,7 +1353,8 @@ static void usbredir_ep_info(void *priv, case usb_redir_type_interrupt: if (dev->endpoint[i].interval == 0) { ERROR("Received 0 interval for isoc or irq endpoint\n"); - usbredir_device_disconnect(dev); + usbredir_reject_device(dev); + return; } /* Fall through */ case usb_redir_type_control: @@ -1363,7 +1364,7 @@ static void usbredir_ep_info(void *priv, break; default: ERROR("Received invalid endpoint type\n"); - usbredir_device_disconnect(dev); + usbredir_reject_device(dev); return; } } From cdfd3530fafbef441ab6b86da64151f74073e5bd Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Wed, 31 Oct 2012 13:47:15 +0100 Subject: [PATCH 228/291] usb-redir: Allow to attach USB 2.0 devices to 1.1 host controller This follows the logic of host-linux: If a 2.0 device has no ISO endpoint and no interrupt endpoint with a packet size > 64, we can attach it also to an 1.1 host controller. In case the redir server does not report endpoint sizes, play safe and remove the 1.1 compatibility as well. Moreover, if we detect a conflicting change in the configuration after the device was already attached, it will be disconnected immediately. HdG: Several small cleanups and fixes Signed-off-by: Jan Kiszka Signed-off-by: Hans de Goede Signed-off-by: Gerd Hoffmann --- hw/usb/redirect.c | 30 +++++++++++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index 5c2d185550..8d4d3f41be 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -106,6 +106,7 @@ struct USBRedirDevice { struct usb_redir_interface_info_header interface_info; struct usbredirfilter_rule *filter_rules; int filter_rules_count; + int compatible_speedmask; }; static void usbredir_hello(void *priv, struct usb_redir_hello_header *h); @@ -962,6 +963,7 @@ static void usbredir_do_attach(void *opaque) } if (usb_device_attach(&dev->dev) != 0) { + WARNING("rejecting device due to speed mismatch\n"); usbredir_reject_device(dev); } } @@ -1068,6 +1070,9 @@ static int usbredir_initfn(USBDevice *udev) /* We'll do the attach once we receive the speed from the usb-host */ udev->auto_attach = 0; + /* Will be cleared during setup when we find conflicts */ + dev->compatible_speedmask = USB_SPEED_MASK_FULL; + /* Let the backend know we are ready */ qemu_chr_fe_open(dev->cs); qemu_chr_add_handlers(dev->cs, usbredir_chardev_can_read, @@ -1208,6 +1213,7 @@ static void usbredir_device_connect(void *priv, case usb_redir_speed_low: speed = "low speed"; dev->dev.speed = USB_SPEED_LOW; + dev->compatible_speedmask &= ~USB_SPEED_MASK_FULL; break; case usb_redir_speed_full: speed = "full speed"; @@ -1241,7 +1247,7 @@ static void usbredir_device_connect(void *priv, device_connect->device_class); } - dev->dev.speedmask = (1 << dev->dev.speed); + dev->dev.speedmask = (1 << dev->dev.speed) | dev->compatible_speedmask; dev->device_info = *device_connect; if (usbredir_check_filter(dev)) { @@ -1281,6 +1287,7 @@ static void usbredir_device_disconnect(void *priv) dev->interface_info.interface_count = NO_INTERFACE_INFO; dev->dev.addr = 0; dev->dev.speed = 0; + dev->compatible_speedmask = USB_SPEED_MASK_FULL; } static void usbredir_interface_info(void *priv, @@ -1302,6 +1309,12 @@ static void usbredir_interface_info(void *priv, } } +static void usbredir_mark_speed_incompatible(USBRedirDevice *dev, int speed) +{ + dev->compatible_speedmask &= ~(1 << speed); + dev->dev.speedmask = (1 << dev->dev.speed) | dev->compatible_speedmask; +} + static void usbredir_set_pipeline(USBRedirDevice *dev, struct USBEndpoint *uep) { if (uep->type != USB_ENDPOINT_XFER_BULK) { @@ -1350,7 +1363,14 @@ static void usbredir_ep_info(void *priv, case usb_redir_type_invalid: break; case usb_redir_type_iso: + usbredir_mark_speed_incompatible(dev, USB_SPEED_FULL); + /* Fall through */ case usb_redir_type_interrupt: + if (!usbredirparser_peer_has_cap(dev->parser, + usb_redir_cap_ep_info_max_packet_size) || + ep_info->max_packet_size[i] > 64) { + usbredir_mark_speed_incompatible(dev, USB_SPEED_FULL); + } if (dev->endpoint[i].interval == 0) { ERROR("Received 0 interval for isoc or irq endpoint\n"); usbredir_reject_device(dev); @@ -1368,6 +1388,14 @@ static void usbredir_ep_info(void *priv, return; } } + /* The new ep info may have caused a speed incompatibility, recheck */ + if (dev->dev.attached && + !(dev->dev.port->speedmask & dev->dev.speedmask)) { + ERROR("Device no longer matches speed after endpoint info change, " + "disconnecting!\n"); + usbredir_reject_device(dev); + return; + } usbredir_setup_usb_eps(dev); } From 95a59dc03988d190bbc72d980a149be3a79592fb Mon Sep 17 00:00:00 2001 From: Hans de Goede Date: Wed, 31 Oct 2012 13:47:16 +0100 Subject: [PATCH 229/291] usb-redir: Allow redirecting super speed devices to high speed controllers Signed-off-by: Hans de Goede Signed-off-by: Gerd Hoffmann --- hw/usb/redirect.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index 8d4d3f41be..c5cfe0b313 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -1071,7 +1071,7 @@ static int usbredir_initfn(USBDevice *udev) udev->auto_attach = 0; /* Will be cleared during setup when we find conflicts */ - dev->compatible_speedmask = USB_SPEED_MASK_FULL; + dev->compatible_speedmask = USB_SPEED_MASK_FULL | USB_SPEED_MASK_HIGH; /* Let the backend know we are ready */ qemu_chr_fe_open(dev->cs); @@ -1214,10 +1214,12 @@ static void usbredir_device_connect(void *priv, speed = "low speed"; dev->dev.speed = USB_SPEED_LOW; dev->compatible_speedmask &= ~USB_SPEED_MASK_FULL; + dev->compatible_speedmask &= ~USB_SPEED_MASK_HIGH; break; case usb_redir_speed_full: speed = "full speed"; dev->dev.speed = USB_SPEED_FULL; + dev->compatible_speedmask &= ~USB_SPEED_MASK_HIGH; break; case usb_redir_speed_high: speed = "high speed"; @@ -1287,7 +1289,7 @@ static void usbredir_device_disconnect(void *priv) dev->interface_info.interface_count = NO_INTERFACE_INFO; dev->dev.addr = 0; dev->dev.speed = 0; - dev->compatible_speedmask = USB_SPEED_MASK_FULL; + dev->compatible_speedmask = USB_SPEED_MASK_FULL | USB_SPEED_MASK_HIGH; } static void usbredir_interface_info(void *priv, @@ -1364,6 +1366,7 @@ static void usbredir_ep_info(void *priv, break; case usb_redir_type_iso: usbredir_mark_speed_incompatible(dev, USB_SPEED_FULL); + usbredir_mark_speed_incompatible(dev, USB_SPEED_HIGH); /* Fall through */ case usb_redir_type_interrupt: if (!usbredirparser_peer_has_cap(dev->parser, @@ -1371,6 +1374,11 @@ static void usbredir_ep_info(void *priv, ep_info->max_packet_size[i] > 64) { usbredir_mark_speed_incompatible(dev, USB_SPEED_FULL); } + if (!usbredirparser_peer_has_cap(dev->parser, + usb_redir_cap_ep_info_max_packet_size) || + ep_info->max_packet_size[i] > 1024) { + usbredir_mark_speed_incompatible(dev, USB_SPEED_HIGH); + } if (dev->endpoint[i].interval == 0) { ERROR("Received 0 interval for isoc or irq endpoint\n"); usbredir_reject_device(dev); @@ -1501,6 +1509,17 @@ static void usbredir_control_packet(void *priv, uint64_t id, DPRINTF("ctrl-in status %d len %d id %"PRIu64"\n", control_packet->status, len, id); + /* Fix up USB-3 ep0 maxpacket size to allow superspeed connected devices + * to work redirected to a not superspeed capable hcd */ + if (dev->dev.speed == USB_SPEED_SUPER && + !((dev->dev.port->speedmask & USB_SPEED_MASK_SUPER)) && + control_packet->requesttype == 0x80 && + control_packet->request == 6 && + control_packet->value == 0x100 && control_packet->index == 0 && + data_len >= 18 && data[7] == 9) { + data[7] = 64; + } + p = usbredir_find_packet_by_id(dev, 0, id); if (p) { len = usbredir_handle_status(dev, control_packet->status, len); From fc53b7d4b7fe409acae7d8d55a868eb5c696d71c Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 26 Oct 2012 16:29:38 +0100 Subject: [PATCH 230/291] arm_boot: Change initrd load address to "halfway through RAM" To avoid continually having to bump the initrd load address to account for larger kernel images, put the initrd halfway through RAM. This allows large kernels on new boards with lots of RAM to work OK, without breaking existing usecases for boards with only 32MB of RAM. Note that this change fixes in passing a bug where we were passing an overly large max_size to load_image_targphys() for the initrd, which meant that we wouldn't correctly refuse to load an enormous initrd that didn't actually fit into RAM. Signed-off-by: Peter Maydell Reviewed-by: Aurelien Jarno Reviewed-by: Igor Mitsyanko Tested-by: Cole Robinson Signed-off-by: Aurelien Jarno --- hw/arm-misc.h | 1 + hw/arm_boot.c | 40 +++++++++++++++++++++++++--------------- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/hw/arm-misc.h b/hw/arm-misc.h index d02f7f08c8..adb166586b 100644 --- a/hw/arm-misc.h +++ b/hw/arm-misc.h @@ -56,6 +56,7 @@ struct arm_boot_info { const struct arm_boot_info *info); /* Used internally by arm_boot.c */ int is_linux; + hwaddr initrd_start; hwaddr initrd_size; hwaddr entry; }; diff --git a/hw/arm_boot.c b/hw/arm_boot.c index 09bf6c5cdc..92e2cab476 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -18,7 +18,6 @@ #define KERNEL_ARGS_ADDR 0x100 #define KERNEL_LOAD_ADDR 0x00010000 -#define INITRD_LOAD_ADDR 0x00d00000 /* The worlds second smallest bootloader. Set r0-r2, then jump to kernel. */ static uint32_t bootloader[] = { @@ -109,7 +108,7 @@ static void set_kernel_args(const struct arm_boot_info *info) /* ATAG_INITRD2 */ WRITE_WORD(p, 4); WRITE_WORD(p, 0x54420005); - WRITE_WORD(p, info->loader_start + INITRD_LOAD_ADDR); + WRITE_WORD(p, info->initrd_start); WRITE_WORD(p, initrd_size); } if (info->kernel_cmdline && *info->kernel_cmdline) { @@ -185,10 +184,11 @@ static void set_kernel_args_old(const struct arm_boot_info *info) /* pages_in_vram */ WRITE_WORD(p, 0); /* initrd_start */ - if (initrd_size) - WRITE_WORD(p, info->loader_start + INITRD_LOAD_ADDR); - else + if (initrd_size) { + WRITE_WORD(p, info->initrd_start); + } else { WRITE_WORD(p, 0); + } /* initrd_size */ WRITE_WORD(p, initrd_size); /* rd_start */ @@ -281,14 +281,13 @@ static int load_dtb(hwaddr addr, const struct arm_boot_info *binfo) if (binfo->initrd_size) { rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start", - binfo->loader_start + INITRD_LOAD_ADDR); + binfo->initrd_start); if (rc < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n"); } rc = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end", - binfo->loader_start + INITRD_LOAD_ADDR + - binfo->initrd_size); + binfo->initrd_start + binfo->initrd_size); if (rc < 0) { fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n"); } @@ -375,6 +374,19 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) big_endian = 0; #endif + /* We want to put the initrd far enough into RAM that when the + * kernel is uncompressed it will not clobber the initrd. However + * on boards without much RAM we must ensure that we still leave + * enough room for a decent sized initrd, and on boards with large + * amounts of RAM we must avoid the initrd being so far up in RAM + * that it is outside lowmem and inaccessible to the kernel. + * So for boards with less than 256MB of RAM we put the initrd + * halfway into RAM, and for boards with 256MB of RAM or more we put + * the initrd at 128MB. + */ + info->initrd_start = info->loader_start + + MIN(info->ram_size / 2, 128 * 1024 * 1024); + /* Assume that raw images are linux kernels, and ELF images are not. */ kernel_size = load_elf(info->kernel_filename, NULL, NULL, &elf_entry, NULL, NULL, big_endian, ELF_MACHINE, 1); @@ -398,10 +410,9 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) if (is_linux) { if (info->initrd_filename) { initrd_size = load_image_targphys(info->initrd_filename, - info->loader_start - + INITRD_LOAD_ADDR, - info->ram_size - - INITRD_LOAD_ADDR); + info->initrd_start, + info->ram_size - + info->initrd_start); if (initrd_size < 0) { fprintf(stderr, "qemu: could not load initrd '%s'\n", info->initrd_filename); @@ -419,9 +430,8 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info) */ if (info->dtb_filename) { /* Place the DTB after the initrd in memory */ - hwaddr dtb_start = TARGET_PAGE_ALIGN(info->loader_start - + INITRD_LOAD_ADDR - + initrd_size); + hwaddr dtb_start = TARGET_PAGE_ALIGN(info->initrd_start + + initrd_size); if (load_dtb(dtb_start, info)) { exit(1); } From 2ddef11bede823b068b59a66b4c5c62377e69b2f Mon Sep 17 00:00:00 2001 From: Peter Crosthwaite Date: Fri, 19 Oct 2012 19:08:04 +1000 Subject: [PATCH 231/291] cadence_uart: More debug information Add more helpful debug information to the cadence UART. Signed-off-by: Peter Crosthwaite Reviewed-by: Peter Maydell Signed-off-by: Stefan Hajnoczi --- hw/cadence_uart.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/cadence_uart.c b/hw/cadence_uart.c index a7d0504c58..686e6172d0 100644 --- a/hw/cadence_uart.c +++ b/hw/cadence_uart.c @@ -359,7 +359,7 @@ static void uart_write(void *opaque, hwaddr offset, { UartState *s = (UartState *)opaque; - DB_PRINT(" offset:%x data:%08x\n", offset, (unsigned)value); + DB_PRINT(" offset:%x data:%08x\n", (unsigned)offset, (unsigned)value); offset >>= 2; switch (offset) { case R_IER: /* ier (wts imr) */ @@ -405,12 +405,15 @@ static uint64_t uart_read(void *opaque, hwaddr offset, offset >>= 2; if (offset >= R_MAX) { - return 0; + c = 0; } else if (offset == R_TX_RX) { uart_read_rx_fifo(s, &c); - return c; + } else { + c = s->r[offset]; } - return s->r[offset]; + + DB_PRINT(" offset:%x data:%08x\n", (unsigned)(offset << 2), (unsigned)c); + return c; } static const MemoryRegionOps uart_ops = { From e88a676e916bd29c1224ea46e037f354776fa3c8 Mon Sep 17 00:00:00 2001 From: Meador Inge Date: Fri, 24 Feb 2012 16:18:41 -0600 Subject: [PATCH 232/291] m68k: Return semihosting errno values correctly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixing a simple typo, s/errno/err/, that caused the error status from GDB semihosted system calls to be returned incorrectly. Signed-off-by: Meador Inge Reviewed-by: Andreas Färber Signed-off-by: Stefan Hajnoczi --- target-m68k/m68k-semi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c index 3bb30cd1f7..fed44ea490 100644 --- a/target-m68k/m68k-semi.c +++ b/target-m68k/m68k-semi.c @@ -150,7 +150,7 @@ static void m68k_semi_cb(CPUM68KState *env, target_ulong ret, target_ulong err) } /* FIXME - handle put_user() failure */ put_user_u32(ret, args); - put_user_u32(errno, args + 4); + put_user_u32(err, args + 4); } #define ARG(n) \ From 8f7219675353f909a1ff1fa4542626a5dc4553cf Mon Sep 17 00:00:00 2001 From: Blue Swirl Date: Sun, 28 Oct 2012 11:04:46 +0000 Subject: [PATCH 233/291] target-sparc: make do_unaligned_access static Signed-off-by: Blue Swirl Signed-off-by: Stefan Hajnoczi --- target-sparc/cpu.h | 3 --- target-sparc/ldst_helper.c | 8 ++++++-- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index a55fe08d36..7c689ee3bb 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -711,9 +711,6 @@ uint64_t cpu_tick_get_count(CPUTimer *timer); void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit); trap_state* cpu_tsptr(CPUSPARCState* env); #endif -void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, target_ulong addr, - int is_write, int is_user, - uintptr_t retaddr); void cpu_restore_state2(CPUSPARCState *env, uintptr_t retaddr); #define TB_FLAG_FPU_ENABLED (1 << 4) diff --git a/target-sparc/ldst_helper.c b/target-sparc/ldst_helper.c index 356144a5c0..f3e08fd6e6 100644 --- a/target-sparc/ldst_helper.c +++ b/target-sparc/ldst_helper.c @@ -65,6 +65,9 @@ #define QT1 (env->qt1) #if !defined(CONFIG_USER_ONLY) +static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, + target_ulong addr, int is_write, + int is_user, uintptr_t retaddr); #include "softmmu_exec.h" #define MMUSUFFIX _mmu #define ALIGNED_ONLY @@ -2407,8 +2410,9 @@ void cpu_restore_state2(CPUSPARCState *env, uintptr_t retaddr) } #if !defined(CONFIG_USER_ONLY) -void do_unaligned_access(CPUSPARCState *env, target_ulong addr, int is_write, - int is_user, uintptr_t retaddr) +static void QEMU_NORETURN do_unaligned_access(CPUSPARCState *env, + target_ulong addr, int is_write, + int is_user, uintptr_t retaddr) { #ifdef DEBUG_UNALIGNED printf("Unaligned access to 0x" TARGET_FMT_lx " from 0x" TARGET_FMT_lx From 4fdcac0e2b102c8017cf81eb6dfb3e5e1c490949 Mon Sep 17 00:00:00 2001 From: Blue Swirl Date: Sun, 28 Oct 2012 11:04:47 +0000 Subject: [PATCH 234/291] vl.c: add missing static Add missing 'static' qualifiers. Signed-off-by: Blue Swirl Signed-off-by: Stefan Hajnoczi --- sysemu.h | 5 ----- vl.c | 21 ++++++++++++--------- 2 files changed, 12 insertions(+), 14 deletions(-) diff --git a/sysemu.h b/sysemu.h index f72b4ce125..f5ac664067 100644 --- a/sysemu.h +++ b/sysemu.h @@ -19,7 +19,6 @@ extern uint8_t qemu_uuid[]; int qemu_uuid_parse(const char *str, uint8_t *uuid); #define UUID_FMT "%02hhx%02hhx%02hhx%02hhx-%02hhx%02hhx-%02hhx%02hhx-%02hhx%02hhx-%02hhx%02hhx%02hhx%02hhx%02hhx%02hhx" -void runstate_init(void); bool runstate_check(RunState state); void runstate_set(RunState new_state); int runstate_is_running(void); @@ -57,11 +56,7 @@ void qemu_system_debug_request(void); void qemu_system_vmstop_request(RunState reason); int qemu_shutdown_requested_get(void); int qemu_reset_requested_get(void); -int qemu_shutdown_requested(void); -int qemu_reset_requested(void); -int qemu_powerdown_requested(void); void qemu_system_killed(int signal, pid_t pid); -void qemu_kill_report(void); void qemu_devices_reset(void); void qemu_system_reset(bool report); diff --git a/vl.c b/vl.c index 5513d1518e..d840c32161 100644 --- a/vl.c +++ b/vl.c @@ -180,7 +180,7 @@ static const char *data_dir; const char *bios_name = NULL; enum vga_retrace_method vga_retrace_method = VGA_RETRACE_DUMB; DisplayType display_type = DT_DEFAULT; -int display_remote = 0; +static int display_remote; const char* keyboard_layout = NULL; ram_addr_t ram_size; const char *mem_path = NULL; @@ -214,7 +214,7 @@ const char *vnc_display; int acpi_enabled = 1; int no_hpet = 0; int fd_bootchk = 1; -int no_reboot = 0; +static int no_reboot; int no_shutdown = 0; int cursor_hide = 1; int graphic_rotate = 0; @@ -242,7 +242,8 @@ struct FWBootEntry { char *suffix; }; -QTAILQ_HEAD(, FWBootEntry) fw_boot_order = QTAILQ_HEAD_INITIALIZER(fw_boot_order); +static QTAILQ_HEAD(, FWBootEntry) fw_boot_order = + QTAILQ_HEAD_INITIALIZER(fw_boot_order); int nb_numa_nodes; uint64_t node_mem[MAX_NODES]; @@ -396,7 +397,7 @@ bool runstate_check(RunState state) return current_run_state == state; } -void runstate_init(void) +static void runstate_init(void) { const RunStateTransition *p; @@ -1457,14 +1458,14 @@ int qemu_reset_requested_get(void) return reset_requested; } -int qemu_shutdown_requested(void) +static int qemu_shutdown_requested(void) { int r = shutdown_requested; shutdown_requested = 0; return r; } -void qemu_kill_report(void) +static void qemu_kill_report(void) { if (!qtest_enabled() && shutdown_signal != -1) { fprintf(stderr, "qemu: terminating on signal %d", shutdown_signal); @@ -1480,7 +1481,7 @@ void qemu_kill_report(void) } } -int qemu_reset_requested(void) +static int qemu_reset_requested(void) { int r = reset_requested; reset_requested = 0; @@ -1501,7 +1502,7 @@ static int qemu_wakeup_requested(void) return r; } -int qemu_powerdown_requested(void) +static int qemu_powerdown_requested(void) { int r = powerdown_requested; powerdown_requested = 0; @@ -2127,7 +2128,9 @@ struct device_config { Location loc; QTAILQ_ENTRY(device_config) next; }; -QTAILQ_HEAD(, device_config) device_configs = QTAILQ_HEAD_INITIALIZER(device_configs); + +static QTAILQ_HEAD(, device_config) device_configs = + QTAILQ_HEAD_INITIALIZER(device_configs); static void add_device_config(int type, const char *cmdline) { From 71a8cdeca095acb2a67924de870f4ee8da5b8803 Mon Sep 17 00:00:00 2001 From: Blue Swirl Date: Sun, 28 Oct 2012 11:04:48 +0000 Subject: [PATCH 235/291] vnc: add missing static Add missing 'static' qualifiers. Signed-off-by: Blue Swirl Signed-off-by: Stefan Hajnoczi --- console.h | 2 -- ui/vnc-jobs.c | 10 +++++----- ui/vnc-jobs.h | 1 - ui/vnc.c | 14 +++++++------- ui/vnc.h | 5 ----- 5 files changed, 12 insertions(+), 20 deletions(-) diff --git a/console.h b/console.h index 6099d8d710..5ad361510a 100644 --- a/console.h +++ b/console.h @@ -377,10 +377,8 @@ void cocoa_display_init(DisplayState *ds, int full_screen); /* vnc.c */ void vnc_display_init(DisplayState *ds); -void vnc_display_close(DisplayState *ds); void vnc_display_open(DisplayState *ds, const char *display, Error **errp); void vnc_display_add_client(DisplayState *ds, int csock, int skipauth); -int vnc_display_disable_login(DisplayState *ds); char *vnc_display_local_addr(DisplayState *ds); #ifdef CONFIG_VNC int vnc_display_password(DisplayState *ds, const char *password); diff --git a/ui/vnc-jobs.c b/ui/vnc-jobs.c index 3c592b3f3d..dfe482dc0f 100644 --- a/ui/vnc-jobs.c +++ b/ui/vnc-jobs.c @@ -320,6 +320,11 @@ static void *vnc_worker_thread(void *arg) return NULL; } +static bool vnc_worker_thread_running(void) +{ + return queue; /* Check global queue */ +} + void vnc_start_worker_thread(void) { VncJobQueue *q; @@ -332,11 +337,6 @@ void vnc_start_worker_thread(void) queue = q; /* Set global queue */ } -bool vnc_worker_thread_running(void) -{ - return queue; /* Check global queue */ -} - void vnc_stop_worker_thread(void) { if (!vnc_worker_thread_running()) diff --git a/ui/vnc-jobs.h b/ui/vnc-jobs.h index 86e6d888c6..31da103fac 100644 --- a/ui/vnc-jobs.h +++ b/ui/vnc-jobs.h @@ -40,7 +40,6 @@ void vnc_jobs_join(VncState *vs); void vnc_jobs_consume_buffer(VncState *vs); void vnc_start_worker_thread(void); -bool vnc_worker_thread_running(void); void vnc_stop_worker_thread(void); /* Locks */ diff --git a/ui/vnc.c b/ui/vnc.c index d0ffcc54af..d95e6ef5f3 100644 --- a/ui/vnc.c +++ b/ui/vnc.c @@ -479,12 +479,12 @@ void buffer_reserve(Buffer *buffer, size_t len) } } -int buffer_empty(Buffer *buffer) +static int buffer_empty(Buffer *buffer) { return buffer->offset == 0; } -uint8_t *buffer_end(Buffer *buffer) +static uint8_t *buffer_end(Buffer *buffer) { return buffer->buffer + buffer->offset; } @@ -1376,17 +1376,17 @@ void vnc_flush(VncState *vs) vnc_unlock_output(vs); } -uint8_t read_u8(uint8_t *data, size_t offset) +static uint8_t read_u8(uint8_t *data, size_t offset) { return data[offset]; } -uint16_t read_u16(uint8_t *data, size_t offset) +static uint16_t read_u16(uint8_t *data, size_t offset) { return ((data[offset] & 0xFF) << 8) | (data[offset + 1] & 0xFF); } -int32_t read_s32(uint8_t *data, size_t offset) +static int32_t read_s32(uint8_t *data, size_t offset) { return (int32_t)((data[offset] << 24) | (data[offset + 1] << 16) | (data[offset + 2] << 8) | data[offset + 3]); @@ -2763,7 +2763,7 @@ void vnc_display_init(DisplayState *ds) } -void vnc_display_close(DisplayState *ds) +static void vnc_display_close(DisplayState *ds) { VncDisplay *vs = ds ? (VncDisplay *)ds->opaque : vnc_display; @@ -2785,7 +2785,7 @@ void vnc_display_close(DisplayState *ds) #endif } -int vnc_display_disable_login(DisplayState *ds) +static int vnc_display_disable_login(DisplayState *ds) { VncDisplay *vs = ds ? (VncDisplay *)ds->opaque : vnc_display; diff --git a/ui/vnc.h b/ui/vnc.h index 068c2fcda5..c89f6934b4 100644 --- a/ui/vnc.h +++ b/ui/vnc.h @@ -493,9 +493,6 @@ void vnc_read_when(VncState *vs, VncReadEvent *func, size_t expecting); /* Buffer I/O functions */ -uint8_t read_u8(uint8_t *data, size_t offset); -uint16_t read_u16(uint8_t *data, size_t offset); -int32_t read_s32(uint8_t *data, size_t offset); uint32_t read_u32(uint8_t *data, size_t offset); /* Protocol stage functions */ @@ -507,8 +504,6 @@ void start_auth_vnc(VncState *vs); /* Buffer management */ void buffer_reserve(Buffer *buffer, size_t len); -int buffer_empty(Buffer *buffer); -uint8_t *buffer_end(Buffer *buffer); void buffer_reset(Buffer *buffer); void buffer_free(Buffer *buffer); void buffer_append(Buffer *buffer, const void *data, size_t len); From 434482925ee11091fc111bd2a86de0b677b3e943 Mon Sep 17 00:00:00 2001 From: Blue Swirl Date: Sun, 28 Oct 2012 11:04:49 +0000 Subject: [PATCH 236/291] ppc: add missing static Add missing 'static' qualifiers. Signed-off-by: Blue Swirl Acked-by: Alexander Graf Signed-off-by: Stefan Hajnoczi --- hw/adb.c | 8 ++++---- hw/adb.h | 4 ---- hw/nvram.h | 10 +--------- hw/ppc.c | 16 ++++++++-------- target-ppc/cpu.h | 1 - 5 files changed, 13 insertions(+), 26 deletions(-) diff --git a/hw/adb.c b/hw/adb.c index aa15f55dc9..3b547f0af7 100644 --- a/hw/adb.c +++ b/hw/adb.c @@ -108,10 +108,10 @@ int adb_poll(ADBBusState *s, uint8_t *obuf) return olen; } -ADBDevice *adb_register_device(ADBBusState *s, int devaddr, - ADBDeviceRequest *devreq, - ADBDeviceReset *devreset, - void *opaque) +static ADBDevice *adb_register_device(ADBBusState *s, int devaddr, + ADBDeviceRequest *devreq, + ADBDeviceReset *devreset, + void *opaque) { ADBDevice *d; if (s->nb_devices >= MAX_ADB_DEVICES) diff --git a/hw/adb.h b/hw/adb.h index b2a591c546..5b27da2dd3 100644 --- a/hw/adb.h +++ b/hw/adb.h @@ -56,10 +56,6 @@ int adb_request(ADBBusState *s, uint8_t *buf_out, const uint8_t *buf, int len); int adb_poll(ADBBusState *s, uint8_t *buf_out); -ADBDevice *adb_register_device(ADBBusState *s, int devaddr, - ADBDeviceRequest *devreq, - ADBDeviceReset *devreset, - void *opaque); void adb_kbd_init(ADBBusState *bus); void adb_mouse_init(ADBBusState *bus); diff --git a/hw/nvram.h b/hw/nvram.h index a4a1db4976..72363ced42 100644 --- a/hw/nvram.h +++ b/hw/nvram.h @@ -10,17 +10,9 @@ typedef struct nvram_t { nvram_write_t write_fn; } nvram_t; -void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value); -uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr); -void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value); -uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr); -void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value); uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr); -void NVRAM_set_string (nvram_t *nvram, uint32_t addr, - const char *str, uint32_t max); int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max); -void NVRAM_set_crc (nvram_t *nvram, uint32_t addr, - uint32_t start, uint32_t count); + int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size, const char *arch, uint32_t RAM_size, int boot_device, diff --git a/hw/ppc.c b/hw/ppc.c index 98546de991..e4a0a3e822 100644 --- a/hw/ppc.c +++ b/hw/ppc.c @@ -721,7 +721,7 @@ static void cpu_ppc_hdecr_cb (void *opaque) _cpu_ppc_store_hdecr(opaque, 0x00000000, 0xFFFFFFFF, 1); } -void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value) +static void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) { ppc_tb_t *tb_env = env->tb_env; @@ -1152,23 +1152,23 @@ static inline void nvram_write (nvram_t *nvram, uint32_t addr, uint32_t val) (*nvram->write_fn)(nvram->opaque, addr, val); } -void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value) +static void NVRAM_set_byte(nvram_t *nvram, uint32_t addr, uint8_t value) { nvram_write(nvram, addr, value); } -uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr) +static uint8_t NVRAM_get_byte(nvram_t *nvram, uint32_t addr) { return nvram_read(nvram, addr); } -void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value) +static void NVRAM_set_word(nvram_t *nvram, uint32_t addr, uint16_t value) { nvram_write(nvram, addr, value >> 8); nvram_write(nvram, addr + 1, value & 0xFF); } -uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) +static uint16_t NVRAM_get_word(nvram_t *nvram, uint32_t addr) { uint16_t tmp; @@ -1178,7 +1178,7 @@ uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr) return tmp; } -void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value) +static void NVRAM_set_lword(nvram_t *nvram, uint32_t addr, uint32_t value) { nvram_write(nvram, addr, value >> 24); nvram_write(nvram, addr + 1, (value >> 16) & 0xFF); @@ -1198,8 +1198,8 @@ uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr) return tmp; } -void NVRAM_set_string (nvram_t *nvram, uint32_t addr, - const char *str, uint32_t max) +static void NVRAM_set_string(nvram_t *nvram, uint32_t addr, const char *str, + uint32_t max) { int i; diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 286f42a808..ddee9a00a4 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1177,7 +1177,6 @@ void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value); uint32_t cpu_ppc_load_hdecr (CPUPPCState *env); void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value); uint64_t cpu_ppc_load_purr (CPUPPCState *env); -void cpu_ppc_store_purr (CPUPPCState *env, uint64_t value); uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env); uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env); #if !defined(CONFIG_USER_ONLY) From 6575c289f8c9820a7a0d2de2b0c3c58b13d9abc8 Mon Sep 17 00:00:00 2001 From: Blue Swirl Date: Sun, 28 Oct 2012 11:04:50 +0000 Subject: [PATCH 237/291] target-ppc: make some functions static Signed-off-by: Blue Swirl Acked-by: Alexander Graf Signed-off-by: Stefan Hajnoczi --- target-ppc/cpu.h | 6 ------ target-ppc/mmu_helper.c | 11 ++++++----- 2 files changed, 6 insertions(+), 11 deletions(-) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index ddee9a00a4..bb5b0a4a99 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1140,10 +1140,6 @@ int cpu_ppc_signal_handler (int host_signum, void *pinfo, int cpu_ppc_handle_mmu_fault (CPUPPCState *env, target_ulong address, int rw, int mmu_idx); #define cpu_handle_mmu_fault cpu_ppc_handle_mmu_fault -#if !defined(CONFIG_USER_ONLY) -int get_physical_address (CPUPPCState *env, mmu_ctx_t *ctx, target_ulong vaddr, - int rw, int access_type); -#endif void do_interrupt (CPUPPCState *env); void ppc_hw_interrupt (CPUPPCState *env); @@ -1188,8 +1184,6 @@ void store_40x_dbcr0 (CPUPPCState *env, uint32_t val); void store_40x_sler (CPUPPCState *env, uint32_t val); void store_booke_tcr (CPUPPCState *env, target_ulong val); void store_booke_tsr (CPUPPCState *env, target_ulong val); -void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot); -hwaddr booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb); int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb, hwaddr *raddrp, target_ulong address, uint32_t pid); diff --git a/target-ppc/mmu_helper.c b/target-ppc/mmu_helper.c index 811f47f309..318ce92adb 100644 --- a/target-ppc/mmu_helper.c +++ b/target-ppc/mmu_helper.c @@ -1276,7 +1276,8 @@ static int mmubooke_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, return ret; } -void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot) +static void booke206_flush_tlb(CPUPPCState *env, int flags, + const int check_iprot) { int tlb_size; int i, j; @@ -1297,8 +1298,8 @@ void booke206_flush_tlb(CPUPPCState *env, int flags, const int check_iprot) tlb_flush(env, 1); } -hwaddr booke206_tlb_to_page_size(CPUPPCState *env, - ppcmas_tlb_t *tlb) +static hwaddr booke206_tlb_to_page_size(CPUPPCState *env, + ppcmas_tlb_t *tlb) { int tlbm_size; @@ -1706,8 +1707,8 @@ static inline int check_physical(CPUPPCState *env, mmu_ctx_t *ctx, return ret; } -int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, target_ulong eaddr, - int rw, int access_type) +static int get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx, + target_ulong eaddr, int rw, int access_type) { int ret; From 8b9c99d9dcbf532649f8e614becfa15d2ac4ea75 Mon Sep 17 00:00:00 2001 From: Blue Swirl Date: Sun, 28 Oct 2012 11:04:51 +0000 Subject: [PATCH 238/291] exec: make some functions static Signed-off-by: Blue Swirl Signed-off-by: Stefan Hajnoczi --- cpu-common.h | 5 ----- exec-all.h | 2 -- exec.c | 15 +++++++++------ memory-internal.h | 2 -- 4 files changed, 9 insertions(+), 15 deletions(-) diff --git a/cpu-common.h b/cpu-common.h index 5f9308933c..d2fbafac9c 100644 --- a/cpu-common.h +++ b/cpu-common.h @@ -39,10 +39,6 @@ typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr); void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); /* This should only be used for ram local to a device. */ void *qemu_get_ram_ptr(ram_addr_t addr); -void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size); -/* Same but slower, to use for migration, where the order of - * RAMBlocks must not change. */ -void *qemu_safe_ram_ptr(ram_addr_t addr); void qemu_put_ram_ptr(void *addr); /* This should not be used by devices. */ int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr); @@ -67,7 +63,6 @@ void *cpu_physical_memory_map(hwaddr addr, void cpu_physical_memory_unmap(void *buffer, hwaddr len, int is_write, hwaddr access_len); void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)); -void cpu_unregister_map_client(void *cookie); bool cpu_physical_memory_is_io(hwaddr phys_addr); diff --git a/exec-all.h b/exec-all.h index 2ea0e4fc24..8db47f5c9b 100644 --- a/exec-all.h +++ b/exec-all.h @@ -194,8 +194,6 @@ static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) void tb_free(TranslationBlock *tb); void tb_flush(CPUArchState *env); -void tb_link_page(TranslationBlock *tb, - tb_page_addr_t phys_pc, tb_page_addr_t phys_page2); void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; diff --git a/exec.c b/exec.c index b0ed5939e9..42cc0975e6 100644 --- a/exec.c +++ b/exec.c @@ -188,9 +188,12 @@ static unsigned phys_map_nodes_nb, phys_map_nodes_nb_alloc; static void io_mem_init(void); static void memory_map_init(void); +static void *qemu_safe_ram_ptr(ram_addr_t addr); static MemoryRegion io_mem_watch; #endif +static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, + tb_page_addr_t phys_page2); /* statistics */ static int tb_flush_count; @@ -1349,8 +1352,8 @@ static inline void tb_alloc_page(TranslationBlock *tb, /* add a new TB and link it to the physical page tables. phys_page2 is (-1) to indicate that only one page contains the TB. */ -void tb_link_page(TranslationBlock *tb, - tb_page_addr_t phys_pc, tb_page_addr_t phys_page2) +static void tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, + tb_page_addr_t phys_page2) { unsigned int h; TranslationBlock **ptb; @@ -1859,7 +1862,7 @@ void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end, } } -int cpu_physical_memory_set_dirty_tracking(int enable) +static int cpu_physical_memory_set_dirty_tracking(int enable) { int ret = 0; in_migration = enable; @@ -2741,7 +2744,7 @@ void *qemu_get_ram_ptr(ram_addr_t addr) /* Return a host pointer to ram allocated with qemu_ram_alloc. * Same as qemu_get_ram_ptr but avoid reordering ramblocks. */ -void *qemu_safe_ram_ptr(ram_addr_t addr) +static void *qemu_safe_ram_ptr(ram_addr_t addr) { RAMBlock *block; @@ -2771,7 +2774,7 @@ void *qemu_safe_ram_ptr(ram_addr_t addr) /* Return a host pointer to guest's ram. Similar to qemu_get_ram_ptr * but takes a size argument */ -void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size) +static void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size) { if (*size == 0) { return NULL; @@ -3519,7 +3522,7 @@ void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque)) return client; } -void cpu_unregister_map_client(void *_client) +static void cpu_unregister_map_client(void *_client) { MapClient *client = (MapClient *)_client; diff --git a/memory-internal.h b/memory-internal.h index 1c34b9751c..1da240039d 100644 --- a/memory-internal.h +++ b/memory-internal.h @@ -55,8 +55,6 @@ struct MemoryRegionSection; void qemu_register_coalesced_mmio(hwaddr addr, ram_addr_t size); void qemu_unregister_coalesced_mmio(hwaddr addr, ram_addr_t size); -int cpu_physical_memory_set_dirty_tracking(int enable); - #define VGA_DIRTY_FLAG 0x01 #define CODE_DIRTY_FLAG 0x02 #define MIGRATION_DIRTY_FLAG 0x08 From 0d3cf3b6ff469bba95ae235021a3be232af4068d Mon Sep 17 00:00:00 2001 From: Jan Kiszka Date: Thu, 1 Nov 2012 17:29:24 +0100 Subject: [PATCH 239/291] pc: Drop redundant test for ROM memory region Just a few lines above, we already initialize rom_memory accordingly. Signed-off-by: Jan Kiszka Signed-off-by: Stefan Hajnoczi --- hw/pc_piix.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pc_piix.c b/hw/pc_piix.c index 85529b2cea..cfa839c8b4 100644 --- a/hw/pc_piix.c +++ b/hw/pc_piix.c @@ -178,7 +178,7 @@ static void pc_init1(MemoryRegion *system_memory, fw_cfg = pc_memory_init(system_memory, kernel_filename, kernel_cmdline, initrd_filename, below_4g_mem_size, above_4g_mem_size, - pci_enabled ? rom_memory : system_memory, &ram_memory); + rom_memory, &ram_memory); } gsi_state = g_malloc0(sizeof(*gsi_state)); From dc63936df7cc4c6f07b8c8c4ba0bf177b8df085e Mon Sep 17 00:00:00 2001 From: Gerd Hoffmann Date: Fri, 2 Nov 2012 08:44:13 +0100 Subject: [PATCH 240/291] xenfb: fix build breakage caused by console cleanup series Console cleanup series renamed dpy_resize and dpy_update all over the tree, but hw/xenfb.c was forgotten. Update it too so it builds again. Reported-by: Jan Kiszka Signed-off-by: Gerd Hoffmann Signed-off-by: Anthony Liguori --- hw/xenfb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/hw/xenfb.c b/hw/xenfb.c index ef24c3315c..442a63a320 100644 --- a/hw/xenfb.c +++ b/hw/xenfb.c @@ -648,7 +648,7 @@ static void xenfb_guest_copy(struct XenFB *xenfb, int x, int y, int w, int h) xen_be_printf(&xenfb->c.xendev, 0, "%s: oops: convert %d -> %d bpp?\n", __FUNCTION__, xenfb->depth, bpp); - dpy_update(xenfb->c.ds, x, y, w, h); + dpy_gfx_update(xenfb->c.ds, x, y, w, h); } #ifdef XENFB_TYPE_REFRESH_PERIOD @@ -766,7 +766,7 @@ static void xenfb_update(void *opaque) xen_be_printf(&xenfb->c.xendev, 1, "update: resizing: %dx%d @ %d bpp%s\n", xenfb->width, xenfb->height, xenfb->depth, is_buffer_shared(xenfb->c.ds->surface) ? " (shared)" : ""); - dpy_resize(xenfb->c.ds); + dpy_gfx_resize(xenfb->c.ds); xenfb->up_fullscreen = 1; } From 1d8ddda045b4b72dc95a325debb6df0fc19ec821 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Fri, 2 Nov 2012 14:54:43 +0000 Subject: [PATCH 241/291] ui/cocoa.m: Update to new DisplayChangeListener member names MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit a93a4a2 changed the names of some fields in DisplayChangeListener and broke compilation of the cocoa UI. Update to the new names. Acked-by: Gerd Hoffmann Reviewed-by: Andreas Färber Signed-off-by: Peter Maydell Signed-off-by: Anthony Liguori --- ui/cocoa.m | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/ui/cocoa.m b/ui/cocoa.m index 2383646dc0..87d2e44c69 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -1017,8 +1017,8 @@ void cocoa_display_init(DisplayState *ds, int full_screen) dcl = g_malloc0(sizeof(DisplayChangeListener)); // register vga output callbacks - dcl->dpy_update = cocoa_update; - dcl->dpy_resize = cocoa_resize; + dcl->dpy_gfx_update = cocoa_update; + dcl->dpy_gfx_resize = cocoa_resize; dcl->dpy_refresh = cocoa_refresh; register_displaychangelistener(ds, dcl); From e4ab0d6b0d1118a90238d8194eedb91aab15ebe1 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Fri, 2 Nov 2012 14:25:15 -0200 Subject: [PATCH 242/291] target-i386: cpu: fix --disable-kvm compilation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This fixes the following: target-i386/cpu.o: In function `kvm_cpu_fill_host': target-i386/cpu.c:783: undefined reference to `kvm_state' I didn't notice the problem before because GCC was optimizing the entire kvm_cpu_fill_host() function out (because all calls are conditional on kvm_enabled()). * cpu_x86_fill_model_id() is used only if CONFIG_KVM is set, so #ifdef it entirely to avoid compiler warnings. * kvm_cpu_fill_host() should be called only if KVM is enabled, so use #ifdef CONFIG_KVM around the entire function body. Reported-by: Andreas Färber Signed-off-by: Eduardo Habkost Signed-off-by: Andreas Färber --- target-i386/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index c46286ab3e..e1db639295 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -758,6 +758,7 @@ static x86_def_t builtin_x86_defs[] = { }, }; +#ifdef CONFIG_KVM static int cpu_x86_fill_model_id(char *str) { uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; @@ -772,6 +773,7 @@ static int cpu_x86_fill_model_id(char *str) } return 0; } +#endif /* Fill a x86_def_t struct with information about the host CPU, and * the CPU features supported by the host hardware + host kernel @@ -780,6 +782,7 @@ static int cpu_x86_fill_model_id(char *str) */ static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def) { +#ifdef CONFIG_KVM KVMState *s = kvm_state; uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0; @@ -838,6 +841,7 @@ static void kvm_cpu_fill_host(x86_def_t *x86_cpu_def) * unsupported ones later. */ x86_cpu_def->svm_features = -1; +#endif /* CONFIG_KVM */ } static int unavailable_host_feature(struct model_features_t *f, uint32_t mask) From 5f0ebf1b4d58be0c0bb05beb195b6f42942eeee8 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 21 Sep 2012 12:04:03 +0200 Subject: [PATCH 243/291] migration: unify stdio-based QEMUFile operations Now that qemu_fseek does not exist anymore, there is no reason to do an fseek before fread/fwrite when operating on an stdio file. Thus, unify the get/put_buffer callbacks used by qemu_fopen with those used for pipes. Reviewed-by: Orit Wasserman Signed-off-by: Paolo Bonzini --- savevm.c | 19 ++----------------- 1 file changed, 2 insertions(+), 17 deletions(-) diff --git a/savevm.c b/savevm.c index 43d3d1bbeb..cfcf91847d 100644 --- a/savevm.c +++ b/savevm.c @@ -343,21 +343,6 @@ QEMUFile *qemu_fopen_socket(int fd) return s->file; } -static int file_put_buffer(void *opaque, const uint8_t *buf, - int64_t pos, int size) -{ - QEMUFileStdio *s = opaque; - fseek(s->stdio_file, pos, SEEK_SET); - return fwrite(buf, 1, size, s->stdio_file); -} - -static int file_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size) -{ - QEMUFileStdio *s = opaque; - fseek(s->stdio_file, pos, SEEK_SET); - return fread(buf, 1, size, s->stdio_file); -} - QEMUFile *qemu_fopen(const char *filename, const char *mode) { QEMUFileStdio *s; @@ -376,10 +361,10 @@ QEMUFile *qemu_fopen(const char *filename, const char *mode) goto fail; if(mode[0] == 'w') { - s->file = qemu_fopen_ops(s, file_put_buffer, NULL, stdio_fclose, + s->file = qemu_fopen_ops(s, stdio_put_buffer, NULL, stdio_fclose, NULL, NULL, NULL); } else { - s->file = qemu_fopen_ops(s, NULL, file_get_buffer, stdio_fclose, + s->file = qemu_fopen_ops(s, NULL, stdio_get_buffer, stdio_fclose, NULL, NULL, NULL); } return s->file; From 9229bf3c2d7afcd1adce7258843d9bc82b066b08 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 8 Aug 2012 10:15:15 +0200 Subject: [PATCH 244/291] migration: consolidate QEMUFile methods in a single QEMUFileOps struct Reviewed-by: Orit Wasserman Signed-off-by: Paolo Bonzini --- buffered_file.c | 13 ++++-- qemu-file.h | 16 ++++--- savevm.c | 108 +++++++++++++++++++++++++++--------------------- 3 files changed, 79 insertions(+), 58 deletions(-) diff --git a/buffered_file.c b/buffered_file.c index ed92df1053..a5c0b128e0 100644 --- a/buffered_file.c +++ b/buffered_file.c @@ -234,6 +234,14 @@ static void buffered_rate_tick(void *opaque) buffered_put_buffer(s, NULL, 0, 0); } +static const QEMUFileOps buffered_file_ops = { + .put_buffer = buffered_put_buffer, + .close = buffered_close, + .rate_limit = buffered_rate_limit, + .get_rate_limit = buffered_get_rate_limit, + .set_rate_limit = buffered_set_rate_limit, +}; + QEMUFile *qemu_fopen_ops_buffered(MigrationState *migration_state) { QEMUFileBuffered *s; @@ -243,10 +251,7 @@ QEMUFile *qemu_fopen_ops_buffered(MigrationState *migration_state) s->migration_state = migration_state; s->xfer_limit = migration_state->bandwidth_limit / 10; - s->file = qemu_fopen_ops(s, buffered_put_buffer, NULL, - buffered_close, buffered_rate_limit, - buffered_set_rate_limit, - buffered_get_rate_limit); + s->file = qemu_fopen_ops(s, &buffered_file_ops); s->timer = qemu_new_timer_ms(rt_clock, buffered_rate_tick, s); diff --git a/qemu-file.h b/qemu-file.h index 9c8985b610..c89e8e09dc 100644 --- a/qemu-file.h +++ b/qemu-file.h @@ -59,12 +59,16 @@ typedef int (QEMUFileRateLimit)(void *opaque); typedef int64_t (QEMUFileSetRateLimit)(void *opaque, int64_t new_rate); typedef int64_t (QEMUFileGetRateLimit)(void *opaque); -QEMUFile *qemu_fopen_ops(void *opaque, QEMUFilePutBufferFunc *put_buffer, - QEMUFileGetBufferFunc *get_buffer, - QEMUFileCloseFunc *close, - QEMUFileRateLimit *rate_limit, - QEMUFileSetRateLimit *set_rate_limit, - QEMUFileGetRateLimit *get_rate_limit); +typedef struct QEMUFileOps { + QEMUFilePutBufferFunc *put_buffer; + QEMUFileGetBufferFunc *get_buffer; + QEMUFileCloseFunc *close; + QEMUFileRateLimit *rate_limit; + QEMUFileSetRateLimit *set_rate_limit; + QEMUFileGetRateLimit *get_rate_limit; +} QEMUFileOps; + +QEMUFile *qemu_fopen_ops(void *opaque, const QEMUFileOps *ops); QEMUFile *qemu_fopen(const char *filename, const char *mode); QEMUFile *qemu_fdopen(int fd, const char *mode); QEMUFile *qemu_fopen_socket(int fd); diff --git a/savevm.c b/savevm.c index cfcf91847d..a4158ecbf7 100644 --- a/savevm.c +++ b/savevm.c @@ -163,12 +163,7 @@ void qemu_announce_self(void) #define IO_BUF_SIZE 32768 struct QEMUFile { - QEMUFilePutBufferFunc *put_buffer; - QEMUFileGetBufferFunc *get_buffer; - QEMUFileCloseFunc *close; - QEMUFileRateLimit *rate_limit; - QEMUFileSetRateLimit *set_rate_limit; - QEMUFileGetRateLimit *get_rate_limit; + const QEMUFileOps *ops; void *opaque; int is_write; @@ -257,6 +252,16 @@ static int stdio_fclose(void *opaque) return ret; } +static const QEMUFileOps stdio_pipe_read_ops = { + .get_buffer = stdio_get_buffer, + .close = stdio_pclose +}; + +static const QEMUFileOps stdio_pipe_write_ops = { + .put_buffer = stdio_put_buffer, + .close = stdio_pclose +}; + QEMUFile *qemu_popen(FILE *stdio_file, const char *mode) { QEMUFileStdio *s; @@ -271,11 +276,9 @@ QEMUFile *qemu_popen(FILE *stdio_file, const char *mode) s->stdio_file = stdio_file; if(mode[0] == 'r') { - s->file = qemu_fopen_ops(s, NULL, stdio_get_buffer, stdio_pclose, - NULL, NULL, NULL); + s->file = qemu_fopen_ops(s, &stdio_pipe_read_ops); } else { - s->file = qemu_fopen_ops(s, stdio_put_buffer, NULL, stdio_pclose, - NULL, NULL, NULL); + s->file = qemu_fopen_ops(s, &stdio_pipe_write_ops); } return s->file; } @@ -303,6 +306,16 @@ int qemu_stdio_fd(QEMUFile *f) return fd; } +static const QEMUFileOps stdio_file_read_ops = { + .get_buffer = stdio_get_buffer, + .close = stdio_fclose +}; + +static const QEMUFileOps stdio_file_write_ops = { + .put_buffer = stdio_put_buffer, + .close = stdio_fclose +}; + QEMUFile *qemu_fdopen(int fd, const char *mode) { QEMUFileStdio *s; @@ -320,11 +333,9 @@ QEMUFile *qemu_fdopen(int fd, const char *mode) goto fail; if(mode[0] == 'r') { - s->file = qemu_fopen_ops(s, NULL, stdio_get_buffer, stdio_fclose, - NULL, NULL, NULL); + s->file = qemu_fopen_ops(s, &stdio_file_read_ops); } else { - s->file = qemu_fopen_ops(s, stdio_put_buffer, NULL, stdio_fclose, - NULL, NULL, NULL); + s->file = qemu_fopen_ops(s, &stdio_file_write_ops); } return s->file; @@ -333,13 +344,17 @@ fail: return NULL; } +static const QEMUFileOps socket_read_ops = { + .get_buffer = socket_get_buffer, + .close = socket_close +}; + QEMUFile *qemu_fopen_socket(int fd) { QEMUFileSocket *s = g_malloc0(sizeof(QEMUFileSocket)); s->fd = fd; - s->file = qemu_fopen_ops(s, NULL, socket_get_buffer, socket_close, - NULL, NULL, NULL); + s->file = qemu_fopen_ops(s, &socket_read_ops); return s->file; } @@ -361,11 +376,9 @@ QEMUFile *qemu_fopen(const char *filename, const char *mode) goto fail; if(mode[0] == 'w') { - s->file = qemu_fopen_ops(s, stdio_put_buffer, NULL, stdio_fclose, - NULL, NULL, NULL); + s->file = qemu_fopen_ops(s, &stdio_file_write_ops); } else { - s->file = qemu_fopen_ops(s, NULL, stdio_get_buffer, stdio_fclose, - NULL, NULL, NULL); + s->file = qemu_fopen_ops(s, &stdio_file_read_ops); } return s->file; fail: @@ -390,32 +403,31 @@ static int bdrv_fclose(void *opaque) return bdrv_flush(opaque); } +static const QEMUFileOps bdrv_read_ops = { + .get_buffer = block_get_buffer, + .close = bdrv_fclose +}; + +static const QEMUFileOps bdrv_write_ops = { + .put_buffer = block_put_buffer, + .close = bdrv_fclose +}; + static QEMUFile *qemu_fopen_bdrv(BlockDriverState *bs, int is_writable) { if (is_writable) - return qemu_fopen_ops(bs, block_put_buffer, NULL, bdrv_fclose, - NULL, NULL, NULL); - return qemu_fopen_ops(bs, NULL, block_get_buffer, bdrv_fclose, NULL, NULL, NULL); + return qemu_fopen_ops(bs, &bdrv_write_ops); + return qemu_fopen_ops(bs, &bdrv_read_ops); } -QEMUFile *qemu_fopen_ops(void *opaque, QEMUFilePutBufferFunc *put_buffer, - QEMUFileGetBufferFunc *get_buffer, - QEMUFileCloseFunc *close, - QEMUFileRateLimit *rate_limit, - QEMUFileSetRateLimit *set_rate_limit, - QEMUFileGetRateLimit *get_rate_limit) +QEMUFile *qemu_fopen_ops(void *opaque, const QEMUFileOps *ops) { QEMUFile *f; f = g_malloc0(sizeof(QEMUFile)); f->opaque = opaque; - f->put_buffer = put_buffer; - f->get_buffer = get_buffer; - f->close = close; - f->rate_limit = rate_limit; - f->set_rate_limit = set_rate_limit; - f->get_rate_limit = get_rate_limit; + f->ops = ops; f->is_write = 0; return f; @@ -438,11 +450,11 @@ static int qemu_fflush(QEMUFile *f) { int ret = 0; - if (!f->put_buffer) + if (!f->ops->put_buffer) return 0; if (f->is_write && f->buf_index > 0) { - ret = f->put_buffer(f->opaque, f->buf, f->buf_offset, f->buf_index); + ret = f->ops->put_buffer(f->opaque, f->buf, f->buf_offset, f->buf_index); if (ret >= 0) { f->buf_offset += f->buf_index; } @@ -456,7 +468,7 @@ static void qemu_fill_buffer(QEMUFile *f) int len; int pending; - if (!f->get_buffer) + if (!f->ops->get_buffer) return; if (f->is_write) @@ -469,7 +481,7 @@ static void qemu_fill_buffer(QEMUFile *f) f->buf_index = 0; f->buf_size = pending; - len = f->get_buffer(f->opaque, f->buf + pending, f->buf_offset, + len = f->ops->get_buffer(f->opaque, f->buf + pending, f->buf_offset, IO_BUF_SIZE - pending); if (len > 0) { f->buf_size += len; @@ -493,8 +505,8 @@ int qemu_fclose(QEMUFile *f) int ret; ret = qemu_fflush(f); - if (f->close) { - int ret2 = f->close(f->opaque); + if (f->ops->close) { + int ret2 = f->ops->close(f->opaque); if (ret >= 0) { ret = ret2; } @@ -511,7 +523,7 @@ int qemu_fclose(QEMUFile *f) int qemu_file_put_notify(QEMUFile *f) { - return f->put_buffer(f->opaque, NULL, 0, 0); + return f->ops->put_buffer(f->opaque, NULL, 0, 0); } void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size) @@ -658,16 +670,16 @@ static int64_t qemu_ftell(QEMUFile *f) int qemu_file_rate_limit(QEMUFile *f) { - if (f->rate_limit) - return f->rate_limit(f->opaque); + if (f->ops->rate_limit) + return f->ops->rate_limit(f->opaque); return 0; } int64_t qemu_file_get_rate_limit(QEMUFile *f) { - if (f->get_rate_limit) - return f->get_rate_limit(f->opaque); + if (f->ops->get_rate_limit) + return f->ops->get_rate_limit(f->opaque); return 0; } @@ -676,8 +688,8 @@ int64_t qemu_file_set_rate_limit(QEMUFile *f, int64_t new_rate) { /* any failed or completed migration keeps its state to allow probing of * migration data, but has no associated file anymore */ - if (f && f->set_rate_limit) - return f->set_rate_limit(f->opaque, new_rate); + if (f && f->ops->set_rate_limit) + return f->ops->set_rate_limit(f->opaque, new_rate); return 0; } From 70eb6330343ebc61e5fb22be3d137df40f4bb058 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 8 Aug 2012 10:20:18 +0200 Subject: [PATCH 245/291] migration: add qemu_get_fd Reviewed-by: Orit Wasserman Signed-off-by: Paolo Bonzini --- buffered_file.c | 8 ++++++++ qemu-file.h | 6 ++++++ savevm.c | 27 +++++++++++++++++++++++++++ 3 files changed, 41 insertions(+) diff --git a/buffered_file.c b/buffered_file.c index a5c0b128e0..bd0f61d8c9 100644 --- a/buffered_file.c +++ b/buffered_file.c @@ -174,6 +174,13 @@ static int buffered_close(void *opaque) * 1: Time to stop * negative: There has been an error */ +static int buffered_get_fd(void *opaque) +{ + QEMUFileBuffered *s = opaque; + + return qemu_get_fd(s->file); +} + static int buffered_rate_limit(void *opaque) { QEMUFileBuffered *s = opaque; @@ -235,6 +242,7 @@ static void buffered_rate_tick(void *opaque) } static const QEMUFileOps buffered_file_ops = { + .get_fd = buffered_get_fd, .put_buffer = buffered_put_buffer, .close = buffered_close, .rate_limit = buffered_rate_limit, diff --git a/qemu-file.h b/qemu-file.h index c89e8e09dc..d552f5d906 100644 --- a/qemu-file.h +++ b/qemu-file.h @@ -47,6 +47,10 @@ typedef int (QEMUFileGetBufferFunc)(void *opaque, uint8_t *buf, */ typedef int (QEMUFileCloseFunc)(void *opaque); +/* Called to return the OS file descriptor associated to the QEMUFile. + */ +typedef int (QEMUFileGetFD)(void *opaque); + /* Called to determine if the file has exceeded its bandwidth allocation. The * bandwidth capping is a soft limit, not a hard limit. */ @@ -63,6 +67,7 @@ typedef struct QEMUFileOps { QEMUFilePutBufferFunc *put_buffer; QEMUFileGetBufferFunc *get_buffer; QEMUFileCloseFunc *close; + QEMUFileGetFD *get_fd; QEMUFileRateLimit *rate_limit; QEMUFileSetRateLimit *set_rate_limit; QEMUFileGetRateLimit *get_rate_limit; @@ -74,6 +79,7 @@ QEMUFile *qemu_fdopen(int fd, const char *mode); QEMUFile *qemu_fopen_socket(int fd); QEMUFile *qemu_popen(FILE *popen_file, const char *mode); QEMUFile *qemu_popen_cmd(const char *command, const char *mode); +int qemu_get_fd(QEMUFile *f); int qemu_stdio_fd(QEMUFile *f); int qemu_fclose(QEMUFile *f); void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size); diff --git a/savevm.c b/savevm.c index a4158ecbf7..a58fe9ac49 100644 --- a/savevm.c +++ b/savevm.c @@ -188,6 +188,13 @@ typedef struct QEMUFileSocket QEMUFile *file; } QEMUFileSocket; +static int socket_get_fd(void *opaque) +{ + QEMUFileSocket *s = opaque; + + return s->fd; +} + static int socket_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size) { QEMUFileSocket *s = opaque; @@ -210,6 +217,13 @@ static int socket_close(void *opaque) return 0; } +static int stdio_get_fd(void *opaque) +{ + QEMUFileStdio *s = opaque; + + return fileno(s->stdio_file); +} + static int stdio_put_buffer(void *opaque, const uint8_t *buf, int64_t pos, int size) { QEMUFileStdio *s = opaque; @@ -253,11 +267,13 @@ static int stdio_fclose(void *opaque) } static const QEMUFileOps stdio_pipe_read_ops = { + .get_fd = stdio_get_fd, .get_buffer = stdio_get_buffer, .close = stdio_pclose }; static const QEMUFileOps stdio_pipe_write_ops = { + .get_fd = stdio_get_fd, .put_buffer = stdio_put_buffer, .close = stdio_pclose }; @@ -307,11 +323,13 @@ int qemu_stdio_fd(QEMUFile *f) } static const QEMUFileOps stdio_file_read_ops = { + .get_fd = stdio_get_fd, .get_buffer = stdio_get_buffer, .close = stdio_fclose }; static const QEMUFileOps stdio_file_write_ops = { + .get_fd = stdio_get_fd, .put_buffer = stdio_put_buffer, .close = stdio_fclose }; @@ -345,6 +363,7 @@ fail: } static const QEMUFileOps socket_read_ops = { + .get_fd = socket_get_fd, .get_buffer = socket_get_buffer, .close = socket_close }; @@ -492,6 +511,14 @@ static void qemu_fill_buffer(QEMUFile *f) qemu_file_set_error(f, len); } +int qemu_get_fd(QEMUFile *f) +{ + if (f->ops->get_fd) { + return f->ops->get_fd(f->opaque); + } + return -1; +} + /** Closes the file * * Returns negative error value if any error happened on previous operations or From d263a20bcfc94a59c87176df6c2d29d65a7e4e6a Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Wed, 8 Aug 2012 10:21:26 +0200 Subject: [PATCH 246/291] migration: replace qemu_stdio_fd with qemu_get_fd Reviewed-by: Orit Wasserman Signed-off-by: Paolo Bonzini --- migration-exec.c | 4 ++-- migration-fd.c | 2 +- qemu-file.h | 1 - savevm.c | 11 ----------- 4 files changed, 3 insertions(+), 15 deletions(-) diff --git a/migration-exec.c b/migration-exec.c index 519af57ac7..452bf071f1 100644 --- a/migration-exec.c +++ b/migration-exec.c @@ -88,7 +88,7 @@ static void exec_accept_incoming_migration(void *opaque) QEMUFile *f = opaque; process_incoming_migration(f); - qemu_set_fd_handler2(qemu_stdio_fd(f), NULL, NULL, NULL, NULL); + qemu_set_fd_handler2(qemu_get_fd(f), NULL, NULL, NULL, NULL); qemu_fclose(f); } @@ -103,6 +103,6 @@ void exec_start_incoming_migration(const char *command, Error **errp) return; } - qemu_set_fd_handler2(qemu_stdio_fd(f), NULL, + qemu_set_fd_handler2(qemu_get_fd(f), NULL, exec_accept_incoming_migration, NULL, f); } diff --git a/migration-fd.c b/migration-fd.c index ce6932d7c3..b47b222e88 100644 --- a/migration-fd.c +++ b/migration-fd.c @@ -93,7 +93,7 @@ static void fd_accept_incoming_migration(void *opaque) QEMUFile *f = opaque; process_incoming_migration(f); - qemu_set_fd_handler2(qemu_stdio_fd(f), NULL, NULL, NULL, NULL); + qemu_set_fd_handler2(qemu_get_fd(f), NULL, NULL, NULL, NULL); qemu_fclose(f); } diff --git a/qemu-file.h b/qemu-file.h index d552f5d906..d64bdbb19b 100644 --- a/qemu-file.h +++ b/qemu-file.h @@ -80,7 +80,6 @@ QEMUFile *qemu_fopen_socket(int fd); QEMUFile *qemu_popen(FILE *popen_file, const char *mode); QEMUFile *qemu_popen_cmd(const char *command, const char *mode); int qemu_get_fd(QEMUFile *f); -int qemu_stdio_fd(QEMUFile *f); int qemu_fclose(QEMUFile *f); void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size); void qemu_put_byte(QEMUFile *f, int v); diff --git a/savevm.c b/savevm.c index a58fe9ac49..0ab1ad4afd 100644 --- a/savevm.c +++ b/savevm.c @@ -311,17 +311,6 @@ QEMUFile *qemu_popen_cmd(const char *command, const char *mode) return qemu_popen(popen_file, mode); } -int qemu_stdio_fd(QEMUFile *f) -{ - QEMUFileStdio *p; - int fd; - - p = (QEMUFileStdio *)f->opaque; - fd = fileno(p->stdio_file); - - return fd; -} - static const QEMUFileOps stdio_file_read_ops = { .get_fd = stdio_get_fd, .get_buffer = stdio_get_buffer, From a6ef29096b89640acaa5edc3a74c2e3efbfa306f Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 7 Aug 2012 10:49:13 +0200 Subject: [PATCH 247/291] migration: clean up server sockets and handlers before invoking process_incoming_migration A first step towards making a common "suffix" for all migration protocols, and moving it to process_incoming_migration. Reviewed-by: Orit Wasserman Signed-off-by: Paolo Bonzini --- migration-exec.c | 2 +- migration-fd.c | 2 +- migration-tcp.c | 7 +++---- migration-unix.c | 7 +++---- 4 files changed, 8 insertions(+), 10 deletions(-) diff --git a/migration-exec.c b/migration-exec.c index 452bf071f1..014c60f01d 100644 --- a/migration-exec.c +++ b/migration-exec.c @@ -87,8 +87,8 @@ static void exec_accept_incoming_migration(void *opaque) { QEMUFile *f = opaque; - process_incoming_migration(f); qemu_set_fd_handler2(qemu_get_fd(f), NULL, NULL, NULL, NULL); + process_incoming_migration(f); qemu_fclose(f); } diff --git a/migration-fd.c b/migration-fd.c index b47b222e88..a4cd83ff7c 100644 --- a/migration-fd.c +++ b/migration-fd.c @@ -92,8 +92,8 @@ static void fd_accept_incoming_migration(void *opaque) { QEMUFile *f = opaque; - process_incoming_migration(f); qemu_set_fd_handler2(qemu_get_fd(f), NULL, NULL, NULL, NULL); + process_incoming_migration(f); qemu_fclose(f); } diff --git a/migration-tcp.c b/migration-tcp.c index 46f6ac545c..96a832caa8 100644 --- a/migration-tcp.c +++ b/migration-tcp.c @@ -88,12 +88,14 @@ static void tcp_accept_incoming_migration(void *opaque) do { c = qemu_accept(s, (struct sockaddr *)&addr, &addrlen); } while (c == -1 && socket_error() == EINTR); + qemu_set_fd_handler2(s, NULL, NULL, NULL, NULL); + close(s); DPRINTF("accepted migration\n"); if (c == -1) { fprintf(stderr, "could not accept migration connection\n"); - goto out2; + goto out; } f = qemu_fopen_socket(c); @@ -106,9 +108,6 @@ static void tcp_accept_incoming_migration(void *opaque) qemu_fclose(f); out: close(c); -out2: - qemu_set_fd_handler2(s, NULL, NULL, NULL, NULL); - close(s); } void tcp_start_incoming_migration(const char *host_port, Error **errp) diff --git a/migration-unix.c b/migration-unix.c index ed3db3a39a..5dc49cdf0f 100644 --- a/migration-unix.c +++ b/migration-unix.c @@ -88,12 +88,14 @@ static void unix_accept_incoming_migration(void *opaque) do { c = qemu_accept(s, (struct sockaddr *)&addr, &addrlen); } while (c == -1 && errno == EINTR); + qemu_set_fd_handler2(s, NULL, NULL, NULL, NULL); + close(s); DPRINTF("accepted migration\n"); if (c == -1) { fprintf(stderr, "could not accept migration connection\n"); - goto out2; + goto out; } f = qemu_fopen_socket(c); @@ -106,9 +108,6 @@ static void unix_accept_incoming_migration(void *opaque) qemu_fclose(f); out: close(c); -out2: - qemu_set_fd_handler2(s, NULL, NULL, NULL, NULL); - close(s); } void unix_start_incoming_migration(const char *path, Error **errp) From 8dc592e620b45c4745380b0694ec1aedc073bda2 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 27 Sep 2012 13:25:45 +0200 Subject: [PATCH 248/291] migration: use migrate_fd_close in migrate_fd_cleanup migrate_fd_cleanup will usually close the file descriptor via buffered_file_close's call to migrate_fd_close. However, in the case of s->file == NULL it is "inlining" migrate_fd_close (almost: there is a direct close() instead of using s->close(s)). To fix the inconsistency and clean up the code, allow multiple calls to migrate_fd_close and use the function in migrate_fd_cleanup. Signed-off-by: Paolo Bonzini --- migration.c | 19 ++++++++----------- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/migration.c b/migration.c index 300ab75aaf..a63596f9a0 100644 --- a/migration.c +++ b/migration.c @@ -243,21 +243,13 @@ static int migrate_fd_cleanup(MigrationState *s) { int ret = 0; - if (s->fd != -1) { - qemu_set_fd_handler2(s->fd, NULL, NULL, NULL, NULL); - } - if (s->file) { DPRINTF("closing file\n"); ret = qemu_fclose(s->file); s->file = NULL; } - if (s->fd != -1) { - close(s->fd); - s->fd = -1; - } - + migrate_fd_close(s); return ret; } @@ -393,8 +385,13 @@ int migrate_fd_wait_for_unfreeze(MigrationState *s) int migrate_fd_close(MigrationState *s) { - qemu_set_fd_handler2(s->fd, NULL, NULL, NULL, NULL); - return s->close(s); + int rc = 0; + if (s->fd != -1) { + qemu_set_fd_handler2(s->fd, NULL, NULL, NULL, NULL); + rc = s->close(s); + s->fd = -1; + } + return rc; } void add_migration_state_change_notifier(Notifier *notify) From 09bac73c13b57acd304efb54a361c244d60d375c Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 27 Sep 2012 13:33:08 +0200 Subject: [PATCH 249/291] migration: use closesocket, not close Windows requires this. Migration does not quite work under Windows but let's be uniform across QEMU. Reviewed-by: Orit Wasserman Signed-off-by: Paolo Bonzini --- migration-tcp.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/migration-tcp.c b/migration-tcp.c index 96a832caa8..1a12f17886 100644 --- a/migration-tcp.c +++ b/migration-tcp.c @@ -45,7 +45,7 @@ static int tcp_close(MigrationState *s) int r = 0; DPRINTF("tcp_close\n"); if (s->fd != -1) { - if (close(s->fd) < 0) { + if (closesocket(s->fd) < 0) { r = -errno; } s->fd = -1; @@ -89,7 +89,7 @@ static void tcp_accept_incoming_migration(void *opaque) c = qemu_accept(s, (struct sockaddr *)&addr, &addrlen); } while (c == -1 && socket_error() == EINTR); qemu_set_fd_handler2(s, NULL, NULL, NULL, NULL); - close(s); + closesocket(s); DPRINTF("accepted migration\n"); @@ -107,7 +107,7 @@ static void tcp_accept_incoming_migration(void *opaque) process_incoming_migration(f); qemu_fclose(f); out: - close(c); + closesocket(c); } void tcp_start_incoming_migration(const char *host_port, Error **errp) From 6c3601361ff22cb8bda3f483ea11c4f7bd095094 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Thu, 27 Sep 2012 13:30:15 +0200 Subject: [PATCH 250/291] migration: xxx_close will only be called once No need to test s->fd again, it is tested in the caller. Reviewed-by: Orit Wasserman Signed-off-by: Paolo Bonzini --- migration-exec.c | 14 ++++++-------- migration-fd.c | 33 +++++++++++++++------------------ migration-tcp.c | 7 ++----- migration-unix.c | 7 ++----- 4 files changed, 25 insertions(+), 36 deletions(-) diff --git a/migration-exec.c b/migration-exec.c index 014c60f01d..2ce7770cfa 100644 --- a/migration-exec.c +++ b/migration-exec.c @@ -48,14 +48,12 @@ static int exec_close(MigrationState *s) { int ret = 0; DPRINTF("exec_close\n"); - if (s->opaque) { - ret = qemu_fclose(s->opaque); - s->opaque = NULL; - s->fd = -1; - if (ret >= 0 && !(WIFEXITED(ret) && WEXITSTATUS(ret) == 0)) { - /* close succeeded, but non-zero exit code: */ - ret = -EIO; /* fake errno value */ - } + ret = qemu_fclose(s->opaque); + s->opaque = NULL; + s->fd = -1; + if (ret >= 0 && !(WIFEXITED(ret) && WEXITSTATUS(ret) == 0)) { + /* close succeeded, but non-zero exit code: */ + ret = -EIO; /* fake errno value */ } return ret; } diff --git a/migration-fd.c b/migration-fd.c index a4cd83ff7c..c678b23b7e 100644 --- a/migration-fd.c +++ b/migration-fd.c @@ -48,29 +48,26 @@ static int fd_close(MigrationState *s) int ret; DPRINTF("fd_close\n"); - if (s->fd != -1) { - ret = fstat(s->fd, &st); - if (ret == 0 && S_ISREG(st.st_mode)) { - /* - * If the file handle is a regular file make sure the - * data is flushed to disk before signaling success. - */ - ret = fsync(s->fd); - if (ret != 0) { - ret = -errno; - perror("migration-fd: fsync"); - return ret; - } - } - ret = close(s->fd); - s->fd = -1; + ret = fstat(s->fd, &st); + if (ret == 0 && S_ISREG(st.st_mode)) { + /* + * If the file handle is a regular file make sure the + * data is flushed to disk before signaling success. + */ + ret = fsync(s->fd); if (ret != 0) { ret = -errno; - perror("migration-fd: close"); + perror("migration-fd: fsync"); return ret; } } - return 0; + ret = close(s->fd); + s->fd = -1; + if (ret != 0) { + ret = -errno; + perror("migration-fd: close"); + } + return ret; } void fd_start_outgoing_migration(MigrationState *s, const char *fdname, Error **errp) diff --git a/migration-tcp.c b/migration-tcp.c index 1a12f17886..bb27ce832a 100644 --- a/migration-tcp.c +++ b/migration-tcp.c @@ -44,11 +44,8 @@ static int tcp_close(MigrationState *s) { int r = 0; DPRINTF("tcp_close\n"); - if (s->fd != -1) { - if (closesocket(s->fd) < 0) { - r = -errno; - } - s->fd = -1; + if (closesocket(s->fd) < 0) { + r = -socket_error(); } return r; } diff --git a/migration-unix.c b/migration-unix.c index 5dc49cdf0f..9b5521edec 100644 --- a/migration-unix.c +++ b/migration-unix.c @@ -44,11 +44,8 @@ static int unix_close(MigrationState *s) { int r = 0; DPRINTF("unix_close\n"); - if (s->fd != -1) { - if (close(s->fd) < 0) { - r = -errno; - } - s->fd = -1; + if (close(s->fd) < 0) { + r = -errno; } return r; } From ab52a824a496f4459539a9a11152d6da68703ea0 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 7 Aug 2012 10:50:26 +0200 Subject: [PATCH 251/291] migration: close socket QEMUFile from socket_close The common suffix now is process_incoming_migration+qemu_fclose. Reviewed-by: Orit Wasserman Signed-off-by: Paolo Bonzini --- migration-tcp.c | 2 ++ migration-unix.c | 2 ++ savevm.c | 1 + 3 files changed, 5 insertions(+) diff --git a/migration-tcp.c b/migration-tcp.c index bb27ce832a..1279cc9677 100644 --- a/migration-tcp.c +++ b/migration-tcp.c @@ -103,6 +103,8 @@ static void tcp_accept_incoming_migration(void *opaque) process_incoming_migration(f); qemu_fclose(f); + return; + out: closesocket(c); } diff --git a/migration-unix.c b/migration-unix.c index 9b5521edec..96ea71b787 100644 --- a/migration-unix.c +++ b/migration-unix.c @@ -103,6 +103,8 @@ static void unix_accept_incoming_migration(void *opaque) process_incoming_migration(f); qemu_fclose(f); + return; + out: close(c); } diff --git a/savevm.c b/savevm.c index 0ab1ad4afd..cdad3ad8e4 100644 --- a/savevm.c +++ b/savevm.c @@ -213,6 +213,7 @@ static int socket_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size) static int socket_close(void *opaque) { QEMUFileSocket *s = opaque; + closesocket(s->fd); g_free(s); return 0; } From 1c12e1f5b2ce215ee25b4a4e365e76269edf911c Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 7 Aug 2012 10:51:51 +0200 Subject: [PATCH 252/291] migration: move qemu_fclose to process_incoming_migration The common suffix is now just process_incoming_migration. Reviewed-by: Orit Wasserman Signed-off-by: Paolo Bonzini --- migration-exec.c | 1 - migration-fd.c | 1 - migration-tcp.c | 1 - migration-unix.c | 1 - migration.c | 6 +++++- 5 files changed, 5 insertions(+), 5 deletions(-) diff --git a/migration-exec.c b/migration-exec.c index 2ce7770cfa..2b6fcb4262 100644 --- a/migration-exec.c +++ b/migration-exec.c @@ -87,7 +87,6 @@ static void exec_accept_incoming_migration(void *opaque) qemu_set_fd_handler2(qemu_get_fd(f), NULL, NULL, NULL, NULL); process_incoming_migration(f); - qemu_fclose(f); } void exec_start_incoming_migration(const char *command, Error **errp) diff --git a/migration-fd.c b/migration-fd.c index c678b23b7e..5fe28e09fd 100644 --- a/migration-fd.c +++ b/migration-fd.c @@ -91,7 +91,6 @@ static void fd_accept_incoming_migration(void *opaque) qemu_set_fd_handler2(qemu_get_fd(f), NULL, NULL, NULL, NULL); process_incoming_migration(f); - qemu_fclose(f); } void fd_start_incoming_migration(const char *infd, Error **errp) diff --git a/migration-tcp.c b/migration-tcp.c index 1279cc9677..5e855fe72f 100644 --- a/migration-tcp.c +++ b/migration-tcp.c @@ -102,7 +102,6 @@ static void tcp_accept_incoming_migration(void *opaque) } process_incoming_migration(f); - qemu_fclose(f); return; out: diff --git a/migration-unix.c b/migration-unix.c index 96ea71b787..dba72b4a54 100644 --- a/migration-unix.c +++ b/migration-unix.c @@ -102,7 +102,6 @@ static void unix_accept_incoming_migration(void *opaque) } process_incoming_migration(f); - qemu_fclose(f); return; out: diff --git a/migration.c b/migration.c index a63596f9a0..2741d979fc 100644 --- a/migration.c +++ b/migration.c @@ -85,7 +85,11 @@ void qemu_start_incoming_migration(const char *uri, Error **errp) void process_incoming_migration(QEMUFile *f) { - if (qemu_loadvm_state(f) < 0) { + int ret; + + ret = qemu_loadvm_state(f); + qemu_fclose(f); + if (ret < 0) { fprintf(stderr, "load of migration failed\n"); exit(0); } From 595ab64169be9063d64c3b1aa1c249fbe2662221 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 7 Aug 2012 11:07:59 +0200 Subject: [PATCH 253/291] migration: handle EAGAIN while reading QEMUFile This will never happen right now (the assertion would fail). The next patch will set the socket or pipe in non-blocking mode, thus enabling this part of the code. Coroutines can just stop whenever they want with qemu_coroutine_yield. As soon as select tells the main loop that the migration stream is readable, the coroutine is re-entered directly in qemu_get_buffer, where it will read more data and pass it to the loading routines. Signed-off-by: Paolo Bonzini --- savevm.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/savevm.c b/savevm.c index cdad3ad8e4..5d04d59688 100644 --- a/savevm.c +++ b/savevm.c @@ -200,13 +200,22 @@ static int socket_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size) QEMUFileSocket *s = opaque; ssize_t len; - do { + for (;;) { len = qemu_recv(s->fd, buf, size, 0); - } while (len == -1 && socket_error() == EINTR); + if (len != -1) { + break; + } + if (socket_error() == EAGAIN) { + assert(qemu_in_coroutine()); + qemu_coroutine_yield(); + } else if (socket_error() != EINTR) { + break; + } + } - if (len == -1) + if (len == -1) { len = -socket_error(); - + } return len; } @@ -237,10 +246,19 @@ static int stdio_get_buffer(void *opaque, uint8_t *buf, int64_t pos, int size) FILE *fp = s->stdio_file; int bytes; - do { + for (;;) { clearerr(fp); bytes = fread(buf, 1, size, fp); - } while ((bytes == 0) && ferror(fp) && (errno == EINTR)); + if (bytes != 0 || !ferror(fp)) { + break; + } + if (errno == EAGAIN) { + assert(qemu_in_coroutine()); + qemu_coroutine_yield(); + } else if (errno != EINTR) { + break; + } + } return bytes; } From 82a4da79fd6c108400637143f8439c2364bdb21e Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Tue, 7 Aug 2012 10:57:43 +0200 Subject: [PATCH 254/291] migration: move process_incoming_migration to a coroutine The final part of incoming migration, which now consists of process_incoming_migration for all protocols, is thus made non-blocking. Reviewed-by: Orit Wasserman Signed-off-by: Paolo Bonzini --- migration.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/migration.c b/migration.c index 2741d979fc..73ce170ddf 100644 --- a/migration.c +++ b/migration.c @@ -83,11 +83,13 @@ void qemu_start_incoming_migration(const char *uri, Error **errp) } } -void process_incoming_migration(QEMUFile *f) +static void process_incoming_migration_co(void *opaque) { + QEMUFile *f = opaque; int ret; ret = qemu_loadvm_state(f); + qemu_set_fd_handler(qemu_get_fd(f), NULL, NULL, NULL); qemu_fclose(f); if (ret < 0) { fprintf(stderr, "load of migration failed\n"); @@ -107,6 +109,23 @@ void process_incoming_migration(QEMUFile *f) } } +static void enter_migration_coroutine(void *opaque) +{ + Coroutine *co = opaque; + qemu_coroutine_enter(co, NULL); +} + +void process_incoming_migration(QEMUFile *f) +{ + Coroutine *co = qemu_coroutine_create(process_incoming_migration_co); + int fd = qemu_get_fd(f); + + assert(fd != -1); + socket_set_nonblock(fd); + qemu_set_fd_handler(fd, enter_migration_coroutine, NULL, co); + qemu_coroutine_enter(co, f); +} + /* amount of nanoseconds we are willing to wait for migration to be down. * the choice of nanoseconds is because it is the maximum resolution that * get_clock() can achieve. It is an internal measure. All user-visible From 1f001dc7bc9e435bf231a5b0edcad1c7c2bd6214 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 2 Nov 2012 15:43:20 +0100 Subject: [PATCH 255/291] compiler: support Darwin weak references Weakrefs only tell you if the symbol was defined elsewhere, so you need a further check at runtime to pick the default definition when needed. This could be automated by the compiler, but it does not do it. Signed-off-by: Paolo Bonzini Signed-off-by: Anthony Liguori --- compiler.h | 9 +++++++- osdep.c | 56 ++++++++++++++++++++++++++++---------------------- oslib-win32.c | 12 ++++++----- qemu-sockets.c | 40 ++++++++++++++++++++---------------- qmp.c | 2 ++ 5 files changed, 71 insertions(+), 48 deletions(-) diff --git a/compiler.h b/compiler.h index 58865d65e8..55d7d74775 100644 --- a/compiler.h +++ b/compiler.h @@ -50,8 +50,15 @@ # define __printf__ __gnu_printf__ # endif # endif -# define QEMU_WEAK_ALIAS(newname, oldname) \ +# if defined(__APPLE__) +# define QEMU_WEAK_ALIAS(newname, oldname) \ + static typeof(oldname) weak_##newname __attribute__((unused, weakref(#oldname))) +# define QEMU_WEAK_REF(newname, oldname) (weak_##newname ? weak_##newname : oldname) +# else +# define QEMU_WEAK_ALIAS(newname, oldname) \ typeof(oldname) newname __attribute__((weak, alias (#oldname))) +# define QEMU_WEAK_REF(newname, oldname) newname +# endif #else #define GCC_ATTR /**/ #define GCC_FMT_ATTR(n, m) diff --git a/osdep.c b/osdep.c index a87d4a453d..2f7a49159a 100644 --- a/osdep.c +++ b/osdep.c @@ -54,6 +54,38 @@ static bool fips_enabled = false; static const char *qemu_version = QEMU_VERSION; +static int default_fdset_get_fd(int64_t fdset_id, int flags) +{ + return -1; +} +QEMU_WEAK_ALIAS(monitor_fdset_get_fd, default_fdset_get_fd); +#define monitor_fdset_get_fd \ + QEMU_WEAK_REF(monitor_fdset_get_fd, default_fdset_get_fd) + +static int default_fdset_dup_fd_add(int64_t fdset_id, int dup_fd) +{ + return -1; +} +QEMU_WEAK_ALIAS(monitor_fdset_dup_fd_add, default_fdset_dup_fd_add); +#define monitor_fdset_dup_fd_add \ + QEMU_WEAK_REF(monitor_fdset_dup_fd_add, default_fdset_dup_fd_add) + +static int default_fdset_dup_fd_remove(int dup_fd) +{ + return -1; +} +QEMU_WEAK_ALIAS(monitor_fdset_dup_fd_remove, default_fdset_dup_fd_remove); +#define monitor_fdset_dup_fd_remove \ + QEMU_WEAK_REF(monitor_fdset_dup_fd_remove, default_fdset_dup_fd_remove) + +static int default_fdset_dup_fd_find(int dup_fd) +{ + return -1; +} +QEMU_WEAK_ALIAS(monitor_fdset_dup_fd_find, default_fdset_dup_fd_find); +#define monitor_fdset_dup_fd_find \ + QEMU_WEAK_REF(monitor_fdset_dup_fd_remove, default_fdset_dup_fd_find) + int socket_set_cork(int fd, int v) { #if defined(SOL_TCP) && defined(TCP_CORK) @@ -400,27 +432,3 @@ bool fips_get_state(void) return fips_enabled; } - -static int default_fdset_get_fd(int64_t fdset_id, int flags) -{ - return -1; -} -QEMU_WEAK_ALIAS(monitor_fdset_get_fd, default_fdset_get_fd); - -static int default_fdset_dup_fd_add(int64_t fdset_id, int dup_fd) -{ - return -1; -} -QEMU_WEAK_ALIAS(monitor_fdset_dup_fd_add, default_fdset_dup_fd_add); - -static int default_fdset_dup_fd_remove(int dup_fd) -{ - return -1; -} -QEMU_WEAK_ALIAS(monitor_fdset_dup_fd_remove, default_fdset_dup_fd_remove); - -static int default_fdset_dup_fd_find(int dup_fd) -{ - return -1; -} -QEMU_WEAK_ALIAS(monitor_fdset_dup_fd_find, default_fdset_dup_fd_find); diff --git a/oslib-win32.c b/oslib-win32.c index 9ca83df011..326a2bddb3 100644 --- a/oslib-win32.c +++ b/oslib-win32.c @@ -32,6 +32,13 @@ #include "trace.h" #include "qemu_socket.h" +static void default_qemu_fd_register(int fd) +{ +} +QEMU_WEAK_ALIAS(qemu_fd_register, default_qemu_fd_register); +#define qemu_fd_register \ + QEMU_WEAK_REF(qemu_fd_register, default_qemu_fd_register) + void *qemu_oom_check(void *ptr) { if (ptr == NULL) { @@ -150,8 +157,3 @@ int qemu_get_thread_id(void) { return GetCurrentThreadId(); } - -static void default_qemu_fd_register(int fd) -{ -} -QEMU_WEAK_ALIAS(qemu_fd_register, default_qemu_fd_register); diff --git a/qemu-sockets.c b/qemu-sockets.c index f2a637165b..abcd791cb6 100644 --- a/qemu-sockets.c +++ b/qemu-sockets.c @@ -61,6 +61,28 @@ static QemuOptsList dummy_opts = { }, }; +static int default_monitor_get_fd(Monitor *mon, const char *name, Error **errp) +{ + error_setg(errp, "only QEMU supports file descriptor passing"); + return -1; +} +QEMU_WEAK_ALIAS(monitor_get_fd, default_monitor_get_fd); +#define monitor_get_fd \ + QEMU_WEAK_REF(monitor_get_fd, default_monitor_get_fd) + +static int default_qemu_set_fd_handler2(int fd, + IOCanReadHandler *fd_read_poll, + IOHandler *fd_read, + IOHandler *fd_write, + void *opaque) + +{ + abort(); +} +QEMU_WEAK_ALIAS(qemu_set_fd_handler2, default_qemu_set_fd_handler2); +#define qemu_set_fd_handler2 \ + QEMU_WEAK_REF(qemu_set_fd_handler2, default_qemu_set_fd_handler2) + static int inet_getport(struct addrinfo *e) { struct sockaddr_in *i4; @@ -967,21 +989,3 @@ int socket_init(void) #endif return 0; } - -static int default_monitor_get_fd(Monitor *mon, const char *name, Error **errp) -{ - error_setg(errp, "only QEMU supports file descriptor passing"); - return -1; -} -QEMU_WEAK_ALIAS(monitor_get_fd, default_monitor_get_fd); - -static int default_qemu_set_fd_handler2(int fd, - IOCanReadHandler *fd_read_poll, - IOHandler *fd_read, - IOHandler *fd_write, - void *opaque) - -{ - abort(); -} -QEMU_WEAK_ALIAS(qemu_set_fd_handler2, default_qemu_set_fd_handler2); diff --git a/qmp.c b/qmp.c index 638888a64e..13e83a59e0 100644 --- a/qmp.c +++ b/qmp.c @@ -477,6 +477,8 @@ static CpuDefinitionInfoList *default_arch_query_cpu_definitions(Error **errp) return NULL; } QEMU_WEAK_ALIAS(arch_query_cpu_definitions, default_arch_query_cpu_definitions); +#define arch_query_cpu_definitions \ + QEMU_WEAK_REF(arch_query_cpu_definitions, default_arch_query_cpu_definitions) CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp) { From c166cb72f1676855816340666c3b618beef4b976 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 2 Nov 2012 15:43:21 +0100 Subject: [PATCH 256/291] semaphore: implement fallback counting semaphores with mutex+condvar OpenBSD and Darwin do not have sem_timedwait. Implement a fallback for them. Signed-off-by: Paolo Bonzini Signed-off-by: Anthony Liguori --- qemu-thread-posix.c | 90 ++++++++++++++++++++++++++++++++++++++++----- qemu-thread-posix.h | 6 +++ 2 files changed, 87 insertions(+), 9 deletions(-) diff --git a/qemu-thread-posix.c b/qemu-thread-posix.c index 6a3d3a12a8..4ef9c7b3f8 100644 --- a/qemu-thread-posix.c +++ b/qemu-thread-posix.c @@ -122,36 +122,106 @@ void qemu_sem_init(QemuSemaphore *sem, int init) { int rc; +#if defined(__OpenBSD__) || defined(__APPLE__) || defined(__NetBSD__) + rc = pthread_mutex_init(&sem->lock, NULL); + if (rc != 0) { + error_exit(rc, __func__); + } + rc = pthread_cond_init(&sem->cond, NULL); + if (rc != 0) { + error_exit(rc, __func__); + } + if (init < 0) { + error_exit(EINVAL, __func__); + } + sem->count = init; +#else rc = sem_init(&sem->sem, 0, init); if (rc < 0) { error_exit(errno, __func__); } +#endif } void qemu_sem_destroy(QemuSemaphore *sem) { int rc; +#if defined(__OpenBSD__) || defined(__APPLE__) || defined(__NetBSD__) + rc = pthread_cond_destroy(&sem->cond); + if (rc < 0) { + error_exit(rc, __func__); + } + rc = pthread_mutex_destroy(&sem->lock); + if (rc < 0) { + error_exit(rc, __func__); + } +#else rc = sem_destroy(&sem->sem); if (rc < 0) { error_exit(errno, __func__); } +#endif } void qemu_sem_post(QemuSemaphore *sem) { int rc; +#if defined(__OpenBSD__) || defined(__APPLE__) || defined(__NetBSD__) + pthread_mutex_lock(&sem->lock); + if (sem->count == INT_MAX) { + rc = EINVAL; + } else if (sem->count++ < 0) { + rc = pthread_cond_signal(&sem->cond); + } else { + rc = 0; + } + pthread_mutex_unlock(&sem->lock); + if (rc != 0) { + error_exit(rc, __func__); + } +#else rc = sem_post(&sem->sem); if (rc < 0) { error_exit(errno, __func__); } +#endif +} + +static void compute_abs_deadline(struct timespec *ts, int ms) +{ + struct timeval tv; + gettimeofday(&tv, NULL); + ts->tv_nsec = tv.tv_usec * 1000 + (ms % 1000) * 1000000; + ts->tv_sec = tv.tv_sec + ms / 1000; + if (ts->tv_nsec >= 1000000000) { + ts->tv_sec++; + ts->tv_nsec -= 1000000000; + } } int qemu_sem_timedwait(QemuSemaphore *sem, int ms) { int rc; + struct timespec ts; +#if defined(__OpenBSD__) || defined(__APPLE__) || defined(__NetBSD__) + compute_abs_deadline(&ts, ms); + pthread_mutex_lock(&sem->lock); + --sem->count; + while (sem->count < 0) { + rc = pthread_cond_timedwait(&sem->cond, &sem->lock, &ts); + if (rc == ETIMEDOUT) { + break; + } + if (rc != 0) { + error_exit(rc, __func__); + } + } + pthread_mutex_unlock(&sem->lock); + return (rc == ETIMEDOUT ? -1 : 0); +#else if (ms <= 0) { /* This is cheaper than sem_timedwait. */ do { @@ -161,15 +231,7 @@ int qemu_sem_timedwait(QemuSemaphore *sem, int ms) return -1; } } else { - struct timeval tv; - struct timespec ts; - gettimeofday(&tv, NULL); - ts.tv_nsec = tv.tv_usec * 1000 + (ms % 1000) * 1000000; - ts.tv_sec = tv.tv_sec + ms / 1000; - if (ts.tv_nsec >= 1000000000) { - ts.tv_sec++; - ts.tv_nsec -= 1000000000; - } + compute_abs_deadline(&ts, ms); do { rc = sem_timedwait(&sem->sem, &ts); } while (rc == -1 && errno == EINTR); @@ -181,10 +243,19 @@ int qemu_sem_timedwait(QemuSemaphore *sem, int ms) error_exit(errno, __func__); } return 0; +#endif } void qemu_sem_wait(QemuSemaphore *sem) { +#if defined(__OpenBSD__) || defined(__APPLE__) || defined(__NetBSD__) + pthread_mutex_lock(&sem->lock); + --sem->count; + while (sem->count < 0) { + pthread_cond_wait(&sem->cond, &sem->lock); + } + pthread_mutex_unlock(&sem->lock); +#else int rc; do { @@ -193,6 +264,7 @@ void qemu_sem_wait(QemuSemaphore *sem) if (rc < 0) { error_exit(errno, __func__); } +#endif } void qemu_thread_create(QemuThread *thread, diff --git a/qemu-thread-posix.h b/qemu-thread-posix.h index 2542c15200..380bae209b 100644 --- a/qemu-thread-posix.h +++ b/qemu-thread-posix.h @@ -12,7 +12,13 @@ struct QemuCond { }; struct QemuSemaphore { +#if defined(__OpenBSD__) || defined(__APPLE__) || defined(__NetBSD__) + pthread_mutex_t lock; + pthread_cond_t cond; + int count; +#else sem_t sem; +#endif }; struct QemuThread { From c8122c35e611385b31e2d8ccb059d0687540244a Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 2 Nov 2012 15:43:22 +0100 Subject: [PATCH 257/291] qemu-timer: reinitialize timers after fork Timers are not inherited by the child of a fork(2), so just use pthread_atfork to reinstate them after daemonize. Signed-off-by: Paolo Bonzini Signed-off-by: Anthony Liguori --- qemu-timer.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/qemu-timer.c b/qemu-timer.c index f3426c9937..7b2217aab0 100644 --- a/qemu-timer.c +++ b/qemu-timer.c @@ -742,6 +742,17 @@ static void quit_timers(void) t->stop(t); } +static void reinit_timers(void) +{ + struct qemu_alarm_timer *t = alarm_timer; + t->stop(t); + if (t->start(t)) { + fprintf(stderr, "Internal timer error: aborting\n"); + exit(1); + } + qemu_rearm_alarm_timer(t); +} + int init_timer_alarm(void) { struct qemu_alarm_timer *t = NULL; @@ -765,6 +776,9 @@ int init_timer_alarm(void) } atexit(quit_timers); +#ifdef CONFIG_POSIX + pthread_atfork(NULL, NULL, reinit_timers); +#endif alarm_timer = t; return 0; From f9ab4654e370ceedb745523b607a628e297cb6ab Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 2 Nov 2012 15:43:23 +0100 Subject: [PATCH 258/291] vl: unify calls to init_timer_alarm init_timer_alarm was being called twice. This is not needed. Signed-off-by: Paolo Bonzini Signed-off-by: Anthony Liguori --- main-loop.c | 5 ++++- vl.c | 5 ----- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/main-loop.c b/main-loop.c index e43c7c8e8d..234a3130c2 100644 --- a/main-loop.c +++ b/main-loop.c @@ -123,7 +123,10 @@ int qemu_init_main_loop(void) GSource *src; init_clocks(); - init_timer_alarm(); + if (init_timer_alarm() < 0) { + fprintf(stderr, "could not initialize alarm timer\n"); + exit(1); + } qemu_mutex_lock_iothread(); ret = qemu_signal_init(); diff --git a/vl.c b/vl.c index 99681dabf5..e2d5276988 100644 --- a/vl.c +++ b/vl.c @@ -3616,11 +3616,6 @@ int main(int argc, char **argv, char **envp) add_device_config(DEV_VIRTCON, "vc:80Cx24C"); } - if (init_timer_alarm() < 0) { - fprintf(stderr, "could not initialize alarm timer\n"); - exit(1); - } - socket_init(); if (qemu_opts_foreach(qemu_find_opts("chardev"), chardev_init_func, NULL, 1) != 0) From 49cf57281b74ccb64587ccc0626fc55a01227a15 Mon Sep 17 00:00:00 2001 From: Paolo Bonzini Date: Fri, 2 Nov 2012 15:43:24 +0100 Subject: [PATCH 259/291] vl: delay thread initialization after daemonization Commit ac4119c (chardev: Use timer instead of bottom-half to postpone open event, 2012-10-12) moved the alarm timer initialization to an earlier point but failed to consider that it depends on qemu_init_main_loop. Later, commit 1c53786 (vl: init main loop earlier, 2012-10-30) fixed this, but left -daemonize in two different ways. First, timers need to be reinitialized after forking. Second, the global mutex was being held by the parent, and thus dropped after forking. The first is now fixed using pthread_atfork. For the second part, make sure that the global mutex is not taken before daemonization, and similarly delay qemu_thread_self. Signed-off-by: Paolo Bonzini Signed-off-by: Anthony Liguori --- main-loop.c | 1 - vl.c | 4 +++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/main-loop.c b/main-loop.c index 234a3130c2..c87624e621 100644 --- a/main-loop.c +++ b/main-loop.c @@ -128,7 +128,6 @@ int qemu_init_main_loop(void) exit(1); } - qemu_mutex_lock_iothread(); ret = qemu_signal_init(); if (ret) { return ret; diff --git a/vl.c b/vl.c index e2d5276988..0f5b07bbde 100644 --- a/vl.c +++ b/vl.c @@ -3477,7 +3477,6 @@ int main(int argc, char **argv, char **envp) } loc_set_none(); - qemu_init_cpu_loop(); if (qemu_init_main_loop()) { fprintf(stderr, "qemu_init_main_loop failed\n"); exit(1); @@ -3677,6 +3676,9 @@ int main(int argc, char **argv, char **envp) os_set_line_buffering(); + qemu_init_cpu_loop(); + qemu_mutex_lock_iothread(); + #ifdef CONFIG_SPICE /* spice needs the timers to be initialized by this point */ qemu_spice_init(); From aed91c1bff5e568c7b0fbd0e1e7e2f9e62409e73 Mon Sep 17 00:00:00 2001 From: Meador Inge Date: Mon, 29 Oct 2012 12:05:09 +0000 Subject: [PATCH 260/291] m68k: Return semihosting errno values correctly MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Fixing a simple typo, s/errno/err/, that caused the error status from GDB semihosted system calls to be returned incorrectly. Signed-off-by: Meador Inge Reviewed-by: Andreas Färber Signed-off-by: Peter Maydell Signed-off-by: Blue Swirl --- target-m68k/m68k-semi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c index 3bb30cd1f7..fed44ea490 100644 --- a/target-m68k/m68k-semi.c +++ b/target-m68k/m68k-semi.c @@ -150,7 +150,7 @@ static void m68k_semi_cb(CPUM68KState *env, target_ulong ret, target_ulong err) } /* FIXME - handle put_user() failure */ put_user_u32(ret, args); - put_user_u32(errno, args + 4); + put_user_u32(err, args + 4); } #define ARG(n) \ From 7ba6c10490cf57608045eb2b6351f185d600f4ea Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 29 Oct 2012 12:05:10 +0000 Subject: [PATCH 261/291] target-m68k/m68k-semi: Handle get_user failure Handle failure of get_user accessing the semihosting argument block, rather than simply ignoring the failures. Signed-off-by: Peter Maydell Signed-off-by: Blue Swirl --- target-m68k/m68k-semi.c | 144 ++++++++++++++++++++++++++-------------- 1 file changed, 93 insertions(+), 51 deletions(-) diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c index fed44ea490..d569bf17c0 100644 --- a/target-m68k/m68k-semi.c +++ b/target-m68k/m68k-semi.c @@ -153,17 +153,21 @@ static void m68k_semi_cb(CPUM68KState *env, target_ulong ret, target_ulong err) put_user_u32(err, args + 4); } -#define ARG(n) \ -({ \ - target_ulong __arg; \ - /* FIXME - handle get_user() failure */ \ - get_user_ual(__arg, args + (n) * 4); \ - __arg; \ -}) -#define PARG(x) ((unsigned long)ARG(x)) +/* Read the input value from the argument block; fail the semihosting + * call if the memory read fails. + */ +#define GET_ARG(n) do { \ + if (get_user_ual(arg ## n, args + (n) * 4)) { \ + result = -1; \ + errno = EFAULT; \ + goto failed; \ + } \ +} while (0) + void do_m68k_semihosting(CPUM68KState *env, int nr) { uint32_t args; + target_ulong arg0, arg1, arg2, arg3; void *p; void *q; uint32_t len; @@ -175,27 +179,33 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) gdb_exit(env, env->dregs[0]); exit(env->dregs[0]); case HOSTED_OPEN: + GET_ARG(0); + GET_ARG(1); + GET_ARG(2); + GET_ARG(3); if (use_gdb_syscalls()) { - gdb_do_syscall(m68k_semi_cb, "open,%s,%x,%x", ARG(0), (int)ARG(1), - ARG(2), ARG(3)); + gdb_do_syscall(m68k_semi_cb, "open,%s,%x,%x", arg0, (int)arg1, + arg2, arg3); return; } else { - if (!(p = lock_user_string(ARG(0)))) { + p = lock_user_string(arg0); + if (!p) { /* FIXME - check error code? */ result = -1; } else { - result = open(p, translate_openflags(ARG(2)), ARG(3)); - unlock_user(p, ARG(0), 0); + result = open(p, translate_openflags(arg2), arg3); + unlock_user(p, arg0, 0); } } break; case HOSTED_CLOSE: { /* Ignore attempts to close stdin/out/err. */ - int fd = ARG(0); + GET_ARG(0); + int fd = arg0; if (fd > 2) { if (use_gdb_syscalls()) { - gdb_do_syscall(m68k_semi_cb, "close,%x", ARG(0)); + gdb_do_syscall(m68k_semi_cb, "close,%x", arg0); return; } else { result = close(fd); @@ -206,47 +216,59 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) break; } case HOSTED_READ: - len = ARG(2); + GET_ARG(0); + GET_ARG(1); + GET_ARG(2); + len = arg2; if (use_gdb_syscalls()) { gdb_do_syscall(m68k_semi_cb, "read,%x,%x,%x", - ARG(0), ARG(1), len); + arg0, arg1, len); return; } else { - if (!(p = lock_user(VERIFY_WRITE, ARG(1), len, 0))) { + p = lock_user(VERIFY_WRITE, arg1, len, 0); + if (!p) { /* FIXME - check error code? */ result = -1; } else { - result = read(ARG(0), p, len); - unlock_user(p, ARG(1), len); + result = read(arg0, p, len); + unlock_user(p, arg1, len); } } break; case HOSTED_WRITE: - len = ARG(2); + GET_ARG(0); + GET_ARG(1); + GET_ARG(2); + len = arg2; if (use_gdb_syscalls()) { gdb_do_syscall(m68k_semi_cb, "write,%x,%x,%x", - ARG(0), ARG(1), len); + arg0, arg1, len); return; } else { - if (!(p = lock_user(VERIFY_READ, ARG(1), len, 1))) { + p = lock_user(VERIFY_READ, arg1, len, 1); + if (!p) { /* FIXME - check error code? */ result = -1; } else { - result = write(ARG(0), p, len); - unlock_user(p, ARG(0), 0); + result = write(arg0, p, len); + unlock_user(p, arg0, 0); } } break; case HOSTED_LSEEK: { uint64_t off; - off = (uint32_t)ARG(2) | ((uint64_t)ARG(1) << 32); + GET_ARG(0); + GET_ARG(1); + GET_ARG(2); + GET_ARG(3); + off = (uint32_t)arg2 | ((uint64_t)arg1 << 32); if (use_gdb_syscalls()) { m68k_semi_is_fseek = 1; gdb_do_syscall(m68k_semi_cb, "fseek,%x,%lx,%x", - ARG(0), off, ARG(3)); + arg0, off, arg3); } else { - off = lseek(ARG(0), off, ARG(3)); + off = lseek(arg0, off, arg3); /* FIXME - handle put_user() failure */ put_user_u32(off >> 32, args); put_user_u32(off, args + 4); @@ -255,74 +277,89 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) return; } case HOSTED_RENAME: + GET_ARG(0); + GET_ARG(1); + GET_ARG(2); + GET_ARG(3); if (use_gdb_syscalls()) { gdb_do_syscall(m68k_semi_cb, "rename,%s,%s", - ARG(0), (int)ARG(1), ARG(2), (int)ARG(3)); + arg0, (int)arg1, arg2, (int)arg3); return; } else { - p = lock_user_string(ARG(0)); - q = lock_user_string(ARG(2)); + p = lock_user_string(arg0); + q = lock_user_string(arg2); if (!p || !q) { /* FIXME - check error code? */ result = -1; } else { result = rename(p, q); } - unlock_user(p, ARG(0), 0); - unlock_user(q, ARG(2), 0); + unlock_user(p, arg0, 0); + unlock_user(q, arg2, 0); } break; case HOSTED_UNLINK: + GET_ARG(0); + GET_ARG(1); if (use_gdb_syscalls()) { gdb_do_syscall(m68k_semi_cb, "unlink,%s", - ARG(0), (int)ARG(1)); + arg0, (int)arg1); return; } else { - if (!(p = lock_user_string(ARG(0)))) { + p = lock_user_string(arg0); + if (!p) { /* FIXME - check error code? */ result = -1; } else { result = unlink(p); - unlock_user(p, ARG(0), 0); + unlock_user(p, arg0, 0); } } break; case HOSTED_STAT: + GET_ARG(0); + GET_ARG(1); + GET_ARG(2); if (use_gdb_syscalls()) { gdb_do_syscall(m68k_semi_cb, "stat,%s,%x", - ARG(0), (int)ARG(1), ARG(2)); + arg0, (int)arg1, arg2); return; } else { struct stat s; - if (!(p = lock_user_string(ARG(0)))) { + p = lock_user_string(arg0); + if (!p) { /* FIXME - check error code? */ result = -1; } else { result = stat(p, &s); - unlock_user(p, ARG(0), 0); + unlock_user(p, arg0, 0); } if (result == 0) { - translate_stat(env, ARG(2), &s); + translate_stat(env, arg2, &s); } } break; case HOSTED_FSTAT: + GET_ARG(0); + GET_ARG(1); if (use_gdb_syscalls()) { gdb_do_syscall(m68k_semi_cb, "fstat,%x,%x", - ARG(0), ARG(1)); + arg0, arg1); return; } else { struct stat s; - result = fstat(ARG(0), &s); + result = fstat(arg0, &s); if (result == 0) { - translate_stat(env, ARG(1), &s); + translate_stat(env, arg1, &s); } } break; case HOSTED_GETTIMEOFDAY: + GET_ARG(0); + GET_ARG(1); if (use_gdb_syscalls()) { gdb_do_syscall(m68k_semi_cb, "gettimeofday,%x,%x", - ARG(0), ARG(1)); + arg0, arg1); return; } else { qemu_timeval tv; @@ -330,37 +367,41 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) result = qemu_gettimeofday(&tv); if (result != 0) { if (!(p = lock_user(VERIFY_WRITE, - ARG(0), sizeof(struct gdb_timeval), 0))) { + arg0, sizeof(struct gdb_timeval), 0))) { /* FIXME - check error code? */ result = -1; } else { p->tv_sec = cpu_to_be32(tv.tv_sec); p->tv_usec = cpu_to_be64(tv.tv_usec); - unlock_user(p, ARG(0), sizeof(struct gdb_timeval)); + unlock_user(p, arg0, sizeof(struct gdb_timeval)); } } } break; case HOSTED_ISATTY: + GET_ARG(0); if (use_gdb_syscalls()) { - gdb_do_syscall(m68k_semi_cb, "isatty,%x", ARG(0)); + gdb_do_syscall(m68k_semi_cb, "isatty,%x", arg0); return; } else { - result = isatty(ARG(0)); + result = isatty(arg0); } break; case HOSTED_SYSTEM: + GET_ARG(0); + GET_ARG(1); if (use_gdb_syscalls()) { gdb_do_syscall(m68k_semi_cb, "system,%s", - ARG(0), (int)ARG(1)); + arg0, (int)arg1); return; } else { - if (!(p = lock_user_string(ARG(0)))) { + p = lock_user_string(arg0); + if (!p) { /* FIXME - check error code? */ result = -1; } else { result = system(p); - unlock_user(p, ARG(0), 0); + unlock_user(p, arg0, 0); } } break; @@ -402,6 +443,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) cpu_abort(env, "Unsupported semihosting syscall %d\n", nr); result = 0; } +failed: /* FIXME - handle put_user() failure */ put_user_u32(result, args); put_user_u32(errno, args + 4); From 1073bfd8c0829be06e6ad1cbb4a2f48f8bb594bc Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 29 Oct 2012 12:05:11 +0000 Subject: [PATCH 262/291] target-m68k/m68k-semi.c: Log when put_user for returning values fails Abstract out the use of put_user for returning semihosting call results, so that we can log when a guest erroneously attempts a semihosting call with an unwritable argument block. Signed-off-by: Peter Maydell Signed-off-by: Blue Swirl --- target-m68k/m68k-semi.c | 47 +++++++++++++++++++++++++++-------------- 1 file changed, 31 insertions(+), 16 deletions(-) diff --git a/target-m68k/m68k-semi.c b/target-m68k/m68k-semi.c index d569bf17c0..9f7a24cdb4 100644 --- a/target-m68k/m68k-semi.c +++ b/target-m68k/m68k-semi.c @@ -133,24 +133,44 @@ static void translate_stat(CPUM68KState *env, target_ulong addr, struct stat *s) unlock_user(p, addr, sizeof(struct m68k_gdb_stat)); } +static void m68k_semi_return_u32(CPUM68KState *env, uint32_t ret, uint32_t err) +{ + target_ulong args = env->dregs[1]; + if (put_user_u32(ret, args) || + put_user_u32(err, args + 4)) { + /* The m68k semihosting ABI does not provide any way to report this + * error to the guest, so the best we can do is log it in qemu. + * It is always a guest error not to pass us a valid argument block. + */ + qemu_log_mask(LOG_GUEST_ERROR, "m68k-semihosting: return value " + "discarded because argument block not writable\n"); + } +} + +static void m68k_semi_return_u64(CPUM68KState *env, uint64_t ret, uint32_t err) +{ + target_ulong args = env->dregs[1]; + if (put_user_u32(ret >> 32, args) || + put_user_u32(ret, args + 4) || + put_user_u32(err, args + 8)) { + /* No way to report this via m68k semihosting ABI; just log it */ + qemu_log_mask(LOG_GUEST_ERROR, "m68k-semihosting: return value " + "discarded because argument block not writable\n"); + } +} + static int m68k_semi_is_fseek; static void m68k_semi_cb(CPUM68KState *env, target_ulong ret, target_ulong err) { - target_ulong args; - - args = env->dregs[1]; if (m68k_semi_is_fseek) { /* FIXME: We've already lost the high bits of the fseek return value. */ - /* FIXME - handle put_user() failure */ - put_user_u32(0, args); - args += 4; + m68k_semi_return_u64(env, ret, err); m68k_semi_is_fseek = 0; + } else { + m68k_semi_return_u32(env, ret, err); } - /* FIXME - handle put_user() failure */ - put_user_u32(ret, args); - put_user_u32(err, args + 4); } /* Read the input value from the argument block; fail the semihosting @@ -269,10 +289,7 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) arg0, off, arg3); } else { off = lseek(arg0, off, arg3); - /* FIXME - handle put_user() failure */ - put_user_u32(off >> 32, args); - put_user_u32(off, args + 4); - put_user_u32(errno, args + 8); + m68k_semi_return_u64(env, off, errno); } return; } @@ -444,7 +461,5 @@ void do_m68k_semihosting(CPUM68KState *env, int nr) result = 0; } failed: - /* FIXME - handle put_user() failure */ - put_user_u32(result, args); - put_user_u32(errno, args + 4); + m68k_semi_return_u32(env, result, errno); } From 32761257c0b9fa7ee04d2871a6e48a41f119c469 Mon Sep 17 00:00:00 2001 From: Yeongkyoon Lee Date: Wed, 31 Oct 2012 16:04:23 +0900 Subject: [PATCH 263/291] configure: Add CONFIG_QEMU_LDST_OPTIMIZATION for TCG qemu_ld/st optimization Enable CONFIG_QEMU_LDST_OPTIMIZATION for TCG qemu_ld/st optimization only when a host is i386 or x86_64. Signed-off-by: Yeongkyoon Lee Signed-off-by: Blue Swirl --- configure | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/configure b/configure index ba99f67dd5..8e70cbb224 100755 --- a/configure +++ b/configure @@ -3881,6 +3881,12 @@ upper() { echo "$@"| LC_ALL=C tr '[a-z]' '[A-Z]' } +case "$cpu" in + i386|x86_64) + echo "CONFIG_QEMU_LDST_OPTIMIZATION=y" >> $config_target_mak + ;; +esac + echo "TARGET_SHORT_ALIGNMENT=$target_short_alignment" >> $config_target_mak echo "TARGET_INT_ALIGNMENT=$target_int_alignment" >> $config_target_mak echo "TARGET_LONG_ALIGNMENT=$target_long_alignment" >> $config_target_mak From fdbb84d1332ae0827d60f1a2ca03c7d5678c6edd Mon Sep 17 00:00:00 2001 From: Yeongkyoon Lee Date: Wed, 31 Oct 2012 16:04:24 +0900 Subject: [PATCH 264/291] tcg: Add extended GETPC mechanism for MMU helpers with ldst optimization Add GETPC_EXT which is used by MMU helpers to selectively calculate the code address of accessing guest memory when called from a qemu_ld/st optimized code or a C function. Currently, it supports only i386 and x86-64 hosts. Signed-off-by: Yeongkyoon Lee Signed-off-by: Blue Swirl --- exec-all.h | 36 ++++++++++++++++++++++++++++++++++++ exec.c | 11 +++++++++++ softmmu_template.h | 16 ++++++++-------- 3 files changed, 55 insertions(+), 8 deletions(-) diff --git a/exec-all.h b/exec-all.h index 2ea0e4fc24..ad6d22b6c5 100644 --- a/exec-all.h +++ b/exec-all.h @@ -310,6 +310,42 @@ extern uintptr_t tci_tb_ptr; # define GETPC() ((uintptr_t)__builtin_return_address(0) - 1) #endif +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU) +/* qemu_ld/st optimization split code generation to fast and slow path, thus, + it needs special handling for an MMU helper which is called from the slow + path, to get the fast path's pc without any additional argument. + It uses a tricky solution which embeds the fast path pc into the slow path. + + Code flow in slow path: + (1) pre-process + (2) call MMU helper + (3) jump to (5) + (4) fast path information (implementation specific) + (5) post-process (e.g. stack adjust) + (6) jump to corresponding code of the next of fast path + */ +# if defined(__i386__) || defined(__x86_64__) +/* To avoid broken disassembling, long jmp is used for embedding fast path pc, + so that the destination is the next code of fast path, though this jmp is + never executed. + + call MMU helper + jmp POST_PROC (2byte) <- GETRA() + jmp NEXT_CODE (5byte) + POST_PROCESS ... <- GETRA() + 7 + */ +# define GETRA() ((uintptr_t)__builtin_return_address(0)) +# define GETPC_LDST() ((uintptr_t)(GETRA() + 7 + \ + *(int32_t *)((void *)GETRA() + 3) - 1)) +# else +# error "CONFIG_QEMU_LDST_OPTIMIZATION needs GETPC_LDST() implementation!" +# endif +bool is_tcg_gen_code(uintptr_t pc_ptr); +# define GETPC_EXT() (is_tcg_gen_code(GETRA()) ? GETPC_LDST() : GETPC()) +#else +# define GETPC_EXT() GETPC() +#endif + #if !defined(CONFIG_USER_ONLY) struct MemoryRegion *iotlb_to_region(hwaddr index); diff --git a/exec.c b/exec.c index df6793812f..8bff743a62 100644 --- a/exec.c +++ b/exec.c @@ -1390,6 +1390,17 @@ void tb_link_page(TranslationBlock *tb, mmap_unlock(); } +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU) +/* check whether the given addr is in TCG generated code buffer or not */ +bool is_tcg_gen_code(uintptr_t tc_ptr) +{ + /* This can be called during code generation, code_gen_buffer_max_size + is used instead of code_gen_ptr for upper boundary checking */ + return (tc_ptr >= (uintptr_t)code_gen_buffer && + tc_ptr < (uintptr_t)(code_gen_buffer + code_gen_buffer_max_size)); +} +#endif + /* find the TB 'tb' such that tb[0].tc_ptr <= tc_ptr < tb[1].tc_ptr. Return NULL if not found */ TranslationBlock *tb_find_pc(uintptr_t tc_ptr) diff --git a/softmmu_template.h b/softmmu_template.h index 20d6baba68..ce30d8bddc 100644 --- a/softmmu_template.h +++ b/softmmu_template.h @@ -111,13 +111,13 @@ glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr, /* IO access */ if ((addr & (DATA_SIZE - 1)) != 0) goto do_unaligned_access; - retaddr = GETPC(); + retaddr = GETPC_EXT(); ioaddr = env->iotlb[mmu_idx][index]; res = glue(io_read, SUFFIX)(env, ioaddr, addr, retaddr); } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { /* slow unaligned access (it spans two pages or IO) */ do_unaligned_access: - retaddr = GETPC(); + retaddr = GETPC_EXT(); #ifdef ALIGNED_ONLY do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); #endif @@ -128,7 +128,7 @@ glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr, uintptr_t addend; #ifdef ALIGNED_ONLY if ((addr & (DATA_SIZE - 1)) != 0) { - retaddr = GETPC(); + retaddr = GETPC_EXT(); do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } #endif @@ -138,7 +138,7 @@ glue(glue(helper_ld, SUFFIX), MMUSUFFIX)(CPUArchState *env, target_ulong addr, } } else { /* the page is not in the TLB : fill it */ - retaddr = GETPC(); + retaddr = GETPC_EXT(); #ifdef ALIGNED_ONLY if ((addr & (DATA_SIZE - 1)) != 0) do_unaligned_access(env, addr, READ_ACCESS_TYPE, mmu_idx, retaddr); @@ -257,12 +257,12 @@ void glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, /* IO access */ if ((addr & (DATA_SIZE - 1)) != 0) goto do_unaligned_access; - retaddr = GETPC(); + retaddr = GETPC_EXT(); ioaddr = env->iotlb[mmu_idx][index]; glue(io_write, SUFFIX)(env, ioaddr, val, addr, retaddr); } else if (((addr & ~TARGET_PAGE_MASK) + DATA_SIZE - 1) >= TARGET_PAGE_SIZE) { do_unaligned_access: - retaddr = GETPC(); + retaddr = GETPC_EXT(); #ifdef ALIGNED_ONLY do_unaligned_access(env, addr, 1, mmu_idx, retaddr); #endif @@ -273,7 +273,7 @@ void glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, uintptr_t addend; #ifdef ALIGNED_ONLY if ((addr & (DATA_SIZE - 1)) != 0) { - retaddr = GETPC(); + retaddr = GETPC_EXT(); do_unaligned_access(env, addr, 1, mmu_idx, retaddr); } #endif @@ -283,7 +283,7 @@ void glue(glue(helper_st, SUFFIX), MMUSUFFIX)(CPUArchState *env, } } else { /* the page is not in the TLB : fill it */ - retaddr = GETPC(); + retaddr = GETPC_EXT(); #ifdef ALIGNED_ONLY if ((addr & (DATA_SIZE - 1)) != 0) do_unaligned_access(env, addr, 1, mmu_idx, retaddr); From b76f0d8c2e3eac94bc7fd90a510cb7426b2a2699 Mon Sep 17 00:00:00 2001 From: Yeongkyoon Lee Date: Wed, 31 Oct 2012 16:04:25 +0900 Subject: [PATCH 265/291] tcg: Optimize qemu_ld/st by generating slow paths at the end of a block Add optimized TCG qemu_ld/st generation which locates the code of TLB miss cases at the end of a block after generating the other IRs. Currently, this optimization supports only i386 and x86_64 hosts. Signed-off-by: Yeongkyoon Lee Signed-off-by: Blue Swirl --- tcg/i386/tcg-target.c | 440 ++++++++++++++++++++++++++++-------------- tcg/tcg.c | 12 ++ tcg/tcg.h | 30 +++ 3 files changed, 338 insertions(+), 144 deletions(-) diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index e45a5a0426..6f3ad3ceab 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -1002,6 +1002,17 @@ static const void *qemu_st_helpers[4] = { helper_stq_mmu, }; +static void add_qemu_ldst_label(TCGContext *s, + int is_ld, + int opc, + int data_reg, + int data_reg2, + int addrlo_reg, + int addrhi_reg, + int mem_index, + uint8_t *raddr, + uint8_t **label_ptr); + /* Perform the TLB load and compare. Inputs: @@ -1060,19 +1071,19 @@ static inline void tcg_out_tlb_load(TCGContext *s, int addrlo_idx, tcg_out_mov(s, type, r1, addrlo); - /* jne label1 */ - tcg_out8(s, OPC_JCC_short + JCC_JNE); + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); label_ptr[0] = s->code_ptr; - s->code_ptr++; + s->code_ptr += 4; if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { /* cmp 4(r0), addrhi */ tcg_out_modrm_offset(s, OPC_CMP_GvEv, args[addrlo_idx+1], r0, 4); - /* jne label1 */ - tcg_out8(s, OPC_JCC_short + JCC_JNE); + /* jne slow_path */ + tcg_out_opc(s, OPC_JCC_long + JCC_JNE, 0, 0, 0); label_ptr[1] = s->code_ptr; - s->code_ptr++; + s->code_ptr += 4; } /* TLB Hit. */ @@ -1193,10 +1204,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, int addrlo_idx; #if defined(CONFIG_SOFTMMU) int mem_index, s_bits; -#if TCG_TARGET_REG_BITS == 32 - int stack_adjust; -#endif - uint8_t *label_ptr[3]; + uint8_t *label_ptr[2]; #endif data_reg = args[0]; @@ -1216,87 +1224,17 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, /* TLB Hit. */ tcg_out_qemu_ld_direct(s, data_reg, data_reg2, TCG_REG_L1, 0, 0, opc); - /* jmp label2 */ - tcg_out8(s, OPC_JMP_short); - label_ptr[2] = s->code_ptr; - s->code_ptr++; - - /* TLB Miss. */ - - /* label1: */ - *label_ptr[0] = s->code_ptr - label_ptr[0] - 1; - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - *label_ptr[1] = s->code_ptr - label_ptr[1] - 1; - } - - /* XXX: move that code at the end of the TB */ -#if TCG_TARGET_REG_BITS == 32 - tcg_out_pushi(s, mem_index); - stack_adjust = 4; - if (TARGET_LONG_BITS == 64) { - tcg_out_push(s, args[addrlo_idx + 1]); - stack_adjust += 4; - } - tcg_out_push(s, args[addrlo_idx]); - stack_adjust += 4; - tcg_out_push(s, TCG_AREG0); - stack_adjust += 4; -#else - tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0], TCG_AREG0); - /* The second argument is already loaded with addrlo. */ - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], mem_index); -#endif - - tcg_out_calli(s, (tcg_target_long)qemu_ld_helpers[s_bits]); - -#if TCG_TARGET_REG_BITS == 32 - if (stack_adjust == (TCG_TARGET_REG_BITS / 8)) { - /* Pop and discard. This is 2 bytes smaller than the add. */ - tcg_out_pop(s, TCG_REG_ECX); - } else if (stack_adjust != 0) { - tcg_out_addi(s, TCG_REG_CALL_STACK, stack_adjust); - } -#endif - - switch(opc) { - case 0 | 4: - tcg_out_ext8s(s, data_reg, TCG_REG_EAX, P_REXW); - break; - case 1 | 4: - tcg_out_ext16s(s, data_reg, TCG_REG_EAX, P_REXW); - break; - case 0: - tcg_out_ext8u(s, data_reg, TCG_REG_EAX); - break; - case 1: - tcg_out_ext16u(s, data_reg, TCG_REG_EAX); - break; - case 2: - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - break; -#if TCG_TARGET_REG_BITS == 64 - case 2 | 4: - tcg_out_ext32s(s, data_reg, TCG_REG_EAX); - break; -#endif - case 3: - if (TCG_TARGET_REG_BITS == 64) { - tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); - } else if (data_reg == TCG_REG_EDX) { - /* xchg %edx, %eax */ - tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); - tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_EAX); - } else { - tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); - tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_EDX); - } - break; - default: - tcg_abort(); - } - - /* label2: */ - *label_ptr[2] = s->code_ptr - label_ptr[2] - 1; + /* Record the current context of a load into ldst label */ + add_qemu_ldst_label(s, + 1, + opc, + data_reg, + data_reg2, + args[addrlo_idx], + args[addrlo_idx + 1], + mem_index, + s->code_ptr, + label_ptr); #else { int32_t offset = GUEST_BASE; @@ -1393,8 +1331,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, int addrlo_idx; #if defined(CONFIG_SOFTMMU) int mem_index, s_bits; - int stack_adjust; - uint8_t *label_ptr[3]; + uint8_t *label_ptr[2]; #endif data_reg = args[0]; @@ -1414,57 +1351,17 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, /* TLB Hit. */ tcg_out_qemu_st_direct(s, data_reg, data_reg2, TCG_REG_L1, 0, 0, opc); - /* jmp label2 */ - tcg_out8(s, OPC_JMP_short); - label_ptr[2] = s->code_ptr; - s->code_ptr++; - - /* TLB Miss. */ - - /* label1: */ - *label_ptr[0] = s->code_ptr - label_ptr[0] - 1; - if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { - *label_ptr[1] = s->code_ptr - label_ptr[1] - 1; - } - - /* XXX: move that code at the end of the TB */ -#if TCG_TARGET_REG_BITS == 32 - tcg_out_pushi(s, mem_index); - stack_adjust = 4; - if (opc == 3) { - tcg_out_push(s, data_reg2); - stack_adjust += 4; - } - tcg_out_push(s, data_reg); - stack_adjust += 4; - if (TARGET_LONG_BITS == 64) { - tcg_out_push(s, args[addrlo_idx + 1]); - stack_adjust += 4; - } - tcg_out_push(s, args[addrlo_idx]); - stack_adjust += 4; - tcg_out_push(s, TCG_AREG0); - stack_adjust += 4; -#else - tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0], TCG_AREG0); - /* The second argument is already loaded with addrlo. */ - tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32), - tcg_target_call_iarg_regs[2], data_reg); - tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], mem_index); - stack_adjust = 0; -#endif - - tcg_out_calli(s, (tcg_target_long)qemu_st_helpers[s_bits]); - - if (stack_adjust == (TCG_TARGET_REG_BITS / 8)) { - /* Pop and discard. This is 2 bytes smaller than the add. */ - tcg_out_pop(s, TCG_REG_ECX); - } else if (stack_adjust != 0) { - tcg_out_addi(s, TCG_REG_CALL_STACK, stack_adjust); - } - - /* label2: */ - *label_ptr[2] = s->code_ptr - label_ptr[2] - 1; + /* Record the current context of a store into ldst label */ + add_qemu_ldst_label(s, + 0, + opc, + data_reg, + data_reg2, + args[addrlo_idx], + args[addrlo_idx + 1], + mem_index, + s->code_ptr, + label_ptr); #else { int32_t offset = GUEST_BASE; @@ -1491,6 +1388,261 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, #endif } +#if defined(CONFIG_SOFTMMU) +/* + * Record the context of a call to the out of line helper code for the slow path + * for a load or store, so that we can later generate the correct helper code + */ +static void add_qemu_ldst_label(TCGContext *s, + int is_ld, + int opc, + int data_reg, + int data_reg2, + int addrlo_reg, + int addrhi_reg, + int mem_index, + uint8_t *raddr, + uint8_t **label_ptr) +{ + int idx; + TCGLabelQemuLdst *label; + + if (s->nb_qemu_ldst_labels >= TCG_MAX_QEMU_LDST) { + tcg_abort(); + } + + idx = s->nb_qemu_ldst_labels++; + label = (TCGLabelQemuLdst *)&s->qemu_ldst_labels[idx]; + label->is_ld = is_ld; + label->opc = opc; + label->datalo_reg = data_reg; + label->datahi_reg = data_reg2; + label->addrlo_reg = addrlo_reg; + label->addrhi_reg = addrhi_reg; + label->mem_index = mem_index; + label->raddr = raddr; + label->label_ptr[0] = label_ptr[0]; + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + label->label_ptr[1] = label_ptr[1]; + } +} + +/* + * Generate code for the slow path for a load at the end of block + */ +static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *label) +{ + int s_bits; + int opc = label->opc; + int mem_index = label->mem_index; +#if TCG_TARGET_REG_BITS == 32 + int stack_adjust; + int addrlo_reg = label->addrlo_reg; + int addrhi_reg = label->addrhi_reg; +#endif + int data_reg = label->datalo_reg; + int data_reg2 = label->datahi_reg; + uint8_t *raddr = label->raddr; + uint8_t **label_ptr = &label->label_ptr[0]; + + s_bits = opc & 3; + + /* resolve label address */ + *(uint32_t *)label_ptr[0] = (uint32_t)(s->code_ptr - label_ptr[0] - 4); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + *(uint32_t *)label_ptr[1] = (uint32_t)(s->code_ptr - label_ptr[1] - 4); + } + +#if TCG_TARGET_REG_BITS == 32 + tcg_out_pushi(s, mem_index); + stack_adjust = 4; + if (TARGET_LONG_BITS == 64) { + tcg_out_push(s, addrhi_reg); + stack_adjust += 4; + } + tcg_out_push(s, addrlo_reg); + stack_adjust += 4; + tcg_out_push(s, TCG_AREG0); + stack_adjust += 4; +#else + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0], TCG_AREG0); + /* The second argument is already loaded with addrlo. */ + tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[2], mem_index); +#endif + + /* Code generation of qemu_ld/st's slow path calling MMU helper + + PRE_PROC ... + call MMU helper + jmp POST_PROC (2b) : short forward jump <- GETRA() + jmp next_code (5b) : dummy long backward jump which is never executed + POST_PROC ... : do post-processing <- GETRA() + 7 + jmp next_code : jump to the code corresponding to next IR of qemu_ld/st + */ + + tcg_out_calli(s, (tcg_target_long)qemu_ld_helpers[s_bits]); + + /* Jump to post-processing code */ + tcg_out8(s, OPC_JMP_short); + tcg_out8(s, 5); + /* Dummy backward jump having information of fast path'pc for MMU helpers */ + tcg_out8(s, OPC_JMP_long); + *(int32_t *)s->code_ptr = (int32_t)(raddr - s->code_ptr - 4); + s->code_ptr += 4; + +#if TCG_TARGET_REG_BITS == 32 + if (stack_adjust == (TCG_TARGET_REG_BITS / 8)) { + /* Pop and discard. This is 2 bytes smaller than the add. */ + tcg_out_pop(s, TCG_REG_ECX); + } else if (stack_adjust != 0) { + tcg_out_addi(s, TCG_REG_CALL_STACK, stack_adjust); + } +#endif + + switch(opc) { + case 0 | 4: + tcg_out_ext8s(s, data_reg, TCG_REG_EAX, P_REXW); + break; + case 1 | 4: + tcg_out_ext16s(s, data_reg, TCG_REG_EAX, P_REXW); + break; + case 0: + tcg_out_ext8u(s, data_reg, TCG_REG_EAX); + break; + case 1: + tcg_out_ext16u(s, data_reg, TCG_REG_EAX); + break; + case 2: + tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); + break; +#if TCG_TARGET_REG_BITS == 64 + case 2 | 4: + tcg_out_ext32s(s, data_reg, TCG_REG_EAX); + break; +#endif + case 3: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_mov(s, TCG_TYPE_I64, data_reg, TCG_REG_RAX); + } else if (data_reg == TCG_REG_EDX) { + /* xchg %edx, %eax */ + tcg_out_opc(s, OPC_XCHG_ax_r32 + TCG_REG_EDX, 0, 0, 0); + tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_EAX); + } else { + tcg_out_mov(s, TCG_TYPE_I32, data_reg, TCG_REG_EAX); + tcg_out_mov(s, TCG_TYPE_I32, data_reg2, TCG_REG_EDX); + } + break; + default: + tcg_abort(); + } + + /* Jump to the code corresponding to next IR of qemu_st */ + tcg_out_jmp(s, (tcg_target_long)raddr); +} + +/* + * Generate code for the slow path for a store at the end of block + */ +static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *label) +{ + int s_bits; + int stack_adjust; + int opc = label->opc; + int mem_index = label->mem_index; + int data_reg = label->datalo_reg; +#if TCG_TARGET_REG_BITS == 32 + int data_reg2 = label->datahi_reg; + int addrlo_reg = label->addrlo_reg; + int addrhi_reg = label->addrhi_reg; +#endif + uint8_t *raddr = label->raddr; + uint8_t **label_ptr = &label->label_ptr[0]; + + s_bits = opc & 3; + + /* resolve label address */ + *(uint32_t *)label_ptr[0] = (uint32_t)(s->code_ptr - label_ptr[0] - 4); + if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) { + *(uint32_t *)label_ptr[1] = (uint32_t)(s->code_ptr - label_ptr[1] - 4); + } + +#if TCG_TARGET_REG_BITS == 32 + tcg_out_pushi(s, mem_index); + stack_adjust = 4; + if (opc == 3) { + tcg_out_push(s, data_reg2); + stack_adjust += 4; + } + tcg_out_push(s, data_reg); + stack_adjust += 4; + if (TARGET_LONG_BITS == 64) { + tcg_out_push(s, addrhi_reg); + stack_adjust += 4; + } + tcg_out_push(s, addrlo_reg); + stack_adjust += 4; + tcg_out_push(s, TCG_AREG0); + stack_adjust += 4; +#else + tcg_out_mov(s, TCG_TYPE_I64, tcg_target_call_iarg_regs[0], TCG_AREG0); + /* The second argument is already loaded with addrlo. */ + tcg_out_mov(s, (opc == 3 ? TCG_TYPE_I64 : TCG_TYPE_I32), + tcg_target_call_iarg_regs[2], data_reg); + tcg_out_movi(s, TCG_TYPE_I32, tcg_target_call_iarg_regs[3], mem_index); + stack_adjust = 0; +#endif + + /* Code generation of qemu_ld/st's slow path calling MMU helper + + PRE_PROC ... + call MMU helper + jmp POST_PROC (2b) : short forward jump <- GETRA() + jmp next_code (5b) : dummy long backward jump which is never executed + POST_PROC ... : do post-processing <- GETRA() + 7 + jmp next_code : jump to the code corresponding to next IR of qemu_ld/st + */ + + tcg_out_calli(s, (tcg_target_long)qemu_st_helpers[s_bits]); + + /* Jump to post-processing code */ + tcg_out8(s, OPC_JMP_short); + tcg_out8(s, 5); + /* Dummy backward jump having information of fast path'pc for MMU helpers */ + tcg_out8(s, OPC_JMP_long); + *(int32_t *)s->code_ptr = (int32_t)(raddr - s->code_ptr - 4); + s->code_ptr += 4; + + if (stack_adjust == (TCG_TARGET_REG_BITS / 8)) { + /* Pop and discard. This is 2 bytes smaller than the add. */ + tcg_out_pop(s, TCG_REG_ECX); + } else if (stack_adjust != 0) { + tcg_out_addi(s, TCG_REG_CALL_STACK, stack_adjust); + } + + /* Jump to the code corresponding to next IR of qemu_st */ + tcg_out_jmp(s, (tcg_target_long)raddr); +} + +/* + * Generate TB finalization at the end of block + */ +void tcg_out_tb_finalize(TCGContext *s) +{ + int i; + TCGLabelQemuLdst *label; + + /* qemu_ld/st slow paths */ + for (i = 0; i < s->nb_qemu_ldst_labels; i++) { + label = (TCGLabelQemuLdst *)&s->qemu_ldst_labels[i]; + if (label->is_ld) { + tcg_out_qemu_ld_slow_path(s, label); + } else { + tcg_out_qemu_st_slow_path(s, label); + } + } +} +#endif /* CONFIG_SOFTMMU */ + static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args, const int *const_args) { diff --git a/tcg/tcg.c b/tcg/tcg.c index 11334387a0..42052dba7b 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -299,6 +299,14 @@ void tcg_func_start(TCGContext *s) gen_opc_ptr = gen_opc_buf; gen_opparam_ptr = gen_opparam_buf; + +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU) + /* Initialize qemu_ld/st labels to assist code generation at the end of TB + for TLB miss cases at the end of TB */ + s->qemu_ldst_labels = tcg_malloc(sizeof(TCGLabelQemuLdst) * + TCG_MAX_QEMU_LDST); + s->nb_qemu_ldst_labels = 0; +#endif } static inline void tcg_temp_alloc(TCGContext *s, int n) @@ -2314,6 +2322,10 @@ static inline int tcg_gen_code_common(TCGContext *s, uint8_t *gen_code_buf, #endif } the_end: +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU) + /* Generate TB finalization at the end of block */ + tcg_out_tb_finalize(s); +#endif return -1; } diff --git a/tcg/tcg.h b/tcg/tcg.h index a6c9256f8b..c2ae873715 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -188,6 +188,24 @@ typedef tcg_target_ulong TCGArg; are aliases for target_ulong and host pointer sized values respectively. */ +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU) +/* Macros/structures for qemu_ld/st IR code optimization: + TCG_MAX_HELPER_LABELS is defined as same as OPC_BUF_SIZE in exec-all.h. */ +#define TCG_MAX_QEMU_LDST 640 + +typedef struct TCGLabelQemuLdst { + int is_ld:1; /* qemu_ld: 1, qemu_st: 0 */ + int opc:4; + int addrlo_reg; /* reg index for low word of guest virtual addr */ + int addrhi_reg; /* reg index for high word of guest virtual addr */ + int datalo_reg; /* reg index for low word to be loaded or stored */ + int datahi_reg; /* reg index for high word to be loaded or stored */ + int mem_index; /* soft MMU memory index */ + uint8_t *raddr; /* gen code addr of the next IR of qemu_ld/st IR */ + uint8_t *label_ptr[2]; /* label pointers to be updated */ +} TCGLabelQemuLdst; +#endif + #ifdef CONFIG_DEBUG_TCG #define DEBUG_TCGV 1 #endif @@ -431,6 +449,13 @@ struct TCGContext { int temps_in_use; int goto_tb_issue_mask; #endif + +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU) + /* labels info for qemu_ld/st IRs + The labels help to generate TLB miss case codes at the end of TB */ + TCGLabelQemuLdst *qemu_ldst_labels; + int nb_qemu_ldst_labels; +#endif }; extern TCGContext tcg_ctx; @@ -634,3 +659,8 @@ extern uint8_t *code_gen_prologue; #endif void tcg_register_jit(void *buf, size_t buf_size); + +#if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU) +/* Generate TB finalization at the end of block */ +void tcg_out_tb_finalize(TCGContext *s); +#endif From 0d7937974cd0504f30ad483c3368b21da426ddf9 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sat, 3 Nov 2012 12:47:08 +0100 Subject: [PATCH 266/291] vmware_vga: Coding style cleanup Fix coding style as suggested by checkpatch.pl Signed-off-by: BALATON Zoltan Signed-off-by: Blue Swirl --- hw/vmware_vga.c | 272 ++++++++++++++++++++++++++---------------------- 1 file changed, 149 insertions(+), 123 deletions(-) diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index 34532e5c3a..bf14e788d2 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -79,7 +79,7 @@ struct vmsvga_state_s { } *cmd; }; -#define REDRAW_FIFO_LEN 512 +#define REDRAW_FIFO_LEN 512 struct vmsvga_rect_s { int x, y, w, h; } redraw_fifo[REDRAW_FIFO_LEN]; @@ -92,31 +92,31 @@ struct pci_vmsvga_state_s { MemoryRegion io_bar; }; -#define SVGA_MAGIC 0x900000UL -#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) -#define SVGA_ID_0 SVGA_MAKE_ID(0) -#define SVGA_ID_1 SVGA_MAKE_ID(1) -#define SVGA_ID_2 SVGA_MAKE_ID(2) +#define SVGA_MAGIC 0x900000UL +#define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver)) +#define SVGA_ID_0 SVGA_MAKE_ID(0) +#define SVGA_ID_1 SVGA_MAKE_ID(1) +#define SVGA_ID_2 SVGA_MAKE_ID(2) -#define SVGA_LEGACY_BASE_PORT 0x4560 -#define SVGA_INDEX_PORT 0x0 -#define SVGA_VALUE_PORT 0x1 -#define SVGA_BIOS_PORT 0x2 +#define SVGA_LEGACY_BASE_PORT 0x4560 +#define SVGA_INDEX_PORT 0x0 +#define SVGA_VALUE_PORT 0x1 +#define SVGA_BIOS_PORT 0x2 #define SVGA_VERSION_2 #ifdef SVGA_VERSION_2 -# define SVGA_ID SVGA_ID_2 -# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT -# define SVGA_IO_MUL 1 -# define SVGA_FIFO_SIZE 0x10000 -# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 +# define SVGA_ID SVGA_ID_2 +# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT +# define SVGA_IO_MUL 1 +# define SVGA_FIFO_SIZE 0x10000 +# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2 #else -# define SVGA_ID SVGA_ID_1 -# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT -# define SVGA_IO_MUL 4 -# define SVGA_FIFO_SIZE 0x10000 -# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA +# define SVGA_ID SVGA_ID_1 +# define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT +# define SVGA_IO_MUL 4 +# define SVGA_FIFO_SIZE 0x10000 +# define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA #endif enum { @@ -128,7 +128,7 @@ enum { SVGA_REG_MAX_WIDTH = 4, SVGA_REG_MAX_HEIGHT = 5, SVGA_REG_DEPTH = 6, - SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ + SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */ SVGA_REG_PSEUDOCOLOR = 8, SVGA_REG_RED_MASK = 9, SVGA_REG_GREEN_MASK = 10, @@ -141,46 +141,46 @@ enum { /* ID 1 and 2 registers */ SVGA_REG_CAPABILITIES = 17, - SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ + SVGA_REG_MEM_START = 18, /* Memory for command FIFO */ SVGA_REG_MEM_SIZE = 19, - SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ - SVGA_REG_SYNC = 21, /* Write to force synchronization */ - SVGA_REG_BUSY = 22, /* Read to check if sync is done */ - SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ - SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ - SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ - SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ - SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ - SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ - SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ - SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ - SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ - SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ + SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */ + SVGA_REG_SYNC = 21, /* Write to force synchronization */ + SVGA_REG_BUSY = 22, /* Read to check if sync is done */ + SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */ + SVGA_REG_CURSOR_ID = 24, /* ID of cursor */ + SVGA_REG_CURSOR_X = 25, /* Set cursor X position */ + SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */ + SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */ + SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */ + SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */ + SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */ + SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */ + SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */ - SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ + SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */ SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767, SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768, }; -#define SVGA_CAP_NONE 0 -#define SVGA_CAP_RECT_FILL (1 << 0) -#define SVGA_CAP_RECT_COPY (1 << 1) -#define SVGA_CAP_RECT_PAT_FILL (1 << 2) -#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) -#define SVGA_CAP_RASTER_OP (1 << 4) -#define SVGA_CAP_CURSOR (1 << 5) -#define SVGA_CAP_CURSOR_BYPASS (1 << 6) -#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) -#define SVGA_CAP_8BIT_EMULATION (1 << 8) -#define SVGA_CAP_ALPHA_CURSOR (1 << 9) -#define SVGA_CAP_GLYPH (1 << 10) -#define SVGA_CAP_GLYPH_CLIPPING (1 << 11) -#define SVGA_CAP_OFFSCREEN_1 (1 << 12) -#define SVGA_CAP_ALPHA_BLEND (1 << 13) -#define SVGA_CAP_3D (1 << 14) -#define SVGA_CAP_EXTENDED_FIFO (1 << 15) -#define SVGA_CAP_MULTIMON (1 << 16) -#define SVGA_CAP_PITCHLOCK (1 << 17) +#define SVGA_CAP_NONE 0 +#define SVGA_CAP_RECT_FILL (1 << 0) +#define SVGA_CAP_RECT_COPY (1 << 1) +#define SVGA_CAP_RECT_PAT_FILL (1 << 2) +#define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3) +#define SVGA_CAP_RASTER_OP (1 << 4) +#define SVGA_CAP_CURSOR (1 << 5) +#define SVGA_CAP_CURSOR_BYPASS (1 << 6) +#define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7) +#define SVGA_CAP_8BIT_EMULATION (1 << 8) +#define SVGA_CAP_ALPHA_CURSOR (1 << 9) +#define SVGA_CAP_GLYPH (1 << 10) +#define SVGA_CAP_GLYPH_CLIPPING (1 << 11) +#define SVGA_CAP_OFFSCREEN_1 (1 << 12) +#define SVGA_CAP_ALPHA_BLEND (1 << 13) +#define SVGA_CAP_3D (1 << 14) +#define SVGA_CAP_EXTENDED_FIFO (1 << 15) +#define SVGA_CAP_MULTIMON (1 << 16) +#define SVGA_CAP_PITCHLOCK (1 << 17) /* * FIFO offsets (seen as an array of 32-bit words) @@ -190,7 +190,7 @@ enum { * The original defined FIFO offsets */ SVGA_FIFO_MIN = 0, - SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ + SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */ SVGA_FIFO_NEXT_CMD, SVGA_FIFO_STOP, @@ -204,21 +204,21 @@ enum { SVGA_FIFO_PITCHLOCK, }; -#define SVGA_FIFO_CAP_NONE 0 -#define SVGA_FIFO_CAP_FENCE (1 << 0) -#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) -#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) +#define SVGA_FIFO_CAP_NONE 0 +#define SVGA_FIFO_CAP_FENCE (1 << 0) +#define SVGA_FIFO_CAP_ACCELFRONT (1 << 1) +#define SVGA_FIFO_CAP_PITCHLOCK (1 << 2) -#define SVGA_FIFO_FLAG_NONE 0 -#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) +#define SVGA_FIFO_FLAG_NONE 0 +#define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0) /* These values can probably be changed arbitrarily. */ -#define SVGA_SCRATCH_SIZE 0x8000 -#define SVGA_MAX_WIDTH 2360 -#define SVGA_MAX_HEIGHT 1770 +#define SVGA_SCRATCH_SIZE 0x8000 +#define SVGA_MAX_WIDTH 2360 +#define SVGA_MAX_HEIGHT 1770 #ifdef VERBOSE -# define GUEST_OS_BASE 0x5001 +# define GUEST_OS_BASE 0x5001 static const char *vmsvga_guest_id[] = { [0x00] = "Dos", [0x01] = "Windows 3.1", @@ -299,28 +299,27 @@ static inline void vmsvga_update_rect(struct vmsvga_state_s *s, if (x + w > s->width) { fprintf(stderr, "%s: update width too large x: %d, w: %d\n", - __FUNCTION__, x, w); + __func__, x, w); x = MIN(x, s->width); w = s->width - x; } if (y + h > s->height) { fprintf(stderr, "%s: update height too large y: %d, h: %d\n", - __FUNCTION__, y, h); + __func__, y, h); y = MIN(y, s->height); h = s->height - y; } - line = h; bypl = s->bypp * s->width; width = s->bypp * w; start = s->bypp * x + bypl * y; src = s->vga.vram_ptr + start; dst = ds_get_data(s->vga.ds) + start; - for (; line > 0; line --, src += bypl, dst += bypl) + for (line = h; line > 0; line--, src += bypl, dst += bypl) { memcpy(dst, src, width); - + } dpy_gfx_update(s->vga.ds, x, y, w, h); } @@ -334,7 +333,8 @@ static inline void vmsvga_update_screen(struct vmsvga_state_s *s) static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, int x, int y, int w, int h) { - struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++]; + struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last++]; + s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1; rect->x = x; rect->y = y; @@ -345,6 +345,7 @@ static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) { struct vmsvga_rect_s *rect; + if (s->invalidated) { s->redraw_fifo_first = s->redraw_fifo_last; return; @@ -352,7 +353,7 @@ static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s) /* Overlapping region updates can be optimised out here - if someone * knows a smart algorithm to do that, please share. */ while (s->redraw_fifo_first != s->redraw_fifo_last) { - rect = &s->redraw_fifo[s->redraw_fifo_first ++]; + rect = &s->redraw_fifo[s->redraw_fifo_first++]; s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1; vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h); } @@ -437,8 +438,8 @@ struct vmsvga_cursor_definition_s { uint32_t image[4096]; }; -#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) -#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) +#define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h)) +#define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h)) #ifdef HW_MOUSE_ACCEL static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, @@ -452,16 +453,16 @@ static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, qc->hot_y = c->hot_y; switch (c->bpp) { case 1: - cursor_set_mono(qc, 0xffffff, 0x000000, (void*)c->image, - 1, (void*)c->mask); + cursor_set_mono(qc, 0xffffff, 0x000000, (void *)c->image, + 1, (void *)c->mask); #ifdef DEBUG cursor_print_ascii_art(qc, "vmware/mono"); #endif break; case 32: /* fill alpha channel from mask, set color to zero */ - cursor_set_mono(qc, 0x000000, 0x000000, (void*)c->mask, - 1, (void*)c->mask); + cursor_set_mono(qc, 0x000000, 0x000000, (void *)c->mask, + 1, (void *)c->mask); /* add in rgb values */ pixels = c->width * c->height; for (i = 0; i < pixels; i++) { @@ -473,7 +474,7 @@ static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, break; default: fprintf(stderr, "%s: unhandled bpp %d, using fallback cursor\n", - __FUNCTION__, c->bpp); + __func__, c->bpp); cursor_put(qc); qc = cursor_builtin_left_ptr(); } @@ -483,25 +484,30 @@ static inline void vmsvga_cursor_define(struct vmsvga_state_s *s, } #endif -#define CMD(f) le32_to_cpu(s->cmd->f) +#define CMD(f) le32_to_cpu(s->cmd->f) static inline int vmsvga_fifo_length(struct vmsvga_state_s *s) { int num; - if (!s->config || !s->enable) + + if (!s->config || !s->enable) { return 0; + } num = CMD(next_cmd) - CMD(stop); - if (num < 0) + if (num < 0) { num += CMD(max) - CMD(min); + } return num >> 2; } static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s) { uint32_t cmd = s->fifo[CMD(stop) >> 2]; + s->cmd->stop = cpu_to_le32(CMD(stop) + 4); - if (CMD(stop) >= CMD(max)) + if (CMD(stop) >= CMD(max)) { s->cmd->stop = s->cmd->min; + } return cmd; } @@ -527,8 +533,9 @@ static void vmsvga_fifo_run(struct vmsvga_state_s *s) case SVGA_CMD_UPDATE: case SVGA_CMD_UPDATE_VERBOSE: len -= 5; - if (len < 0) + if (len < 0) { goto rewind; + } x = vmsvga_fifo_read(s); y = vmsvga_fifo_read(s); @@ -539,8 +546,9 @@ static void vmsvga_fifo_run(struct vmsvga_state_s *s) case SVGA_CMD_RECT_FILL: len -= 6; - if (len < 0) + if (len < 0) { goto rewind; + } colour = vmsvga_fifo_read(s); x = vmsvga_fifo_read(s); @@ -557,8 +565,9 @@ static void vmsvga_fifo_run(struct vmsvga_state_s *s) case SVGA_CMD_RECT_COPY: len -= 7; - if (len < 0) + if (len < 0) { goto rewind; + } x = vmsvga_fifo_read(s); y = vmsvga_fifo_read(s); @@ -576,8 +585,9 @@ static void vmsvga_fifo_run(struct vmsvga_state_s *s) case SVGA_CMD_DEFINE_CURSOR: len -= 8; - if (len < 0) + if (len < 0) { goto rewind; + } cursor.id = vmsvga_fifo_read(s); cursor.hot_x = vmsvga_fifo_read(s); @@ -589,17 +599,21 @@ static void vmsvga_fifo_run(struct vmsvga_state_s *s) args = SVGA_BITMAP_SIZE(x, y) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp); if (SVGA_BITMAP_SIZE(x, y) > sizeof cursor.mask || - SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) + SVGA_PIXMAP_SIZE(x, y, cursor.bpp) > sizeof cursor.image) { goto badcmd; + } len -= args; - if (len < 0) + if (len < 0) { goto rewind; + } - for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++) + for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args++) { cursor.mask[args] = vmsvga_fifo_read_raw(s); - for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++) + } + for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args++) { cursor.image[args] = vmsvga_fifo_read_raw(s); + } #ifdef HW_MOUSE_ACCEL vmsvga_cursor_define(s, &cursor); break; @@ -614,9 +628,9 @@ static void vmsvga_fifo_run(struct vmsvga_state_s *s) */ case SVGA_CMD_DEFINE_ALPHA_CURSOR: len -= 6; - if (len < 0) + if (len < 0) { goto rewind; - + } vmsvga_fifo_read(s); vmsvga_fifo_read(s); vmsvga_fifo_read(s); @@ -632,9 +646,9 @@ static void vmsvga_fifo_run(struct vmsvga_state_s *s) goto badcmd; case SVGA_CMD_DRAW_GLYPH_CLIPPED: len -= 4; - if (len < 0) + if (len < 0) { goto rewind; - + } vmsvga_fifo_read(s); vmsvga_fifo_read(s); args = 7 + (vmsvga_fifo_read(s) >> 2); @@ -658,12 +672,14 @@ static void vmsvga_fifo_run(struct vmsvga_state_s *s) args = 0; badcmd: len -= args; - if (len < 0) + if (len < 0) { goto rewind; - while (args --) + } + while (args--) { vmsvga_fifo_read(s); + } printf("%s: Unknown command 0x%02x in SVGA command FIFO\n", - __FUNCTION__, cmd); + __func__, cmd); break; rewind: @@ -678,12 +694,14 @@ static void vmsvga_fifo_run(struct vmsvga_state_s *s) static uint32_t vmsvga_index_read(void *opaque, uint32_t address) { struct vmsvga_state_s *s = opaque; + return s->index; } static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index) { struct vmsvga_state_s *s = opaque; + s->index = index; } @@ -691,6 +709,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) { uint32_t caps; struct vmsvga_state_s *s = opaque; + switch (s->index) { case SVGA_REG_ID: return s->svgaid; @@ -805,9 +824,10 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) default: if (s->index >= SVGA_SCRATCH_BASE && - s->index < SVGA_SCRATCH_BASE + s->scratch_size) + s->index < SVGA_SCRATCH_BASE + s->scratch_size) { return s->scratch[s->index - SVGA_SCRATCH_BASE]; - printf("%s: Bad register %02x\n", __FUNCTION__, s->index); + } + printf("%s: Bad register %02x\n", __func__, s->index); } return 0; @@ -816,10 +836,12 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) { struct vmsvga_state_s *s = opaque; + switch (s->index) { case SVGA_REG_ID: - if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) + if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0) { s->svgaid = value; + } break; case SVGA_REG_ENABLE: @@ -850,7 +872,7 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) case SVGA_REG_DEPTH: case SVGA_REG_BITS_PER_PIXEL: if (value != s->depth) { - printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value); + printf("%s: Bad colour depth: %i bits\n", __func__, value); s->config = 0; } break; @@ -859,15 +881,18 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) if (value) { s->fifo = (uint32_t *) s->fifo_ptr; /* Check range and alignment. */ - if ((CMD(min) | CMD(max) | - CMD(next_cmd) | CMD(stop)) & 3) + if ((CMD(min) | CMD(max) | CMD(next_cmd) | CMD(stop)) & 3) { break; - if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) + } + if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo) { break; - if (CMD(max) > SVGA_FIFO_SIZE) + } + if (CMD(max) > SVGA_FIFO_SIZE) { break; - if (CMD(max) < CMD(min) + 10 * 1024) + } + if (CMD(max) < CMD(min) + 10 * 1024) { break; + } } s->config = !!value; break; @@ -881,9 +906,10 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) s->guest = value; #ifdef VERBOSE if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE + - ARRAY_SIZE(vmsvga_guest_id)) - printf("%s: guest runs %s.\n", __FUNCTION__, - vmsvga_guest_id[value - GUEST_OS_BASE]); + ARRAY_SIZE(vmsvga_guest_id)) { + printf("%s: guest runs %s.\n", __func__, + vmsvga_guest_id[value - GUEST_OS_BASE]); + } #endif break; @@ -921,20 +947,19 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) s->scratch[s->index - SVGA_SCRATCH_BASE] = value; break; } - printf("%s: Bad register %02x\n", __FUNCTION__, s->index); + printf("%s: Bad register %02x\n", __func__, s->index); } } static uint32_t vmsvga_bios_read(void *opaque, uint32_t address) { - printf("%s: what are we supposed to return?\n", __FUNCTION__); + printf("%s: what are we supposed to return?\n", __func__); return 0xcafe; } static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) { - printf("%s: what are we supposed to do with (%08x)?\n", - __FUNCTION__, data); + printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); } static inline void vmsvga_size(struct vmsvga_state_s *s) @@ -1024,8 +1049,9 @@ static void vmsvga_text_update(void *opaque, console_ch_t *chardata) { struct vmsvga_state_s *s = opaque; - if (s->vga.text_update) + if (s->vga.text_update) { s->vga.text_update(&s->vga, chardata); + } } static int vmsvga_post_load(void *opaque, int version_id) @@ -1033,9 +1059,9 @@ static int vmsvga_post_load(void *opaque, int version_id) struct vmsvga_state_s *s = opaque; s->invalidated = 1; - if (s->config) + if (s->config) { s->fifo = (uint32_t *) s->fifo_ptr; - + } return 0; } @@ -1045,7 +1071,7 @@ static const VMStateDescription vmstate_vmware_vga_internal = { .minimum_version_id = 0, .minimum_version_id_old = 0, .post_load = vmsvga_post_load, - .fields = (VMStateField []) { + .fields = (VMStateField[]) { VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s), VMSTATE_INT32(enable, struct vmsvga_state_s), VMSTATE_INT32(config, struct vmsvga_state_s), @@ -1071,7 +1097,7 @@ static const VMStateDescription vmstate_vmware_vga = { .version_id = 0, .minimum_version_id = 0, .minimum_version_id_old = 0, - .fields = (VMStateField []) { + .fields = (VMStateField[]) { VMSTATE_PCI_DEVICE(card, struct pci_vmsvga_state_s), VMSTATE_STRUCT(chip, struct pci_vmsvga_state_s, 0, vmstate_vmware_vga_internal, struct vmsvga_state_s), @@ -1180,9 +1206,9 @@ static int pci_vmsvga_initfn(PCIDevice *dev) iomem = &s->chip.vga.vram; - s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ - s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ - s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */ + s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ + s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ + s->card.config[PCI_INTERRUPT_LINE] = 0xff; /* End */ memory_region_init_io(&s->io_bar, &vmsvga_io_ops, &s->chip, "vmsvga-io", 0x10); From aa32b38c5b2eb1afe30b3292454411bb760a432d Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sat, 3 Nov 2012 12:47:08 +0100 Subject: [PATCH 267/291] vmware_vga: Remove duplicated info from local state Removed info from vmsvga_state that is available from elsewhere and thus was duplicated here unnecessarily. Signed-off-by: BALATON Zoltan Signed-off-by: Blue Swirl --- console.h | 20 ++++++ hw/vmware_vga.c | 159 ++++++++++++++++++++---------------------------- 2 files changed, 85 insertions(+), 94 deletions(-) diff --git a/console.h b/console.h index 0df033d674..70c9a55942 100644 --- a/console.h +++ b/console.h @@ -377,6 +377,26 @@ static inline pixman_format_code_t ds_get_format(DisplayState *ds) return ds->surface->format; } +static inline int ds_get_depth(DisplayState *ds) +{ + return ds->surface->pf.depth; +} + +static inline int ds_get_rmask(DisplayState *ds) +{ + return ds->surface->pf.rmask; +} + +static inline int ds_get_gmask(DisplayState *ds) +{ + return ds->surface->pf.gmask; +} + +static inline int ds_get_bmask(DisplayState *ds) +{ + return ds->surface->pf.bmask; +} + #ifdef CONFIG_CURSES #include typedef chtype console_ch_t; diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index bf14e788d2..240443bfda 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -36,11 +36,8 @@ struct vmsvga_state_s { VGACommonState vga; - int width; - int height; int invalidated; int depth; - int bypp; int enable; int config; struct { @@ -57,9 +54,6 @@ struct vmsvga_state_s { int new_height; uint32_t guest; uint32_t svgaid; - uint32_t wred; - uint32_t wgreen; - uint32_t wblue; int syncing; int fb_size; @@ -297,23 +291,23 @@ static inline void vmsvga_update_rect(struct vmsvga_state_s *s, uint8_t *src; uint8_t *dst; - if (x + w > s->width) { + if (x + w > ds_get_width(s->vga.ds)) { fprintf(stderr, "%s: update width too large x: %d, w: %d\n", __func__, x, w); - x = MIN(x, s->width); - w = s->width - x; + x = MIN(x, ds_get_width(s->vga.ds)); + w = ds_get_width(s->vga.ds) - x; } - if (y + h > s->height) { + if (y + h > ds_get_height(s->vga.ds)) { fprintf(stderr, "%s: update height too large y: %d, h: %d\n", __func__, y, h); - y = MIN(y, s->height); - h = s->height - y; + y = MIN(y, ds_get_height(s->vga.ds)); + h = ds_get_height(s->vga.ds) - y; } - bypl = s->bypp * s->width; - width = s->bypp * w; - start = s->bypp * x + bypl * y; + bypl = ds_get_linesize(s->vga.ds); + width = ds_get_bytes_per_pixel(s->vga.ds) * w; + start = ds_get_bytes_per_pixel(s->vga.ds) * x + bypl * y; src = s->vga.vram_ptr + start; dst = ds_get_data(s->vga.ds) + start; @@ -326,8 +320,9 @@ static inline void vmsvga_update_rect(struct vmsvga_state_s *s, static inline void vmsvga_update_screen(struct vmsvga_state_s *s) { memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, - s->bypp * s->width * s->height); - dpy_gfx_update(s->vga.ds, 0, 0, s->width, s->height); + ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds)); + dpy_gfx_update(s->vga.ds, 0, 0, + ds_get_width(s->vga.ds), ds_get_height(s->vga.ds)); } static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, @@ -364,20 +359,21 @@ static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, int x0, int y0, int x1, int y1, int w, int h) { uint8_t *vram = s->vga.vram_ptr; - int bypl = s->bypp * s->width; - int width = s->bypp * w; + int bypl = ds_get_linesize(s->vga.ds); + int bypp = ds_get_bytes_per_pixel(s->vga.ds); + int width = bypp * w; int line = h; uint8_t *ptr[2]; if (y1 > y0) { - ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1); - ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1); + ptr[0] = vram + bypp * x0 + bypl * (y0 + h - 1); + ptr[1] = vram + bypp * x1 + bypl * (y1 + h - 1); for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl) { memmove(ptr[1], ptr[0], width); } } else { - ptr[0] = vram + s->bypp * x0 + bypl * y0; - ptr[1] = vram + s->bypp * x1 + bypl * y1; + ptr[0] = vram + bypp * x0 + bypl * y0; + ptr[1] = vram + bypp * x1 + bypl * y1; for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl) { memmove(ptr[1], ptr[0], width); } @@ -391,13 +387,11 @@ static inline void vmsvga_copy_rect(struct vmsvga_state_s *s, static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, uint32_t c, int x, int y, int w, int h) { - uint8_t *vram = s->vga.vram_ptr; - int bypp = s->bypp; - int bypl = bypp * s->width; - int width = bypp * w; + int bypl = ds_get_linesize(s->vga.ds); + int width = ds_get_bytes_per_pixel(s->vga.ds) * w; int line = h; int column; - uint8_t *fst = vram + bypp * x + bypl * y; + uint8_t *fst; uint8_t *dst; uint8_t *src; uint8_t col[4]; @@ -407,12 +401,14 @@ static inline void vmsvga_fill_rect(struct vmsvga_state_s *s, col[2] = c >> 16; col[3] = c >> 24; + fst = s->vga.vram_ptr + ds_get_bytes_per_pixel(s->vga.ds) * x + bypl * y; + if (line--) { dst = fst; src = col; for (column = width; column > 0; column--) { *(dst++) = *(src++); - if (src - col == bypp) { + if (src - col == ds_get_bytes_per_pixel(s->vga.ds)) { src = col; } } @@ -718,10 +714,10 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) return s->enable; case SVGA_REG_WIDTH: - return s->width; + return ds_get_width(s->vga.ds); case SVGA_REG_HEIGHT: - return s->height; + return ds_get_height(s->vga.ds); case SVGA_REG_MAX_WIDTH: return SVGA_MAX_WIDTH; @@ -730,23 +726,25 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) return SVGA_MAX_HEIGHT; case SVGA_REG_DEPTH: - return s->depth; + return ds_get_depth(s->vga.ds); case SVGA_REG_BITS_PER_PIXEL: - return (s->depth + 7) & ~7; + return ds_get_bits_per_pixel(s->vga.ds); case SVGA_REG_PSEUDOCOLOR: return 0x0; case SVGA_REG_RED_MASK: - return s->wred; + return ds_get_rmask(s->vga.ds); + case SVGA_REG_GREEN_MASK: - return s->wgreen; + return ds_get_gmask(s->vga.ds); + case SVGA_REG_BLUE_MASK: - return s->wblue; + return ds_get_bmask(s->vga.ds); case SVGA_REG_BYTES_PER_LINE: - return ((s->depth + 7) >> 3) * s->new_width; + return ds_get_bytes_per_pixel(s->vga.ds) * s->new_width; case SVGA_REG_FB_START: { struct pci_vmsvga_state_s *pci_vmsvga @@ -811,7 +809,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) return s->cursor.on; case SVGA_REG_HOST_BITS_PER_PIXEL: - return (s->depth + 7) & ~7; + return ds_get_bits_per_pixel(s->vga.ds); case SVGA_REG_SCRATCH_SIZE: return s->scratch_size; @@ -847,8 +845,6 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) case SVGA_REG_ENABLE: s->enable = value; s->config &= !!value; - s->width = -1; - s->height = -1; s->invalidated = 1; s->vga.invalidate(&s->vga); if (s->enable) { @@ -860,18 +856,26 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) break; case SVGA_REG_WIDTH: - s->new_width = value; - s->invalidated = 1; + if (value <= SVGA_MAX_WIDTH) { + s->new_width = value; + s->invalidated = 1; + } else { + printf("%s: Bad width: %i\n", __func__, value); + } break; case SVGA_REG_HEIGHT: - s->new_height = value; - s->invalidated = 1; + if (value <= SVGA_MAX_HEIGHT) { + s->new_height = value; + s->invalidated = 1; + } else { + printf("%s: Bad height: %i\n", __func__, value); + } break; case SVGA_REG_DEPTH: case SVGA_REG_BITS_PER_PIXEL: - if (value != s->depth) { + if (value != ds_get_bits_per_pixel(s->vga.ds)) { printf("%s: Bad colour depth: %i bits\n", __func__, value); s->config = 0; } @@ -962,12 +966,11 @@ static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data) printf("%s: what are we supposed to do with (%08x)?\n", __func__, data); } -static inline void vmsvga_size(struct vmsvga_state_s *s) +static inline void vmsvga_check_size(struct vmsvga_state_s *s) { - if (s->new_width != s->width || s->new_height != s->height) { - s->width = s->new_width; - s->height = s->new_height; - qemu_console_resize(s->vga.ds, s->width, s->height); + if (s->new_width != ds_get_width(s->vga.ds) || + s->new_height != ds_get_height(s->vga.ds)) { + qemu_console_resize(s->vga.ds, s->new_width, s->new_height); s->invalidated = 1; } } @@ -980,7 +983,7 @@ static void vmsvga_update_display(void *opaque) return; } - vmsvga_size(s); + vmsvga_check_size(s); vmsvga_fifo_run(s); vmsvga_update_rect_flush(s); @@ -1004,8 +1007,6 @@ static void vmsvga_reset(DeviceState *dev) s->index = 0; s->enable = 0; s->config = 0; - s->width = -1; - s->height = -1; s->svgaid = SVGA_ID; s->cursor.on = 0; s->redraw_fifo_first = 0; @@ -1037,9 +1038,13 @@ static void vmsvga_screen_dump(void *opaque, const char *filename, bool cswitch, return; } - if (s->depth == 32) { - DisplaySurface *ds = qemu_create_displaysurface_from(s->width, - s->height, 32, ds_get_linesize(s->vga.ds), s->vga.vram_ptr); + if (ds_get_bits_per_pixel(s->vga.ds) == 32) { + DisplaySurface *ds = qemu_create_displaysurface_from( + ds_get_width(s->vga.ds), + ds_get_height(s->vga.ds), + 32, + ds_get_linesize(s->vga.ds), + s->vga.vram_ptr); ppm_save(filename, ds, errp); g_free(ds); } @@ -1125,40 +1130,9 @@ static void vmsvga_init(struct vmsvga_state_s *s, vga_common_init(&s->vga); vga_init(&s->vga, address_space, io, true); vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga); - - s->depth = ds_get_bits_per_pixel(s->vga.ds); - s->bypp = ds_get_bytes_per_pixel(s->vga.ds); - switch (s->depth) { - case 8: - s->wred = 0x00000007; - s->wgreen = 0x00000038; - s->wblue = 0x000000c0; - break; - case 15: - s->wred = 0x0000001f; - s->wgreen = 0x000003e0; - s->wblue = 0x00007c00; - break; - case 16: - s->wred = 0x0000001f; - s->wgreen = 0x000007e0; - s->wblue = 0x0000f800; - break; - case 24: - s->wred = 0x00ff0000; - s->wgreen = 0x0000ff00; - s->wblue = 0x000000ff; - break; - case 32: - s->wred = 0x00ff0000; - s->wgreen = 0x0000ff00; - s->wblue = 0x000000ff; - break; - } } -static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, - unsigned size) +static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size) { struct vmsvga_state_s *s = opaque; @@ -1202,9 +1176,6 @@ static int pci_vmsvga_initfn(PCIDevice *dev) { struct pci_vmsvga_state_s *s = DO_UPCAST(struct pci_vmsvga_state_s, card, dev); - MemoryRegion *iomem; - - iomem = &s->chip.vga.vram; s->card.config[PCI_CACHE_LINE_SIZE] = 0x08; /* Cache line size */ s->card.config[PCI_LATENCY_TIMER] = 0x40; /* Latency timer */ @@ -1215,10 +1186,10 @@ static int pci_vmsvga_initfn(PCIDevice *dev) memory_region_set_flush_coalesced(&s->io_bar); pci_register_bar(&s->card, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io_bar); - vmsvga_init(&s->chip, pci_address_space(dev), - pci_address_space_io(dev)); + vmsvga_init(&s->chip, pci_address_space(dev), pci_address_space_io(dev)); - pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, iomem); + pci_register_bar(&s->card, 1, PCI_BASE_ADDRESS_MEM_PREFETCH, + &s->chip.vga.vram); pci_register_bar(&s->card, 2, PCI_BASE_ADDRESS_MEM_PREFETCH, &s->chip.fifo_ram); From 5b9575c8b7873dee4ab233e065888bbce6dfbaa8 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sat, 3 Nov 2012 12:47:08 +0100 Subject: [PATCH 268/291] vmware_vga: Return a value for FB_SIZE before the device is enabled According to the documentation drivers using this device should read FB_SIZE before enabling the device to know what memory to map. This would not work if we return 0 before enabled. The docs also mention reading SVGA_REG_DEPTH but not writing it. (Only SVGA_REG_BITS_PER_PIXEL can be written but we don't really support that either.) Signed-off-by: BALATON Zoltan Signed-off-by: Blue Swirl --- hw/vmware_vga.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index 240443bfda..038994e705 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -31,13 +31,14 @@ #define HW_FILL_ACCEL #define HW_MOUSE_ACCEL -# include "vga_int.h" +#include "vga_int.h" + +/* See http://vmware-svga.sf.net/ for some documentation on VMWare SVGA */ struct vmsvga_state_s { VGACommonState vga; int invalidated; - int depth; int enable; int config; struct { @@ -55,7 +56,6 @@ struct vmsvga_state_s { uint32_t guest; uint32_t svgaid; int syncing; - int fb_size; MemoryRegion fifo_ram; uint8_t *fifo_ptr; @@ -756,10 +756,10 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address) return 0x0; case SVGA_REG_VRAM_SIZE: - return s->vga.vram_size; + return s->vga.vram_size; /* No physical VRAM besides the framebuffer */ case SVGA_REG_FB_SIZE: - return s->fb_size; + return s->vga.vram_size; case SVGA_REG_CAPABILITIES: caps = SVGA_CAP_NONE; @@ -848,7 +848,6 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) s->invalidated = 1; s->vga.invalidate(&s->vga); if (s->enable) { - s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height; vga_dirty_log_stop(&s->vga); } else { vga_dirty_log_start(&s->vga); @@ -873,10 +872,9 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) } break; - case SVGA_REG_DEPTH: case SVGA_REG_BITS_PER_PIXEL: if (value != ds_get_bits_per_pixel(s->vga.ds)) { - printf("%s: Bad colour depth: %i bits\n", __func__, value); + printf("%s: Bad bits per pixel: %i bits\n", __func__, value); s->config = 0; } break; @@ -939,6 +937,7 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) #endif break; + case SVGA_REG_DEPTH: case SVGA_REG_MEM_REGS: case SVGA_REG_NUM_DISPLAYS: case SVGA_REG_PITCHLOCK: @@ -1077,7 +1076,7 @@ static const VMStateDescription vmstate_vmware_vga_internal = { .minimum_version_id_old = 0, .post_load = vmsvga_post_load, .fields = (VMStateField[]) { - VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s), + VMSTATE_UNUSED(4), /* was depth */ VMSTATE_INT32(enable, struct vmsvga_state_s), VMSTATE_INT32(config, struct vmsvga_state_s), VMSTATE_INT32(cursor.id, struct vmsvga_state_s), @@ -1092,7 +1091,7 @@ static const VMStateDescription vmstate_vmware_vga_internal = { VMSTATE_UINT32(guest, struct vmsvga_state_s), VMSTATE_UINT32(svgaid, struct vmsvga_state_s), VMSTATE_INT32(syncing, struct vmsvga_state_s), - VMSTATE_INT32(fb_size, struct vmsvga_state_s), + VMSTATE_UNUSED(4), /* was fb_size */ VMSTATE_END_OF_LIST() } }; From b51d7b2e10564aedc83513d3961a69f22509eaa9 Mon Sep 17 00:00:00 2001 From: BALATON Zoltan Date: Sat, 3 Nov 2012 12:47:08 +0100 Subject: [PATCH 269/291] vmware_vga: Allow simple drivers to work without using the fifo Postpone stopping the dirty log to the point where the command fifo is configured to allow drivers which don't use the fifo to work too. (Without this the picture rendered into the vram never got to the screen and the DIRECT_VRAM option meant to support this case was removed a year ago.) Signed-off-by: BALATON Zoltan Signed-off-by: Blue Swirl --- hw/vga.c | 2 +- hw/vga_int.h | 1 + hw/vmware_vga.c | 34 +++++++++++++++++++++------------- 3 files changed, 23 insertions(+), 14 deletions(-) diff --git a/hw/vga.c b/hw/vga.c index 023134ef68..81aa76bef9 100644 --- a/hw/vga.c +++ b/hw/vga.c @@ -1616,7 +1616,7 @@ void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2) } } -static void vga_sync_dirty_bitmap(VGACommonState *s) +void vga_sync_dirty_bitmap(VGACommonState *s) { memory_region_sync_dirty_bitmap(&s->vram); } diff --git a/hw/vga_int.h b/hw/vga_int.h index d4da777e62..bcb738d8c9 100644 --- a/hw/vga_int.h +++ b/hw/vga_int.h @@ -186,6 +186,7 @@ MemoryRegion *vga_init_io(VGACommonState *s, const MemoryRegionPortio **vbe_ports); void vga_common_reset(VGACommonState *s); +void vga_sync_dirty_bitmap(VGACommonState *s); void vga_dirty_log_start(VGACommonState *s); void vga_dirty_log_stop(VGACommonState *s); diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c index 038994e705..7c766fb3da 100644 --- a/hw/vmware_vga.c +++ b/hw/vmware_vga.c @@ -317,14 +317,6 @@ static inline void vmsvga_update_rect(struct vmsvga_state_s *s, dpy_gfx_update(s->vga.ds, x, y, w, h); } -static inline void vmsvga_update_screen(struct vmsvga_state_s *s) -{ - memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, - ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds)); - dpy_gfx_update(s->vga.ds, 0, 0, - ds_get_width(s->vga.ds), ds_get_height(s->vga.ds)); -} - static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s, int x, int y, int w, int h) { @@ -843,11 +835,10 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) break; case SVGA_REG_ENABLE: - s->enable = value; - s->config &= !!value; + s->enable = !!value; s->invalidated = 1; s->vga.invalidate(&s->vga); - if (s->enable) { + if (s->enable && s->config) { vga_dirty_log_stop(&s->vga); } else { vga_dirty_log_start(&s->vga); @@ -895,6 +886,7 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value) if (CMD(max) < CMD(min) + 10 * 1024) { break; } + vga_dirty_log_stop(&s->vga); } s->config = !!value; break; @@ -977,6 +969,8 @@ static inline void vmsvga_check_size(struct vmsvga_state_s *s) static void vmsvga_update_display(void *opaque) { struct vmsvga_state_s *s = opaque; + bool dirty = false; + if (!s->enable) { s->vga.update(&s->vga); return; @@ -991,9 +985,23 @@ static void vmsvga_update_display(void *opaque) * Is it more efficient to look at vram VGA-dirty bits or wait * for the driver to issue SVGA_CMD_UPDATE? */ - if (s->invalidated) { + if (memory_region_is_logging(&s->vga.vram)) { + vga_sync_dirty_bitmap(&s->vga); + dirty = memory_region_get_dirty(&s->vga.vram, 0, + ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds), + DIRTY_MEMORY_VGA); + } + if (s->invalidated || dirty) { s->invalidated = 0; - vmsvga_update_screen(s); + memcpy(ds_get_data(s->vga.ds), s->vga.vram_ptr, + ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds)); + dpy_gfx_update(s->vga.ds, 0, 0, + ds_get_width(s->vga.ds), ds_get_height(s->vga.ds)); + } + if (dirty) { + memory_region_reset_dirty(&s->vga.vram, 0, + ds_get_linesize(s->vga.ds) * ds_get_height(s->vga.ds), + DIRTY_MEMORY_VGA); } } From ed224a56b3b3234d99832a063ee3aaee3613d115 Mon Sep 17 00:00:00 2001 From: malc Date: Sat, 3 Nov 2012 19:38:32 +0400 Subject: [PATCH 270/291] tcg/ppc: ld/st optimization Signed-off-by: malc --- configure | 2 +- exec-all.h | 3 + tcg/ppc/tcg-target.c | 465 ++++++++++++++++++++++++------------------- 3 files changed, 268 insertions(+), 202 deletions(-) diff --git a/configure b/configure index 8e70cbb224..7290f50e11 100755 --- a/configure +++ b/configure @@ -3882,7 +3882,7 @@ upper() { } case "$cpu" in - i386|x86_64) + i386|x86_64|ppc) echo "CONFIG_QEMU_LDST_OPTIMIZATION=y" >> $config_target_mak ;; esac diff --git a/exec-all.h b/exec-all.h index 898fe2d862..94ed613e37 100644 --- a/exec-all.h +++ b/exec-all.h @@ -335,6 +335,9 @@ extern uintptr_t tci_tb_ptr; # define GETRA() ((uintptr_t)__builtin_return_address(0)) # define GETPC_LDST() ((uintptr_t)(GETRA() + 7 + \ *(int32_t *)((void *)GETRA() + 3) - 1)) +# elif defined (_ARCH_PPC) && !defined (_ARCH_PPC64) +# define GETRA() ((uintptr_t)__builtin_return_address(0)) +# define GETPC_LDST() ((uintptr_t) ((*(int32_t *)(GETRA() + 4)) - 1)) # else # error "CONFIG_QEMU_LDST_OPTIMIZATION needs GETPC_LDST() implementation!" # endif diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c index 60b7b92621..a1c74cea63 100644 --- a/tcg/ppc/tcg-target.c +++ b/tcg/ppc/tcg-target.c @@ -39,8 +39,6 @@ static uint8_t *tb_ret_addr; #define LR_OFFSET 4 #endif -#define FAST_PATH - #ifndef GUEST_BASE #define GUEST_BASE 0 #endif @@ -520,6 +518,37 @@ static void tcg_out_call (TCGContext *s, tcg_target_long arg, int const_arg) #if defined(CONFIG_SOFTMMU) +static void add_qemu_ldst_label (TCGContext *s, + int is_ld, + int opc, + int data_reg, + int data_reg2, + int addrlo_reg, + int addrhi_reg, + int mem_index, + uint8_t *raddr, + uint8_t *label_ptr) +{ + int idx; + TCGLabelQemuLdst *label; + + if (s->nb_qemu_ldst_labels >= TCG_MAX_QEMU_LDST) { + tcg_abort(); + } + + idx = s->nb_qemu_ldst_labels++; + label = (TCGLabelQemuLdst *)&s->qemu_ldst_labels[idx]; + label->is_ld = is_ld; + label->opc = opc; + label->datalo_reg = data_reg; + label->datahi_reg = data_reg2; + label->addrlo_reg = addrlo_reg; + label->addrhi_reg = addrhi_reg; + label->mem_index = mem_index; + label->raddr = raddr; + label->label_ptr[0] = label_ptr; +} + #include "../../softmmu_defs.h" /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr, @@ -539,36 +568,12 @@ static const void * const qemu_st_helpers[4] = { helper_stl_mmu, helper_stq_mmu, }; -#endif -static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) +static void tcg_out_tlb_check (TCGContext *s, int r0, int r1, int r2, + int addr_reg, int addr_reg2, int s_bits, + int offset1, int offset2, uint8_t **label_ptr) { - int addr_reg, data_reg, data_reg2, r0, r1, rbase, bswap; -#ifdef CONFIG_SOFTMMU - int mem_index, s_bits, r2, ir; - void *label1_ptr, *label2_ptr; -#if TARGET_LONG_BITS == 64 - int addr_reg2; -#endif -#endif - - data_reg = *args++; - if (opc == 3) - data_reg2 = *args++; - else - data_reg2 = 0; - addr_reg = *args++; - -#ifdef CONFIG_SOFTMMU -#if TARGET_LONG_BITS == 64 - addr_reg2 = *args++; -#endif - mem_index = *args; - s_bits = opc & 3; - r0 = 3; - r1 = 4; - r2 = 0; - rbase = 0; + uint16_t retranst; tcg_out32 (s, (RLWINM | RA (r0) @@ -582,7 +587,7 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) tcg_out32 (s, (LWZU | RT (r1) | RA (r0) - | offsetof (CPUArchState, tlb_table[mem_index][0].addr_read) + | offset1 ) ); tcg_out32 (s, (RLWINM @@ -600,77 +605,58 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1)); tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ)); #endif + *label_ptr = s->code_ptr; + retranst = ((uint16_t *) s->code_ptr)[1] & ~3; + tcg_out32 (s, BC | BI (7, CR_EQ) | retranst | BO_COND_FALSE); - label1_ptr = s->code_ptr; -#ifdef FAST_PATH - tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE); -#endif - - /* slow path */ - ir = 3; - tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0); -#if TARGET_LONG_BITS == 32 - tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); -#else -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - ir |= 1; -#endif - tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg2); - tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); -#endif - tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index); - - tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1); - switch (opc) { - case 0|4: - tcg_out32 (s, EXTSB | RA (data_reg) | RS (3)); - break; - case 1|4: - tcg_out32 (s, EXTSH | RA (data_reg) | RS (3)); - break; - case 0: - case 1: - case 2: - if (data_reg != 3) - tcg_out_mov (s, TCG_TYPE_I32, data_reg, 3); - break; - case 3: - if (data_reg == 3) { - if (data_reg2 == 4) { - tcg_out_mov (s, TCG_TYPE_I32, 0, 4); - tcg_out_mov (s, TCG_TYPE_I32, 4, 3); - tcg_out_mov (s, TCG_TYPE_I32, 3, 0); - } - else { - tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3); - tcg_out_mov (s, TCG_TYPE_I32, 3, 4); - } - } - else { - if (data_reg != 4) tcg_out_mov (s, TCG_TYPE_I32, data_reg, 4); - if (data_reg2 != 3) tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3); - } - break; - } - label2_ptr = s->code_ptr; - tcg_out32 (s, B); - - /* label1: fast path */ -#ifdef FAST_PATH - reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr); -#endif - - /* r0 now contains &env->tlb_table[mem_index][index].addr_read */ + /* r0 now contains &env->tlb_table[mem_index][index].addr_x */ tcg_out32 (s, (LWZ | RT (r0) | RA (r0) - | (offsetof (CPUTLBEntry, addend) - - offsetof (CPUTLBEntry, addr_read)) - )); + | offset2 + ) + ); /* r0 = env->tlb_table[mem_index][index].addend */ tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg)); /* r0 = env->tlb_table[mem_index][index].addend + addr */ +} +#endif + +static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) +{ + int addr_reg, addr_reg2, data_reg, data_reg2, r0, r1, rbase, bswap; +#ifdef CONFIG_SOFTMMU + int mem_index, s_bits, r2; + uint8_t *label_ptr; +#endif + + data_reg = *args++; + if (opc == 3) + data_reg2 = *args++; + else + data_reg2 = 0; + addr_reg = *args++; + +#ifdef CONFIG_SOFTMMU +#if TARGET_LONG_BITS == 64 + addr_reg2 = *args++; +#else + addr_reg2 = 0; +#endif + mem_index = *args; + s_bits = opc & 3; + r0 = 3; + r1 = 4; + r2 = 0; + rbase = 0; + + tcg_out_tlb_check ( + s, r0, r1, r2, addr_reg, addr_reg2, s_bits, + offsetof (CPUArchState, tlb_table[mem_index][0].addr_read), + offsetof (CPUTLBEntry, addend) - offsetof (CPUTLBEntry, addr_read), + &label_ptr + ); #else /* !CONFIG_SOFTMMU */ r0 = addr_reg; r1 = 3; @@ -736,21 +722,26 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc) } break; } - #ifdef CONFIG_SOFTMMU - reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr); + add_qemu_ldst_label (s, + 1, + opc, + data_reg, + data_reg2, + addr_reg, + addr_reg2, + mem_index, + s->code_ptr, + label_ptr); #endif } static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) { - int addr_reg, r0, r1, data_reg, data_reg2, bswap, rbase; + int addr_reg, addr_reg2, r0, r1, data_reg, data_reg2, bswap, rbase; #ifdef CONFIG_SOFTMMU - int mem_index, r2, ir; - void *label1_ptr, *label2_ptr; -#if TARGET_LONG_BITS == 64 - int addr_reg2; -#endif + int mem_index, r2; + uint8_t *label_ptr; #endif data_reg = *args++; @@ -763,6 +754,8 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) #ifdef CONFIG_SOFTMMU #if TARGET_LONG_BITS == 64 addr_reg2 = *args++; +#else + addr_reg2 = 0; #endif mem_index = *args; r0 = 3; @@ -770,105 +763,12 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) r2 = 0; rbase = 0; - tcg_out32 (s, (RLWINM - | RA (r0) - | RS (addr_reg) - | SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS)) - | MB (32 - (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)) - | ME (31 - CPU_TLB_ENTRY_BITS) - ) + tcg_out_tlb_check ( + s, r0, r1, r2, addr_reg, addr_reg2, opc & 3, + offsetof (CPUArchState, tlb_table[mem_index][0].addr_write), + offsetof (CPUTLBEntry, addend) - offsetof (CPUTLBEntry, addr_write), + &label_ptr ); - tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0)); - tcg_out32 (s, (LWZU - | RT (r1) - | RA (r0) - | offsetof (CPUArchState, tlb_table[mem_index][0].addr_write) - ) - ); - tcg_out32 (s, (RLWINM - | RA (r2) - | RS (addr_reg) - | SH (0) - | MB ((32 - opc) & 31) - | ME (31 - TARGET_PAGE_BITS) - ) - ); - - tcg_out32 (s, CMP | (7 << 23) | RA (r2) | RB (r1)); -#if TARGET_LONG_BITS == 64 - tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4); - tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1)); - tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ)); -#endif - - label1_ptr = s->code_ptr; -#ifdef FAST_PATH - tcg_out32 (s, BC | BI (7, CR_EQ) | BO_COND_TRUE); -#endif - - /* slow path */ - ir = 3; - tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0); -#if TARGET_LONG_BITS == 32 - tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); -#else -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - ir |= 1; -#endif - tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg2); - tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); -#endif - - switch (opc) { - case 0: - tcg_out32 (s, (RLWINM - | RA (ir) - | RS (data_reg) - | SH (0) - | MB (24) - | ME (31))); - break; - case 1: - tcg_out32 (s, (RLWINM - | RA (ir) - | RS (data_reg) - | SH (0) - | MB (16) - | ME (31))); - break; - case 2: - tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg); - break; - case 3: -#ifdef TCG_TARGET_CALL_ALIGN_ARGS - ir |= 1; -#endif - tcg_out_mov (s, TCG_TYPE_I32, ir++, data_reg2); - tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg); - break; - } - ir++; - - tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index); - tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1); - label2_ptr = s->code_ptr; - tcg_out32 (s, B); - - /* label1: fast path */ -#ifdef FAST_PATH - reloc_pc14 (label1_ptr, (tcg_target_long) s->code_ptr); -#endif - - tcg_out32 (s, (LWZ - | RT (r0) - | RA (r0) - | (offsetof (CPUTLBEntry, addend) - - offsetof (CPUTLBEntry, addr_write)) - )); - /* r0 = env->tlb_table[mem_index][index].addend */ - tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg)); - /* r0 = env->tlb_table[mem_index][index].addend + addr */ - #else /* !CONFIG_SOFTMMU */ r0 = addr_reg; r1 = 3; @@ -916,10 +816,173 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc) } #ifdef CONFIG_SOFTMMU - reloc_pc24 (label2_ptr, (tcg_target_long) s->code_ptr); + add_qemu_ldst_label (s, + 0, + opc, + data_reg, + data_reg2, + addr_reg, + addr_reg2, + mem_index, + s->code_ptr, + label_ptr); #endif } +#if defined(CONFIG_SOFTMMU) +static void tcg_out_qemu_ld_slow_path (TCGContext *s, TCGLabelQemuLdst *label) +{ + int s_bits; + int ir; + int opc = label->opc; + int mem_index = label->mem_index; + int data_reg = label->datalo_reg; + int data_reg2 = label->datahi_reg; + int addr_reg = label->addrlo_reg; + uint8_t *raddr = label->raddr; + uint8_t **label_ptr = &label->label_ptr[0]; + + s_bits = opc & 3; + + /* resolve label address */ + reloc_pc14 (label_ptr[0], (tcg_target_long) s->code_ptr); + + /* slow path */ + ir = 3; + tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0); +#if TARGET_LONG_BITS == 32 + tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); +#else +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + ir |= 1; +#endif + tcg_out_mov (s, TCG_TYPE_I32, ir++, label->addrhi_reg); + tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); +#endif + tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index); + tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1); + tcg_out32 (s, B | 8); + tcg_out32 (s, (tcg_target_long) raddr); + switch (opc) { + case 0|4: + tcg_out32 (s, EXTSB | RA (data_reg) | RS (3)); + break; + case 1|4: + tcg_out32 (s, EXTSH | RA (data_reg) | RS (3)); + break; + case 0: + case 1: + case 2: + if (data_reg != 3) + tcg_out_mov (s, TCG_TYPE_I32, data_reg, 3); + break; + case 3: + if (data_reg == 3) { + if (data_reg2 == 4) { + tcg_out_mov (s, TCG_TYPE_I32, 0, 4); + tcg_out_mov (s, TCG_TYPE_I32, 4, 3); + tcg_out_mov (s, TCG_TYPE_I32, 3, 0); + } + else { + tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3); + tcg_out_mov (s, TCG_TYPE_I32, 3, 4); + } + } + else { + if (data_reg != 4) tcg_out_mov (s, TCG_TYPE_I32, data_reg, 4); + if (data_reg2 != 3) tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 3); + } + break; + } + /* Jump to the code corresponding to next IR of qemu_st */ + tcg_out_b (s, 0, (tcg_target_long) raddr); +} + +static void tcg_out_qemu_st_slow_path (TCGContext *s, TCGLabelQemuLdst *label) +{ + int s_bits; + int ir; + int opc = label->opc; + int mem_index = label->mem_index; + int data_reg = label->datalo_reg; + int data_reg2 = label->datahi_reg; + int addr_reg = label->addrlo_reg; + uint8_t *raddr = label->raddr; + uint8_t **label_ptr = &label->label_ptr[0]; + + s_bits = opc & 3; + + /* resolve label address */ + reloc_pc14 (label_ptr[0], (tcg_target_long) s->code_ptr); + + /* slow path */ + ir = 3; + tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0); +#if TARGET_LONG_BITS == 32 + tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); +#else +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + ir |= 1; +#endif + tcg_out_mov (s, TCG_TYPE_I32, ir++, label->addrhi_reg); + tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg); +#endif + + switch (opc) { + case 0: + tcg_out32 (s, (RLWINM + | RA (ir) + | RS (data_reg) + | SH (0) + | MB (24) + | ME (31))); + break; + case 1: + tcg_out32 (s, (RLWINM + | RA (ir) + | RS (data_reg) + | SH (0) + | MB (16) + | ME (31))); + break; + case 2: + tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg); + break; + case 3: +#ifdef TCG_TARGET_CALL_ALIGN_ARGS + ir |= 1; +#endif + tcg_out_mov (s, TCG_TYPE_I32, ir++, data_reg2); + tcg_out_mov (s, TCG_TYPE_I32, ir, data_reg); + break; + } + ir++; + + tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index); + tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1); + tcg_out32 (s, B | 8); + tcg_out32 (s, (tcg_target_long) raddr); + tcg_out_b (s, 0, (tcg_target_long) raddr); +} + +void tcg_out_tb_finalize(TCGContext *s) +{ + int i; + TCGLabelQemuLdst *label; + + /* qemu_ld/st slow paths */ + for (i = 0; i < s->nb_qemu_ldst_labels; i++) { + label = (TCGLabelQemuLdst *) &s->qemu_ldst_labels[i]; + if (label->is_ld) { + tcg_out_qemu_ld_slow_path (s, label); + } + else { + tcg_out_qemu_st_slow_path (s, label); + } + } +} +#endif + static void tcg_target_qemu_prologue (TCGContext *s) { int i, frame_size; From 30ea833941a7de51454cf99913f5edb3e7e21c0d Mon Sep 17 00:00:00 2001 From: Anthony Liguori Date: Fri, 2 Nov 2012 16:12:53 -0500 Subject: [PATCH 271/291] build: pthread_atfork() needs include of pthread.h Cc: Paolo Bonzini Signed-off-by: Anthony Liguori --- qemu-timer.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qemu-timer.c b/qemu-timer.c index 7b2217aab0..8d9cf38bb2 100644 --- a/qemu-timer.c +++ b/qemu-timer.c @@ -30,6 +30,9 @@ #include "hw/hw.h" #include "qemu-timer.h" +#ifdef CONFIG_POSIX +#include +#endif #ifdef _WIN32 #include From 1cfd981ff1e8ff0858cd71cfae0c7c7ba741f380 Mon Sep 17 00:00:00 2001 From: Blue Swirl Date: Sat, 3 Nov 2012 18:48:35 +0000 Subject: [PATCH 272/291] target-mips: use ULL for 64 bit constants Fix build on a 32 bit host: CC mips-softmmu/target-mips/dsp_helper.o /src/qemu/target-mips/dsp_helper.c: In function 'helper_dextr_rs_w': /src/qemu/target-mips/dsp_helper.c:3556: error: integer constant is too large for 'long' type /src/qemu/target-mips/dsp_helper.c: In function 'helper_extr_s_h': /src/qemu/target-mips/dsp_helper.c:3656: error: integer constant is too large for 'long' type Signed-off-by: Blue Swirl Signed-off-by: Aurelien Jarno --- target-mips/dsp_helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target-mips/dsp_helper.c b/target-mips/dsp_helper.c index b59133ea8f..e7949c22c0 100644 --- a/target-mips/dsp_helper.c +++ b/target-mips/dsp_helper.c @@ -3553,7 +3553,7 @@ target_ulong helper_dextr_rs_w(target_ulong ac, target_ulong shift, if (temp128 == 0) { temp[0] = 0x0FFFFFFFF; } else { - temp[0] = 0x0100000000; + temp[0] = 0x0100000000ULL; } set_DSPControl_overflow_flag(1, 23, env); } @@ -3653,7 +3653,7 @@ target_ulong helper_extr_s_h(target_ulong ac, target_ulong shift, if (temp > (int64_t)0x7FFF) { temp = 0x00007FFF; set_DSPControl_overflow_flag(1, 23, env); - } else if (temp < (int64_t)0xFFFFFFFFFFFF8000) { + } else if (temp < (int64_t)0xFFFFFFFFFFFF8000ULL) { temp = 0xFFFF8000; set_DSPControl_overflow_flag(1, 23, env); } From c878da3b27ceeed953c9f9a1eb002d59e9dcb4c6 Mon Sep 17 00:00:00 2001 From: malc Date: Mon, 5 Nov 2012 21:47:04 +0400 Subject: [PATCH 273/291] tcg/ppc32: Use trampolines to trim the code size for mmu slow path accessors mmu access looks something like: if miss goto slow_path done: ... ; end of the TB slow_path: 
 mr r3, r27         ; move areg0 to r3
                    ; (r3 holds the first argument for all the PPC32 ABIs)
 
 b $+8
 .long done
 
 b done

On ppc32  is:

(SysV and Darwin)

mmu_helper is most likely not within direct branching distance from
the call site, necessitating

a. moving 32 bit offset of mmu_helper into a GPR ; 8 bytes
b. moving GPR to CTR/LR                          ; 4 bytes
c. (finally) branching to CTR/LR                 ; 4 bytes

r3 setting              - 4 bytes
call                    - 16 bytes
dummy jump over retaddr - 4 bytes
embedded retaddr        - 4 bytes
         Total overhead - 28 bytes

(PowerOpen (AIX))
a. moving 32 bit offset of mmu_helper's TOC into a GPR1 ; 8 bytes
b. loading 32 bit function pointer into GPR2            ; 4 bytes
c. moving GPR2 to CTR/LR                                ; 4 bytes
d. loading 32 bit small area pointer into R2            ; 4 bytes
e. (finally) branching to CTR/LR                        ; 4 bytes

r3 setting              - 4 bytes
call                    - 24 bytes
dummy jump over retaddr - 4 bytes
embedded retaddr        - 4 bytes
         Total overhead - 36 bytes

Following is done to trim the code size of slow path sections:

In tcg_target_qemu_prologue trampolines are emitted that look like this:

trampoline:
mfspr r3, LR
addi  r3, 4
mtspr LR, r3      ; fixup LR to point over embedded retaddr
mr    r3, r27
 ; tail call of sorts

And slow path becomes:

slow_path:
 
 
 .long done
 
 b done

call                    - 4 bytes (trampoline is within code gen buffer
                                   and most likely accessible via
                                   direct branch)
embedded retaddr        - 4 bytes
         Total overhead - 8 bytes

In the end the icache pressure is decreased by 20/28 bytes at the cost
of an extra jump to trampoline and adjusting LR (to skip over embedded
retaddr) once inside.

Signed-off-by: malc 
---
 exec-all.h           |  2 +-
 tcg/ppc/tcg-target.c | 32 ++++++++++++++++++++++++--------
 2 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/exec-all.h b/exec-all.h
index 94ed613e37..6b3272ab9e 100644
--- a/exec-all.h
+++ b/exec-all.h
@@ -337,7 +337,7 @@ extern uintptr_t tci_tb_ptr;
                                     *(int32_t *)((void *)GETRA() + 3) - 1))
 # elif defined (_ARCH_PPC) && !defined (_ARCH_PPC64)
 #  define GETRA() ((uintptr_t)__builtin_return_address(0))
-#  define GETPC_LDST() ((uintptr_t) ((*(int32_t *)(GETRA() + 4)) - 1))
+#  define GETPC_LDST() ((uintptr_t) ((*(int32_t *)(GETRA() - 4)) - 1))
 # else
 #  error "CONFIG_QEMU_LDST_OPTIMIZATION needs GETPC_LDST() implementation!"
 # endif
diff --git a/tcg/ppc/tcg-target.c b/tcg/ppc/tcg-target.c
index a1c74cea63..34a0693c58 100644
--- a/tcg/ppc/tcg-target.c
+++ b/tcg/ppc/tcg-target.c
@@ -569,6 +569,9 @@ static const void * const qemu_st_helpers[4] = {
     helper_stq_mmu,
 };
 
+static void *ld_trampolines[4];
+static void *st_trampolines[4];
+
 static void tcg_out_tlb_check (TCGContext *s, int r0, int r1, int r2,
                                int addr_reg, int addr_reg2, int s_bits,
                                int offset1, int offset2, uint8_t **label_ptr)
@@ -848,8 +851,7 @@ static void tcg_out_qemu_ld_slow_path (TCGContext *s, TCGLabelQemuLdst *label)
     reloc_pc14 (label_ptr[0], (tcg_target_long) s->code_ptr);
 
     /* slow path */
-    ir = 3;
-    tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
+    ir = 4;
 #if TARGET_LONG_BITS == 32
     tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
 #else
@@ -860,8 +862,7 @@ static void tcg_out_qemu_ld_slow_path (TCGContext *s, TCGLabelQemuLdst *label)
     tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
 #endif
     tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
-    tcg_out_call (s, (tcg_target_long) qemu_ld_helpers[s_bits], 1);
-    tcg_out32 (s, B | 8);
+    tcg_out_call (s, (tcg_target_long) ld_trampolines[s_bits], 1);
     tcg_out32 (s, (tcg_target_long) raddr);
     switch (opc) {
     case 0|4:
@@ -916,8 +917,7 @@ static void tcg_out_qemu_st_slow_path (TCGContext *s, TCGLabelQemuLdst *label)
     reloc_pc14 (label_ptr[0], (tcg_target_long) s->code_ptr);
 
     /* slow path */
-    ir = 3;
-    tcg_out_mov (s, TCG_TYPE_I32, ir++, TCG_AREG0);
+    ir = 4;
 #if TARGET_LONG_BITS == 32
     tcg_out_mov (s, TCG_TYPE_I32, ir++, addr_reg);
 #else
@@ -959,8 +959,7 @@ static void tcg_out_qemu_st_slow_path (TCGContext *s, TCGLabelQemuLdst *label)
     ir++;
 
     tcg_out_movi (s, TCG_TYPE_I32, ir, mem_index);
-    tcg_out_call (s, (tcg_target_long) qemu_st_helpers[opc], 1);
-    tcg_out32 (s, B | 8);
+    tcg_out_call (s, (tcg_target_long) st_trampolines[opc], 1);
     tcg_out32 (s, (tcg_target_long) raddr);
     tcg_out_b (s, 0, (tcg_target_long) raddr);
 }
@@ -983,6 +982,15 @@ void tcg_out_tb_finalize(TCGContext *s)
 }
 #endif
 
+static void emit_ldst_trampoline (TCGContext *s, const void *ptr)
+{
+    tcg_out32 (s, MFSPR | RT (3) | LR);
+    tcg_out32 (s, ADDI | RT (3) | RA (3) | 4);
+    tcg_out32 (s, MTSPR | RS (3) | LR);
+    tcg_out_mov (s, TCG_TYPE_I32, 3, TCG_AREG0);
+    tcg_out_b (s, 0, (tcg_target_long) ptr);
+}
+
 static void tcg_target_qemu_prologue (TCGContext *s)
 {
     int i, frame_size;
@@ -1043,6 +1051,14 @@ static void tcg_target_qemu_prologue (TCGContext *s)
     tcg_out32 (s, MTSPR | RS (0) | LR);
     tcg_out32 (s, ADDI | RT (1) | RA (1) | frame_size);
     tcg_out32 (s, BCLR | BO_ALWAYS);
+
+    for (i = 0; i < 4; ++i) {
+        ld_trampolines[i] = s->code_ptr;
+        emit_ldst_trampoline (s, qemu_ld_helpers[i]);
+
+        st_trampolines[i] = s->code_ptr;
+        emit_ldst_trampoline (s, qemu_st_helpers[i]);
+    }
 }
 
 static void tcg_out_ld (TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,

From 2592c59a66d456fe98fe96cb5787b356c40ee66f Mon Sep 17 00:00:00 2001
From: Paolo Bonzini 
Date: Sat, 3 Nov 2012 18:10:17 +0100
Subject: [PATCH 274/291] tools: initialize main loop before block layer

Tools were broken because they initialized the block layer while
qemu_aio_context was still NULL.

Reported-by: malc 
Signed-off-by: Paolo Bonzini 
Signed-off-by: malc 
---
 qemu-img.c | 3 +--
 qemu-io.c  | 3 +--
 2 files changed, 2 insertions(+), 4 deletions(-)

diff --git a/qemu-img.c b/qemu-img.c
index b17bddd25c..e29e01b729 100644
--- a/qemu-img.c
+++ b/qemu-img.c
@@ -2001,14 +2001,13 @@ int main(int argc, char **argv)
 
     error_set_progname(argv[0]);
 
+    qemu_init_main_loop();
     bdrv_init();
     if (argc < 2)
         help();
     cmdname = argv[1];
     argc--; argv++;
 
-    qemu_init_main_loop();
-
     /* find the command */
     for(cmd = img_cmds; cmd->name != NULL; cmd++) {
         if (!strcmp(cmdname, cmd->name)) {
diff --git a/qemu-io.c b/qemu-io.c
index d0f4fb70c7..1ad7d3adb9 100644
--- a/qemu-io.c
+++ b/qemu-io.c
@@ -1892,9 +1892,8 @@ int main(int argc, char **argv)
         exit(1);
     }
 
-    bdrv_init();
-
     qemu_init_main_loop();
+    bdrv_init();
 
     /* initialize commands */
     quit_init();

From b8c6a5d9d0ab426c1626cd6c228b09b9529dba31 Mon Sep 17 00:00:00 2001
From: Peter Crosthwaite 
Date: Thu, 8 Nov 2012 14:01:19 +1000
Subject: [PATCH 275/291] microblaze: translate.c: Fix swaph decoding

The swaph instruction was not decoding correctly. s/1e1/1e2 on the
9 LSBs on the instruction decode.

Reported-by: David Holsgrove 
Signed-off-by: Peter Crosthwaite 
Signed-off-by: Edgar E. Iglesias 
---
 target-microblaze/translate.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 7d864b1dac..6f27c24b76 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -840,7 +840,7 @@ static void dec_bit(DisasContext *dc)
             LOG_DIS("swapb r%d r%d\n", dc->rd, dc->ra);
             tcg_gen_bswap32_i32(cpu_R[dc->rd], cpu_R[dc->ra]);
             break;
-        case 0x1e1:
+        case 0x1e2:
             /*swaph */
             LOG_DIS("swaph r%d r%d\n", dc->rd, dc->ra);
             tcg_gen_rotri_i32(cpu_R[dc->rd], cpu_R[dc->ra], 16);

From 5c61afec86e5b2597b19b4657edc404fd76e6eb9 Mon Sep 17 00:00:00 2001
From: Jan Kiszka 
Date: Sun, 4 Nov 2012 09:16:55 +0100
Subject: [PATCH 276/291] kvmvapic: Fix TB invalidation after instruction
 patching
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Since 0b57e287, cpu_memory_rw_debug already triggers a TB invalidation.
As it doesn't (and cannot) set is_cpu_write_access=1 but "consumes" the
currently executed TB, the tb_invalidate_phys_page_range call from
patch_instruction didn't work anymore.

Fix this by open-coding the required bits to restore the CPU state from
the current TB position before patching and resume execution on the
patched instruction afterward.

Signed-off-by: Jan Kiszka 
Tested-by: Hervé Poussineau 
Signed-off-by: Blue Swirl 
---
 hw/kvmvapic.c | 20 ++++++++++++++++----
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/hw/kvmvapic.c b/hw/kvmvapic.c
index dc111ee8e6..e04c4011d7 100644
--- a/hw/kvmvapic.c
+++ b/hw/kvmvapic.c
@@ -384,10 +384,13 @@ static void patch_call(VAPICROMState *s, CPUX86State *env, target_ulong ip,
 
 static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong ip)
 {
-    hwaddr paddr;
     VAPICHandlers *handlers;
     uint8_t opcode[2];
     uint32_t imm32;
+    TranslationBlock *current_tb;
+    target_ulong current_pc = 0;
+    target_ulong current_cs_base = 0;
+    int current_flags = 0;
 
     if (smp_cpus == 1) {
         handlers = &s->rom_state.up;
@@ -395,6 +398,13 @@ static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong i
         handlers = &s->rom_state.mp;
     }
 
+    if (!kvm_enabled()) {
+        current_tb = tb_find_pc(env->mem_io_pc);
+        cpu_restore_state(current_tb, env, env->mem_io_pc);
+        cpu_get_tb_cpu_state(env, ¤t_pc, ¤t_cs_base,
+                             ¤t_flags);
+    }
+
     pause_all_vcpus();
 
     cpu_memory_rw_debug(env, ip, opcode, sizeof(opcode), 0);
@@ -430,9 +440,11 @@ static void patch_instruction(VAPICROMState *s, CPUX86State *env, target_ulong i
 
     resume_all_vcpus();
 
-    paddr = cpu_get_phys_page_debug(env, ip);
-    paddr += ip & ~TARGET_PAGE_MASK;
-    tb_invalidate_phys_page_range(paddr, paddr + 1, 1);
+    if (!kvm_enabled()) {
+        env->current_tb = NULL;
+        tb_gen_code(env, current_pc, current_cs_base, current_flags, 1);
+        cpu_resume_from_signal(env, NULL);
+    }
 }
 
 void vapic_report_tpr_access(DeviceState *dev, void *cpu, target_ulong ip,

From 1f202568e0553b416483e5993f1bde219c22cf72 Mon Sep 17 00:00:00 2001
From: BALATON Zoltan 
Date: Sun, 4 Nov 2012 18:41:59 +0100
Subject: [PATCH 277/291] vmware_vga: Add back some info in local state
 partially reverting aa32b38c

Keep saving display surface parameters at init and using these cached
values instead of getting them when needed. Not sure why this is
needed (maybe due to the interaction with the vga device) but not
doing this broke the Xorg vmware driver at least.

Signed-off-by: BALATON Zoltan 
Tested-by: Jan Kiszka 
Signed-off-by: Blue Swirl 
---
 hw/vmware_vga.c | 30 +++++++++++++++++++++---------
 1 file changed, 21 insertions(+), 9 deletions(-)

diff --git a/hw/vmware_vga.c b/hw/vmware_vga.c
index 7c766fb3da..834588daf6 100644
--- a/hw/vmware_vga.c
+++ b/hw/vmware_vga.c
@@ -39,6 +39,8 @@ struct vmsvga_state_s {
     VGACommonState vga;
 
     int invalidated;
+    int depth;
+    int bypp;
     int enable;
     int config;
     struct {
@@ -55,6 +57,9 @@ struct vmsvga_state_s {
     int new_height;
     uint32_t guest;
     uint32_t svgaid;
+    uint32_t wred;
+    uint32_t wgreen;
+    uint32_t wblue;
     int syncing;
 
     MemoryRegion fifo_ram;
@@ -718,25 +723,25 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
         return SVGA_MAX_HEIGHT;
 
     case SVGA_REG_DEPTH:
-        return ds_get_depth(s->vga.ds);
+        return s->depth;
 
     case SVGA_REG_BITS_PER_PIXEL:
-        return ds_get_bits_per_pixel(s->vga.ds);
+        return (s->depth + 7) & ~7;
 
     case SVGA_REG_PSEUDOCOLOR:
         return 0x0;
 
     case SVGA_REG_RED_MASK:
-        return ds_get_rmask(s->vga.ds);
+        return s->wred;
 
     case SVGA_REG_GREEN_MASK:
-        return ds_get_gmask(s->vga.ds);
+        return s->wgreen;
 
     case SVGA_REG_BLUE_MASK:
-        return ds_get_bmask(s->vga.ds);
+        return s->wblue;
 
     case SVGA_REG_BYTES_PER_LINE:
-        return ds_get_bytes_per_pixel(s->vga.ds) * s->new_width;
+        return s->bypp * s->new_width;
 
     case SVGA_REG_FB_START: {
         struct pci_vmsvga_state_s *pci_vmsvga
@@ -801,7 +806,7 @@ static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
         return s->cursor.on;
 
     case SVGA_REG_HOST_BITS_PER_PIXEL:
-        return ds_get_bits_per_pixel(s->vga.ds);
+        return (s->depth + 7) & ~7;
 
     case SVGA_REG_SCRATCH_SIZE:
         return s->scratch_size;
@@ -864,7 +869,7 @@ static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
         break;
 
     case SVGA_REG_BITS_PER_PIXEL:
-        if (value != ds_get_bits_per_pixel(s->vga.ds)) {
+        if (value != s->depth) {
             printf("%s: Bad bits per pixel: %i bits\n", __func__, value);
             s->config = 0;
         }
@@ -1084,7 +1089,7 @@ static const VMStateDescription vmstate_vmware_vga_internal = {
     .minimum_version_id_old = 0,
     .post_load = vmsvga_post_load,
     .fields      = (VMStateField[]) {
-        VMSTATE_UNUSED(4), /* was depth */
+        VMSTATE_INT32_EQUAL(depth, struct vmsvga_state_s),
         VMSTATE_INT32(enable, struct vmsvga_state_s),
         VMSTATE_INT32(config, struct vmsvga_state_s),
         VMSTATE_INT32(cursor.id, struct vmsvga_state_s),
@@ -1137,6 +1142,13 @@ static void vmsvga_init(struct vmsvga_state_s *s,
     vga_common_init(&s->vga);
     vga_init(&s->vga, address_space, io, true);
     vmstate_register(NULL, 0, &vmstate_vga_common, &s->vga);
+    /* Save some values here in case they are changed later.
+     * This is suspicious and needs more though why it is needed. */
+    s->depth = ds_get_bits_per_pixel(s->vga.ds);
+    s->bypp = ds_get_bytes_per_pixel(s->vga.ds);
+    s->wred = ds_get_rmask(s->vga.ds);
+    s->wgreen = ds_get_gmask(s->vga.ds);
+    s->wblue = ds_get_bmask(s->vga.ds);
 }
 
 static uint64_t vmsvga_io_read(void *opaque, hwaddr addr, unsigned size)

From 253ecf83bcc658316bab3250401943d9b44c7898 Mon Sep 17 00:00:00 2001
From: Stefan Weil 
Date: Sun, 4 Nov 2012 21:42:08 +0100
Subject: [PATCH 278/291] qemu-timer: Fix compilation for non-POSIX hosts

A compiler warning is caused by the unused local function reinit_timers
on non-POSIX hosts. Include that function only for POSIX hosts.

Signed-off-by: Stefan Weil 
Signed-off-by: Blue Swirl 
---
 qemu-timer.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/qemu-timer.c b/qemu-timer.c
index 8d9cf38bb2..0d2bb94289 100644
--- a/qemu-timer.c
+++ b/qemu-timer.c
@@ -745,6 +745,7 @@ static void quit_timers(void)
     t->stop(t);
 }
 
+#ifdef CONFIG_POSIX
 static void reinit_timers(void)
 {
     struct qemu_alarm_timer *t = alarm_timer;
@@ -755,6 +756,7 @@ static void reinit_timers(void)
     }
     qemu_rearm_alarm_timer(t);
 }
+#endif /* CONFIG_POSIX */
 
 int init_timer_alarm(void)
 {

From 22bde7145495ad78c4bed8bb76d9401ec8d107b2 Mon Sep 17 00:00:00 2001
From: Jan Kiszka 
Date: Mon, 5 Nov 2012 16:45:56 +0100
Subject: [PATCH 279/291] memory: Reintroduce dirty flag to optimize changes on
 disabled regions

Cirrus is triggering this, e.g. during Win2k boot: Changes only on
disabled regions require no topology update when transaction depth drops
to 0 again.

Signed-off-by: Jan Kiszka 
Signed-off-by: Blue Swirl 
---
 memory.c | 15 +++++++++++++--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/memory.c b/memory.c
index 243cb23969..09e44b84ab 100644
--- a/memory.c
+++ b/memory.c
@@ -22,7 +22,8 @@
 
 #include "memory-internal.h"
 
-unsigned memory_region_transaction_depth = 0;
+static unsigned memory_region_transaction_depth;
+static bool memory_region_update_pending;
 static bool global_dirty_log = false;
 
 static QTAILQ_HEAD(memory_listeners, MemoryListener) memory_listeners
@@ -741,7 +742,8 @@ void memory_region_transaction_commit(void)
 
     assert(memory_region_transaction_depth);
     --memory_region_transaction_depth;
-    if (!memory_region_transaction_depth) {
+    if (!memory_region_transaction_depth && memory_region_update_pending) {
+        memory_region_update_pending = false;
         MEMORY_LISTENER_CALL_GLOBAL(begin, Forward);
 
         QTAILQ_FOREACH(as, &address_spaces, address_spaces_link) {
@@ -1060,6 +1062,7 @@ void memory_region_set_log(MemoryRegion *mr, bool log, unsigned client)
 
     memory_region_transaction_begin();
     mr->dirty_log_mask = (mr->dirty_log_mask & ~mask) | (log * mask);
+    memory_region_update_pending |= mr->enabled;
     memory_region_transaction_commit();
 }
 
@@ -1097,6 +1100,7 @@ void memory_region_set_readonly(MemoryRegion *mr, bool readonly)
     if (mr->readonly != readonly) {
         memory_region_transaction_begin();
         mr->readonly = readonly;
+        memory_region_update_pending |= mr->enabled;
         memory_region_transaction_commit();
     }
 }
@@ -1106,6 +1110,7 @@ void memory_region_rom_device_set_readable(MemoryRegion *mr, bool readable)
     if (mr->readable != readable) {
         memory_region_transaction_begin();
         mr->readable = readable;
+        memory_region_update_pending |= mr->enabled;
         memory_region_transaction_commit();
     }
 }
@@ -1248,6 +1253,7 @@ void memory_region_add_eventfd(MemoryRegion *mr,
     memmove(&mr->ioeventfds[i+1], &mr->ioeventfds[i],
             sizeof(*mr->ioeventfds) * (mr->ioeventfd_nb-1 - i));
     mr->ioeventfds[i] = mrfd;
+    memory_region_update_pending |= mr->enabled;
     memory_region_transaction_commit();
 }
 
@@ -1280,6 +1286,7 @@ void memory_region_del_eventfd(MemoryRegion *mr,
     --mr->ioeventfd_nb;
     mr->ioeventfds = g_realloc(mr->ioeventfds,
                                   sizeof(*mr->ioeventfds)*mr->ioeventfd_nb + 1);
+    memory_region_update_pending |= mr->enabled;
     memory_region_transaction_commit();
 }
 
@@ -1323,6 +1330,7 @@ static void memory_region_add_subregion_common(MemoryRegion *mr,
     }
     QTAILQ_INSERT_TAIL(&mr->subregions, subregion, subregions_link);
 done:
+    memory_region_update_pending |= mr->enabled && subregion->enabled;
     memory_region_transaction_commit();
 }
 
@@ -1353,6 +1361,7 @@ void memory_region_del_subregion(MemoryRegion *mr,
     assert(subregion->parent == mr);
     subregion->parent = NULL;
     QTAILQ_REMOVE(&mr->subregions, subregion, subregions_link);
+    memory_region_update_pending |= mr->enabled && subregion->enabled;
     memory_region_transaction_commit();
 }
 
@@ -1363,6 +1372,7 @@ void memory_region_set_enabled(MemoryRegion *mr, bool enabled)
     }
     memory_region_transaction_begin();
     mr->enabled = enabled;
+    memory_region_update_pending = true;
     memory_region_transaction_commit();
 }
 
@@ -1397,6 +1407,7 @@ void memory_region_set_alias_offset(MemoryRegion *mr, hwaddr offset)
 
     memory_region_transaction_begin();
     mr->alias_offset = offset;
+    memory_region_update_pending |= mr->enabled;
     memory_region_transaction_commit();
 }
 

From 7ea692b24055022248b895f2203a6ab1ad54859b Mon Sep 17 00:00:00 2001
From: Jan Kiszka 
Date: Wed, 31 Oct 2012 10:49:02 +0100
Subject: [PATCH 280/291] memory: Don't dump disabled regions

This makes "info mtree" output readable again.

Signed-off-by: Jan Kiszka 
Signed-off-by: Blue Swirl 
---
 memory.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/memory.c b/memory.c
index 09e44b84ab..741985385c 100644
--- a/memory.c
+++ b/memory.c
@@ -1601,7 +1601,7 @@ static void mtree_print_mr(fprintf_function mon_printf, void *f,
     const MemoryRegion *submr;
     unsigned int i;
 
-    if (!mr) {
+    if (!mr || !mr->enabled) {
         return;
     }
 

From a9523d14c47fbdecb319211afac00caa62d998a8 Mon Sep 17 00:00:00 2001
From: Catalin Patulea 
Date: Mon, 29 Oct 2012 03:45:51 -0400
Subject: [PATCH 281/291] tests/tcg: new test for i386 FPREM and FPREM1

This is setting the stage for a cleanup of FPREM and FPREM1 helpers while being
sure that they behave same as bare metal.

The test constructs operands using combinations of corner cases for the
floating-point bitfields and prints operands, result and FPU status word for
FPREM and FPREM1. The outputs can then be compared between bare metal and QEMU.
The 'run-test-i386-fprem' make target does just that.

Signed-off-by: Catalin Patulea 
Signed-off-by: Blue Swirl 
---
 tests/tcg/Makefile          |   9 +
 tests/tcg/test-i386-fprem.c | 353 ++++++++++++++++++++++++++++++++++++
 2 files changed, 362 insertions(+)
 create mode 100644 tests/tcg/test-i386-fprem.c

diff --git a/tests/tcg/Makefile b/tests/tcg/Makefile
index 80b1a4b529..24e3154cae 100644
--- a/tests/tcg/Makefile
+++ b/tests/tcg/Makefile
@@ -22,6 +22,7 @@ I386_TESTS=hello-i386 \
 	   testthread \
 	   sha1-i386 \
 	   test-i386 \
+	   test-i386-fprem \
 	   test-mmap \
 	   # runcom
 
@@ -55,6 +56,11 @@ run-test-i386: test-i386
 	-$(QEMU) test-i386 > test-i386.out
 	@if diff -u test-i386.ref test-i386.out ; then echo "Auto Test OK"; fi
 
+run-test-i386-fprem: test-i386-fprem
+	./test-i386-fprem > test-i386-fprem.ref
+	-$(QEMU) test-i386-fprem > test-i386-fprem.out
+	@if diff -u test-i386-fprem.ref test-i386-fprem.out ; then echo "Auto Test OK"; fi
+
 run-test-x86_64: test-x86_64
 	./test-x86_64 > test-x86_64.ref
 	-$(QEMU_X86_64) test-x86_64 > test-x86_64.out
@@ -93,6 +99,9 @@ test-i386: test-i386.c test-i386-code16.S test-i386-vm86.S \
 	$(CC_I386) $(QEMU_INCLUDES) $(CFLAGS) $(LDFLAGS) -o $@ \
               $(.
+ */
+#include "compiler.h"
+#include "osdep.h"
+#include 
+#include 
+
+/*
+ * Inspired by 's union ieee854_long_double, but with single
+ * long long mantissa fields and assuming little-endianness for simplicity.
+ */
+union float80u {
+    long double d;
+
+    /* This is the IEEE 854 double-extended-precision format.  */
+    struct {
+        unsigned long long mantissa:63;
+        unsigned int one:1;
+        unsigned int exponent:15;
+        unsigned int negative:1;
+        unsigned int empty:16;
+    } QEMU_PACKED ieee;
+
+    /* This is for NaNs in the IEEE 854 double-extended-precision format.  */
+    struct {
+        unsigned long long mantissa:62;
+        unsigned int quiet_nan:1;
+        unsigned int one:1;
+        unsigned int exponent:15;
+        unsigned int negative:1;
+        unsigned int empty:16;
+    } QEMU_PACKED ieee_nan;
+};
+
+#define IEEE854_LONG_DOUBLE_BIAS 0x3fff
+
+static const union float80u q_nan = {
+    .ieee_nan.negative = 0,  /* X */
+    .ieee_nan.exponent = 0x7fff,
+    .ieee_nan.one = 1,
+    .ieee_nan.quiet_nan = 1,
+    .ieee_nan.mantissa = 0,
+};
+
+static const union float80u s_nan = {
+    .ieee_nan.negative = 0,  /* X */
+    .ieee_nan.exponent = 0x7fff,
+    .ieee_nan.one = 1,
+    .ieee_nan.quiet_nan = 0,
+    .ieee_nan.mantissa = 1,  /* nonzero */
+};
+
+static const union float80u pos_inf = {
+    .ieee.negative = 0,
+    .ieee.exponent = 0x7fff,
+    .ieee.one = 1,
+    .ieee.mantissa = 0,
+};
+
+static const union float80u pseudo_pos_inf = {  /* "unsupported" */
+    .ieee.negative = 0,
+    .ieee.exponent = 0x7fff,
+    .ieee.one = 0,
+    .ieee.mantissa = 0,
+};
+
+static const union float80u pos_denorm = {
+    .ieee.negative = 0,
+    .ieee.exponent = 0,
+    .ieee.one = 0,
+    .ieee.mantissa = 1,
+};
+
+static const union float80u smallest_positive_norm = {
+    .ieee.negative = 0,
+    .ieee.exponent = 1,
+    .ieee.one = 1,
+    .ieee.mantissa = 0,
+};
+
+static void fninit()
+{
+    asm volatile ("fninit\n");
+}
+
+static long double fprem(long double a, long double b, uint16_t *sw)
+{
+    long double result;
+    asm volatile ("fprem\n"
+                  "fnstsw %1\n"
+                  : "=t" (result), "=m" (*sw)
+                  : "0" (a), "u" (b)
+                  : "st(1)");
+    return result;
+}
+
+static long double fprem1(long double a, long double b, uint16_t *sw)
+{
+    long double result;
+    asm volatile ("fprem1\n"
+                  "fnstsw %1\n"
+                  : "=t" (result), "=m" (*sw)
+                  : "0" (a), "u" (b)
+                  : "st(1)");
+    return result;
+}
+
+#define FPUS_IE (1 << 0)
+#define FPUS_DE (1 << 1)
+#define FPUS_ZE (1 << 2)
+#define FPUS_OE (1 << 3)
+#define FPUS_UE (1 << 4)
+#define FPUS_PE (1 << 5)
+#define FPUS_SF (1 << 6)
+#define FPUS_SE (1 << 7)
+#define FPUS_C0 (1 << 8)
+#define FPUS_C1 (1 << 9)
+#define FPUS_C2 (1 << 10)
+#define FPUS_TOP 0x3800
+#define FPUS_C3 (1 << 14)
+#define FPUS_B  (1 << 15)
+
+#define FPUS_EMASK 0x007f
+
+#define FPUC_EM 0x3f
+
+static void psw(uint16_t sw)
+{
+    printf("SW:  C3 TopC2C1C0\n");
+    printf("SW: %c %d %3d %d %d %d %c %c %c %c %c %c %c %c\n",
+           sw & FPUS_B ? 'B' : 'b',
+           !!(sw & FPUS_C3),
+           (sw & FPUS_TOP) >> 11,
+           !!(sw & FPUS_C2),
+           !!(sw & FPUS_C1),
+           !!(sw & FPUS_C0),
+           (sw & FPUS_SE) ? 'S' : 's',
+           (sw & FPUS_SF) ? 'F' : 'f',
+           (sw & FPUS_PE) ? 'P' : 'p',
+           (sw & FPUS_UE) ? 'U' : 'u',
+           (sw & FPUS_OE) ? 'O' : 'o',
+           (sw & FPUS_ZE) ? 'Z' : 'z',
+           (sw & FPUS_DE) ? 'D' : 'd',
+           (sw & FPUS_IE) ? 'I' : 'i');
+}
+
+static void do_fprem(long double a, long double b)
+{
+    const union float80u au = {.d = a};
+    const union float80u bu = {.d = b};
+    union float80u ru;
+    uint16_t sw;
+
+    printf("A: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n",
+           au.ieee.negative, au.ieee.exponent, au.ieee.one,
+           au.ieee_nan.quiet_nan, (unsigned long long)au.ieee.mantissa,
+           a);
+    printf("B: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n",
+           bu.ieee.negative, bu.ieee.exponent, bu.ieee.one,
+           bu.ieee_nan.quiet_nan, (unsigned long long)bu.ieee.mantissa,
+           b);
+    fflush(stdout);
+
+    fninit();
+    ru.d = fprem(a, b, &sw);
+    psw(sw);
+
+    printf("R : S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n",
+           ru.ieee.negative, ru.ieee.exponent, ru.ieee.one,
+           ru.ieee_nan.quiet_nan, (unsigned long long)ru.ieee.mantissa,
+           ru.d);
+
+    fninit();
+    ru.d = fprem1(a, b, &sw);
+    psw(sw);
+
+    printf("R1: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n",
+           ru.ieee.negative, ru.ieee.exponent, ru.ieee.one,
+           ru.ieee_nan.quiet_nan, (unsigned long long)ru.ieee.mantissa,
+           ru.d);
+
+    printf("\n");
+}
+
+static void do_fprem_stack_underflow(void)
+{
+    const long double a = 1.0;
+    union float80u ru;
+    uint16_t sw;
+
+    fninit();
+    asm volatile ("fprem\n"
+                  "fnstsw %1\n"
+                  : "=t" (ru.d), "=m" (sw)
+                  : "0" (a)
+                  : "st(1)");
+    psw(sw);
+
+    printf("R: S=%d Exp=%04x Int=%d (QNaN=%d) Sig=%016llx (%.06Le)\n",
+           ru.ieee.negative, ru.ieee.exponent, ru.ieee.one,
+           ru.ieee_nan.quiet_nan, (unsigned long long)ru.ieee.mantissa,
+           ru.d);
+    printf("\n");
+}
+
+static void test_fprem_cases(void)
+{
+    printf("= stack underflow =\n");
+    do_fprem_stack_underflow();
+
+    printf("= invalid operation =\n");
+    do_fprem(s_nan.d, 1.0);
+    do_fprem(1.0, 0.0);
+    do_fprem(pos_inf.d, 1.0);
+    do_fprem(pseudo_pos_inf.d, 1.0);
+
+    printf("= denormal =\n");
+    do_fprem(pos_denorm.d, 1.0);
+    do_fprem(1.0, pos_denorm.d);
+
+    /* printf("= underflow =\n"); */
+    /* TODO: Is there a case where FPREM raises underflow? */
+}
+
+static void test_fprem_pairs(void)
+{
+    unsigned long long count;
+
+    unsigned int negative_index_a = 0;
+    unsigned int negative_index_b = 0;
+    static const unsigned int negative_values[] = {
+        0,
+        1,
+    };
+
+    unsigned int exponent_index_a = 0;
+    unsigned int exponent_index_b = 0;
+    static const unsigned int exponent_values[] = {
+        0,
+        1,
+        2,
+        IEEE854_LONG_DOUBLE_BIAS - 1,
+        IEEE854_LONG_DOUBLE_BIAS,
+        IEEE854_LONG_DOUBLE_BIAS + 1,
+        0x7ffd,
+        0x7ffe,
+        0x7fff,
+    };
+
+    unsigned int one_index_a = 0;
+    unsigned int one_index_b = 0;
+    static const unsigned int one_values[] = {
+        0,
+        1,
+    };
+
+    unsigned int quiet_nan_index_a = 0;
+    unsigned int quiet_nan_index_b = 0;
+    static const unsigned int quiet_nan_values[] = {
+        0,
+        1,
+    };
+
+    unsigned int mantissa_index_a = 0;
+    unsigned int mantissa_index_b = 0;
+    static const unsigned long long mantissa_values[] = {
+        0,
+        1,
+        2,
+        0x3ffffffffffffffdULL,
+        0x3ffffffffffffffeULL,
+        0x3fffffffffffffffULL,
+    };
+
+    for (count = 0; ; ++count) {
+#define INIT_FIELD(var, field) \
+            .ieee_nan.field = field##_values[field##_index_##var]
+        const union float80u a = {
+            INIT_FIELD(a, negative),
+            INIT_FIELD(a, exponent),
+            INIT_FIELD(a, one),
+            INIT_FIELD(a, quiet_nan),
+            INIT_FIELD(a, mantissa),
+        };
+        const union float80u b = {
+            INIT_FIELD(b, negative),
+            INIT_FIELD(b, exponent),
+            INIT_FIELD(b, one),
+            INIT_FIELD(b, quiet_nan),
+            INIT_FIELD(b, mantissa),
+        };
+#undef INIT_FIELD
+
+        do_fprem(a.d, b.d);
+
+        int carry = 1;
+#define CARRY_INTO(var, field) do { \
+            if (carry) { \
+                if (++field##_index_##var == ARRAY_SIZE(field##_values)) { \
+                    field##_index_##var = 0; \
+                } else { \
+                    carry = 0; \
+                } \
+            } \
+        } while (0)
+        CARRY_INTO(b, mantissa);
+        CARRY_INTO(b, quiet_nan);
+        CARRY_INTO(b, one);
+        CARRY_INTO(b, exponent);
+        CARRY_INTO(b, negative);
+        CARRY_INTO(a, mantissa);
+        CARRY_INTO(a, quiet_nan);
+        CARRY_INTO(a, one);
+        CARRY_INTO(a, exponent);
+        CARRY_INTO(a, negative);
+#undef CARRY_INTO
+
+        if (carry) {
+            break;
+        }
+    }
+
+    fprintf(stderr, "test-i386-fprem: tested %llu cases\n", count);
+}
+
+int main(int argc, char **argv)
+{
+    test_fprem_cases();
+    test_fprem_pairs();
+    return 0;
+}

From 4d4d9b3adb0e36e75cf9b2126ee1d01b1d59f8a1 Mon Sep 17 00:00:00 2001
From: Blue Swirl 
Date: Sat, 13 Oct 2012 18:46:05 +0000
Subject: [PATCH 282/291] m48t59: remove unused m48t59_set_addr

Signed-off-by: Blue Swirl 
---
 hw/m48t59.c | 7 -------
 hw/nvram.h  | 1 -
 2 files changed, 8 deletions(-)

diff --git a/hw/m48t59.c b/hw/m48t59.c
index 9e8e692669..7da7e7c822 100644
--- a/hw/m48t59.c
+++ b/hw/m48t59.c
@@ -468,13 +468,6 @@ uint32_t m48t59_read (void *opaque, uint32_t addr)
     return retval;
 }
 
-void m48t59_set_addr (void *opaque, uint32_t addr)
-{
-    M48t59State *NVRAM = opaque;
-
-    NVRAM->addr = addr;
-}
-
 void m48t59_toggle_lock (void *opaque, int lock)
 {
     M48t59State *NVRAM = opaque;
diff --git a/hw/nvram.h b/hw/nvram.h
index 72363ced42..59337faaad 100644
--- a/hw/nvram.h
+++ b/hw/nvram.h
@@ -30,6 +30,5 @@ M48t59State *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
                              int type);
 M48t59State *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
                          uint32_t io_base, uint16_t size, int type);
-void m48t59_set_addr (void *opaque, uint32_t addr);
 
 #endif /* !NVRAM_H */

From e62774c41006bc8072579515b9f6782b56c33bd1 Mon Sep 17 00:00:00 2001
From: Blue Swirl 
Date: Sat, 13 Oct 2012 18:49:20 +0000
Subject: [PATCH 283/291] sun4c: remove unused functions

Signed-off-by: Blue Swirl 
---
 hw/sun4c_intctl.c | 23 -----------------------
 hw/sun4m.h        |  4 ----
 2 files changed, 27 deletions(-)

diff --git a/hw/sun4c_intctl.c b/hw/sun4c_intctl.c
index 8cd70ab64c..702e9f5444 100644
--- a/hw/sun4c_intctl.c
+++ b/hw/sun4c_intctl.c
@@ -94,29 +94,6 @@ static const MemoryRegionOps sun4c_intctl_mem_ops = {
     },
 };
 
-void sun4c_pic_info(Monitor *mon, void *opaque)
-{
-    Sun4c_INTCTLState *s = opaque;
-
-    monitor_printf(mon, "master: pending 0x%2.2x, enabled 0x%2.2x\n",
-                   s->pending, s->reg);
-}
-
-void sun4c_irq_info(Monitor *mon, void *opaque)
-{
-#ifndef DEBUG_IRQ_COUNT
-    monitor_printf(mon, "irq statistic code not compiled.\n");
-#else
-    Sun4c_INTCTLState *s = opaque;
-    int64_t count;
-
-    monitor_printf(mon, "IRQ statistics:\n");
-    count = s->irq_count;
-    if (count > 0)
-        monitor_printf(mon, " %" PRId64 "\n", count);
-#endif
-}
-
 static const uint32_t intbit_to_level[] = { 0, 1, 4, 6, 8, 10, 0, 14, };
 
 static void sun4c_check_interrupts(void *opaque)
diff --git a/hw/sun4m.h b/hw/sun4m.h
index a8c3133703..47eb945f07 100644
--- a/hw/sun4m.h
+++ b/hw/sun4m.h
@@ -26,10 +26,6 @@ static inline void sparc_iommu_memory_write(void *opaque,
 void slavio_pic_info(Monitor *mon, DeviceState *dev);
 void slavio_irq_info(Monitor *mon, DeviceState *dev);
 
-/* sun4c_intctl.c */
-void sun4c_pic_info(Monitor *mon, void *opaque);
-void sun4c_irq_info(Monitor *mon, void *opaque);
-
 /* sun4m.c */
 void sun4m_pic_info(Monitor *mon);
 void sun4m_irq_info(Monitor *mon);

From 036208c9ab50b0910c24b28a440c15e66e8a2652 Mon Sep 17 00:00:00 2001
From: Blue Swirl 
Date: Sat, 13 Oct 2012 18:52:23 +0000
Subject: [PATCH 284/291] slirp: remove unused function u_sleep

Signed-off-by: Blue Swirl 
---
 slirp/misc.c | 14 --------------
 slirp/misc.h |  1 -
 2 files changed, 15 deletions(-)

diff --git a/slirp/misc.c b/slirp/misc.c
index 0bee864337..664532a663 100644
--- a/slirp/misc.c
+++ b/slirp/misc.c
@@ -253,20 +253,6 @@ void lprint(const char *format, ...)
     va_end(args);
 }
 
-void
-u_sleep(int usec)
-{
-	struct timeval t;
-	fd_set fdset;
-
-	FD_ZERO(&fdset);
-
-	t.tv_sec = 0;
-	t.tv_usec = usec * 1000;
-
-	select(0, &fdset, &fdset, &fdset, &t);
-}
-
 void slirp_connection_info(Slirp *slirp, Monitor *mon)
 {
     const char * const tcpstates[] = {
diff --git a/slirp/misc.h b/slirp/misc.h
index ed40a103c5..cc36aeb959 100644
--- a/slirp/misc.h
+++ b/slirp/misc.h
@@ -64,7 +64,6 @@ void snooze_hup(int);
 void snooze(void);
 void relay(int);
 void add_emu(char *);
-void u_sleep(int);
 void fd_nonblock(int);
 void fd_block(int);
 int rsh_exec(struct socket *, struct socket *, char *, char *, char *);

From f4359b9ffe895fda6d1ec3dd441cb8a208fb4dce Mon Sep 17 00:00:00 2001
From: Blue Swirl 
Date: Sat, 8 Sep 2012 12:40:00 +0000
Subject: [PATCH 285/291] disas: avoid using cpu_single_env

Pass around CPUArchState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl 
Acked-by: Richard Henderson 
Acked-by: Aurelien Jarno 
Acked-by: Guan Xuetao 
---
 disas.c                       | 149 ++++++++++++++++++----------------
 disas.h                       |   3 +-
 qemu-log.h                    |   6 +-
 target-alpha/translate.c      |   2 +-
 target-arm/translate.c        |   2 +-
 target-cris/translate.c       |   2 +-
 target-i386/translate.c       |   2 +-
 target-lm32/translate.c       |   2 +-
 target-m68k/translate.c       |   2 +-
 target-microblaze/translate.c |   2 +-
 target-mips/translate.c       |   2 +-
 target-openrisc/translate.c   |   2 +-
 target-ppc/translate.c        |   2 +-
 target-s390x/translate.c      |   2 +-
 target-sh4/translate.c        |   2 +-
 target-sparc/translate.c      |   2 +-
 target-unicore32/translate.c  |   2 +-
 17 files changed, 100 insertions(+), 86 deletions(-)

diff --git a/disas.c b/disas.c
index b801c8f51d..6da1dd09f4 100644
--- a/disas.c
+++ b/disas.c
@@ -7,6 +7,11 @@
 #include "cpu.h"
 #include "disas.h"
 
+typedef struct CPUDebug {
+    struct disassemble_info info;
+    CPUArchState *env;
+} CPUDebug;
+
 /* Filled in by elfload.c.  Simplistic, but will do for now. */
 struct syminfo *syminfos = NULL;
 
@@ -32,7 +37,9 @@ target_read_memory (bfd_vma memaddr,
                     int length,
                     struct disassemble_info *info)
 {
-    cpu_memory_rw_debug(cpu_single_env, memaddr, myaddr, length, 0);
+    CPUDebug *s = container_of(info, CPUDebug, info);
+
+    cpu_memory_rw_debug(s->env, memaddr, myaddr, length, 0);
     return 0;
 }
 
@@ -158,32 +165,35 @@ print_insn_thumb1(bfd_vma pc, disassemble_info *info)
     ppc  - nonzero means little endian
     other targets - unused
  */
-void target_disas(FILE *out, target_ulong code, target_ulong size, int flags)
+void target_disas(FILE *out, CPUArchState *env, target_ulong code,
+                  target_ulong size, int flags)
 {
     target_ulong pc;
     int count;
-    struct disassemble_info disasm_info;
+    CPUDebug s;
     int (*print_insn)(bfd_vma pc, disassemble_info *info);
 
-    INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf);
+    INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
 
-    disasm_info.read_memory_func = target_read_memory;
-    disasm_info.buffer_vma = code;
-    disasm_info.buffer_length = size;
-    disasm_info.print_address_func = generic_print_target_address;
+    s.env = env;
+    s.info.read_memory_func = target_read_memory;
+    s.info.buffer_vma = code;
+    s.info.buffer_length = size;
+    s.info.print_address_func = generic_print_target_address;
 
 #ifdef TARGET_WORDS_BIGENDIAN
-    disasm_info.endian = BFD_ENDIAN_BIG;
+    s.info.endian = BFD_ENDIAN_BIG;
 #else
-    disasm_info.endian = BFD_ENDIAN_LITTLE;
+    s.info.endian = BFD_ENDIAN_LITTLE;
 #endif
 #if defined(TARGET_I386)
-    if (flags == 2)
-        disasm_info.mach = bfd_mach_x86_64;
-    else if (flags == 1)
-        disasm_info.mach = bfd_mach_i386_i8086;
-    else
-        disasm_info.mach = bfd_mach_i386_i386;
+    if (flags == 2) {
+        s.info.mach = bfd_mach_x86_64;
+    } else if (flags == 1) {
+        s.info.mach = bfd_mach_i386_i8086;
+    } else {
+        s.info.mach = bfd_mach_i386_i386;
+    }
     print_insn = print_insn_i386;
 #elif defined(TARGET_ARM)
     if (flags & 1) {
@@ -193,27 +203,28 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags)
     }
     if (flags & 2) {
 #ifdef TARGET_WORDS_BIGENDIAN
-        disasm_info.endian = BFD_ENDIAN_LITTLE;
+        s.info.endian = BFD_ENDIAN_LITTLE;
 #else
-        disasm_info.endian = BFD_ENDIAN_BIG;
+        s.info.endian = BFD_ENDIAN_BIG;
 #endif
     }
 #elif defined(TARGET_SPARC)
     print_insn = print_insn_sparc;
 #ifdef TARGET_SPARC64
-    disasm_info.mach = bfd_mach_sparc_v9b;
+    s.info.mach = bfd_mach_sparc_v9b;
 #endif
 #elif defined(TARGET_PPC)
-    if (flags >> 16)
-        disasm_info.endian = BFD_ENDIAN_LITTLE;
+    if (flags >> 16) {
+        s.info.endian = BFD_ENDIAN_LITTLE;
+    }
     if (flags & 0xFFFF) {
         /* If we have a precise definitions of the instructions set, use it */
-        disasm_info.mach = flags & 0xFFFF;
+        s.info.mach = flags & 0xFFFF;
     } else {
 #ifdef TARGET_PPC64
-        disasm_info.mach = bfd_mach_ppc64;
+        s.info.mach = bfd_mach_ppc64;
 #else
-        disasm_info.mach = bfd_mach_ppc;
+        s.info.mach = bfd_mach_ppc;
 #endif
     }
     print_insn = print_insn_ppc;
@@ -226,27 +237,27 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags)
     print_insn = print_insn_little_mips;
 #endif
 #elif defined(TARGET_SH4)
-    disasm_info.mach = bfd_mach_sh4;
+    s.info.mach = bfd_mach_sh4;
     print_insn = print_insn_sh;
 #elif defined(TARGET_ALPHA)
-    disasm_info.mach = bfd_mach_alpha_ev6;
+    s.info.mach = bfd_mach_alpha_ev6;
     print_insn = print_insn_alpha;
 #elif defined(TARGET_CRIS)
     if (flags != 32) {
-        disasm_info.mach = bfd_mach_cris_v0_v10;
+        s.info.mach = bfd_mach_cris_v0_v10;
         print_insn = print_insn_crisv10;
     } else {
-        disasm_info.mach = bfd_mach_cris_v32;
+        s.info.mach = bfd_mach_cris_v32;
         print_insn = print_insn_crisv32;
     }
 #elif defined(TARGET_S390X)
-    disasm_info.mach = bfd_mach_s390_64;
+    s.info.mach = bfd_mach_s390_64;
     print_insn = print_insn_s390;
 #elif defined(TARGET_MICROBLAZE)
-    disasm_info.mach = bfd_arch_microblaze;
+    s.info.mach = bfd_arch_microblaze;
     print_insn = print_insn_microblaze;
 #elif defined(TARGET_LM32)
-    disasm_info.mach = bfd_mach_lm32;
+    s.info.mach = bfd_mach_lm32;
     print_insn = print_insn_lm32;
 #else
     fprintf(out, "0x" TARGET_FMT_lx
@@ -256,14 +267,14 @@ void target_disas(FILE *out, target_ulong code, target_ulong size, int flags)
 
     for (pc = code; size > 0; pc += count, size -= count) {
 	fprintf(out, "0x" TARGET_FMT_lx ":  ", pc);
-	count = print_insn(pc, &disasm_info);
+	count = print_insn(pc, &s.info);
 #if 0
         {
             int i;
             uint8_t b;
             fprintf(out, " {");
             for(i = 0; i < count; i++) {
-                target_read_memory(pc + i, &b, 1, &disasm_info);
+                target_read_memory(pc + i, &b, 1, &s.info);
                 fprintf(out, " %02x", b);
             }
             fprintf(out, " }");
@@ -287,28 +298,28 @@ void disas(FILE *out, void *code, unsigned long size)
 {
     uintptr_t pc;
     int count;
-    struct disassemble_info disasm_info;
+    CPUDebug s;
     int (*print_insn)(bfd_vma pc, disassemble_info *info);
 
-    INIT_DISASSEMBLE_INFO(disasm_info, out, fprintf);
-    disasm_info.print_address_func = generic_print_host_address;
+    INIT_DISASSEMBLE_INFO(s.info, out, fprintf);
+    s.info.print_address_func = generic_print_host_address;
 
-    disasm_info.buffer = code;
-    disasm_info.buffer_vma = (uintptr_t)code;
-    disasm_info.buffer_length = size;
+    s.info.buffer = code;
+    s.info.buffer_vma = (uintptr_t)code;
+    s.info.buffer_length = size;
 
 #ifdef HOST_WORDS_BIGENDIAN
-    disasm_info.endian = BFD_ENDIAN_BIG;
+    s.info.endian = BFD_ENDIAN_BIG;
 #else
-    disasm_info.endian = BFD_ENDIAN_LITTLE;
+    s.info.endian = BFD_ENDIAN_LITTLE;
 #endif
 #if defined(CONFIG_TCG_INTERPRETER)
     print_insn = print_insn_tci;
 #elif defined(__i386__)
-    disasm_info.mach = bfd_mach_i386_i386;
+    s.info.mach = bfd_mach_i386_i386;
     print_insn = print_insn_i386;
 #elif defined(__x86_64__)
-    disasm_info.mach = bfd_mach_x86_64;
+    s.info.mach = bfd_mach_x86_64;
     print_insn = print_insn_i386;
 #elif defined(_ARCH_PPC)
     print_insn = print_insn_ppc;
@@ -316,7 +327,7 @@ void disas(FILE *out, void *code, unsigned long size)
     print_insn = print_insn_alpha;
 #elif defined(__sparc__)
     print_insn = print_insn_sparc;
-    disasm_info.mach = bfd_mach_sparc_v9b;
+    s.info.mach = bfd_mach_sparc_v9b;
 #elif defined(__arm__)
     print_insn = print_insn_arm;
 #elif defined(__MIPSEB__)
@@ -338,7 +349,7 @@ void disas(FILE *out, void *code, unsigned long size)
 #endif
     for (pc = (uintptr_t)code; size > 0; pc += count, size -= count) {
         fprintf(out, "0x%08" PRIxPTR ":  ", pc);
-	count = print_insn(pc, &disasm_info);
+        count = print_insn(pc, &s.info);
 	fprintf(out, "\n");
 	if (count < 0)
 	    break;
@@ -366,16 +377,17 @@ const char *lookup_symbol(target_ulong orig_addr)
 #include "monitor.h"
 
 static int monitor_disas_is_physical;
-static CPUArchState *monitor_disas_env;
 
 static int
 monitor_read_memory (bfd_vma memaddr, bfd_byte *myaddr, int length,
                      struct disassemble_info *info)
 {
+    CPUDebug *s = container_of(info, CPUDebug, info);
+
     if (monitor_disas_is_physical) {
         cpu_physical_memory_read(memaddr, myaddr, length);
     } else {
-        cpu_memory_rw_debug(monitor_disas_env, memaddr,myaddr, length, 0);
+        cpu_memory_rw_debug(s->env, memaddr,myaddr, length, 0);
     }
     return 0;
 }
@@ -394,30 +406,31 @@ void monitor_disas(Monitor *mon, CPUArchState *env,
                    target_ulong pc, int nb_insn, int is_physical, int flags)
 {
     int count, i;
-    struct disassemble_info disasm_info;
+    CPUDebug s;
     int (*print_insn)(bfd_vma pc, disassemble_info *info);
 
-    INIT_DISASSEMBLE_INFO(disasm_info, (FILE *)mon, monitor_fprintf);
+    INIT_DISASSEMBLE_INFO(s.info, (FILE *)mon, monitor_fprintf);
 
-    monitor_disas_env = env;
+    s.env = env;
     monitor_disas_is_physical = is_physical;
-    disasm_info.read_memory_func = monitor_read_memory;
-    disasm_info.print_address_func = generic_print_target_address;
+    s.info.read_memory_func = monitor_read_memory;
+    s.info.print_address_func = generic_print_target_address;
 
-    disasm_info.buffer_vma = pc;
+    s.info.buffer_vma = pc;
 
 #ifdef TARGET_WORDS_BIGENDIAN
-    disasm_info.endian = BFD_ENDIAN_BIG;
+    s.info.endian = BFD_ENDIAN_BIG;
 #else
-    disasm_info.endian = BFD_ENDIAN_LITTLE;
+    s.info.endian = BFD_ENDIAN_LITTLE;
 #endif
 #if defined(TARGET_I386)
-    if (flags == 2)
-        disasm_info.mach = bfd_mach_x86_64;
-    else if (flags == 1)
-        disasm_info.mach = bfd_mach_i386_i8086;
-    else
-        disasm_info.mach = bfd_mach_i386_i386;
+    if (flags == 2) {
+        s.info.mach = bfd_mach_x86_64;
+    } else if (flags == 1) {
+        s.info.mach = bfd_mach_i386_i8086;
+    } else {
+        s.info.mach = bfd_mach_i386_i386;
+    }
     print_insn = print_insn_i386;
 #elif defined(TARGET_ARM)
     print_insn = print_insn_arm;
@@ -426,13 +439,13 @@ void monitor_disas(Monitor *mon, CPUArchState *env,
 #elif defined(TARGET_SPARC)
     print_insn = print_insn_sparc;
 #ifdef TARGET_SPARC64
-    disasm_info.mach = bfd_mach_sparc_v9b;
+    s.info.mach = bfd_mach_sparc_v9b;
 #endif
 #elif defined(TARGET_PPC)
 #ifdef TARGET_PPC64
-    disasm_info.mach = bfd_mach_ppc64;
+    s.info.mach = bfd_mach_ppc64;
 #else
-    disasm_info.mach = bfd_mach_ppc;
+    s.info.mach = bfd_mach_ppc;
 #endif
     print_insn = print_insn_ppc;
 #elif defined(TARGET_M68K)
@@ -444,13 +457,13 @@ void monitor_disas(Monitor *mon, CPUArchState *env,
     print_insn = print_insn_little_mips;
 #endif
 #elif defined(TARGET_SH4)
-    disasm_info.mach = bfd_mach_sh4;
+    s.info.mach = bfd_mach_sh4;
     print_insn = print_insn_sh;
 #elif defined(TARGET_S390X)
-    disasm_info.mach = bfd_mach_s390_64;
+    s.info.mach = bfd_mach_s390_64;
     print_insn = print_insn_s390;
 #elif defined(TARGET_LM32)
-    disasm_info.mach = bfd_mach_lm32;
+    s.info.mach = bfd_mach_lm32;
     print_insn = print_insn_lm32;
 #else
     monitor_printf(mon, "0x" TARGET_FMT_lx
@@ -460,7 +473,7 @@ void monitor_disas(Monitor *mon, CPUArchState *env,
 
     for(i = 0; i < nb_insn; i++) {
 	monitor_printf(mon, "0x" TARGET_FMT_lx ":  ", pc);
-	count = print_insn(pc, &disasm_info);
+        count = print_insn(pc, &s.info);
 	monitor_printf(mon, "\n");
 	if (count < 0)
 	    break;
diff --git a/disas.h b/disas.h
index a8a09740db..c13ca9a3a4 100644
--- a/disas.h
+++ b/disas.h
@@ -6,7 +6,8 @@
 #ifdef NEED_CPU_H
 /* Disassemble this for me please... (debugging). */
 void disas(FILE *out, void *code, unsigned long size);
-void target_disas(FILE *out, target_ulong code, target_ulong size, int flags);
+void target_disas(FILE *out, CPUArchState *env, target_ulong code,
+                  target_ulong size, int flags);
 
 void monitor_disas(Monitor *mon, CPUArchState *env,
                    target_ulong pc, int nb_insn, int is_physical, int flags);
diff --git a/qemu-log.h b/qemu-log.h
index ce6bb095b3..344eca3f1b 100644
--- a/qemu-log.h
+++ b/qemu-log.h
@@ -84,10 +84,10 @@ static inline void log_cpu_state_mask(int mask, CPUArchState *env1, int flags)
 }
 
 /* disas() and target_disas() to qemu_logfile: */
-static inline void log_target_disas(target_ulong start, target_ulong len,
-                                    int flags)
+static inline void log_target_disas(CPUArchState *env, target_ulong start,
+                                    target_ulong len, int flags)
 {
-    target_disas(qemu_logfile, start, len, flags);
+    target_disas(qemu_logfile, env, start, len, flags);
 }
 
 static inline void log_disas(void *code, unsigned long size)
diff --git a/target-alpha/translate.c b/target-alpha/translate.c
index f707d8deb9..8c4dd021f3 100644
--- a/target-alpha/translate.c
+++ b/target-alpha/translate.c
@@ -3477,7 +3477,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env,
 #ifdef DEBUG_DISAS
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("IN: %s\n", lookup_symbol(pc_start));
-        log_target_disas(pc_start, ctx.pc - pc_start, 1);
+        log_target_disas(env, pc_start, ctx.pc - pc_start, 1);
         qemu_log("\n");
     }
 #endif
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 25433da037..7d8f8e5edc 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -9968,7 +9968,7 @@ done_generating:
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("----------------\n");
         qemu_log("IN: %s\n", lookup_symbol(pc_start));
-        log_target_disas(pc_start, dc->pc - pc_start,
+        log_target_disas(env, pc_start, dc->pc - pc_start,
                          dc->thumb | (dc->bswap_code << 1));
         qemu_log("\n");
     }
diff --git a/target-cris/translate.c b/target-cris/translate.c
index 755de659df..f8ebc43a86 100644
--- a/target-cris/translate.c
+++ b/target-cris/translate.c
@@ -3413,7 +3413,7 @@ gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb,
 #ifdef DEBUG_DISAS
 #if !DISAS_CRIS
 	if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
-		log_target_disas(pc_start, dc->pc - pc_start,
+                log_target_disas(env, pc_start, dc->pc - pc_start,
                                  dc->env->pregs[PR_VR]);
 		qemu_log("\nisize=%d osize=%td\n",
 			dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
diff --git a/target-i386/translate.c b/target-i386/translate.c
index ee7585044b..bf52eefa55 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -8047,7 +8047,7 @@ static inline void gen_intermediate_code_internal(CPUX86State *env,
         else
 #endif
             disas_flags = !dc->code32;
-        log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
+        log_target_disas(env, pc_start, pc_ptr - pc_start, disas_flags);
         qemu_log("\n");
     }
 #endif
diff --git a/target-lm32/translate.c b/target-lm32/translate.c
index 77c2866611..3307daaf11 100644
--- a/target-lm32/translate.c
+++ b/target-lm32/translate.c
@@ -1120,7 +1120,7 @@ static void gen_intermediate_code_internal(CPULM32State *env,
 #ifdef DEBUG_DISAS
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("\n");
-        log_target_disas(pc_start, dc->pc - pc_start, 0);
+        log_target_disas(env, pc_start, dc->pc - pc_start, 0);
         qemu_log("\nisize=%d osize=%td\n",
             dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
     }
diff --git a/target-m68k/translate.c b/target-m68k/translate.c
index 451ef7410f..1430d4c991 100644
--- a/target-m68k/translate.c
+++ b/target-m68k/translate.c
@@ -3070,7 +3070,7 @@ gen_intermediate_code_internal(CPUM68KState *env, TranslationBlock *tb,
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("----------------\n");
         qemu_log("IN: %s\n", lookup_symbol(pc_start));
-        log_target_disas(pc_start, dc->pc - pc_start, 0);
+        log_target_disas(env, pc_start, dc->pc - pc_start, 0);
         qemu_log("\n");
     }
 #endif
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 6f27c24b76..13fd73574b 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -1913,7 +1913,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb,
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("\n");
 #if DISAS_GNU
-        log_target_disas(pc_start, dc->pc - pc_start, 0);
+        log_target_disas(env, pc_start, dc->pc - pc_start, 0);
 #endif
         qemu_log("\nisize=%d osize=%td\n",
             dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 8175da05d0..df92781b2c 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -15640,7 +15640,7 @@ done_generating:
     LOG_DISAS("\n");
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("IN: %s\n", lookup_symbol(pc_start));
-        log_target_disas(pc_start, ctx.pc - pc_start, 0);
+        log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
         qemu_log("\n");
     }
 #endif
diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c
index e2cad3ad42..ff2feb48db 100644
--- a/target-openrisc/translate.c
+++ b/target-openrisc/translate.c
@@ -1797,7 +1797,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu,
 #ifdef DEBUG_DISAS
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("\n");
-        log_target_disas(pc_start, dc->pc - pc_start, 0);
+        log_target_disas(&cpu->env, pc_start, dc->pc - pc_start, 0);
         qemu_log("\nisize=%d osize=%td\n",
             dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
     }
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 56725e6a61..f0d49eea3f 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -9790,7 +9790,7 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env,
         flags = env->bfd_mach;
         flags |= ctx.le_mode << 16;
         qemu_log("IN: %s\n", lookup_symbol(pc_start));
-        log_target_disas(pc_start, ctx.nip - pc_start, flags);
+        log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
         qemu_log("\n");
     }
 #endif
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index db464cc073..c6267a8769 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -5220,7 +5220,7 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env,
 #if defined(S390X_DEBUG_DISAS)
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("IN: %s\n", lookup_symbol(pc_start));
-        log_target_disas(pc_start, dc.pc - pc_start, 1);
+        log_target_disas(env, pc_start, dc.pc - pc_start, 1);
         qemu_log("\n");
     }
 #endif
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index 9d955eb204..2ae7f03d35 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
@@ -2070,7 +2070,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb,
 #ifdef DEBUG_DISAS
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
 	qemu_log("IN:\n");	/* , lookup_symbol(pc_start)); */
-	log_target_disas(pc_start, ctx.pc - pc_start, 0);
+        log_target_disas(env, pc_start, ctx.pc - pc_start, 0);
 	qemu_log("\n");
     }
 #endif
diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 9e46f1424b..1d8b8ad9b9 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -5353,7 +5353,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb,
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("--------------\n");
         qemu_log("IN: %s\n", lookup_symbol(pc_start));
-        log_target_disas(pc_start, last_pc + 4 - pc_start, 0);
+        log_target_disas(env, pc_start, last_pc + 4 - pc_start, 0);
         qemu_log("\n");
     }
 #endif
diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c
index c3cdafa18e..57b18ac0c6 100644
--- a/target-unicore32/translate.c
+++ b/target-unicore32/translate.c
@@ -2109,7 +2109,7 @@ done_generating:
     if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
         qemu_log("----------------\n");
         qemu_log("IN: %s\n", lookup_symbol(pc_start));
-        log_target_disas(pc_start, dc->pc - pc_start, 0);
+        log_target_disas(env, pc_start, dc->pc - pc_start, 0);
         qemu_log("\n");
     }
 #endif

From 4840552601caf1779b3de34bc8ea3fc128a52d04 Mon Sep 17 00:00:00 2001
From: Blue Swirl 
Date: Sat, 8 Sep 2012 12:43:16 +0000
Subject: [PATCH 286/291] kvm: avoid using cpu_single_env
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Pass around CPUArchState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl 
Reviewed-by: Andreas Färber 
---
 target-i386/kvm.c | 21 +++++++++++----------
 1 file changed, 11 insertions(+), 10 deletions(-)

diff --git a/target-i386/kvm.c b/target-i386/kvm.c
index 73e2035637..f669281e13 100644
--- a/target-i386/kvm.c
+++ b/target-i386/kvm.c
@@ -1945,14 +1945,15 @@ void kvm_arch_remove_all_hw_breakpoints(void)
 
 static CPUWatchpoint hw_watchpoint;
 
-static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
+static int kvm_handle_debug(CPUX86State *env,
+                            struct kvm_debug_exit_arch *arch_info)
 {
     int ret = 0;
     int n;
 
     if (arch_info->exception == 1) {
         if (arch_info->dr6 & (1 << 14)) {
-            if (cpu_single_env->singlestep_enabled) {
+            if (env->singlestep_enabled) {
                 ret = EXCP_DEBUG;
             }
         } else {
@@ -1964,13 +1965,13 @@ static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
                         break;
                     case 0x1:
                         ret = EXCP_DEBUG;
-                        cpu_single_env->watchpoint_hit = &hw_watchpoint;
+                        env->watchpoint_hit = &hw_watchpoint;
                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
                         hw_watchpoint.flags = BP_MEM_WRITE;
                         break;
                     case 0x3:
                         ret = EXCP_DEBUG;
-                        cpu_single_env->watchpoint_hit = &hw_watchpoint;
+                        env->watchpoint_hit = &hw_watchpoint;
                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
                         hw_watchpoint.flags = BP_MEM_ACCESS;
                         break;
@@ -1978,16 +1979,16 @@ static int kvm_handle_debug(struct kvm_debug_exit_arch *arch_info)
                 }
             }
         }
-    } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc)) {
+    } else if (kvm_find_sw_breakpoint(env, arch_info->pc)) {
         ret = EXCP_DEBUG;
     }
     if (ret == 0) {
-        cpu_synchronize_state(cpu_single_env);
-        assert(cpu_single_env->exception_injected == -1);
+        cpu_synchronize_state(env);
+        assert(env->exception_injected == -1);
 
         /* pass to guest */
-        cpu_single_env->exception_injected = arch_info->exception;
-        cpu_single_env->has_error_code = 0;
+        env->exception_injected = arch_info->exception;
+        env->has_error_code = 0;
     }
 
     return ret;
@@ -2071,7 +2072,7 @@ int kvm_arch_handle_exit(CPUX86State *env, struct kvm_run *run)
         break;
     case KVM_EXIT_DEBUG:
         DPRINTF("kvm_exit_debug\n");
-        ret = kvm_handle_debug(&run->debug.arch);
+        ret = kvm_handle_debug(env, &run->debug.arch);
         break;
     default:
         fprintf(stderr, "KVM: unknown exit reason %d\n", run->exit_reason);

From 447b3b60d15e1db6967a19e40284d33136a7c9e7 Mon Sep 17 00:00:00 2001
From: Blue Swirl 
Date: Sat, 8 Sep 2012 12:58:13 +0000
Subject: [PATCH 287/291] target-unicore32: avoid using cpu_single_env
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Pass around CPUArchState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl 
Acked-by: Guan Xuetao 
Reviewed-by: Andreas Färber 
---
 target-unicore32/softmmu.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 9c2c54cbc8..fc27100f27 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -31,7 +31,7 @@
 
 
 /* Map CPU modes onto saved register banks.  */
-static inline int bank_number(int mode)
+static inline int bank_number(CPUUniCore32State *env, int mode)
 {
     switch (mode) {
     case ASR_MODE_USER:
@@ -46,7 +46,7 @@ static inline int bank_number(int mode)
     case ASR_MODE_INTR:
         return 4;
     }
-    cpu_abort(cpu_single_env, "Bad mode %x\n", mode);
+    cpu_abort(env, "Bad mode %x\n", mode);
     return -1;
 }
 
@@ -60,12 +60,12 @@ void switch_mode(CPUUniCore32State *env, int mode)
         return;
     }
 
-    i = bank_number(old_mode);
+    i = bank_number(env, old_mode);
     env->banked_r29[i] = env->regs[29];
     env->banked_r30[i] = env->regs[30];
     env->banked_bsr[i] = env->bsr;
 
-    i = bank_number(mode);
+    i = bank_number(env, mode);
     env->regs[29] = env->banked_r29[i];
     env->regs[30] = env->banked_r30[i];
     env->bsr = env->banked_bsr[i];

From 0c4fabea809008702645e6b2c64926892b47f76d Mon Sep 17 00:00:00 2001
From: Blue Swirl 
Date: Sat, 8 Sep 2012 13:09:07 +0000
Subject: [PATCH 288/291] target-xtensa: avoid using cpu_single_env
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Pass around CPUArchState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl 
Acked-by: Max Filippov 
Reviewed-by: Andreas Färber 
---
 target-xtensa/translate.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index 82e8cccadc..3c03775a76 100644
--- a/target-xtensa/translate.c
+++ b/target-xtensa/translate.c
@@ -810,7 +810,7 @@ static TCGv_i32 gen_mac16_m(TCGv_i32 v, bool hi, bool is_unsigned)
     return m;
 }
 
-static void disas_xtensa_insn(DisasContext *dc)
+static void disas_xtensa_insn(CPUXtensaState *env, DisasContext *dc)
 {
 #define HAS_OPTION_BITS(opt) do { \
         if (!option_bits_enabled(dc, opt)) { \
@@ -900,8 +900,8 @@ static void disas_xtensa_insn(DisasContext *dc)
 
 #define RSR_SR (b1)
 
-    uint8_t b0 = cpu_ldub_code(cpu_single_env, dc->pc);
-    uint8_t b1 = cpu_ldub_code(cpu_single_env, dc->pc + 1);
+    uint8_t b0 = cpu_ldub_code(env, dc->pc);
+    uint8_t b1 = cpu_ldub_code(env, dc->pc + 1);
     uint8_t b2 = 0;
 
     static const uint32_t B4CONST[] = {
@@ -917,7 +917,7 @@ static void disas_xtensa_insn(DisasContext *dc)
         HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
     } else {
         dc->next_pc = dc->pc + 3;
-        b2 = cpu_ldub_code(cpu_single_env, dc->pc + 2);
+        b2 = cpu_ldub_code(env, dc->pc + 2);
     }
 
     switch (OP0) {
@@ -2931,7 +2931,7 @@ static void gen_intermediate_code_internal(
             gen_ibreak_check(env, &dc);
         }
 
-        disas_xtensa_insn(&dc);
+        disas_xtensa_insn(env, &dc);
         ++insn_count;
         if (dc.icount) {
             tcg_gen_mov_i32(cpu_SR[ICOUNT], dc.next_icount);

From 0af10c86ed6656da0c9b680ec9d1c65768dd99b2 Mon Sep 17 00:00:00 2001
From: Blue Swirl 
Date: Sat, 8 Sep 2012 13:26:02 +0000
Subject: [PATCH 289/291] target-i386: avoid using cpu_single_env
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Pass around CPUArchState instead of using global cpu_single_env.

Signed-off-by: Blue Swirl 
Reviewed-by: Andreas Färber 
---
 target-i386/translate.c | 440 ++++++++++++++++++++--------------------
 1 file changed, 222 insertions(+), 218 deletions(-)

diff --git a/target-i386/translate.c b/target-i386/translate.c
index bf52eefa55..7fdb8bcbbe 100644
--- a/target-i386/translate.c
+++ b/target-i386/translate.c
@@ -2018,7 +2018,8 @@ static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
     }
 }
 
-static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
+static void gen_lea_modrm(CPUX86State *env, DisasContext *s, int modrm,
+                          int *reg_ptr, int *offset_ptr)
 {
     target_long disp;
     int havesib;
@@ -2044,7 +2045,7 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_
 
         if (base == 4) {
             havesib = 1;
-            code = cpu_ldub_code(cpu_single_env, s->pc++);
+            code = cpu_ldub_code(env, s->pc++);
             scale = (code >> 6) & 3;
             index = ((code >> 3) & 7) | REX_X(s);
             base = (code & 7);
@@ -2055,7 +2056,7 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_
         case 0:
             if ((base & 7) == 5) {
                 base = -1;
-                disp = (int32_t)cpu_ldl_code(cpu_single_env, s->pc);
+                disp = (int32_t)cpu_ldl_code(env, s->pc);
                 s->pc += 4;
                 if (CODE64(s) && !havesib) {
                     disp += s->pc + s->rip_offset;
@@ -2065,11 +2066,11 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_
             }
             break;
         case 1:
-            disp = (int8_t)cpu_ldub_code(cpu_single_env, s->pc++);
+            disp = (int8_t)cpu_ldub_code(env, s->pc++);
             break;
         default:
         case 2:
-            disp = (int32_t)cpu_ldl_code(cpu_single_env, s->pc);
+            disp = (int32_t)cpu_ldl_code(env, s->pc);
             s->pc += 4;
             break;
         }
@@ -2132,7 +2133,7 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_
         switch (mod) {
         case 0:
             if (rm == 6) {
-                disp = cpu_lduw_code(cpu_single_env, s->pc);
+                disp = cpu_lduw_code(env, s->pc);
                 s->pc += 2;
                 gen_op_movl_A0_im(disp);
                 rm = 0; /* avoid SS override */
@@ -2142,11 +2143,11 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_
             }
             break;
         case 1:
-            disp = (int8_t)cpu_ldub_code(cpu_single_env, s->pc++);
+            disp = (int8_t)cpu_ldub_code(env, s->pc++);
             break;
         default:
         case 2:
-            disp = cpu_lduw_code(cpu_single_env, s->pc);
+            disp = cpu_lduw_code(env, s->pc);
             s->pc += 2;
             break;
         }
@@ -2202,7 +2203,7 @@ static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_
     *offset_ptr = disp;
 }
 
-static void gen_nop_modrm(DisasContext *s, int modrm)
+static void gen_nop_modrm(CPUX86State *env, DisasContext *s, int modrm)
 {
     int mod, rm, base, code;
 
@@ -2216,7 +2217,7 @@ static void gen_nop_modrm(DisasContext *s, int modrm)
         base = rm;
 
         if (base == 4) {
-            code = cpu_ldub_code(cpu_single_env, s->pc++);
+            code = cpu_ldub_code(env, s->pc++);
             base = (code & 7);
         }
 
@@ -2276,7 +2277,8 @@ static void gen_add_A0_ds_seg(DisasContext *s)
 
 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
    OR_TMP0 */
-static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
+static void gen_ldst_modrm(CPUX86State *env, DisasContext *s, int modrm,
+                           int ot, int reg, int is_store)
 {
     int mod, rm, opreg, disp;
 
@@ -2293,7 +2295,7 @@ static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_s
                 gen_op_mov_reg_T0(ot, reg);
         }
     } else {
-        gen_lea_modrm(s, modrm, &opreg, &disp);
+        gen_lea_modrm(env, s, modrm, &opreg, &disp);
         if (is_store) {
             if (reg != OR_TMP0)
                 gen_op_mov_TN_reg(ot, 0, reg);
@@ -2306,22 +2308,22 @@ static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_s
     }
 }
 
-static inline uint32_t insn_get(DisasContext *s, int ot)
+static inline uint32_t insn_get(CPUX86State *env, DisasContext *s, int ot)
 {
     uint32_t ret;
 
     switch(ot) {
     case OT_BYTE:
-        ret = cpu_ldub_code(cpu_single_env, s->pc);
+        ret = cpu_ldub_code(env, s->pc);
         s->pc++;
         break;
     case OT_WORD:
-        ret = cpu_lduw_code(cpu_single_env, s->pc);
+        ret = cpu_lduw_code(env, s->pc);
         s->pc += 2;
         break;
     default:
     case OT_LONG:
-        ret = cpu_ldl_code(cpu_single_env, s->pc);
+        ret = cpu_ldl_code(env, s->pc);
         s->pc += 4;
         break;
     }
@@ -3167,7 +3169,8 @@ static const struct SSEOpHelper_eppi sse_op_table7[256] = {
     [0x63] = SSE42_OP(pcmpistri),
 };
 
-static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
+static void gen_sse(CPUX86State *env, DisasContext *s, int b,
+                    target_ulong pc_start, int rex_r)
 {
     int b1, op1_offset, op2_offset, is_xmm, val, ot;
     int modrm, mod, rm, reg, reg_addr, offset_addr;
@@ -3230,7 +3233,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         gen_helper_enter_mmx(cpu_env);
     }
 
-    modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+    modrm = cpu_ldub_code(env, s->pc++);
     reg = ((modrm >> 3) & 7);
     if (is_xmm)
         reg |= rex_r;
@@ -3241,7 +3244,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x0e7: /* movntq */
             if (mod == 3)
                 goto illegal_op;
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
             break;
         case 0x1e7: /* movntdq */
@@ -3249,20 +3252,20 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x12b: /* movntps */
             if (mod == 3)
                 goto illegal_op;
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
             break;
         case 0x3f0: /* lddqu */
             if (mod == 3)
                 goto illegal_op;
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
             break;
         case 0x22b: /* movntss */
         case 0x32b: /* movntsd */
             if (mod == 3)
                 goto illegal_op;
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             if (b1 & 1) {
                 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
                     xmm_regs[reg]));
@@ -3275,12 +3278,12 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x6e: /* movd mm, ea */
 #ifdef TARGET_X86_64
             if (s->dflag == 2) {
-                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
+                gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0);
                 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
             } else
 #endif
             {
-                gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
+                gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0);
                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 
                                  offsetof(CPUX86State,fpregs[reg].mmx));
                 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -3290,14 +3293,14 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x16e: /* movd xmm, ea */
 #ifdef TARGET_X86_64
             if (s->dflag == 2) {
-                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
+                gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 0);
                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 
                                  offsetof(CPUX86State,xmm_regs[reg]));
                 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
             } else
 #endif
             {
-                gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
+                gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 0);
                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, 
                                  offsetof(CPUX86State,xmm_regs[reg]));
                 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -3306,7 +3309,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x6f: /* movq mm, ea */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
             } else {
                 rm = (modrm & 7);
@@ -3323,7 +3326,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x16f: /* movdqa xmm, ea */
         case 0x26f: /* movdqu xmm, ea */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
             } else {
                 rm = (modrm & 7) | REX_B(s);
@@ -3333,7 +3336,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x210: /* movss xmm, ea */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
                 gen_op_movl_T0_0();
@@ -3348,7 +3351,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x310: /* movsd xmm, ea */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
                 gen_op_movl_T0_0();
                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
@@ -3362,7 +3365,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x012: /* movlps */
         case 0x112: /* movlpd */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
             } else {
                 /* movhlps */
@@ -3373,7 +3376,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x212: /* movsldup */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
             } else {
                 rm = (modrm & 7) | REX_B(s);
@@ -3389,7 +3392,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x312: /* movddup */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
             } else {
                 rm = (modrm & 7) | REX_B(s);
@@ -3402,7 +3405,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x016: /* movhps */
         case 0x116: /* movhpd */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
             } else {
                 /* movlhps */
@@ -3413,7 +3416,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x216: /* movshdup */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
             } else {
                 rm = (modrm & 7) | REX_B(s);
@@ -3434,8 +3437,8 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
 
                 if (b1 == 1 && reg != 0)
                     goto illegal_op;
-                field_length = cpu_ldub_code(cpu_single_env, s->pc++) & 0x3F;
-                bit_index = cpu_ldub_code(cpu_single_env, s->pc++) & 0x3F;
+                field_length = cpu_ldub_code(env, s->pc++) & 0x3F;
+                bit_index = cpu_ldub_code(env, s->pc++) & 0x3F;
                 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
                     offsetof(CPUX86State,xmm_regs[reg]));
                 if (b1 == 1)
@@ -3453,13 +3456,13 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             if (s->dflag == 2) {
                 tcg_gen_ld_i64(cpu_T[0], cpu_env, 
                                offsetof(CPUX86State,fpregs[reg].mmx));
-                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
+                gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1);
             } else
 #endif
             {
                 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 
                                  offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
-                gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
+                gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1);
             }
             break;
         case 0x17e: /* movd ea, xmm */
@@ -3467,18 +3470,18 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             if (s->dflag == 2) {
                 tcg_gen_ld_i64(cpu_T[0], cpu_env, 
                                offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
-                gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
+                gen_ldst_modrm(env, s, modrm, OT_QUAD, OR_TMP0, 1);
             } else
 #endif
             {
                 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, 
                                  offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
-                gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
+                gen_ldst_modrm(env, s, modrm, OT_LONG, OR_TMP0, 1);
             }
             break;
         case 0x27e: /* movq xmm, ea */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
             } else {
                 rm = (modrm & 7) | REX_B(s);
@@ -3489,7 +3492,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x7f: /* movq ea, mm */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
             } else {
                 rm = (modrm & 7);
@@ -3504,7 +3507,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x17f: /* movdqa ea, xmm */
         case 0x27f: /* movdqu ea, xmm */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
             } else {
                 rm = (modrm & 7) | REX_B(s);
@@ -3514,7 +3517,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x211: /* movss ea, xmm */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
                 gen_op_st_T0_A0(OT_LONG + s->mem_index);
             } else {
@@ -3525,7 +3528,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x311: /* movsd ea, xmm */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
             } else {
                 rm = (modrm & 7) | REX_B(s);
@@ -3536,7 +3539,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x013: /* movlps */
         case 0x113: /* movlpd */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
             } else {
                 goto illegal_op;
@@ -3545,7 +3548,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x017: /* movhps */
         case 0x117: /* movhpd */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
             } else {
                 goto illegal_op;
@@ -3560,7 +3563,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             if (b1 >= 2) {
 	        goto illegal_op;
             }
-            val = cpu_ldub_code(cpu_single_env, s->pc++);
+            val = cpu_ldub_code(env, s->pc++);
             if (is_xmm) {
                 gen_op_movl_T0_im(val);
                 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
@@ -3610,7 +3613,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x12a: /* cvtpi2pd */
             gen_helper_enter_mmx(cpu_env);
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 op2_offset = offsetof(CPUX86State,mmx_t0);
                 gen_ldq_env_A0(s->mem_index, op2_offset);
             } else {
@@ -3633,7 +3636,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x22a: /* cvtsi2ss */
         case 0x32a: /* cvtsi2sd */
             ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
-            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
+            gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
             op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
             if (ot == OT_LONG) {
@@ -3655,7 +3658,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x12d: /* cvtpd2pi */
             gen_helper_enter_mmx(cpu_env);
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 op2_offset = offsetof(CPUX86State,xmm_t0);
                 gen_ldo_env_A0(s->mem_index, op2_offset);
             } else {
@@ -3686,7 +3689,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x32d: /* cvtsd2si */
             ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 if ((b >> 8) & 1) {
                     gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
                 } else {
@@ -3718,8 +3721,8 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0xc4: /* pinsrw */
         case 0x1c4:
             s->rip_offset = 1;
-            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
-            val = cpu_ldub_code(cpu_single_env, s->pc++);
+            gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
+            val = cpu_ldub_code(env, s->pc++);
             if (b1) {
                 val &= 7;
                 tcg_gen_st16_tl(cpu_T[0], cpu_env,
@@ -3735,7 +3738,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             if (mod != 3)
                 goto illegal_op;
             ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
-            val = cpu_ldub_code(cpu_single_env, s->pc++);
+            val = cpu_ldub_code(env, s->pc++);
             if (b1) {
                 val &= 7;
                 rm = (modrm & 7) | REX_B(s);
@@ -3752,7 +3755,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x1d6: /* movq ea, xmm */
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
             } else {
                 rm = (modrm & 7) | REX_B(s);
@@ -3796,7 +3799,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
                 goto crc32;
         case 0x038:
             b = modrm;
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             rm = modrm & 7;
             reg = ((modrm >> 3) & 7) | rex_r;
             mod = (modrm >> 6) & 3;
@@ -3817,7 +3820,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
                     op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
                 } else {
                     op2_offset = offsetof(CPUX86State,xmm_t0);
-                    gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                    gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                     switch (b) {
                     case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
                     case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
@@ -3852,7 +3855,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
                     op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
                 } else {
                     op2_offset = offsetof(CPUX86State,mmx_t0);
-                    gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                    gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                     gen_ldq_env_A0(s->mem_index, op2_offset);
                 }
             }
@@ -3870,7 +3873,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x338: /* crc32 */
         crc32:
             b = modrm;
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             reg = ((modrm >> 3) & 7) | rex_r;
 
             if (b != 0xf0 && b != 0xf1)
@@ -3890,7 +3893,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
 
             gen_op_mov_TN_reg(OT_LONG, 0, reg);
             tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
-            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
+            gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
             gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
                              cpu_T[0], tcg_const_i32(8 << ot));
 
@@ -3900,7 +3903,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x03a:
         case 0x13a:
             b = modrm;
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             rm = modrm & 7;
             reg = ((modrm >> 3) & 7) | rex_r;
             mod = (modrm >> 6) & 3;
@@ -3919,9 +3922,9 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
                 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
                 rm = (modrm & 7) | REX_B(s);
                 if (mod != 3)
-                    gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                    gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 reg = ((modrm >> 3) & 7) | rex_r;
-                val = cpu_ldub_code(cpu_single_env, s->pc++);
+                val = cpu_ldub_code(env, s->pc++);
                 switch (b) {
                 case 0x14: /* pextrb */
                     tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
@@ -4051,7 +4054,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
                     op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
                 } else {
                     op2_offset = offsetof(CPUX86State,xmm_t0);
-                    gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                    gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                     gen_ldo_env_A0(s->mem_index, op2_offset);
                 }
             } else {
@@ -4060,11 +4063,11 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
                     op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
                 } else {
                     op2_offset = offsetof(CPUX86State,mmx_t0);
-                    gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                    gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                     gen_ldq_env_A0(s->mem_index, op2_offset);
                 }
             }
-            val = cpu_ldub_code(cpu_single_env, s->pc++);
+            val = cpu_ldub_code(env, s->pc++);
 
             if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
                 s->cc_op = CC_OP_EFLAGS;
@@ -4095,7 +4098,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         if (is_xmm) {
             op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 op2_offset = offsetof(CPUX86State,xmm_t0);
                 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
                                 b == 0xc2)) {
@@ -4118,7 +4121,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         } else {
             op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 op2_offset = offsetof(CPUX86State,mmx_t0);
                 gen_ldq_env_A0(s->mem_index, op2_offset);
             } else {
@@ -4130,7 +4133,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
         case 0x0f: /* 3DNow! data insns */
             if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
                 goto illegal_op;
-            val = cpu_ldub_code(cpu_single_env, s->pc++);
+            val = cpu_ldub_code(env, s->pc++);
             sse_fn_epp = sse_op_table5[val];
             if (!sse_fn_epp) {
                 goto illegal_op;
@@ -4141,7 +4144,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0x70: /* pshufx insn */
         case 0xc6: /* pshufx insn */
-            val = cpu_ldub_code(cpu_single_env, s->pc++);
+            val = cpu_ldub_code(env, s->pc++);
             tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
             tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
             /* XXX: introduce a new table? */
@@ -4150,7 +4153,7 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
             break;
         case 0xc2:
             /* compare insns */
-            val = cpu_ldub_code(cpu_single_env, s->pc++);
+            val = cpu_ldub_code(env, s->pc++);
             if (val >= 8)
                 goto illegal_op;
             sse_fn_epp = sse_op_table4[val][b1];
@@ -4195,7 +4198,8 @@ static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
 
 /* convert one instruction. s->is_jmp is set if the translation must
    be stopped. Return the next pc value */
-static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
+static target_ulong disas_insn(CPUX86State *env, DisasContext *s,
+                               target_ulong pc_start)
 {
     int b, prefixes, aflag, dflag;
     int shift, ot;
@@ -4220,7 +4224,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
 #endif
     s->rip_offset = 0; /* for relative ip address */
  next_byte:
-    b = cpu_ldub_code(cpu_single_env, s->pc);
+    b = cpu_ldub_code(env, s->pc);
     s->pc++;
     /* check prefixes */
 #ifdef TARGET_X86_64
@@ -4335,7 +4339,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
     case 0x0f:
         /**************************/
         /* extended op code */
-        b = cpu_ldub_code(cpu_single_env, s->pc++) | 0x100;
+        b = cpu_ldub_code(env, s->pc++) | 0x100;
         goto reswitch;
 
         /**************************/
@@ -4360,12 +4364,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
 
             switch(f) {
             case 0: /* OP Ev, Gv */
-                modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+                modrm = cpu_ldub_code(env, s->pc++);
                 reg = ((modrm >> 3) & 7) | rex_r;
                 mod = (modrm >> 6) & 3;
                 rm = (modrm & 7) | REX_B(s);
                 if (mod != 3) {
-                    gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                    gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                     opreg = OR_TMP0;
                 } else if (op == OP_XORL && rm == reg) {
                 xor_zero:
@@ -4382,12 +4386,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 gen_op(s, op, ot, opreg);
                 break;
             case 1: /* OP Gv, Ev */
-                modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+                modrm = cpu_ldub_code(env, s->pc++);
                 mod = (modrm >> 6) & 3;
                 reg = ((modrm >> 3) & 7) | rex_r;
                 rm = (modrm & 7) | REX_B(s);
                 if (mod != 3) {
-                    gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                    gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                     gen_op_ld_T1_A0(ot + s->mem_index);
                 } else if (op == OP_XORL && rm == reg) {
                     goto xor_zero;
@@ -4397,7 +4401,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 gen_op(s, op, ot, reg);
                 break;
             case 2: /* OP A, Iv */
-                val = insn_get(s, ot);
+                val = insn_get(env, s, ot);
                 gen_op_movl_T1_im(val);
                 gen_op(s, op, ot, OR_EAX);
                 break;
@@ -4419,7 +4423,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             else
                 ot = dflag + OT_WORD;
 
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             mod = (modrm >> 6) & 3;
             rm = (modrm & 7) | REX_B(s);
             op = (modrm >> 3) & 7;
@@ -4429,7 +4433,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                     s->rip_offset = 1;
                 else
                     s->rip_offset = insn_const_size(ot);
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 opreg = OR_TMP0;
             } else {
                 opreg = rm;
@@ -4440,10 +4444,10 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             case 0x80:
             case 0x81:
             case 0x82:
-                val = insn_get(s, ot);
+                val = insn_get(env, s, ot);
                 break;
             case 0x83:
-                val = (int8_t)insn_get(s, OT_BYTE);
+                val = (int8_t)insn_get(env, s, OT_BYTE);
                 break;
             }
             gen_op_movl_T1_im(val);
@@ -4468,14 +4472,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         else
             ot = dflag + OT_WORD;
 
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         rm = (modrm & 7) | REX_B(s);
         op = (modrm >> 3) & 7;
         if (mod != 3) {
             if (op == 0)
                 s->rip_offset = insn_const_size(ot);
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             gen_op_ld_T0_A0(ot + s->mem_index);
         } else {
             gen_op_mov_TN_reg(ot, 0, rm);
@@ -4483,7 +4487,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
 
         switch(op) {
         case 0: /* test */
-            val = insn_get(s, ot);
+            val = insn_get(env, s, ot);
             gen_op_movl_T1_im(val);
             gen_op_testl_T0_T1_cc();
             s->cc_op = CC_OP_LOGICB + ot;
@@ -4700,7 +4704,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         else
             ot = dflag + OT_WORD;
 
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         rm = (modrm & 7) | REX_B(s);
         op = (modrm >> 3) & 7;
@@ -4719,7 +4723,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             }
         }
         if (mod != 3) {
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             if (op >= 2 && op != 3 && op != 5)
                 gen_op_ld_T0_A0(ot + s->mem_index);
         } else {
@@ -4812,10 +4816,10 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         else
             ot = dflag + OT_WORD;
 
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
 
-        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
+        gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
         gen_op_mov_TN_reg(ot, 1, reg);
         gen_op_testl_T0_T1_cc();
         s->cc_op = CC_OP_LOGICB + ot;
@@ -4827,7 +4831,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_BYTE;
         else
             ot = dflag + OT_WORD;
-        val = insn_get(s, ot);
+        val = insn_get(env, s, ot);
 
         gen_op_mov_TN_reg(ot, 0, OR_EAX);
         gen_op_movl_T1_im(val);
@@ -4877,18 +4881,18 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
     case 0x69: /* imul Gv, Ev, I */
     case 0x6b:
         ot = dflag + OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
         if (b == 0x69)
             s->rip_offset = insn_const_size(ot);
         else if (b == 0x6b)
             s->rip_offset = 1;
-        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
+        gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
         if (b == 0x69) {
-            val = insn_get(s, ot);
+            val = insn_get(env, s, ot);
             gen_op_movl_T1_im(val);
         } else if (b == 0x6b) {
-            val = (int8_t)insn_get(s, OT_BYTE);
+            val = (int8_t)insn_get(env, s, OT_BYTE);
             gen_op_movl_T1_im(val);
         } else {
             gen_op_mov_TN_reg(ot, 1, reg);
@@ -4941,7 +4945,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_BYTE;
         else
             ot = dflag + OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
         mod = (modrm >> 6) & 3;
         if (mod == 3) {
@@ -4952,7 +4956,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             gen_op_mov_reg_T1(ot, reg);
             gen_op_mov_reg_T0(ot, rm);
         } else {
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             gen_op_mov_TN_reg(ot, 0, reg);
             gen_op_ld_T1_A0(ot + s->mem_index);
             gen_op_addl_T0_T1();
@@ -4972,7 +4976,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 ot = OT_BYTE;
             else
                 ot = dflag + OT_WORD;
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             reg = ((modrm >> 3) & 7) | rex_r;
             mod = (modrm >> 6) & 3;
             t0 = tcg_temp_local_new();
@@ -4984,7 +4988,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 rm = (modrm & 7) | REX_B(s);
                 gen_op_mov_v_reg(ot, t0, rm);
             } else {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 tcg_gen_mov_tl(a0, cpu_A0);
                 gen_op_ld_v(ot + s->mem_index, t0, a0);
                 rm = 0; /* avoid warning */
@@ -5020,7 +5024,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         }
         break;
     case 0x1c7: /* cmpxchg8b */
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         if ((mod == 3) || ((modrm & 0x38) != 0x8))
             goto illegal_op;
@@ -5031,7 +5035,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             gen_jmp_im(pc_start - s->cs_base);
             if (s->cc_op != CC_OP_DYNAMIC)
                 gen_op_set_cc_op(s->cc_op);
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             gen_helper_cmpxchg16b(cpu_env, cpu_A0);
         } else
 #endif        
@@ -5041,7 +5045,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             gen_jmp_im(pc_start - s->cs_base);
             if (s->cc_op != CC_OP_DYNAMIC)
                 gen_op_set_cc_op(s->cc_op);
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             gen_helper_cmpxchg8b(cpu_env, cpu_A0);
         }
         s->cc_op = CC_OP_EFLAGS;
@@ -5082,9 +5086,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = dflag + OT_WORD;
         }
         if (b == 0x68)
-            val = insn_get(s, ot);
+            val = insn_get(env, s, ot);
         else
-            val = (int8_t)insn_get(s, OT_BYTE);
+            val = (int8_t)insn_get(env, s, OT_BYTE);
         gen_op_movl_T0_im(val);
         gen_push_T0(s);
         break;
@@ -5094,7 +5098,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         } else {
             ot = dflag + OT_WORD;
         }
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         gen_pop_T0(s);
         if (mod == 3) {
@@ -5105,7 +5109,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         } else {
             /* NOTE: order is important too for MMU exceptions */
             s->popl_esp_hack = 1 << ot;
-            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
+            gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
             s->popl_esp_hack = 0;
             gen_pop_update(s);
         }
@@ -5113,9 +5117,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
     case 0xc8: /* enter */
         {
             int level;
-            val = cpu_lduw_code(cpu_single_env, s->pc);
+            val = cpu_lduw_code(env, s->pc);
             s->pc += 2;
-            level = cpu_ldub_code(cpu_single_env, s->pc++);
+            level = cpu_ldub_code(env, s->pc++);
             gen_enter(s, val, level);
         }
         break;
@@ -5195,11 +5199,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_BYTE;
         else
             ot = dflag + OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
 
         /* generate a generic store */
-        gen_ldst_modrm(s, modrm, ot, reg, 1);
+        gen_ldst_modrm(env, s, modrm, ot, reg, 1);
         break;
     case 0xc6:
     case 0xc7: /* mov Ev, Iv */
@@ -5207,13 +5211,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_BYTE;
         else
             ot = dflag + OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         if (mod != 3) {
             s->rip_offset = insn_const_size(ot);
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
         }
-        val = insn_get(s, ot);
+        val = insn_get(env, s, ot);
         gen_op_movl_T0_im(val);
         if (mod != 3)
             gen_op_st_T0_A0(ot + s->mem_index);
@@ -5226,18 +5230,18 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_BYTE;
         else
             ot = OT_WORD + dflag;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
 
-        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
+        gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
         gen_op_mov_reg_T0(ot, reg);
         break;
     case 0x8e: /* mov seg, Gv */
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = (modrm >> 3) & 7;
         if (reg >= 6 || reg == R_CS)
             goto illegal_op;
-        gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+        gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
         gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
         if (reg == R_SS) {
             /* if reg == SS, inhibit interrupts/trace */
@@ -5253,7 +5257,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         }
         break;
     case 0x8c: /* mov Gv, seg */
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = (modrm >> 3) & 7;
         mod = (modrm >> 6) & 3;
         if (reg >= 6)
@@ -5263,7 +5267,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_WORD + dflag;
         else
             ot = OT_WORD;
-        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
+        gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
         break;
 
     case 0x1b6: /* movzbS Gv, Eb */
@@ -5276,7 +5280,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             d_ot = dflag + OT_WORD;
             /* ot is the size of source */
             ot = (b & 1) + OT_BYTE;
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             reg = ((modrm >> 3) & 7) | rex_r;
             mod = (modrm >> 6) & 3;
             rm = (modrm & 7) | REX_B(s);
@@ -5300,7 +5304,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 }
                 gen_op_mov_reg_T0(d_ot, reg);
             } else {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 if (b & 8) {
                     gen_op_lds_T0_A0(ot + s->mem_index);
                 } else {
@@ -5313,7 +5317,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
 
     case 0x8d: /* lea */
         ot = dflag + OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         if (mod == 3)
             goto illegal_op;
@@ -5322,7 +5326,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         s->override = -1;
         val = s->addseg;
         s->addseg = 0;
-        gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+        gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
         s->addseg = val;
         gen_op_mov_reg_A0(ot - OT_WORD, reg);
         break;
@@ -5340,16 +5344,16 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 ot = dflag + OT_WORD;
 #ifdef TARGET_X86_64
             if (s->aflag == 2) {
-                offset_addr = cpu_ldq_code(cpu_single_env, s->pc);
+                offset_addr = cpu_ldq_code(env, s->pc);
                 s->pc += 8;
                 gen_op_movq_A0_im(offset_addr);
             } else
 #endif
             {
                 if (s->aflag) {
-                    offset_addr = insn_get(s, OT_LONG);
+                    offset_addr = insn_get(env, s, OT_LONG);
                 } else {
-                    offset_addr = insn_get(s, OT_WORD);
+                    offset_addr = insn_get(env, s, OT_WORD);
                 }
                 gen_op_movl_A0_im(offset_addr);
             }
@@ -5387,7 +5391,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         gen_op_mov_reg_T0(OT_BYTE, R_EAX);
         break;
     case 0xb0 ... 0xb7: /* mov R, Ib */
-        val = insn_get(s, OT_BYTE);
+        val = insn_get(env, s, OT_BYTE);
         gen_op_movl_T0_im(val);
         gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
         break;
@@ -5396,7 +5400,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         if (dflag == 2) {
             uint64_t tmp;
             /* 64 bit case */
-            tmp = cpu_ldq_code(cpu_single_env, s->pc);
+            tmp = cpu_ldq_code(env, s->pc);
             s->pc += 8;
             reg = (b & 7) | REX_B(s);
             gen_movtl_T0_im(tmp);
@@ -5405,7 +5409,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
 #endif
         {
             ot = dflag ? OT_LONG : OT_WORD;
-            val = insn_get(s, ot);
+            val = insn_get(env, s, ot);
             reg = (b & 7) | REX_B(s);
             gen_op_movl_T0_im(val);
             gen_op_mov_reg_T0(ot, reg);
@@ -5424,7 +5428,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_BYTE;
         else
             ot = dflag + OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
         mod = (modrm >> 6) & 3;
         if (mod == 3) {
@@ -5435,7 +5439,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             gen_op_mov_reg_T0(ot, rm);
             gen_op_mov_reg_T1(ot, reg);
         } else {
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             gen_op_mov_TN_reg(ot, 0, reg);
             /* for xchg, lock is implicit */
             if (!(prefixes & PREFIX_LOCK))
@@ -5467,12 +5471,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         op = R_GS;
     do_lxx:
         ot = dflag ? OT_LONG : OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
         mod = (modrm >> 6) & 3;
         if (mod == 3)
             goto illegal_op;
-        gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+        gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
         gen_op_ld_T1_A0(ot + s->mem_index);
         gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
         /* load the segment first to handle exceptions properly */
@@ -5499,7 +5503,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             else
                 ot = dflag + OT_WORD;
 
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             mod = (modrm >> 6) & 3;
             op = (modrm >> 3) & 7;
 
@@ -5507,7 +5511,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 if (shift == 2) {
                     s->rip_offset = 1;
                 }
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 opreg = OR_TMP0;
             } else {
                 opreg = (modrm & 7) | REX_B(s);
@@ -5518,7 +5522,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 gen_shift(s, op, ot, opreg, OR_ECX);
             } else {
                 if (shift == 2) {
-                    shift = cpu_ldub_code(cpu_single_env, s->pc++);
+                    shift = cpu_ldub_code(env, s->pc++);
                 }
                 gen_shifti(s, op, ot, opreg, shift);
             }
@@ -5552,12 +5556,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         shift = 0;
     do_shiftd:
         ot = dflag + OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         rm = (modrm & 7) | REX_B(s);
         reg = ((modrm >> 3) & 7) | rex_r;
         if (mod != 3) {
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             opreg = OR_TMP0;
         } else {
             opreg = rm;
@@ -5565,7 +5569,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         gen_op_mov_TN_reg(ot, 1, reg);
 
         if (shift) {
-            val = cpu_ldub_code(cpu_single_env, s->pc++);
+            val = cpu_ldub_code(env, s->pc++);
             tcg_gen_movi_tl(cpu_T3, val);
         } else {
             tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
@@ -5582,13 +5586,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
             break;
         }
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         rm = modrm & 7;
         op = ((b & 7) << 3) | ((modrm >> 3) & 7);
         if (mod != 3) {
             /* memory op */
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             switch(op) {
             case 0x00 ... 0x07: /* fxxxs */
             case 0x10 ... 0x17: /* fixxxl */
@@ -6213,7 +6217,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_BYTE;
         else
             ot = dflag ? OT_LONG : OT_WORD;
-        val = cpu_ldub_code(cpu_single_env, s->pc++);
+        val = cpu_ldub_code(env, s->pc++);
         gen_op_movl_T0_im(val);
         gen_check_io(s, ot, pc_start - s->cs_base,
                      SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
@@ -6233,7 +6237,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_BYTE;
         else
             ot = dflag ? OT_LONG : OT_WORD;
-        val = cpu_ldub_code(cpu_single_env, s->pc++);
+        val = cpu_ldub_code(env, s->pc++);
         gen_op_movl_T0_im(val);
         gen_check_io(s, ot, pc_start - s->cs_base,
                      svm_is_rep(prefixes));
@@ -6295,7 +6299,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         /************************/
         /* control */
     case 0xc2: /* ret im */
-        val = cpu_ldsw_code(cpu_single_env, s->pc);
+        val = cpu_ldsw_code(env, s->pc);
         s->pc += 2;
         gen_pop_T0(s);
         if (CODE64(s) && s->dflag)
@@ -6315,7 +6319,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         gen_eob(s);
         break;
     case 0xca: /* lret im */
-        val = cpu_ldsw_code(cpu_single_env, s->pc);
+        val = cpu_ldsw_code(env, s->pc);
         s->pc += 2;
     do_lret:
         if (s->pe && !s->vm86) {
@@ -6371,9 +6375,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
     case 0xe8: /* call im */
         {
             if (dflag)
-                tval = (int32_t)insn_get(s, OT_LONG);
+                tval = (int32_t)insn_get(env, s, OT_LONG);
             else
-                tval = (int16_t)insn_get(s, OT_WORD);
+                tval = (int16_t)insn_get(env, s, OT_WORD);
             next_eip = s->pc - s->cs_base;
             tval += next_eip;
             if (s->dflag == 0)
@@ -6392,8 +6396,8 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             if (CODE64(s))
                 goto illegal_op;
             ot = dflag ? OT_LONG : OT_WORD;
-            offset = insn_get(s, ot);
-            selector = insn_get(s, OT_WORD);
+            offset = insn_get(env, s, ot);
+            selector = insn_get(env, s, OT_WORD);
 
             gen_op_movl_T0_im(selector);
             gen_op_movl_T1_imu(offset);
@@ -6401,9 +6405,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         goto do_lcall;
     case 0xe9: /* jmp im */
         if (dflag)
-            tval = (int32_t)insn_get(s, OT_LONG);
+            tval = (int32_t)insn_get(env, s, OT_LONG);
         else
-            tval = (int16_t)insn_get(s, OT_WORD);
+            tval = (int16_t)insn_get(env, s, OT_WORD);
         tval += s->pc - s->cs_base;
         if (s->dflag == 0)
             tval &= 0xffff;
@@ -6418,28 +6422,28 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             if (CODE64(s))
                 goto illegal_op;
             ot = dflag ? OT_LONG : OT_WORD;
-            offset = insn_get(s, ot);
-            selector = insn_get(s, OT_WORD);
+            offset = insn_get(env, s, ot);
+            selector = insn_get(env, s, OT_WORD);
 
             gen_op_movl_T0_im(selector);
             gen_op_movl_T1_imu(offset);
         }
         goto do_ljmp;
     case 0xeb: /* jmp Jb */
-        tval = (int8_t)insn_get(s, OT_BYTE);
+        tval = (int8_t)insn_get(env, s, OT_BYTE);
         tval += s->pc - s->cs_base;
         if (s->dflag == 0)
             tval &= 0xffff;
         gen_jmp(s, tval);
         break;
     case 0x70 ... 0x7f: /* jcc Jb */
-        tval = (int8_t)insn_get(s, OT_BYTE);
+        tval = (int8_t)insn_get(env, s, OT_BYTE);
         goto do_jcc;
     case 0x180 ... 0x18f: /* jcc Jv */
         if (dflag) {
-            tval = (int32_t)insn_get(s, OT_LONG);
+            tval = (int32_t)insn_get(env, s, OT_LONG);
         } else {
-            tval = (int16_t)insn_get(s, OT_WORD);
+            tval = (int16_t)insn_get(env, s, OT_WORD);
         }
     do_jcc:
         next_eip = s->pc - s->cs_base;
@@ -6450,9 +6454,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         break;
 
     case 0x190 ... 0x19f: /* setcc Gv */
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         gen_setcc(s, b);
-        gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
+        gen_ldst_modrm(env, s, modrm, OT_BYTE, OR_TMP0, 1);
         break;
     case 0x140 ... 0x14f: /* cmov Gv, Ev */
         {
@@ -6460,12 +6464,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             TCGv t0;
 
             ot = dflag + OT_WORD;
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             reg = ((modrm >> 3) & 7) | rex_r;
             mod = (modrm >> 6) & 3;
             t0 = tcg_temp_local_new();
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
             } else {
                 rm = (modrm & 7) | REX_B(s);
@@ -6618,19 +6622,19 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         /* bit operations */
     case 0x1ba: /* bt/bts/btr/btc Gv, im */
         ot = dflag + OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         op = (modrm >> 3) & 7;
         mod = (modrm >> 6) & 3;
         rm = (modrm & 7) | REX_B(s);
         if (mod != 3) {
             s->rip_offset = 1;
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             gen_op_ld_T0_A0(ot + s->mem_index);
         } else {
             gen_op_mov_TN_reg(ot, 0, rm);
         }
         /* load shift */
-        val = cpu_ldub_code(cpu_single_env, s->pc++);
+        val = cpu_ldub_code(env, s->pc++);
         gen_op_movl_T1_im(val);
         if (op < 4)
             goto illegal_op;
@@ -6649,13 +6653,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         op = 3;
     do_btx:
         ot = dflag + OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
         mod = (modrm >> 6) & 3;
         rm = (modrm & 7) | REX_B(s);
         gen_op_mov_TN_reg(OT_LONG, 1, reg);
         if (mod != 3) {
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             /* specific case: we need to add a displacement */
             gen_exts(ot, cpu_T[1]);
             tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
@@ -6710,9 +6714,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             TCGv t0;
 
             ot = dflag + OT_WORD;
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             reg = ((modrm >> 3) & 7) | rex_r;
-            gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0);
+            gen_ldst_modrm(env, s,modrm, ot, OR_TMP0, 0);
             gen_extu(ot, cpu_T[0]);
             t0 = tcg_temp_local_new();
             tcg_gen_mov_tl(t0, cpu_T[0]);
@@ -6782,7 +6786,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
     case 0xd4: /* aam */
         if (CODE64(s))
             goto illegal_op;
-        val = cpu_ldub_code(cpu_single_env, s->pc++);
+        val = cpu_ldub_code(env, s->pc++);
         if (val == 0) {
             gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
         } else {
@@ -6793,7 +6797,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
     case 0xd5: /* aad */
         if (CODE64(s))
             goto illegal_op;
-        val = cpu_ldub_code(cpu_single_env, s->pc++);
+        val = cpu_ldub_code(env, s->pc++);
         gen_helper_aad(cpu_env, tcg_const_i32(val));
         s->cc_op = CC_OP_LOGICB;
         break;
@@ -6827,7 +6831,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
         break;
     case 0xcd: /* int N */
-        val = cpu_ldub_code(cpu_single_env, s->pc++);
+        val = cpu_ldub_code(env, s->pc++);
         if (s->vm86 && s->iopl != 3) {
             gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
         } else {
@@ -6849,7 +6853,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         gen_debug(s, pc_start - s->cs_base);
 #else
         /* start debug */
-        tb_flush(cpu_single_env);
+        tb_flush(env);
         cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
 #endif
         break;
@@ -6897,13 +6901,13 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         if (CODE64(s))
             goto illegal_op;
         ot = dflag ? OT_LONG : OT_WORD;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = (modrm >> 3) & 7;
         mod = (modrm >> 6) & 3;
         if (mod == 3)
             goto illegal_op;
         gen_op_mov_TN_reg(ot, 0, reg);
-        gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+        gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
         gen_jmp_im(pc_start - s->cs_base);
         tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
         if (ot == OT_WORD) {
@@ -6944,7 +6948,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         {
             int l1, l2, l3;
 
-            tval = (int8_t)insn_get(s, OT_BYTE);
+            tval = (int8_t)insn_get(env, s, OT_BYTE);
             next_eip = s->pc - s->cs_base;
             tval += next_eip;
             if (s->dflag == 0)
@@ -7024,7 +7028,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         break;
     case 0x134: /* sysenter */
         /* For Intel SYSENTER is valid on 64-bit */
-        if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
+        if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
             goto illegal_op;
         if (!s->pe) {
             gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
@@ -7037,7 +7041,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         break;
     case 0x135: /* sysexit */
         /* For Intel SYSEXIT is valid on 64-bit */
-        if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
+        if (CODE64(s) && env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
             goto illegal_op;
         if (!s->pe) {
             gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
@@ -7088,7 +7092,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         }
         break;
     case 0x100:
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         op = (modrm >> 3) & 7;
         switch(op) {
@@ -7100,7 +7104,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_WORD;
             if (mod == 3)
                 ot += s->dflag;
-            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
+            gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
             break;
         case 2: /* lldt */
             if (!s->pe || s->vm86)
@@ -7109,7 +7113,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
             } else {
                 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
-                gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+                gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
                 gen_jmp_im(pc_start - s->cs_base);
                 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
                 gen_helper_lldt(cpu_env, cpu_tmp2_i32);
@@ -7123,7 +7127,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             ot = OT_WORD;
             if (mod == 3)
                 ot += s->dflag;
-            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
+            gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 1);
             break;
         case 3: /* ltr */
             if (!s->pe || s->vm86)
@@ -7132,7 +7136,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
             } else {
                 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
-                gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+                gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
                 gen_jmp_im(pc_start - s->cs_base);
                 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
                 gen_helper_ltr(cpu_env, cpu_tmp2_i32);
@@ -7142,7 +7146,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         case 5: /* verw */
             if (!s->pe || s->vm86)
                 goto illegal_op;
-            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+            gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
             if (s->cc_op != CC_OP_DYNAMIC)
                 gen_op_set_cc_op(s->cc_op);
             if (op == 4) {
@@ -7157,7 +7161,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         }
         break;
     case 0x101:
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         op = (modrm >> 3) & 7;
         rm = modrm & 7;
@@ -7166,7 +7170,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             if (mod == 3)
                 goto illegal_op;
             gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
             gen_op_st_T0_A0(OT_WORD + s->mem_index);
             gen_add_A0_im(s, 2);
@@ -7230,7 +7234,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 }
             } else { /* sidt */
                 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
                 gen_op_st_T0_A0(OT_WORD + s->mem_index);
                 gen_add_A0_im(s, 2);
@@ -7332,7 +7336,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             } else {
                 gen_svm_check_intercept(s, pc_start,
                                         op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
                 gen_add_A0_im(s, 2);
                 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
@@ -7354,14 +7358,14 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
 #else
             tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
 #endif
-            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
+            gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 1);
             break;
         case 6: /* lmsw */
             if (s->cpl != 0) {
                 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
             } else {
                 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
-                gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+                gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
                 gen_helper_lmsw(cpu_env, cpu_T[0]);
                 gen_jmp_im(s->pc - s->cs_base);
                 gen_eob(s);
@@ -7375,7 +7379,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                     if (s->cc_op != CC_OP_DYNAMIC)
                         gen_op_set_cc_op(s->cc_op);
                     gen_jmp_im(pc_start - s->cs_base);
-                    gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                    gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                     gen_helper_invlpg(cpu_env, cpu_A0);
                     gen_jmp_im(s->pc - s->cs_base);
                     gen_eob(s);
@@ -7442,7 +7446,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             /* d_ot is the size of destination */
             d_ot = dflag + OT_WORD;
 
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             reg = ((modrm >> 3) & 7) | rex_r;
             mod = (modrm >> 6) & 3;
             rm = (modrm & 7) | REX_B(s);
@@ -7454,7 +7458,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                     tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
                 gen_op_mov_reg_T0(d_ot, reg);
             } else {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 if (d_ot == OT_QUAD) {
                     gen_op_lds_T0_A0(OT_LONG + s->mem_index);
                 } else {
@@ -7474,12 +7478,12 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             t1 = tcg_temp_local_new();
             t2 = tcg_temp_local_new();
             ot = OT_WORD;
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             reg = (modrm >> 3) & 7;
             mod = (modrm >> 6) & 3;
             rm = modrm & 7;
             if (mod != 3) {
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
                 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
                 a0 = tcg_temp_local_new();
                 tcg_gen_mov_tl(a0, cpu_A0);
@@ -7522,9 +7526,9 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             if (!s->pe || s->vm86)
                 goto illegal_op;
             ot = dflag ? OT_LONG : OT_WORD;
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             reg = ((modrm >> 3) & 7) | rex_r;
-            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
+            gen_ldst_modrm(env, s, modrm, OT_WORD, OR_TMP0, 0);
             t0 = tcg_temp_local_new();
             if (s->cc_op != CC_OP_DYNAMIC)
                 gen_op_set_cc_op(s->cc_op);
@@ -7543,7 +7547,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         }
         break;
     case 0x118:
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         op = (modrm >> 3) & 7;
         switch(op) {
@@ -7553,24 +7557,24 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         case 3: /* prefetchnt0 */
             if (mod == 3)
                 goto illegal_op;
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             /* nothing more to do */
             break;
         default: /* nop (multi byte) */
-            gen_nop_modrm(s, modrm);
+            gen_nop_modrm(env, s, modrm);
             break;
         }
         break;
     case 0x119 ... 0x11f: /* nop (multi byte) */
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
-        gen_nop_modrm(s, modrm);
+        modrm = cpu_ldub_code(env, s->pc++);
+        gen_nop_modrm(env, s, modrm);
         break;
     case 0x120: /* mov reg, crN */
     case 0x122: /* mov crN, reg */
         if (s->cpl != 0) {
             gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
         } else {
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
              * AMD documentation (24594.pdf) and testing of
              * intel 386 and 486 processors all show that the mod bits
@@ -7616,7 +7620,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         if (s->cpl != 0) {
             gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
         } else {
-            modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+            modrm = cpu_ldub_code(env, s->pc++);
             /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
              * AMD documentation (24594.pdf) and testing of
              * intel 386 and 486 processors all show that the mod bits
@@ -7660,16 +7664,16 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         if (!(s->cpuid_features & CPUID_SSE2))
             goto illegal_op;
         ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         if (mod == 3)
             goto illegal_op;
         reg = ((modrm >> 3) & 7) | rex_r;
         /* generate a generic store */
-        gen_ldst_modrm(s, modrm, ot, reg, 1);
+        gen_ldst_modrm(env, s, modrm, ot, reg, 1);
         break;
     case 0x1ae:
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         op = (modrm >> 3) & 7;
         switch(op) {
@@ -7681,7 +7685,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
                 break;
             }
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             if (s->cc_op != CC_OP_DYNAMIC)
                 gen_op_set_cc_op(s->cc_op);
             gen_jmp_im(pc_start - s->cs_base);
@@ -7695,7 +7699,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
                 break;
             }
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             if (s->cc_op != CC_OP_DYNAMIC)
                 gen_op_set_cc_op(s->cc_op);
             gen_jmp_im(pc_start - s->cs_base);
@@ -7711,7 +7715,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
             if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
                 mod == 3)
                 goto illegal_op;
-            gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+            gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             if (op == 2) {
                 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
                 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
@@ -7736,7 +7740,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
                 /* clflush */
                 if (!(s->cpuid_features & CPUID_CLFLUSH))
                     goto illegal_op;
-                gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+                gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
             }
             break;
         default:
@@ -7744,11 +7748,11 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         }
         break;
     case 0x10d: /* 3DNow! prefetch(w) */
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         mod = (modrm >> 6) & 3;
         if (mod == 3)
             goto illegal_op;
-        gen_lea_modrm(s, modrm, ®_addr, &offset_addr);
+        gen_lea_modrm(env, s, modrm, ®_addr, &offset_addr);
         /* ignore for now */
         break;
     case 0x1aa: /* rsm */
@@ -7767,7 +7771,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
             goto illegal_op;
 
-        modrm = cpu_ldub_code(cpu_single_env, s->pc++);
+        modrm = cpu_ldub_code(env, s->pc++);
         reg = ((modrm >> 3) & 7) | rex_r;
 
         if (s->prefix & PREFIX_DATA)
@@ -7777,7 +7781,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
         else
             ot = OT_QUAD;
 
-        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
+        gen_ldst_modrm(env, s, modrm, ot, OR_TMP0, 0);
         gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
         gen_op_mov_reg_T0(ot, reg);
 
@@ -7794,7 +7798,7 @@ static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
     case 0x1c2:
     case 0x1c4 ... 0x1c6:
     case 0x1d0 ... 0x1fe:
-        gen_sse(s, b, pc_start, rex_r);
+        gen_sse(env, s, b, pc_start, rex_r);
         break;
     default:
         goto illegal_op;
@@ -7994,7 +7998,7 @@ static inline void gen_intermediate_code_internal(CPUX86State *env,
         if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
             gen_io_start();
 
-        pc_ptr = disas_insn(dc, pc_ptr);
+        pc_ptr = disas_insn(env, dc, pc_ptr);
         num_insns++;
         /* stop translation if indicated */
         if (dc->is_jmp)

From 7c2c3ea3fd9e108a1c174a5db021ac1d33b1a22d Mon Sep 17 00:00:00 2001
From: Eric Johnson 
Date: Fri, 9 Nov 2012 19:40:51 -0800
Subject: [PATCH 290/291] target-mips: Fix seg fault for LUI when
 MIPS_DEBUG_DISAS==1.

The call to gen_logic_imm for OPC_LUI passes -1 for rs.  This
causes the MIPS_DEBUG statement to seg fault due to the deference
of regnames[rs].  This patch fixes that.

Signed-off-by: Eric Johnson 
Signed-off-by: Aurelien Jarno 
(aurel32: replaced static string formating by a static string)
---
 target-mips/translate.c | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index df92781b2c..f6fc0c27ae 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -2013,7 +2013,6 @@ static void gen_logic_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
                           int rt, int rs, int16_t imm)
 {
     target_ulong uimm;
-    const char *opn = "imm logic";
 
     if (rt == 0) {
         /* If no destination, treat it as a NOP. */
@@ -2027,29 +2026,34 @@ static void gen_logic_imm(CPUMIPSState *env, DisasContext *ctx, uint32_t opc,
             tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
         else
             tcg_gen_movi_tl(cpu_gpr[rt], 0);
-        opn = "andi";
+        MIPS_DEBUG("andi %s, %s, " TARGET_FMT_lx, regnames[rt],
+                   regnames[rs], uimm);
         break;
     case OPC_ORI:
         if (rs != 0)
             tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
         else
             tcg_gen_movi_tl(cpu_gpr[rt], uimm);
-        opn = "ori";
+        MIPS_DEBUG("ori %s, %s, " TARGET_FMT_lx, regnames[rt],
+                   regnames[rs], uimm);
         break;
     case OPC_XORI:
         if (likely(rs != 0))
             tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm);
         else
             tcg_gen_movi_tl(cpu_gpr[rt], uimm);
-        opn = "xori";
+        MIPS_DEBUG("xori %s, %s, " TARGET_FMT_lx, regnames[rt],
+                   regnames[rs], uimm);
         break;
     case OPC_LUI:
         tcg_gen_movi_tl(cpu_gpr[rt], imm << 16);
-        opn = "lui";
+        MIPS_DEBUG("lui %s, " TARGET_FMT_lx, regnames[rt], uimm);
+        break;
+
+    default:
+        MIPS_DEBUG("Unknown logical immediate opcode %08x", opc);
         break;
     }
-    (void)opn; /* avoid a compiler warning */
-    MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm);
 }
 
 /* Set on less than with immediate operand */

From 3c5645fab3c4b65d0cffbe1aaafc787e4be63d0f Mon Sep 17 00:00:00 2001
From: Kirill Batuzov 
Date: Wed, 7 Nov 2012 15:26:38 +0400
Subject: [PATCH 291/291] tcg: properly check that op's output needs to be
 synced to memory

Fix typo introduced in b3a1be87bac3a6aaa59bb88c1410f170dc9b22d5.

Reported-by: Ruslan Savchenko 
Signed-off-by: Kirill Batuzov 
Signed-off-by: Aurelien Jarno 
---
 tcg/tcg.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index 42052dba7b..35fba50c7f 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -1337,8 +1337,8 @@ static void tcg_liveness_analysis(TCGContext *s)
                the low part.  The result can be optimized to a simple
                add or sub.  This happens often for x86_64 guest when the
                cpu mode is set to 32 bit.  */
-            if (dead_temps[args[1]] && !mem_temps[1]) {
-                if (dead_temps[args[0]] && !mem_temps[0]) {
+            if (dead_temps[args[1]] && !mem_temps[args[1]]) {
+                if (dead_temps[args[0]] && !mem_temps[args[0]]) {
                     goto do_remove;
                 }
                 /* Create the single operation plus nop.  */
@@ -1363,8 +1363,8 @@ static void tcg_liveness_analysis(TCGContext *s)
             nb_iargs = 2;
             nb_oargs = 2;
             /* Likewise, test for the high part of the operation dead.  */
-            if (dead_temps[args[1]] && !mem_temps[1]) {
-                if (dead_temps[args[0]] && !mem_temps[0]) {
+            if (dead_temps[args[1]] && !mem_temps[args[1]]) {
+                if (dead_temps[args[0]] && !mem_temps[args[0]]) {
                     goto do_remove;
                 }
                 gen_opc_buf[op_index] = op = INDEX_op_mul_i32;