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xbox: call southbridge components xbox* instead of mcpx* 

'mcpx' seems refer specifically to the APU
This commit is contained in:
espes 2012-10-27 18:23:46 +11:00
parent 0134ec8a81
commit cd5a59724d
6 changed files with 123 additions and 124 deletions
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69
hw/acpi_mcpx.c → hw/acpi_xbox.c
View File

@ -31,87 +31,86 @@
#include "sysemu.h"
#include "acpi.h"
#include "xbox_pci.h"
#include "acpi_mcpx.h"
#include "acpi_xbox.h"
//#define DEBUG
#ifdef DEBUG
# define MCPX_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
# define XBOX_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
#else
# define MCPX_DPRINTF(format, ...) do { } while (0)
# define XBOX_DPRINTF(format, ...) do { } while (0)
#endif
static void mcpx_pm_update_sci_gn(ACPIREGS *regs)
static void xbox_pm_update_sci_gn(ACPIREGS *regs)
{
MCPX_PMRegs *pm = container_of(regs, MCPX_PMRegs, acpi_regs);
XBOX_PMRegs *pm = container_of(regs, XBOX_PMRegs, acpi_regs);
//pm_update_sci(pm);
}
#define MCPX_PMIO_PM1_STS 0x0
#define MCPX_PMIO_PM1_EN 0x2
#define MCPX_PMIO_PM1_CNT 0x4
#define MCPX_PMIO_PM_TMR 0x8
#define XBOX_PMIO_PM1_STS 0x0
#define XBOX_PMIO_PM1_EN 0x2
#define XBOX_PMIO_PM1_CNT 0x4
#define XBOX_PMIO_PM_TMR 0x8
static void mcpx_pm_ioport_write(void *opaque,
static void xbox_pm_ioport_write(void *opaque,
hwaddr addr,
uint64_t val, unsigned size)
{
MCPX_PMRegs *pm = opaque;
XBOX_PMRegs *pm = opaque;
switch (addr) {
case MCPX_PMIO_PM1_STS:
case XBOX_PMIO_PM1_STS:
acpi_pm1_evt_write_sts(&pm->acpi_regs, val);
//pm_update_sci(pm);
break;
case MCPX_PMIO_PM1_EN:
case XBOX_PMIO_PM1_EN:
pm->acpi_regs.pm1.evt.en = val;
//pm_update_sci(pm);
break;
case MCPX_PMIO_PM1_CNT:
case XBOX_PMIO_PM1_CNT:
acpi_pm1_cnt_write(&pm->acpi_regs, val, 0);
break;
default:
break;
}
MCPX_DPRINTF("PM: write port=0x%04x val=0x%04x\n",
XBOX_DPRINTF("PM: write port=0x%04x val=0x%04x\n",
(unsigned int)addr, (unsigned int)val);
}
static uint64_t mcpx_pm_ioport_read(void *opaque,
static uint64_t xbox_pm_ioport_read(void *opaque,
hwaddr addr,
unsigned size)
{
MCPX_PMRegs *pm = opaque;
XBOX_PMRegs *pm = opaque;
uint64_t val;
switch (addr) {
case MCPX_PMIO_PM1_STS:
case XBOX_PMIO_PM1_STS:
val = acpi_pm1_evt_get_sts(&pm->acpi_regs);
break;
case MCPX_PMIO_PM1_EN:
case XBOX_PMIO_PM1_EN:
val = pm->acpi_regs.pm1.evt.en;
break;
case MCPX_PMIO_PM1_CNT:
case XBOX_PMIO_PM1_CNT:
val = pm->acpi_regs.pm1.cnt.cnt;
break;
case MCPX_PMIO_PM_TMR:
case XBOX_PMIO_PM_TMR:
val = acpi_pm_tmr_get(&pm->acpi_regs);
break;
default:
val = 0;
break;
}
MCPX_DPRINTF("PM: read port=0x%04x val=0x%04x\n",
XBOX_DPRINTF("PM: read port=0x%04x val=0x%04x\n",
(unsigned int)addr, (unsigned int)val);
return val;
}
static const MemoryRegionOps mcpx_pm_ops = {
.read = mcpx_pm_ioport_read,
.write = mcpx_pm_ioport_write,
static const MemoryRegionOps xbox_pm_ops = {
.read = xbox_pm_ioport_read,
.write = xbox_pm_ioport_write,
.impl = {
.min_access_size = 1,
.max_access_size = 1,
@ -119,28 +118,28 @@ static const MemoryRegionOps mcpx_pm_ops = {
};
#if 0
void mcpx_pm_iospace_update(MCPX_PMRegs *pm, uint32_t pm_io_base) {
MCPX_DPRINTF("PM: iospace update to 0x%x\n", pm_io_base);
void xbox_pm_iospace_update(XBOX_PMRegs *pm, uint32_t pm_io_base) {
XBOX_DPRINTF("PM: iospace update to 0x%x\n", pm_io_base);
//Disabled when 0
if (pm_io_base != 0) {
iorange_init(&pm->ioport, &mcpx_iorange_ops, pm_io_base, 256);
iorange_init(&pm->ioport, &xbox_iorange_ops, pm_io_base, 256);
ioport_register(&pm->ioport);
}
}
#endif
#define MCPX_PM_BASE_BAR 0
#define XBOX_PM_BASE_BAR 0
void mcpx_pm_init(PCIDevice *dev, MCPX_PMRegs *pm/*, qemu_irq sci_irq*/) {
void xbox_pm_init(PCIDevice *dev, XBOX_PMRegs *pm/*, qemu_irq sci_irq*/) {
memory_region_init_io(&pm->bar, &mcpx_pm_ops,
pm, "mcpx-pm-bar", 256);
pci_register_bar(dev, MCPX_PM_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
memory_region_init_io(&pm->bar, &xbox_pm_ops,
pm, "xbox-pm-bar", 256);
pci_register_bar(dev, XBOX_PM_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
&pm->bar);
acpi_pm_tmr_init(&pm->acpi_regs, mcpx_pm_update_sci_gn);
acpi_pm_tmr_init(&pm->acpi_regs, xbox_pm_update_sci_gn);
acpi_pm1_cnt_init(&pm->acpi_regs);
//acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN);

14
hw/acpi_mcpx.h → hw/acpi_xbox.h
View File

@ -1,5 +1,5 @@
/*
* QEMU MCPX PM Emulation
* QEMU Xbox PM Emulation
*
* Copyright (c) 2012 espes
*
@ -17,20 +17,20 @@
* License along with this library; if not, see <http://www.gnu.org/licenses/>
*/
#ifndef HW_ACPI_MCPX_H
#define HW_ACPI_MCPX_H
#ifndef HW_ACPI_XBOX_H
#define HW_ACPI_XBOX_H
#include "acpi.h"
typedef struct MCPX_PMRegs {
typedef struct XBOX_PMRegs {
MemoryRegion bar;
ACPIREGS acpi_regs;
qemu_irq irq;
} MCPX_PMRegs;
} XBOX_PMRegs;
void mcpx_pm_init(PCIDevice *dev, MCPX_PMRegs *pm/*, qemu_irq sci_irq*/);
//void mcpx_pm_iospace_update(MCPX_PMRegs *pm, uint32_t pm_io_base);
void xbox_pm_init(PCIDevice *dev, XBOX_PMRegs *pm/*, qemu_irq sci_irq*/);
//void xbox_pm_iospace_update(MCPX_PMRegs *pm, uint32_t pm_io_base);
#endif

2
hw/i386/Makefile.objs
View File

@ -12,6 +12,6 @@ obj-$(CONFIG_XEN_PCI_PASSTHROUGH) += xen_pt.o xen_pt_config_init.o xen_pt_msi.o
obj-y += kvm/
obj-$(CONFIG_SPICE) += qxl.o qxl-logger.o qxl-render.o
obj-$(CONFIG_XBOX) += xbox.o xbox_pci.o acpi_mcpx.o amd_smbus.o nv2a.o smbus_xbox_smc.o smbus_cx25871.o smbus_adm1032.o
obj-$(CONFIG_XBOX) += xbox.o xbox_pci.o acpi_xbox.o amd_smbus.o nv2a.o smbus_xbox_smc.o smbus_cx25871.o smbus_adm1032.o
obj-y := $(addprefix ../,$(obj-y))

4
hw/xbox.c
View File

@ -216,8 +216,8 @@ static void xbox_init(QEMUMachineInitArgs *args)
/* bridges */
agp_bus = xbox_agp_init(host_bus);
isa_bus = mcpx_lpc_init(host_bus, gsi);
smbus = mcpx_smbus_init(host_bus, gsi);
isa_bus = xbox_lpc_init(host_bus, gsi);
smbus = xbox_smbus_init(host_bus, gsi);
/* irq shit */

134
hw/xbox_pci.c
View File

@ -27,7 +27,7 @@
#include "pci_bridge.h"
#include "pci_internals.h"
#include "exec-memory.h"
#include "acpi_mcpx.h"
#include "acpi_xbox.h"
#include "amd_smbus.h"
#include "qemu-common.h"
@ -128,34 +128,34 @@ PCIBus *xbox_agp_init(PCIBus *bus)
}
ISABus *mcpx_lpc_init(PCIBus *bus, qemu_irq *gsi)
ISABus *xbox_lpc_init(PCIBus *bus, qemu_irq *gsi)
{
PCIDevice *d;
MCPX_LPCState *s;
XBOX_LPCState *s;
//qemu_irq *sci_irq;
d = pci_create_simple_multifunction(bus, PCI_DEVFN(1, 0),
true, "mcpx-lpc");
true, "xbox-lpc");
s = MCPX_LPC_DEVICE(d);
s = XBOX_LPC_DEVICE(d);
//sci_irq = qemu_allocate_irqs(mcpx_set_sci, &s->irq_state, 1);
mcpx_pm_init(d, &s->pm /*, sci_irq[0]*/);
//mcpx_lpc_reset(&s->dev.qdev);
//sci_irq = qemu_allocate_irqs(xbox_set_sci, &s->irq_state, 1);
xbox_pm_init(d, &s->pm /*, sci_irq[0]*/);
//xbox_lpc_reset(&s->dev.qdev);
return s->isa_bus;
}
i2c_bus *mcpx_smbus_init(PCIBus *bus, qemu_irq *gsi)
i2c_bus *xbox_smbus_init(PCIBus *bus, qemu_irq *gsi)
{
PCIDevice *d;
MCPX_SMBState *s;
XBOX_SMBState *s;
d = pci_create_simple_multifunction(bus, PCI_DEVFN(1, 1),
true, "mcpx-smbus");
true, "xbox-smbus");
s = MCPX_SMBUS_DEVICE(d);
s = XBOX_SMBUS_DEVICE(d);
amd756_smbus_init(&d->qdev, &s->smb, gsi[11]);
return s->smb.smbus;
@ -164,29 +164,29 @@ i2c_bus *mcpx_smbus_init(PCIBus *bus, qemu_irq *gsi)
#define MCPX_SMBUS_BASE_BAR 1
#define XBOX_SMBUS_BASE_BAR 1
static void mcpx_smb_ioport_writeb(void *opaque, hwaddr addr,
static void xbox_smb_ioport_writeb(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
MCPX_SMBState *s = opaque;
XBOX_SMBState *s = opaque;
uint64_t offset = addr - s->dev.io_regions[MCPX_SMBUS_BASE_BAR].addr;
uint64_t offset = addr - s->dev.io_regions[XBOX_SMBUS_BASE_BAR].addr;
amd756_smb_ioport_writeb(&s->smb, offset, val);
}
static uint64_t mcpx_smb_ioport_readb(void *opaque, hwaddr addr,
static uint64_t xbox_smb_ioport_readb(void *opaque, hwaddr addr,
unsigned size)
{
MCPX_SMBState *s = opaque;
XBOX_SMBState *s = opaque;
uint64_t offset = addr - s->dev.io_regions[MCPX_SMBUS_BASE_BAR].addr;
uint64_t offset = addr - s->dev.io_regions[XBOX_SMBUS_BASE_BAR].addr;
return amd756_smb_ioport_readb(&s->smb, offset);
}
static const MemoryRegionOps mcpx_smbus_ops = {
.read = mcpx_smb_ioport_readb,
.write = mcpx_smb_ioport_writeb,
static const MemoryRegionOps xbox_smbus_ops = {
.read = xbox_smb_ioport_readb,
.write = xbox_smb_ioport_writeb,
.endianness = DEVICE_LITTLE_ENDIAN,
.impl = {
.min_access_size = 1,
@ -194,25 +194,25 @@ static const MemoryRegionOps mcpx_smbus_ops = {
},
};
static int mcpx_smbus_initfn(PCIDevice *dev)
static int xbox_smbus_initfn(PCIDevice *dev)
{
MCPX_SMBState *s = MCPX_SMBUS_DEVICE(dev);
XBOX_SMBState *s = XBOX_SMBUS_DEVICE(dev);
memory_region_init_io(&s->smb_bar, &mcpx_smbus_ops,
s, "mcpx-smbus-bar", 32);
pci_register_bar(dev, MCPX_SMBUS_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
memory_region_init_io(&s->smb_bar, &xbox_smbus_ops,
s, "xbox-smbus-bar", 32);
pci_register_bar(dev, XBOX_SMBUS_BASE_BAR, PCI_BASE_ADDRESS_SPACE_IO,
&s->smb_bar);
return 0;
}
static void mcpx_smbus_class_init(ObjectClass *klass, void *data)
static void xbox_smbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->init = mcpx_smbus_initfn;
k->init = xbox_smbus_initfn;
k->vendor_id = PCI_VENDOR_ID_NVIDIA;
k->device_id = PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS;
k->revision = 161;
@ -222,11 +222,11 @@ static void mcpx_smbus_class_init(ObjectClass *klass, void *data)
dc->no_user = 1;
}
static const TypeInfo mcpx_smbus_info = {
.name = "mcpx-smbus",
static const TypeInfo xbox_smbus_info = {
.name = "xbox-smbus",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(MCPX_SMBState),
.class_init = mcpx_smbus_class_init,
.instance_size = sizeof(XBOX_SMBState),
.class_init = xbox_smbus_class_init,
};
@ -234,9 +234,9 @@ static const TypeInfo mcpx_smbus_info = {
static int mcpx_lpc_initfn(PCIDevice *d)
static int xbox_lpc_initfn(PCIDevice *d)
{
MCPX_LPCState *lpc = MCPX_LPC_DEVICE(d);
XBOX_LPCState *lpc = XBOX_LPC_DEVICE(d);
ISABus *isa_bus;
isa_bus = isa_bus_new(&d->qdev, get_system_io());
@ -247,60 +247,60 @@ static int mcpx_lpc_initfn(PCIDevice *d)
#if 0
/* Xbox 1.1 uses a config register instead of a bar to set the pm base address */
#define MCPX_LPC_PMBASE 0x84
#define MCPX_LPC_PMBASE_ADDRESS_MASK 0xff00
#define MCPX_LPC_PMBASE_DEFAULT 0x1
#define XBOX_LPC_PMBASE 0x84
#define XBOX_LPC_PMBASE_ADDRESS_MASK 0xff00
#define XBOX_LPC_PMBASE_DEFAULT 0x1
static void mcpx_lpc_pmbase_update(MCPX_LPCState *s)
static void xbox_lpc_pmbase_update(XBOX_LPCState *s)
{
uint32_t pm_io_base = pci_get_long(s->dev.config + MCPX_LPC_PMBASE);
pm_io_base &= MCPX_LPC_PMBASE_ADDRESS_MASK;
uint32_t pm_io_base = pci_get_long(s->dev.config + XBOX_LPC_PMBASE);
pm_io_base &= XBOX_LPC_PMBASE_ADDRESS_MASK;
mcpx_pm_iospace_update(&s->pm, pm_io_base);
xbox_pm_iospace_update(&s->pm, pm_io_base);
}
static void mcpx_lpc_reset(DeviceState *dev)
static void xbox_lpc_reset(DeviceState *dev)
{
PCIDevice *d = PCI_DEVICE(dev);
MCPX_LPCState *s = MCPX_LPC_DEVICE(d);
XBOX_LPCState *s = XBOX_LPC_DEVICE(d);
pci_set_long(s->dev.config + MCPX_LPC_PMBASE, MCPX_LPC_PMBASE_DEFAULT);
mcpx_lpc_pmbase_update(s);
pci_set_long(s->dev.config + XBOX_LPC_PMBASE, XBOX_LPC_PMBASE_DEFAULT);
xbox_lpc_pmbase_update(s);
}
static void mcpx_lpc_config_write(PCIDevice *dev,
static void xbox_lpc_config_write(PCIDevice *dev,
uint32_t addr, uint32_t val, int len)
{
MCPX_LPCState *s = MCPX_LPC_DEVICE(dev);
XBOX_LPCState *s = XBOX_LPC_DEVICE(dev);
pci_default_write_config(dev, addr, val, len);
if (ranges_overlap(addr, len, MCPX_LPC_PMBASE, 2)) {
mcpx_lpc_pmbase_update(s);
if (ranges_overlap(addr, len, XBOX_LPC_PMBASE, 2)) {
xbox_lpc_pmbase_update(s);
}
}
static int mcpx_lpc_post_load(void *opaque, int version_id)
static int xbox_lpc_post_load(void *opaque, int version_id)
{
MCPX_LPCState *s = opaque;
mcpx_lpc_pmbase_update(s);
XBOX_LPCState *s = opaque;
xbox_lpc_pmbase_update(s);
return 0;
}
static const VMStateDescription vmstate_mcpx_lpc = {
.name = "MCPX LPC",
static const VMStateDescription vmstate_xbox_lpc = {
.name = "XBOX LPC",
.version_id = 1,
.post_load = mcpx_lpc_post_load,
.post_load = xbox_lpc_post_load,
};
#endif
static void mcpx_lpc_class_init(ObjectClass *klass, void *data)
static void xbox_lpc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
k->no_hotplug = 1;
k->init = mcpx_lpc_initfn;
//k->config_write = mcpx_lpc_config_write;
k->init = xbox_lpc_initfn;
//k->config_write = xbox_lpc_config_write;
k->vendor_id = PCI_VENDOR_ID_NVIDIA;
k->device_id = PCI_DEVICE_ID_NVIDIA_NFORCE_LPC;
k->revision = 212;
@ -308,15 +308,15 @@ static void mcpx_lpc_class_init(ObjectClass *klass, void *data)
dc->desc = "nForce LPC Bridge";
dc->no_user = 1;
//dc->reset = mcpx_lpc_reset;
//dc->vmsd = &vmstate_mcpx_lpc;
//dc->reset = xbox_lpc_reset;
//dc->vmsd = &vmstate_xbox_lpc;
}
static const TypeInfo mcpx_lpc_info = {
.name = "mcpx-lpc",
static const TypeInfo xbox_lpc_info = {
.name = "xbox-lpc",
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(MCPX_LPCState),
.class_init = mcpx_lpc_class_init,
.instance_size = sizeof(XBOX_LPCState),
.class_init = xbox_lpc_class_init,
};
@ -435,8 +435,8 @@ static void xboxpci_register_types(void)
type_register(&xbox_pci_info);
type_register(&xbox_agp_info);
type_register(&mcpx_lpc_info);
type_register(&mcpx_smbus_info);
type_register(&xbox_lpc_info);
type_register(&xbox_smbus_info);
}
type_init(xboxpci_register_types)

24
hw/xbox_pci.h
View File

@ -28,7 +28,7 @@
#include "pci_host.h"
#include "amd_smbus.h"
#include "acpi.h"
#include "acpi_mcpx.h"
#include "acpi_xbox.h"
typedef struct XBOX_PCIState {
@ -40,28 +40,28 @@ typedef struct XBOX_PCIState {
MemoryRegion pci_hole;
} XBOX_PCIState;
typedef struct MCPX_SMBState {
typedef struct XBOX_SMBState {
PCIDevice dev;
AMD756SMBus smb;
MemoryRegion smb_bar;
} MCPX_SMBState;
} XBOX_SMBState;
typedef struct MCPX_LPCState {
typedef struct XBOX_LPCState {
PCIDevice dev;
ISABus *isa_bus;
MCPX_PMRegs pm;
} MCPX_LPCState;
XBOX_PMRegs pm;
} XBOX_LPCState;
#define XBOX_PCI_DEVICE(obj) \
OBJECT_CHECK(XBOX_PCIState, (obj), "xbox-pci")
#define MCPX_SMBUS_DEVICE(obj) \
OBJECT_CHECK(MCPX_SMBState, (obj), "mcpx-smbus")
#define XBOX_SMBUS_DEVICE(obj) \
OBJECT_CHECK(XBOX_SMBState, (obj), "xbox-smbus")
#define MCPX_LPC_DEVICE(obj) \
OBJECT_CHECK(MCPX_LPCState, (obj), "mcpx-lpc")
#define XBOX_LPC_DEVICE(obj) \
OBJECT_CHECK(XBOX_LPCState, (obj), "xbox-lpc")
@ -73,9 +73,9 @@ PCIBus *xbox_pci_init(qemu_irq *pic,
PCIBus *xbox_agp_init(PCIBus *bus);
ISABus *mcpx_lpc_init(PCIBus *bus, qemu_irq *gsi);
ISABus *xbox_lpc_init(PCIBus *bus, qemu_irq *gsi);
i2c_bus *mcpx_smbus_init(PCIBus *bus, qemu_irq *gsi);
i2c_bus *xbox_smbus_init(PCIBus *bus, qemu_irq *gsi);
#endif