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target-arm: A64: Add "Floating-point data-processing (3 source)" insns
This patch adds emulation for the "Floating-point data-processing (3 source)" group of instructions. Signed-off-by: Alexander Graf <agraf@suse.de> [WN: Commit message tweak, merged single and double precision patches. Implement using muladd as suggested by Richard Henderson.] Signed-off-by: Will Newton <will.newton@linaro.org> [PMM: pull field decode up a level, use register accessors] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -3367,6 +3367,82 @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
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}
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}
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}
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}
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/* C3.6.27 Floating-point data-processing (3 source) - single precision */
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static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1,
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int rd, int rn, int rm, int ra)
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{
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TCGv_i32 tcg_op1, tcg_op2, tcg_op3;
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TCGv_i32 tcg_res = tcg_temp_new_i32();
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TCGv_ptr fpst = get_fpstatus_ptr();
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tcg_op1 = read_fp_sreg(s, rn);
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tcg_op2 = read_fp_sreg(s, rm);
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tcg_op3 = read_fp_sreg(s, ra);
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/* These are fused multiply-add, and must be done as one
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* floating point operation with no rounding between the
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* multiplication and addition steps.
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* NB that doing the negations here as separate steps is
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* correct : an input NaN should come out with its sign bit
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* flipped if it is a negated-input.
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*/
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if (o1 == true) {
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gen_helper_vfp_negs(tcg_op3, tcg_op3);
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}
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if (o0 != o1) {
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gen_helper_vfp_negs(tcg_op1, tcg_op1);
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}
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gen_helper_vfp_muladds(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
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write_fp_sreg(s, rd, tcg_res);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i32(tcg_op1);
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tcg_temp_free_i32(tcg_op2);
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tcg_temp_free_i32(tcg_op3);
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tcg_temp_free_i32(tcg_res);
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}
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/* C3.6.27 Floating-point data-processing (3 source) - double precision */
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static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1,
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int rd, int rn, int rm, int ra)
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{
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TCGv_i64 tcg_op1, tcg_op2, tcg_op3;
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TCGv_i64 tcg_res = tcg_temp_new_i64();
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TCGv_ptr fpst = get_fpstatus_ptr();
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tcg_op1 = read_fp_dreg(s, rn);
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tcg_op2 = read_fp_dreg(s, rm);
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tcg_op3 = read_fp_dreg(s, ra);
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/* These are fused multiply-add, and must be done as one
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* floating point operation with no rounding between the
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* multiplication and addition steps.
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* NB that doing the negations here as separate steps is
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* correct : an input NaN should come out with its sign bit
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* flipped if it is a negated-input.
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*/
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if (o1 == true) {
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gen_helper_vfp_negd(tcg_op3, tcg_op3);
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}
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if (o0 != o1) {
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gen_helper_vfp_negd(tcg_op1, tcg_op1);
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}
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gen_helper_vfp_muladdd(tcg_res, tcg_op1, tcg_op2, tcg_op3, fpst);
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write_fp_dreg(s, rd, tcg_res);
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tcg_temp_free_ptr(fpst);
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tcg_temp_free_i64(tcg_op1);
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tcg_temp_free_i64(tcg_op2);
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tcg_temp_free_i64(tcg_op3);
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tcg_temp_free_i64(tcg_res);
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}
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/* C3.6.27 Floating point data-processing (3 source)
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/* C3.6.27 Floating point data-processing (3 source)
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* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
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* 31 30 29 28 24 23 22 21 20 16 15 14 10 9 5 4 0
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* +---+---+---+-----------+------+----+------+----+------+------+------+
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* +---+---+---+-----------+------+----+------+----+------+------+------+
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@ -3375,7 +3451,24 @@ static void disas_fp_2src(DisasContext *s, uint32_t insn)
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*/
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*/
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static void disas_fp_3src(DisasContext *s, uint32_t insn)
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static void disas_fp_3src(DisasContext *s, uint32_t insn)
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{
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{
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unsupported_encoding(s, insn);
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int type = extract32(insn, 22, 2);
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int rd = extract32(insn, 0, 5);
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int rn = extract32(insn, 5, 5);
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int ra = extract32(insn, 10, 5);
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int rm = extract32(insn, 16, 5);
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bool o0 = extract32(insn, 15, 1);
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bool o1 = extract32(insn, 21, 1);
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switch (type) {
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case 0:
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handle_fp_3src_single(s, o0, o1, rd, rn, rm, ra);
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break;
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case 1:
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handle_fp_3src_double(s, o0, o1, rd, rn, rm, ra);
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break;
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default:
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unallocated_encoding(s);
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}
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}
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}
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/* C3.6.28 Floating point immediate
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/* C3.6.28 Floating point immediate
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