From cca80462598c93858d7b07136e8d163ce8278566 Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Tue, 26 Apr 2022 09:30:23 -0700
Subject: [PATCH] target/arm: Use tcg_constant for gen_srs
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220426163043.100432-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/translate.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e4f3db26f6..8476f259fc 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -5137,12 +5137,10 @@ static void gen_srs(DisasContext *s,
}
addr = tcg_temp_new_i32();
- tmp = tcg_const_i32(mode);
/* get_r13_banked() will raise an exception if called from System mode */
gen_set_condexec(s);
gen_set_pc_im(s, s->pc_curr);
- gen_helper_get_r13_banked(addr, cpu_env, tmp);
- tcg_temp_free_i32(tmp);
+ gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode));
switch (amode) {
case 0: /* DA */
offset = -4;
@@ -5185,9 +5183,7 @@ static void gen_srs(DisasContext *s,
abort();
}
tcg_gen_addi_i32(addr, addr, offset);
- tmp = tcg_const_i32(mode);
- gen_helper_set_r13_banked(cpu_env, tmp, addr);
- tcg_temp_free_i32(tmp);
+ gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr);
}
tcg_temp_free_i32(addr);
s->base.is_jmp = DISAS_UPDATE_EXIT;