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target/arm: remove redundant tests 

In this context, the HCR value is the effective value, and thus is
zero in secure mode. The tests for HCR.{F,I}MO are sufficient.

Signed-off-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210112104511.36576-1-remi.denis.courmont@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Rémi Denis-Courmont 2021-01-12 12:44:53 +02:00 committed by Peter Maydell
parent 8073b87187
commit cc974d5cd8
2 changed files with 8 additions and 10 deletions
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8
target/arm/cpu.c
View File

@ -451,14 +451,14 @@ static inline bool arm_excp_unmasked(CPUState *cs, unsigned int excp_idx,
break; break;
case EXCP_VFIQ: case EXCP_VFIQ:
if (secure || !(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) { if (!(hcr_el2 & HCR_FMO) || (hcr_el2 & HCR_TGE)) {
/* VFIQs are only taken when hypervized and non-secure. */ /* VFIQs are only taken when hypervized. */
return false; return false;
} }
return !(env->daif & PSTATE_F); return !(env->daif & PSTATE_F);
case EXCP_VIRQ: case EXCP_VIRQ:
if (secure || !(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) { if (!(hcr_el2 & HCR_IMO) || (hcr_el2 & HCR_TGE)) {
/* VIRQs are only taken when hypervized and non-secure. */ /* VIRQs are only taken when hypervized. */
return false; return false;
} }
return !(env->daif & PSTATE_I); return !(env->daif & PSTATE_I);

10
target/arm/helper.c
View File

@ -2084,13 +2084,11 @@ static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri) static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
{ {
CPUState *cs = env_cpu(env); CPUState *cs = env_cpu(env);
uint64_t hcr_el2 = arm_hcr_el2_eff(env); bool el1 = arm_current_el(env) == 1;
uint64_t hcr_el2 = el1 ? arm_hcr_el2_eff(env) : 0;
uint64_t ret = 0; uint64_t ret = 0;
bool allow_virt = (arm_current_el(env) == 1 &&
(!arm_is_secure_below_el3(env) ||
(env->cp15.scr_el3 & SCR_EEL2)));
if (allow_virt && (hcr_el2 & HCR_IMO)) { if (hcr_el2 & HCR_IMO) {
if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) {
ret |= CPSR_I; ret |= CPSR_I;
} }
@ -2100,7 +2098,7 @@ static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
} }
} }
if (allow_virt && (hcr_el2 & HCR_FMO)) { if (hcr_el2 & HCR_FMO) {
if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) {
ret |= CPSR_F; ret |= CPSR_F;
} }