mirror of https://github.com/xemu-project/xemu.git
target/i386: Fix exception classes for SSE/AVX instructions.
Fix the exception classes for some SSE/AVX instructions to match what is documented in the Intel manual. These changes are expected to have no functional effect on the behavior that qemu implements (primarily >= 16-byte memory alignment checks). For instance, since qemu does not implement the AC flag, there is no difference in behavior between Exception Classes 4 and 5 for instructions where the SSE version only takes <16 byte memory operands. Message-Id: <20230501111428.95998-2-ricky@rzhou.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Ricky Zhou
Paolo Bonzini
parent
afa94dabc5
commit
cab529b0dc
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@ -237,7 +237,7 @@ static void decode_group14(DisasContext *s, CPUX86State *env, X86OpEntry *entry,
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static void decode_0F6F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry opcodes_0F6F[4] = {
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X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex1 mmx), /* movq */
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X86_OP_ENTRY3(MOVDQ, P,q, None,None, Q,q, vex5 mmx), /* movq */
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X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa */
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X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu */
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{},
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@ -306,7 +306,7 @@ static void decode_0F7E(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
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static void decode_0F7F(DisasContext *s, CPUX86State *env, X86OpEntry *entry, uint8_t *b)
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{
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static const X86OpEntry opcodes_0F7F[4] = {
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1 mmx), /* movq */
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex5 mmx), /* movq */
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex1), /* movdqa */
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4_unal), /* movdqu */
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{},
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@ -639,15 +639,15 @@ static void decode_0F10(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
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static const X86OpEntry opcodes_0F10_reg[4] = {
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X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
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X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
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X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex4),
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X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex4), /* MOVSD */
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X86_OP_ENTRY3(VMOVSS, V,x, H,x, W,x, vex5),
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X86_OP_ENTRY3(VMOVLPx, V,x, H,x, W,x, vex5), /* MOVSD */
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};
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static const X86OpEntry opcodes_0F10_mem[4] = {
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X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPS */
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X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* MOVUPD */
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X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex4),
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X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex4),
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X86_OP_ENTRY3(VMOVSS_ld, V,x, H,x, M,ss, vex5),
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X86_OP_ENTRY3(VMOVSD_ld, V,x, H,x, M,sd, vex5),
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};
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if ((get_modrm(s, env) >> 6) == 3) {
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@ -662,15 +662,15 @@ static void decode_0F11(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
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static const X86OpEntry opcodes_0F11_reg[4] = {
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */
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X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex4),
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X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex4), /* MOVSD */
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X86_OP_ENTRY3(VMOVSS, W,x, H,x, V,x, vex5),
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X86_OP_ENTRY3(VMOVLPx, W,x, H,x, V,q, vex5), /* MOVSD */
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};
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static const X86OpEntry opcodes_0F11_mem[4] = {
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPS */
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X86_OP_ENTRY3(MOVDQ, W,x, None,None, V,x, vex4), /* MOVUPD */
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X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex4),
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X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex4), /* MOVSD */
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X86_OP_ENTRY3(VMOVSS_st, M,ss, None,None, V,x, vex5),
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X86_OP_ENTRY3(VMOVLPx_st, M,sd, None,None, V,x, vex5), /* MOVSD */
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};
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if ((get_modrm(s, env) >> 6) == 3) {
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@ -687,16 +687,16 @@ static void decode_0F12(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
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* Use dq for operand for compatibility with gen_MOVSD and
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* to allow VEX128 only.
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*/
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X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex4), /* MOVLPS */
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X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex4), /* MOVLPD */
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X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPS */
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X86_OP_ENTRY3(VMOVLPx_ld, V,dq, H,dq, M,q, vex5), /* MOVLPD */
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X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
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X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex4 cpuid(SSE3)), /* qq if VEX.256 */
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X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, WM,q, vex5 cpuid(SSE3)), /* qq if VEX.256 */
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};
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static const X86OpEntry opcodes_0F12_reg[4] = {
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X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex4),
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X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex4), /* MOVLPD */
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X86_OP_ENTRY3(VMOVHLPS, V,dq, H,dq, U,dq, vex7),
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X86_OP_ENTRY3(VMOVLPx, W,x, H,x, U,q, vex5), /* MOVLPD */
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X86_OP_ENTRY3(VMOVSLDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
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X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
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X86_OP_ENTRY3(VMOVDDUP, V,x, None,None, U,x, vex5 cpuid(SSE3)),
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};
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if ((get_modrm(s, env) >> 6) == 3) {
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@ -716,15 +716,15 @@ static void decode_0F16(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
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* Operand 1 technically only reads the low 64 bits, but uses dq so that
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* it is easier to check for op0 == op1 in an endianness-neutral manner.
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*/
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X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex4), /* MOVHPS */
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X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex4), /* MOVHPD */
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X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPS */
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X86_OP_ENTRY3(VMOVHPx_ld, V,dq, H,dq, M,q, vex5), /* MOVHPD */
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X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, W,x, vex4 cpuid(SSE3)),
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{},
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};
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static const X86OpEntry opcodes_0F16_reg[4] = {
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/* Same as above, operand 1 could be Hq if it wasn't for big-endian. */
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X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex4),
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X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex4), /* MOVHPD */
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X86_OP_ENTRY3(VMOVLHPS, V,dq, H,dq, U,q, vex7),
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X86_OP_ENTRY3(VMOVHPx, V,x, H,x, U,x, vex5), /* MOVHPD */
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X86_OP_ENTRY3(VMOVSHDUP, V,x, None,None, U,x, vex4 cpuid(SSE3)),
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{},
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};
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@ -824,7 +824,7 @@ static void decode_0FE6(DisasContext *s, CPUX86State *env, X86OpEntry *entry, ui
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static const X86OpEntry opcodes_0FE6[4] = {
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{},
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X86_OP_ENTRY2(VCVTTPD2DQ, V,x, W,x, vex2),
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X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex2),
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X86_OP_ENTRY2(VCVTDQ2PD, V,x, W,x, vex5),
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X86_OP_ENTRY2(VCVTPD2DQ, V,x, W,x, vex2),
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};
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*entry = *decode_by_prefix(s, opcodes_0FE6);
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@ -842,12 +842,12 @@ static const X86OpEntry opcodes_0F[256] = {
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[0x10] = X86_OP_GROUP0(0F10),
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[0x11] = X86_OP_GROUP0(0F11),
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[0x12] = X86_OP_GROUP0(0F12),
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[0x13] = X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex4 p_00_66),
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[0x13] = X86_OP_ENTRY3(VMOVLPx_st, M,q, None,None, V,q, vex5 p_00_66),
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[0x14] = X86_OP_ENTRY3(VUNPCKLPx, V,x, H,x, W,x, vex4 p_00_66),
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[0x15] = X86_OP_ENTRY3(VUNPCKHPx, V,x, H,x, W,x, vex4 p_00_66),
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[0x16] = X86_OP_GROUP0(0F16),
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/* Incorrectly listed as Mq,Vq in the manual */
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[0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex4 p_00_66),
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[0x17] = X86_OP_ENTRY3(VMOVHPx_st, M,q, None,None, V,dq, vex5 p_00_66),
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[0x50] = X86_OP_ENTRY3(MOVMSK, G,y, None,None, U,x, vex7 p_00_66),
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[0x51] = X86_OP_GROUP3(sse_unary, V,x, H,x, W,x, vex2_rep3 p_00_66_f3_f2), /* sqrtps */
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