hw/nvme updates

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Merge tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme into staging

hw/nvme updates

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# gpg: Signature made Fri 03 Jun 2022 12:52:08 PM PDT
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# gpg: Good signature from "Klaus Jensen <its@irrelevant.dk>" [unknown]
# gpg:                 aka "Klaus Jensen <k.jensen@samsung.com>" [unknown]
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# Primary key fingerprint: DDCA 4D9C 9EF9 31CC 3468  4272 63D5 6FC5 E55D A838
#      Subkey fingerprint: 5228 33AA 75E2 DCE6 A247  66C0 4DE1 AF31 6D4F 0DE9

* tag 'nvme-next-pull-request' of git://git.infradead.org/qemu-nvme:
  hw/nvme: add new command abort case
  hw/nvme: deprecate the use-intel-id compatibility parameter
  hw/nvme: bump firmware revision
  hw/nvme: do not report null uuid
  hw/nvme: do not auto-generate uuid
  hw/nvme: do not auto-generate eui64
  hw/nvme: enforce common serial per subsystem
  hw/nvme: fix smart aen
  hw/nvme: fix copy cmd for pi enabled namespaces
  hw/nvme: add missing return statement
  hw/nvme: fix narrowing conversion

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2022-06-03 14:14:24 -07:00
commit ca127b3fc2
7 changed files with 48 additions and 16 deletions

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@ -296,6 +296,21 @@ contains native support for this feature and thus use of the option
ROM approach is obsolete. The native SeaBIOS support can be activated ROM approach is obsolete. The native SeaBIOS support can be activated
by using ``-machine graphics=off``. by using ``-machine graphics=off``.
``-device nvme-ns,eui64-default=on|off`` (since 7.1)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
In QEMU versions 6.1, 6.2 and 7.0, the ``nvme-ns`` generates an EUI-64
identifer that is not globally unique. If an EUI-64 identifer is required, the
user must set it explicitly using the ``nvme-ns`` device parameter ``eui64``.
``-device nvme,use-intel-id=on|off`` (since 7.1)
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The ``nvme`` device originally used a PCI Vendor/Device Identifier combination
from Intel that was not properly allocated. Since version 5.2, the controller
has used a properly allocated identifier. Deprecate the ``use-intel-id``
machine compatibility parameter.
Block device options Block device options
'''''''''''''''''''' ''''''''''''''''''''

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@ -43,6 +43,7 @@
GlobalProperty hw_compat_7_0[] = { GlobalProperty hw_compat_7_0[] = {
{ "arm-gicv3-common", "force-8-bit-prio", "on" }, { "arm-gicv3-common", "force-8-bit-prio", "on" },
{ "nvme-ns", "eui64-default", "on"},
}; };
const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0); const size_t hw_compat_7_0_len = G_N_ELEMENTS(hw_compat_7_0);

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@ -2372,6 +2372,7 @@ static void nvme_dsm_md_cb(void *opaque, int ret)
} }
nvme_dsm_cb(iocb, 0); nvme_dsm_cb(iocb, 0);
return;
} }
iocb->aiocb = blk_aio_pwrite_zeroes(ns->blkconf.blk, nvme_moff(ns, slba), iocb->aiocb = blk_aio_pwrite_zeroes(ns->blkconf.blk, nvme_moff(ns, slba),
@ -2786,6 +2787,10 @@ static void nvme_copy_in_completed_cb(void *opaque, int ret)
size_t mlen = nvme_m2b(ns, nlb); size_t mlen = nvme_m2b(ns, nlb);
uint8_t *mbounce = iocb->bounce + nvme_l2b(ns, nlb); uint8_t *mbounce = iocb->bounce + nvme_l2b(ns, nlb);
status = nvme_dif_mangle_mdata(ns, mbounce, mlen, slba);
if (status) {
goto invalid;
}
status = nvme_dif_check(ns, iocb->bounce, len, mbounce, mlen, prinfor, status = nvme_dif_check(ns, iocb->bounce, len, mbounce, mlen, prinfor,
slba, apptag, appmask, &reftag); slba, apptag, appmask, &reftag);
if (status) { if (status) {
@ -4950,16 +4955,13 @@ static uint16_t nvme_identify_ns_descr_list(NvmeCtrl *n, NvmeRequest *req)
return NVME_INVALID_FIELD | NVME_DNR; return NVME_INVALID_FIELD | NVME_DNR;
} }
/* if (!qemu_uuid_is_null(&ns->params.uuid)) {
* If the EUI-64 field is 0 and the NGUID field is 0, the namespace must uuid.hdr.nidt = NVME_NIDT_UUID;
* provide a valid Namespace UUID in the Namespace Identification Descriptor uuid.hdr.nidl = NVME_NIDL_UUID;
* data structure. QEMU does not yet support setting NGUID. memcpy(uuid.v, ns->params.uuid.data, NVME_NIDL_UUID);
*/ memcpy(pos, &uuid, sizeof(uuid));
uuid.hdr.nidt = NVME_NIDT_UUID; pos += sizeof(uuid);
uuid.hdr.nidl = NVME_NIDL_UUID; }
memcpy(uuid.v, ns->params.uuid.data, NVME_NIDL_UUID);
memcpy(pos, &uuid, sizeof(uuid));
pos += sizeof(uuid);
if (ns->params.eui64) { if (ns->params.eui64) {
eui64.hdr.nidt = NVME_NIDT_EUI64; eui64.hdr.nidt = NVME_NIDT_EUI64;
@ -5320,7 +5322,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeRequest *req)
if ((n->temperature >= n->features.temp_thresh_hi) || if ((n->temperature >= n->features.temp_thresh_hi) ||
(n->temperature <= n->features.temp_thresh_low)) { (n->temperature <= n->features.temp_thresh_low)) {
nvme_smart_event(n, NVME_AER_INFO_SMART_TEMP_THRESH); nvme_smart_event(n, NVME_SMART_TEMPERATURE);
} }
break; break;
@ -6711,7 +6713,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev)
id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->vid = cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID));
id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID)); id->ssvid = cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR_ID));
strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' ');
strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' '); strpadcpy((char *)id->fr, sizeof(id->fr), QEMU_VERSION, ' ');
strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' '); strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' ');
id->cntlid = cpu_to_le16(n->cntlid); id->cntlid = cpu_to_le16(n->cntlid);

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@ -26,6 +26,11 @@ uint16_t nvme_check_prinfo(NvmeNamespace *ns, uint8_t prinfo, uint64_t slba,
return NVME_INVALID_PROT_INFO | NVME_DNR; return NVME_INVALID_PROT_INFO | NVME_DNR;
} }
if ((NVME_ID_NS_DPS_TYPE(ns->id_ns.dps) == NVME_ID_NS_DPS_TYPE_3) &&
(prinfo & NVME_PRINFO_PRCHK_REF)) {
return NVME_INVALID_PROT_INFO;
}
return NVME_SUCCESS; return NVME_SUCCESS;
} }

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@ -29,7 +29,8 @@ void nvme_ns_init_format(NvmeNamespace *ns)
{ {
NvmeIdNs *id_ns = &ns->id_ns; NvmeIdNs *id_ns = &ns->id_ns;
BlockDriverInfo bdi; BlockDriverInfo bdi;
int npdg, nlbas, ret; int npdg, ret;
int64_t nlbas;
ns->lbaf = id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)]; ns->lbaf = id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)];
ns->lbasz = 1 << ns->lbaf.ds; ns->lbasz = 1 << ns->lbaf.ds;
@ -42,7 +43,7 @@ void nvme_ns_init_format(NvmeNamespace *ns)
id_ns->ncap = id_ns->nsze; id_ns->ncap = id_ns->nsze;
id_ns->nuse = id_ns->ncap; id_ns->nuse = id_ns->ncap;
ns->moff = (int64_t)nlbas << ns->lbaf.ds; ns->moff = nlbas << ns->lbaf.ds;
npdg = ns->blkconf.discard_granularity / ns->lbasz; npdg = ns->blkconf.discard_granularity / ns->lbasz;
@ -613,7 +614,7 @@ static Property nvme_ns_props[] = {
DEFINE_PROP_BOOL("detached", NvmeNamespace, params.detached, false), DEFINE_PROP_BOOL("detached", NvmeNamespace, params.detached, false),
DEFINE_PROP_BOOL("shared", NvmeNamespace, params.shared, true), DEFINE_PROP_BOOL("shared", NvmeNamespace, params.shared, true),
DEFINE_PROP_UINT32("nsid", NvmeNamespace, params.nsid, 0), DEFINE_PROP_UINT32("nsid", NvmeNamespace, params.nsid, 0),
DEFINE_PROP_UUID("uuid", NvmeNamespace, params.uuid), DEFINE_PROP_UUID_NODEFAULT("uuid", NvmeNamespace, params.uuid),
DEFINE_PROP_UINT64("eui64", NvmeNamespace, params.eui64, 0), DEFINE_PROP_UINT64("eui64", NvmeNamespace, params.eui64, 0),
DEFINE_PROP_UINT16("ms", NvmeNamespace, params.ms, 0), DEFINE_PROP_UINT16("ms", NvmeNamespace, params.ms, 0),
DEFINE_PROP_UINT8("mset", NvmeNamespace, params.mset, 0), DEFINE_PROP_UINT8("mset", NvmeNamespace, params.mset, 0),
@ -640,7 +641,7 @@ static Property nvme_ns_props[] = {
DEFINE_PROP_SIZE("zoned.zrwas", NvmeNamespace, params.zrwas, 0), DEFINE_PROP_SIZE("zoned.zrwas", NvmeNamespace, params.zrwas, 0),
DEFINE_PROP_SIZE("zoned.zrwafg", NvmeNamespace, params.zrwafg, -1), DEFINE_PROP_SIZE("zoned.zrwafg", NvmeNamespace, params.zrwafg, -1),
DEFINE_PROP_BOOL("eui64-default", NvmeNamespace, params.eui64_default, DEFINE_PROP_BOOL("eui64-default", NvmeNamespace, params.eui64_default,
true), false),
DEFINE_PROP_END_OF_LIST(), DEFINE_PROP_END_OF_LIST(),
}; };

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@ -48,6 +48,7 @@ typedef struct NvmeSubsystem {
DeviceState parent_obj; DeviceState parent_obj;
NvmeBus bus; NvmeBus bus;
uint8_t subnqn[256]; uint8_t subnqn[256];
char *serial;
NvmeCtrl *ctrls[NVME_MAX_CONTROLLERS]; NvmeCtrl *ctrls[NVME_MAX_CONTROLLERS];
NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1]; NvmeNamespace *namespaces[NVME_MAX_NAMESPACES + 1];

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@ -27,6 +27,13 @@ int nvme_subsys_register_ctrl(NvmeCtrl *n, Error **errp)
return -1; return -1;
} }
if (!subsys->serial) {
subsys->serial = g_strdup(n->params.serial);
} else if (strcmp(subsys->serial, n->params.serial)) {
error_setg(errp, "invalid controller serial");
return -1;
}
subsys->ctrls[cntlid] = n; subsys->ctrls[cntlid] = n;
for (nsid = 1; nsid < ARRAY_SIZE(subsys->namespaces); nsid++) { for (nsid = 1; nsid < ARRAY_SIZE(subsys->namespaces); nsid++) {