ShuriZma
/
xemu
mirror of https://github.com/xemu-project/xemu.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

target/riscv: Allow enabling the Hypervisor extension 

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
This commit is contained in:
Alistair Francis 2020-01-31 17:03:11 -08:00 committed by Palmer Dabbelt
parent e44b50b5b2
commit c9eefe05a4
No known key found for this signature in database
GPG Key ID: 2E1319F35FBB1889
2 changed files with 6 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
target/riscv/cpu.c
View File

@ -453,6 +453,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
if (cpu->cfg.ext_u) {
target_misa |= RVU;
}
if (cpu->cfg.ext_h) {
target_misa |= RVH;
}
set_misa(env, RVXLEN | target_misa);
}
@ -488,6 +491,8 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
/* This is experimental so mark with 'x-' */
DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false),
DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),

1
target/riscv/cpu.h
View File

@ -258,6 +258,7 @@ typedef struct RISCVCPU {
bool ext_c;
bool ext_s;
bool ext_u;
bool ext_h;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;