mirror of https://github.com/xemu-project/xemu.git
RISC-V: Adding XTheadBa ISA extension
This patch adds support for the XTheadBa ISA extension. The patch uses the T-Head specific decoder and translation. Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu> Message-Id: <20230131202013.2541053-4-christoph.muellner@vrull.eu> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -109,6 +109,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
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ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
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ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
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ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
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ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
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ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
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ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
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ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
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ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
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ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
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ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
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ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
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ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
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ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0, ext_XVentanaCondOps),
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@ -1090,6 +1091,7 @@ static Property riscv_cpu_extensions[] = {
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DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
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DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
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/* Vendor-specific custom extensions */
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/* Vendor-specific custom extensions */
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DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
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DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
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DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
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DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
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DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
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DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
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DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps, false),
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@ -473,6 +473,7 @@ struct RISCVCPUConfig {
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uint64_t mimpid;
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uint64_t mimpid;
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/* Vendor-specific custom extensions */
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/* Vendor-specific custom extensions */
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bool ext_xtheadba;
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bool ext_xtheadcmo;
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bool ext_xtheadcmo;
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bool ext_xtheadsync;
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bool ext_xtheadsync;
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bool ext_XVentanaCondOps;
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bool ext_XVentanaCondOps;
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@ -16,6 +16,12 @@
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* this program. If not, see <http://www.gnu.org/licenses/>.
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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*/
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#define REQUIRE_XTHEADBA(ctx) do { \
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if (!ctx->cfg_ptr->ext_xtheadba) { \
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return false; \
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} \
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} while (0)
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#define REQUIRE_XTHEADCMO(ctx) do { \
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#define REQUIRE_XTHEADCMO(ctx) do { \
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if (!ctx->cfg_ptr->ext_xtheadcmo) { \
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if (!ctx->cfg_ptr->ext_xtheadcmo) { \
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return false; \
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return false; \
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@ -28,6 +34,39 @@
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} \
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} \
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} while (0)
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} while (0)
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/* XTheadBa */
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/*
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* th.addsl is similar to sh[123]add (from Zba), but not an
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* alternative encoding: while sh[123] applies the shift to rs1,
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* th.addsl shifts rs2.
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*/
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#define GEN_TH_ADDSL(SHAMT) \
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static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \
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{ \
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TCGv t = tcg_temp_new(); \
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tcg_gen_shli_tl(t, arg2, SHAMT); \
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tcg_gen_add_tl(ret, t, arg1); \
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tcg_temp_free(t); \
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}
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GEN_TH_ADDSL(1)
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GEN_TH_ADDSL(2)
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GEN_TH_ADDSL(3)
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#define GEN_TRANS_TH_ADDSL(SHAMT) \
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static bool trans_th_addsl##SHAMT(DisasContext *ctx, \
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arg_th_addsl##SHAMT * a) \
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{ \
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REQUIRE_XTHEADBA(ctx); \
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return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \
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}
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GEN_TRANS_TH_ADDSL(1)
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GEN_TRANS_TH_ADDSL(2)
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GEN_TRANS_TH_ADDSL(3)
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/* XTheadCmo */
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/* XTheadCmo */
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static inline int priv_level(DisasContext *ctx)
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static inline int priv_level(DisasContext *ctx)
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@ -132,7 +132,8 @@ static bool always_true_p(DisasContext *ctx __attribute__((__unused__)))
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static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
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static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
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{
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{
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return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
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return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo ||
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ctx->cfg_ptr->ext_xtheadsync;
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}
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}
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#define MATERIALISE_EXT_PREDICATE(ext) \
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#define MATERIALISE_EXT_PREDICATE(ext) \
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@ -2,6 +2,7 @@
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# Translation routines for the instructions of the XThead* ISA extensions
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# Translation routines for the instructions of the XThead* ISA extensions
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#
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#
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# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
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# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
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# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
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#
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#
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# SPDX-License-Identifier: LGPL-2.1-or-later
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# SPDX-License-Identifier: LGPL-2.1-or-later
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#
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#
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@ -9,12 +10,33 @@
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# https://github.com/T-head-Semi/thead-extension-spec/releases/latest
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# https://github.com/T-head-Semi/thead-extension-spec/releases/latest
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# Fields:
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# Fields:
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%rd 7:5
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%rs1 15:5
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%rs1 15:5
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%rs2 20:5
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%rs2 20:5
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# Argument sets
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&r rd rs1 rs2 !extern
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# Formats
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# Formats
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@sfence_vm ....... ..... ..... ... ..... ....... %rs1
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@sfence_vm ....... ..... ..... ... ..... ....... %rs1
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@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
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@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
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@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
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# XTheadBa
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# Instead of defining a new encoding, we simply use the decoder to
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# extract the imm[0:1] field and dispatch to separate translation
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# functions (mirroring the `sh[123]add` instructions from Zba and
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# the regular RVI `add` instruction.
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#
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# The only difference between sh[123]add and addsl is that the shift
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# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
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#
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# Note that shift-by-0 is a valid operation according to the manual.
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# This will be equivalent to a regular add.
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add 0000000 ..... ..... 001 ..... 0001011 @r
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th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r
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th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r
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th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r
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# XTheadCmo
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# XTheadCmo
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th_dcache_call 0000000 00001 00000 000 00000 0001011
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th_dcache_call 0000000 00001 00000 000 00000 0001011
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