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hw/pci/pci: Remove multifunction parameter from pci_new_multifunction() 

There is also pci_new() which creates non-multifunction PCI devices.
Accordingly the parameter is always set to true when a multi function PCI
device is to be created.

The reason for the parameter's existence seems to be that it is used in the
internal PCI code as well which is the only location where it gets set to
false. This one usage can be resolved by factoring out an internal helper
function.

Remove this redundant, error-prone parameter.

Signed-off-by: Bernhard Beschow <shentey@gmail.com>
Message-Id: <20230304114043.121024-6-shentey@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
This commit is contained in:
Bernhard Beschow 2023-03-04 12:40:43 +01:00 committed by Michael S. Tsirkin
parent e052944a96
commit c925f40a29
5 changed files with 17 additions and 16 deletions
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6
hw/i386/pc_q35.c
View File

@ -100,12 +100,12 @@ static int ehci_create_ich9_with_companions(PCIBus *bus, int slot)
return -1;
}
ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), true, name);
ehci = pci_new_multifunction(PCI_DEVFN(slot, 7), name);
pci_realize_and_unref(ehci, bus, &error_fatal);
usbbus = QLIST_FIRST(&ehci->qdev.child_bus);
for (i = 0; i < 3; i++) {
uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func), true,
uhci = pci_new_multifunction(PCI_DEVFN(slot, comp[i].func),
comp[i].name);
qdev_prop_set_string(&uhci->qdev, "masterbus", usbbus->name);
qdev_prop_set_uint32(&uhci->qdev, "firstport", comp[i].port);
@ -239,7 +239,7 @@ static void pc_q35_init(MachineState *machine)
pcms->bus = host_bus;
/* create ISA bus */
lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC), true,
lpc = pci_new_multifunction(PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC),
TYPE_ICH9_LPC_DEVICE);
qdev_prop_set_bit(DEVICE(lpc), "smm-enabled",
x86_machine_is_smm_enabled(x86ms));

6
hw/pci-host/sabre.c
View File

@ -387,14 +387,12 @@ static void sabre_realize(DeviceState *dev, Error **errp)
pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu);
/* APB secondary busses */
pci_dev = pci_new_multifunction(PCI_DEVFN(1, 0), true,
TYPE_SIMBA_PCI_BRIDGE);
pci_dev = pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_SIMBA_PCI_BRIDGE);
s->bridgeB = PCI_BRIDGE(pci_dev);
pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq);
pci_realize_and_unref(pci_dev, phb->bus, &error_fatal);
pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), true,
TYPE_SIMBA_PCI_BRIDGE);
pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), TYPE_SIMBA_PCI_BRIDGE);
s->bridgeA = PCI_BRIDGE(pci_dev);
pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq);
pci_realize_and_unref(pci_dev, phb->bus, &error_fatal);

11
hw/pci/pci.c
View File

@ -2164,7 +2164,7 @@ static void pci_qdev_realize(DeviceState *qdev, Error **errp)
pci_dev->msi_trigger = pci_msi_trigger;
}
PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
static PCIDevice *pci_new_internal(int devfn, bool multifunction,
const char *name)
{
DeviceState *dev;
@ -2175,9 +2175,14 @@ PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
return PCI_DEVICE(dev);
}
PCIDevice *pci_new_multifunction(int devfn, const char *name)
{
return pci_new_internal(devfn, true, name);
}
PCIDevice *pci_new(int devfn, const char *name)
{
return pci_new_multifunction(devfn, false, name);
return pci_new_internal(devfn, false, name);
}
bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp)
@ -2188,7 +2193,7 @@ bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp)
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
const char *name)
{
PCIDevice *dev = pci_new_multifunction(devfn, true, name);
PCIDevice *dev = pci_new_multifunction(devfn, name);
pci_realize_and_unref(dev, bus, &error_fatal);
return dev;
}

5
hw/sparc64/sun4u.c
View File

@ -612,7 +612,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
pci_bus_set_slot_reserved_mask(pci_busA, 0xfffffff1);
pci_bus_set_slot_reserved_mask(pci_busB, 0xfffffff0);
ebus = pci_new_multifunction(PCI_DEVFN(1, 0), true, TYPE_EBUS);
ebus = pci_new_multifunction(PCI_DEVFN(1, 0), TYPE_EBUS);
qdev_prop_set_uint64(DEVICE(ebus), "console-serial-base",
hwdef->console_serial_base);
pci_realize_and_unref(ebus, pci_busA, &error_fatal);
@ -648,8 +648,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
if (!nd->model || strcmp(nd->model, mc->default_nic) == 0) {
if (!onboard_nic) {
pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1),
true, mc->default_nic);
pci_dev = pci_new_multifunction(PCI_DEVFN(1, 1), mc->default_nic);
bus = pci_busA;
memcpy(&macaddr, &nd->macaddr.a, sizeof(MACAddr));
onboard_nic = true;

3
include/hw/pci/pci.h
View File

@ -577,8 +577,7 @@ pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
pci_set_quad(config, (~mask & val) | (mask & rval));
}
PCIDevice *pci_new_multifunction(int devfn, bool multifunction,
const char *name);
PCIDevice *pci_new_multifunction(int devfn, const char *name);
PCIDevice *pci_new(int devfn, const char *name);
bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);