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target/mips: Fix cycle counter timing calculations 

The cp0_count_ns value is calculated from the CP0_COUNT_RATE_DEFAULT
constant in target/mips/cpu.c.  The cycle counter resolution is defined
per-CPU in target/mips/cpu-defs.c.inc; use this value for calculating
cp0_count_ns.  Fixings timing problems on guest OSs for the 20Kc CPU
which has a CCRes of 1.

Signed-off-by: Simon Burge <simonb@NetBSD.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211213135125.18378-1-simonb@NetBSD.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Simon Burge 2021-12-14 00:51:27 +11:00 committed by Philippe Mathieu-Daudé
parent b49872aa8f
commit c8aeab3a09
1 changed files with 2 additions and 1 deletions
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3
target/mips/cpu.c
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@ -440,8 +440,9 @@ static void mips_cp0_period_set(MIPSCPU *cpu)
{ {
CPUMIPSState *env = &cpu->env; CPUMIPSState *env = &cpu->env;
/* env->CCRes isn't initialised this early, use env->cpu_model->CCRes. */
env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock, env->cp0_count_ns = clock_ticks_to_ns(MIPS_CPU(cpu)->clock,
cpu->cp0_count_rate); env->cpu_model->CCRes);
assert(env->cp0_count_ns); assert(env->cp0_count_ns);
} }