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target/riscv: rvv-1.0: Add Zve64f support for configuration insns 

All Zve* extensions support the vector configuration instructions.

Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20220118014522.13613-3-frank.chang@sifive.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Frank Chang 2022-01-18 09:45:05 +08:00 committed by Alistair Francis
parent b4a99d4027
commit c7a26fb2f6
1 changed files with 4 additions and 2 deletions
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6
target/riscv/insn_trans/trans_rvv.c.inc
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@ -129,7 +129,8 @@ static bool do_vsetvl(DisasContext *s, int rd, int rs1, TCGv s2)
{ {
TCGv s1, dst; TCGv s1, dst;
if (!require_rvv(s) || !has_ext(s, RVV)) { if (!require_rvv(s) ||
!(has_ext(s, RVV) || s->ext_zve64f)) {
return false; return false;
} }
@ -164,7 +165,8 @@ static bool do_vsetivli(DisasContext *s, int rd, TCGv s1, TCGv s2)
{ {
TCGv dst; TCGv dst;
if (!require_rvv(s) || !has_ext(s, RVV)) { if (!require_rvv(s) ||
!(has_ext(s, RVV) || s->ext_zve64f)) {
return false; return false;
} }