From ecb4e01e3449074576ae866c4547b5ff3849ddd7 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Sun, 16 Mar 2014 14:49:11 +0100 Subject: [PATCH 01/23] target-s390x: Add missing 'static' and 'const' attributes This fixes warnings from the static code analysis (smatch). Signed-off-by: Stefan Weil Reviewed-by: Richard Henderson Signed-off-by: Michael Tokarev --- target-s390x/arch_dump.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target-s390x/arch_dump.c b/target-s390x/arch_dump.c index 5cbb53ca2e..a1554f5754 100644 --- a/target-s390x/arch_dump.c +++ b/target-s390x/arch_dump.c @@ -123,7 +123,7 @@ static void s390x_write_elf64_prefix(Note *note, S390CPU *cpu) } -struct NoteFuncDescStruct { +static const struct NoteFuncDescStruct { int contents_size; void (*note_contents_func)(Note *note, S390CPU *cpu); } note_func[] = { @@ -146,7 +146,7 @@ static int s390x_write_all_elf64_notes(const char *note_name, void *opaque) { Note note; - NoteFuncDesc *nf; + const NoteFuncDesc *nf; int note_size; int ret = -1; @@ -192,7 +192,7 @@ ssize_t cpu_get_note_size(int class, int machine, int nr_cpus) int name_size = 8; /* "CORE" or "QEMU" rounded */ size_t elf_note_size = 0; int note_head_size; - NoteFuncDesc *nf; + const NoteFuncDesc *nf; assert(class == ELFCLASS64); assert(machine == EM_S390); From 6df05bdd172d26b699fecf162c277286579f2c16 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Sun, 16 Mar 2014 19:07:55 +0100 Subject: [PATCH 02/23] target-arm: Add missing 'static' attribute This fixes a warning from the static code analysis (smatch). Signed-off-by: Stefan Weil Signed-off-by: Michael Tokarev --- target-arm/machine.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target-arm/machine.c b/target-arm/machine.c index 8f9e7d4d28..7ced87af58 100644 --- a/target-arm/machine.c +++ b/target-arm/machine.c @@ -88,7 +88,7 @@ static bool m_needed(void *opaque) return arm_feature(env, ARM_FEATURE_M); } -const VMStateDescription vmstate_m = { +static const VMStateDescription vmstate_m = { .name = "cpu/m", .version_id = 1, .minimum_version_id = 1, From 06ab66cfab317741ab55d164ec3530c08ce1a547 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Sun, 16 Mar 2014 19:13:18 +0100 Subject: [PATCH 03/23] hw/ide: Add missing 'static' attributes This fixes a warning from the static code analysis (smatch). Signed-off-by: Stefan Weil Signed-off-by: Michael Tokarev --- hw/ide/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ide/pci.c b/hw/ide/pci.c index 91151fc85e..d8b1157c2e 100644 --- a/hw/ide/pci.c +++ b/hw/ide/pci.c @@ -421,7 +421,7 @@ static const VMStateDescription vmstate_bmdma_current = { } }; -const VMStateDescription vmstate_bmdma_status = { +static const VMStateDescription vmstate_bmdma_status = { .name ="ide bmdma/status", .version_id = 1, .minimum_version_id = 1, From 08cf99629d5de859aad0d54bafb2f18803a86dfe Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Sun, 16 Mar 2014 19:02:52 +0100 Subject: [PATCH 04/23] util: Add 'static' attribute to function implementation The static code analyzer smatch complains because of a missing 'static' attribute: util/module.c:166:6: warning: symbol 'module_load' was not declared. Should it be static? 'static' is used in the forward declaration, but not in the implementation. Add it there, too. Signed-off-by: Stefan Weil Reviewed-by: Richard Henderson Signed-off-by: Michael Tokarev --- util/module.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/module.c b/util/module.c index 863a8a32a3..214effb39f 100644 --- a/util/module.c +++ b/util/module.c @@ -163,7 +163,7 @@ out: } #endif -void module_load(module_init_type type) +static void module_load(module_init_type type) { #ifdef CONFIG_MODULES char *fname = NULL; From a443bc3496658c9e144ad914933607ebc8418979 Mon Sep 17 00:00:00 2001 From: Stefan Weil Date: Sun, 16 Mar 2014 15:03:41 +0100 Subject: [PATCH 05/23] target-i386: Add missing 'static' and 'const' attributes This fixes warnings from the static code analysis (smatch). Signed-off-by: Stefan Weil Signed-off-by: Michael Tokarev --- target-i386/cpu.c | 2 +- target-i386/kvm.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index e7e62c5897..8fd1497dc4 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -316,7 +316,7 @@ typedef struct X86RegisterInfo32 { #define REGISTER(reg) \ [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg } -X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { +static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = { REGISTER(EAX), REGISTER(ECX), REGISTER(EDX), diff --git a/target-i386/kvm.c b/target-i386/kvm.c index 7a295f6f20..4389959f61 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -122,7 +122,7 @@ static struct kvm_cpuid2 *get_supported_cpuid(KVMState *s) return cpuid; } -struct kvm_para_features { +static const struct kvm_para_features { int cap; int feature; } para_features[] = { From b533f658a98325d0e47b36113bd9f5bcc046fdae Mon Sep 17 00:00:00 2001 From: Mario Smarduch Date: Wed, 19 Mar 2014 10:24:26 -0700 Subject: [PATCH 06/23] fix return check for KVM_GET_DIRTY_LOG ioctl Fix return condition check from kvm_vm_ioctl(s, KVM_GET_DIRTY_LOG, &d) to handle internal failures or no support for memory slot dirty bitmap. Otherwise the ioctl succeeds and continues with migration. Addresses BUG# 1294227 Signed-off-by: Mario Smarduch Signed-off-by: Michael Tokarev --- kvm-all.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/kvm-all.c b/kvm-all.c index 82a91199e1..cd4111dbda 100644 --- a/kvm-all.c +++ b/kvm-all.c @@ -441,7 +441,7 @@ static int kvm_physical_sync_dirty_bitmap(MemoryRegionSection *section) d.slot = mem->slot; - if (kvm_vm_ioctl(s, KVM_GET_DIRTY_LOG, &d) == -1) { + if (kvm_vm_ioctl(s, KVM_GET_DIRTY_LOG, &d) < 0) { DPRINTF("ioctl failed %d\n", errno); ret = -1; break; From 33632788089531a4452976ff40bbb15551d37fea Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 17 Mar 2014 21:46:25 +0000 Subject: [PATCH 07/23] doc: update sun4m documentation A few minor tidy-ups, plus add reference to the new -vga tcx and cg3 options. Signed-off-by: Mark Cave-Ayland Signed-off-by: Michael Tokarev --- qemu-doc.texi | 9 +++++---- qemu-options.hx | 10 +++++++++- 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/qemu-doc.texi b/qemu-doc.texi index ad31f2d2d0..6d684e2c21 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -1996,7 +1996,7 @@ QEMU emulates the following sun4m peripherals: @item IOMMU @item -TCX Frame buffer +TCX or cgthree Frame buffer @item Lance (Am7990) Ethernet @item @@ -2023,7 +2023,7 @@ firmware implementation. The goal is to implement a 100% IEEE A sample Linux 2.6 series kernel and ram disk image are available on the QEMU web site. There are still issues with NetBSD and OpenBSD, but -some kernel versions work. Please note that currently Solaris kernels +some kernel versions work. Please note that currently older Solaris kernels don't work probably due to interface issues between OpenBIOS and Solaris. @@ -2035,8 +2035,9 @@ The following options are specific to the Sparc32 emulation: @item -g @var{W}x@var{H}x[x@var{DEPTH}] -Set the initial TCX graphic mode. The default is 1024x768x8, currently -the only other possible mode is 1024x768x24. +Set the initial graphics mode. For TCX, the default is 1024x768x8 with the +option of 1024x768x24. For cgthree, the default is 1024x768x8 with the option +of 1152x900x8 for people who wish to use OBP. @item -prom-env @var{string} diff --git a/qemu-options.hx b/qemu-options.hx index ee5437b230..2d33815fb9 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -1043,7 +1043,7 @@ Rotate graphical output some deg left (only PXA LCD). ETEXI DEF("vga", HAS_ARG, QEMU_OPTION_vga, - "-vga [std|cirrus|vmware|qxl|xenfb|none]\n" + "-vga [std|cirrus|vmware|qxl|xenfb|tcx|cg3|none]\n" " select video card type\n", QEMU_ARCH_ALL) STEXI @item -vga @var{type} @@ -1068,6 +1068,14 @@ card. QXL paravirtual graphic card. It is VGA compatible (including VESA 2.0 VBE support). Works best with qxl guest drivers installed though. Recommended choice when using the spice protocol. +@item tcx +(sun4m only) Sun TCX framebuffer. This is the default framebuffer for +sun4m machines and offers both 8-bit and 24-bit colour depths at a +fixed resolution of 1024x768. +@item cg3 +(sun4m only) Sun cgthree framebuffer. This is a simple 8-bit framebuffer +for sun4m machines available in both 1024x768 (OpenBIOS) and 1152x900 (OBP) +resolutions aimed at people wishing to run older Solaris versions. @item none Disable VGA card. @end table From 340fb41b311356d66b280468698b1f2d7b0c1a56 Mon Sep 17 00:00:00 2001 From: Mark Cave-Ayland Date: Mon, 17 Mar 2014 21:46:26 +0000 Subject: [PATCH 08/23] doc: update default PowerPC framebuffer settings Since 1.7, the default framebuffer settings for PowerPC are 800x600x32. Signed-off-by: Mark Cave-Ayland CC: qemu-ppc@nongnu.org Signed-off-by: Michael Tokarev --- qemu-doc.texi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu-doc.texi b/qemu-doc.texi index 6d684e2c21..e6e20ebbd3 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -1938,7 +1938,7 @@ The following options are specific to the PowerPC emulation: @item -g @var{W}x@var{H}[x@var{DEPTH}] -Set the initial VGA graphic mode. The default is 800x600x15. +Set the initial VGA graphic mode. The default is 800x600x32. @item -prom-env @var{string} From e939c6ed619e2cf98c379318f6ee389c97163f18 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Mon, 17 Mar 2014 15:26:31 -0300 Subject: [PATCH 09/23] CODING_STYLE: Section about mixed declarations We had an unwritten rule about declarations having to be at beginning of blocks. Make it a written rule. Signed-off-by: Eduardo Habkost Reviewed-by: Stefan Weil Reviewed-by: Markus Armbruster Reviewed-by: Peter Maydell Signed-off-by: Michael Tokarev --- CODING_STYLE | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/CODING_STYLE b/CODING_STYLE index dcbce28a27..4280945ff0 100644 --- a/CODING_STYLE +++ b/CODING_STYLE @@ -84,3 +84,10 @@ and clarity it comes on a line by itself: Rationale: a consistent (except for functions...) bracing style reduces ambiguity and avoids needless churn when lines are added or removed. Furthermore, it is the QEMU coding style. + +5. Declarations + +Mixed declarations (interleaving statements and declarations within blocks) +are not allowed; declarations should be at the beginning of blocks. In other +words, the code should not generate warnings if using GCC's +-Wdeclaration-after-statement option. From 2cd49cbfab0dd294de421893048ab614518fa263 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:30 +0000 Subject: [PATCH 10/23] target-i386: Avoid shifting left into sign bit Add 'U' suffixes where necessary to avoid (1 << 31) which shifts left into the sign bit, which is undefined behaviour. Add the suffix also for other constants in the same groupings even if they don't shift into bit 31, for consistency. Signed-off-by: Peter Maydell Signed-off-by: Michael Tokarev --- target-i386/cpu.h | 324 +++++++++++++++++++++++----------------------- 1 file changed, 162 insertions(+), 162 deletions(-) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 4d1374c6cc..2a22a7d64e 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -194,35 +194,35 @@ #define CR0_PE_SHIFT 0 #define CR0_MP_SHIFT 1 -#define CR0_PE_MASK (1 << 0) -#define CR0_MP_MASK (1 << 1) -#define CR0_EM_MASK (1 << 2) -#define CR0_TS_MASK (1 << 3) -#define CR0_ET_MASK (1 << 4) -#define CR0_NE_MASK (1 << 5) -#define CR0_WP_MASK (1 << 16) -#define CR0_AM_MASK (1 << 18) -#define CR0_PG_MASK (1 << 31) +#define CR0_PE_MASK (1U << 0) +#define CR0_MP_MASK (1U << 1) +#define CR0_EM_MASK (1U << 2) +#define CR0_TS_MASK (1U << 3) +#define CR0_ET_MASK (1U << 4) +#define CR0_NE_MASK (1U << 5) +#define CR0_WP_MASK (1U << 16) +#define CR0_AM_MASK (1U << 18) +#define CR0_PG_MASK (1U << 31) -#define CR4_VME_MASK (1 << 0) -#define CR4_PVI_MASK (1 << 1) -#define CR4_TSD_MASK (1 << 2) -#define CR4_DE_MASK (1 << 3) -#define CR4_PSE_MASK (1 << 4) -#define CR4_PAE_MASK (1 << 5) -#define CR4_MCE_MASK (1 << 6) -#define CR4_PGE_MASK (1 << 7) -#define CR4_PCE_MASK (1 << 8) +#define CR4_VME_MASK (1U << 0) +#define CR4_PVI_MASK (1U << 1) +#define CR4_TSD_MASK (1U << 2) +#define CR4_DE_MASK (1U << 3) +#define CR4_PSE_MASK (1U << 4) +#define CR4_PAE_MASK (1U << 5) +#define CR4_MCE_MASK (1U << 6) +#define CR4_PGE_MASK (1U << 7) +#define CR4_PCE_MASK (1U << 8) #define CR4_OSFXSR_SHIFT 9 -#define CR4_OSFXSR_MASK (1 << CR4_OSFXSR_SHIFT) -#define CR4_OSXMMEXCPT_MASK (1 << 10) -#define CR4_VMXE_MASK (1 << 13) -#define CR4_SMXE_MASK (1 << 14) -#define CR4_FSGSBASE_MASK (1 << 16) -#define CR4_PCIDE_MASK (1 << 17) -#define CR4_OSXSAVE_MASK (1 << 18) -#define CR4_SMEP_MASK (1 << 20) -#define CR4_SMAP_MASK (1 << 21) +#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT) +#define CR4_OSXMMEXCPT_MASK (1U << 10) +#define CR4_VMXE_MASK (1U << 13) +#define CR4_SMXE_MASK (1U << 14) +#define CR4_FSGSBASE_MASK (1U << 16) +#define CR4_PCIDE_MASK (1U << 17) +#define CR4_OSXSAVE_MASK (1U << 18) +#define CR4_SMEP_MASK (1U << 20) +#define CR4_SMAP_MASK (1U << 21) #define DR6_BD (1 << 13) #define DR6_BS (1 << 14) @@ -407,96 +407,96 @@ typedef enum FeatureWord { typedef uint32_t FeatureWordArray[FEATURE_WORDS]; /* cpuid_features bits */ -#define CPUID_FP87 (1 << 0) -#define CPUID_VME (1 << 1) -#define CPUID_DE (1 << 2) -#define CPUID_PSE (1 << 3) -#define CPUID_TSC (1 << 4) -#define CPUID_MSR (1 << 5) -#define CPUID_PAE (1 << 6) -#define CPUID_MCE (1 << 7) -#define CPUID_CX8 (1 << 8) -#define CPUID_APIC (1 << 9) -#define CPUID_SEP (1 << 11) /* sysenter/sysexit */ -#define CPUID_MTRR (1 << 12) -#define CPUID_PGE (1 << 13) -#define CPUID_MCA (1 << 14) -#define CPUID_CMOV (1 << 15) -#define CPUID_PAT (1 << 16) -#define CPUID_PSE36 (1 << 17) -#define CPUID_PN (1 << 18) -#define CPUID_CLFLUSH (1 << 19) -#define CPUID_DTS (1 << 21) -#define CPUID_ACPI (1 << 22) -#define CPUID_MMX (1 << 23) -#define CPUID_FXSR (1 << 24) -#define CPUID_SSE (1 << 25) -#define CPUID_SSE2 (1 << 26) -#define CPUID_SS (1 << 27) -#define CPUID_HT (1 << 28) -#define CPUID_TM (1 << 29) -#define CPUID_IA64 (1 << 30) -#define CPUID_PBE (1 << 31) +#define CPUID_FP87 (1U << 0) +#define CPUID_VME (1U << 1) +#define CPUID_DE (1U << 2) +#define CPUID_PSE (1U << 3) +#define CPUID_TSC (1U << 4) +#define CPUID_MSR (1U << 5) +#define CPUID_PAE (1U << 6) +#define CPUID_MCE (1U << 7) +#define CPUID_CX8 (1U << 8) +#define CPUID_APIC (1U << 9) +#define CPUID_SEP (1U << 11) /* sysenter/sysexit */ +#define CPUID_MTRR (1U << 12) +#define CPUID_PGE (1U << 13) +#define CPUID_MCA (1U << 14) +#define CPUID_CMOV (1U << 15) +#define CPUID_PAT (1U << 16) +#define CPUID_PSE36 (1U << 17) +#define CPUID_PN (1U << 18) +#define CPUID_CLFLUSH (1U << 19) +#define CPUID_DTS (1U << 21) +#define CPUID_ACPI (1U << 22) +#define CPUID_MMX (1U << 23) +#define CPUID_FXSR (1U << 24) +#define CPUID_SSE (1U << 25) +#define CPUID_SSE2 (1U << 26) +#define CPUID_SS (1U << 27) +#define CPUID_HT (1U << 28) +#define CPUID_TM (1U << 29) +#define CPUID_IA64 (1U << 30) +#define CPUID_PBE (1U << 31) -#define CPUID_EXT_SSE3 (1 << 0) -#define CPUID_EXT_PCLMULQDQ (1 << 1) -#define CPUID_EXT_DTES64 (1 << 2) -#define CPUID_EXT_MONITOR (1 << 3) -#define CPUID_EXT_DSCPL (1 << 4) -#define CPUID_EXT_VMX (1 << 5) -#define CPUID_EXT_SMX (1 << 6) -#define CPUID_EXT_EST (1 << 7) -#define CPUID_EXT_TM2 (1 << 8) -#define CPUID_EXT_SSSE3 (1 << 9) -#define CPUID_EXT_CID (1 << 10) -#define CPUID_EXT_FMA (1 << 12) -#define CPUID_EXT_CX16 (1 << 13) -#define CPUID_EXT_XTPR (1 << 14) -#define CPUID_EXT_PDCM (1 << 15) -#define CPUID_EXT_PCID (1 << 17) -#define CPUID_EXT_DCA (1 << 18) -#define CPUID_EXT_SSE41 (1 << 19) -#define CPUID_EXT_SSE42 (1 << 20) -#define CPUID_EXT_X2APIC (1 << 21) -#define CPUID_EXT_MOVBE (1 << 22) -#define CPUID_EXT_POPCNT (1 << 23) -#define CPUID_EXT_TSC_DEADLINE_TIMER (1 << 24) -#define CPUID_EXT_AES (1 << 25) -#define CPUID_EXT_XSAVE (1 << 26) -#define CPUID_EXT_OSXSAVE (1 << 27) -#define CPUID_EXT_AVX (1 << 28) -#define CPUID_EXT_F16C (1 << 29) -#define CPUID_EXT_RDRAND (1 << 30) -#define CPUID_EXT_HYPERVISOR (1 << 31) +#define CPUID_EXT_SSE3 (1U << 0) +#define CPUID_EXT_PCLMULQDQ (1U << 1) +#define CPUID_EXT_DTES64 (1U << 2) +#define CPUID_EXT_MONITOR (1U << 3) +#define CPUID_EXT_DSCPL (1U << 4) +#define CPUID_EXT_VMX (1U << 5) +#define CPUID_EXT_SMX (1U << 6) +#define CPUID_EXT_EST (1U << 7) +#define CPUID_EXT_TM2 (1U << 8) +#define CPUID_EXT_SSSE3 (1U << 9) +#define CPUID_EXT_CID (1U << 10) +#define CPUID_EXT_FMA (1U << 12) +#define CPUID_EXT_CX16 (1U << 13) +#define CPUID_EXT_XTPR (1U << 14) +#define CPUID_EXT_PDCM (1U << 15) +#define CPUID_EXT_PCID (1U << 17) +#define CPUID_EXT_DCA (1U << 18) +#define CPUID_EXT_SSE41 (1U << 19) +#define CPUID_EXT_SSE42 (1U << 20) +#define CPUID_EXT_X2APIC (1U << 21) +#define CPUID_EXT_MOVBE (1U << 22) +#define CPUID_EXT_POPCNT (1U << 23) +#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24) +#define CPUID_EXT_AES (1U << 25) +#define CPUID_EXT_XSAVE (1U << 26) +#define CPUID_EXT_OSXSAVE (1U << 27) +#define CPUID_EXT_AVX (1U << 28) +#define CPUID_EXT_F16C (1U << 29) +#define CPUID_EXT_RDRAND (1U << 30) +#define CPUID_EXT_HYPERVISOR (1U << 31) -#define CPUID_EXT2_FPU (1 << 0) -#define CPUID_EXT2_VME (1 << 1) -#define CPUID_EXT2_DE (1 << 2) -#define CPUID_EXT2_PSE (1 << 3) -#define CPUID_EXT2_TSC (1 << 4) -#define CPUID_EXT2_MSR (1 << 5) -#define CPUID_EXT2_PAE (1 << 6) -#define CPUID_EXT2_MCE (1 << 7) -#define CPUID_EXT2_CX8 (1 << 8) -#define CPUID_EXT2_APIC (1 << 9) -#define CPUID_EXT2_SYSCALL (1 << 11) -#define CPUID_EXT2_MTRR (1 << 12) -#define CPUID_EXT2_PGE (1 << 13) -#define CPUID_EXT2_MCA (1 << 14) -#define CPUID_EXT2_CMOV (1 << 15) -#define CPUID_EXT2_PAT (1 << 16) -#define CPUID_EXT2_PSE36 (1 << 17) -#define CPUID_EXT2_MP (1 << 19) -#define CPUID_EXT2_NX (1 << 20) -#define CPUID_EXT2_MMXEXT (1 << 22) -#define CPUID_EXT2_MMX (1 << 23) -#define CPUID_EXT2_FXSR (1 << 24) -#define CPUID_EXT2_FFXSR (1 << 25) -#define CPUID_EXT2_PDPE1GB (1 << 26) -#define CPUID_EXT2_RDTSCP (1 << 27) -#define CPUID_EXT2_LM (1 << 29) -#define CPUID_EXT2_3DNOWEXT (1 << 30) -#define CPUID_EXT2_3DNOW (1 << 31) +#define CPUID_EXT2_FPU (1U << 0) +#define CPUID_EXT2_VME (1U << 1) +#define CPUID_EXT2_DE (1U << 2) +#define CPUID_EXT2_PSE (1U << 3) +#define CPUID_EXT2_TSC (1U << 4) +#define CPUID_EXT2_MSR (1U << 5) +#define CPUID_EXT2_PAE (1U << 6) +#define CPUID_EXT2_MCE (1U << 7) +#define CPUID_EXT2_CX8 (1U << 8) +#define CPUID_EXT2_APIC (1U << 9) +#define CPUID_EXT2_SYSCALL (1U << 11) +#define CPUID_EXT2_MTRR (1U << 12) +#define CPUID_EXT2_PGE (1U << 13) +#define CPUID_EXT2_MCA (1U << 14) +#define CPUID_EXT2_CMOV (1U << 15) +#define CPUID_EXT2_PAT (1U << 16) +#define CPUID_EXT2_PSE36 (1U << 17) +#define CPUID_EXT2_MP (1U << 19) +#define CPUID_EXT2_NX (1U << 20) +#define CPUID_EXT2_MMXEXT (1U << 22) +#define CPUID_EXT2_MMX (1U << 23) +#define CPUID_EXT2_FXSR (1U << 24) +#define CPUID_EXT2_FFXSR (1U << 25) +#define CPUID_EXT2_PDPE1GB (1U << 26) +#define CPUID_EXT2_RDTSCP (1U << 27) +#define CPUID_EXT2_LM (1U << 29) +#define CPUID_EXT2_3DNOWEXT (1U << 30) +#define CPUID_EXT2_3DNOW (1U << 31) /* CPUID[8000_0001].EDX bits that are aliase of CPUID[1].EDX bits on AMD CPUs */ #define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \ @@ -509,53 +509,53 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \ CPUID_EXT2_MMX | CPUID_EXT2_FXSR) -#define CPUID_EXT3_LAHF_LM (1 << 0) -#define CPUID_EXT3_CMP_LEG (1 << 1) -#define CPUID_EXT3_SVM (1 << 2) -#define CPUID_EXT3_EXTAPIC (1 << 3) -#define CPUID_EXT3_CR8LEG (1 << 4) -#define CPUID_EXT3_ABM (1 << 5) -#define CPUID_EXT3_SSE4A (1 << 6) -#define CPUID_EXT3_MISALIGNSSE (1 << 7) -#define CPUID_EXT3_3DNOWPREFETCH (1 << 8) -#define CPUID_EXT3_OSVW (1 << 9) -#define CPUID_EXT3_IBS (1 << 10) -#define CPUID_EXT3_XOP (1 << 11) -#define CPUID_EXT3_SKINIT (1 << 12) -#define CPUID_EXT3_WDT (1 << 13) -#define CPUID_EXT3_LWP (1 << 15) -#define CPUID_EXT3_FMA4 (1 << 16) -#define CPUID_EXT3_TCE (1 << 17) -#define CPUID_EXT3_NODEID (1 << 19) -#define CPUID_EXT3_TBM (1 << 21) -#define CPUID_EXT3_TOPOEXT (1 << 22) -#define CPUID_EXT3_PERFCORE (1 << 23) -#define CPUID_EXT3_PERFNB (1 << 24) +#define CPUID_EXT3_LAHF_LM (1U << 0) +#define CPUID_EXT3_CMP_LEG (1U << 1) +#define CPUID_EXT3_SVM (1U << 2) +#define CPUID_EXT3_EXTAPIC (1U << 3) +#define CPUID_EXT3_CR8LEG (1U << 4) +#define CPUID_EXT3_ABM (1U << 5) +#define CPUID_EXT3_SSE4A (1U << 6) +#define CPUID_EXT3_MISALIGNSSE (1U << 7) +#define CPUID_EXT3_3DNOWPREFETCH (1U << 8) +#define CPUID_EXT3_OSVW (1U << 9) +#define CPUID_EXT3_IBS (1U << 10) +#define CPUID_EXT3_XOP (1U << 11) +#define CPUID_EXT3_SKINIT (1U << 12) +#define CPUID_EXT3_WDT (1U << 13) +#define CPUID_EXT3_LWP (1U << 15) +#define CPUID_EXT3_FMA4 (1U << 16) +#define CPUID_EXT3_TCE (1U << 17) +#define CPUID_EXT3_NODEID (1U << 19) +#define CPUID_EXT3_TBM (1U << 21) +#define CPUID_EXT3_TOPOEXT (1U << 22) +#define CPUID_EXT3_PERFCORE (1U << 23) +#define CPUID_EXT3_PERFNB (1U << 24) -#define CPUID_SVM_NPT (1 << 0) -#define CPUID_SVM_LBRV (1 << 1) -#define CPUID_SVM_SVMLOCK (1 << 2) -#define CPUID_SVM_NRIPSAVE (1 << 3) -#define CPUID_SVM_TSCSCALE (1 << 4) -#define CPUID_SVM_VMCBCLEAN (1 << 5) -#define CPUID_SVM_FLUSHASID (1 << 6) -#define CPUID_SVM_DECODEASSIST (1 << 7) -#define CPUID_SVM_PAUSEFILTER (1 << 10) -#define CPUID_SVM_PFTHRESHOLD (1 << 12) +#define CPUID_SVM_NPT (1U << 0) +#define CPUID_SVM_LBRV (1U << 1) +#define CPUID_SVM_SVMLOCK (1U << 2) +#define CPUID_SVM_NRIPSAVE (1U << 3) +#define CPUID_SVM_TSCSCALE (1U << 4) +#define CPUID_SVM_VMCBCLEAN (1U << 5) +#define CPUID_SVM_FLUSHASID (1U << 6) +#define CPUID_SVM_DECODEASSIST (1U << 7) +#define CPUID_SVM_PAUSEFILTER (1U << 10) +#define CPUID_SVM_PFTHRESHOLD (1U << 12) -#define CPUID_7_0_EBX_FSGSBASE (1 << 0) -#define CPUID_7_0_EBX_BMI1 (1 << 3) -#define CPUID_7_0_EBX_HLE (1 << 4) -#define CPUID_7_0_EBX_AVX2 (1 << 5) -#define CPUID_7_0_EBX_SMEP (1 << 7) -#define CPUID_7_0_EBX_BMI2 (1 << 8) -#define CPUID_7_0_EBX_ERMS (1 << 9) -#define CPUID_7_0_EBX_INVPCID (1 << 10) -#define CPUID_7_0_EBX_RTM (1 << 11) -#define CPUID_7_0_EBX_MPX (1 << 14) -#define CPUID_7_0_EBX_RDSEED (1 << 18) -#define CPUID_7_0_EBX_ADX (1 << 19) -#define CPUID_7_0_EBX_SMAP (1 << 20) +#define CPUID_7_0_EBX_FSGSBASE (1U << 0) +#define CPUID_7_0_EBX_BMI1 (1U << 3) +#define CPUID_7_0_EBX_HLE (1U << 4) +#define CPUID_7_0_EBX_AVX2 (1U << 5) +#define CPUID_7_0_EBX_SMEP (1U << 7) +#define CPUID_7_0_EBX_BMI2 (1U << 8) +#define CPUID_7_0_EBX_ERMS (1U << 9) +#define CPUID_7_0_EBX_INVPCID (1U << 10) +#define CPUID_7_0_EBX_RTM (1U << 11) +#define CPUID_7_0_EBX_MPX (1U << 14) +#define CPUID_7_0_EBX_RDSEED (1U << 18) +#define CPUID_7_0_EBX_ADX (1U << 19) +#define CPUID_7_0_EBX_SMAP (1U << 20) #define CPUID_VENDOR_SZ 12 @@ -571,8 +571,8 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_VENDOR_VIA "CentaurHauls" -#define CPUID_MWAIT_IBE (1 << 1) /* Interrupts can exit capability */ -#define CPUID_MWAIT_EMX (1 << 0) /* enumeration supported */ +#define CPUID_MWAIT_IBE (1U << 1) /* Interrupts can exit capability */ +#define CPUID_MWAIT_EMX (1U << 0) /* enumeration supported */ #ifndef HYPERV_SPINLOCK_NEVER_RETRY #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF From 6d55574a656f3a533a370156aaefedcf7980d4d8 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:31 +0000 Subject: [PATCH 11/23] hw/intc/apic.c: Use uint32_t for mask word in foreach_apic Use unsigned arithmetic for operations on the mask word in the foreach_apic() macro, to avoid relying on undefined behaviour when shifting into the sign bit. Signed-off-by: Peter Maydell Reviewed-by: Stefan Weil Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael Tokarev --- hw/intc/apic.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/intc/apic.c b/hw/intc/apic.c index 361ae90b65..b8c061bdaa 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -201,12 +201,12 @@ static void apic_external_nmi(APICCommonState *s) #define foreach_apic(apic, deliver_bitmask, code) \ {\ - int __i, __j, __mask;\ + int __i, __j;\ for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\ - __mask = deliver_bitmask[__i];\ + uint32_t __mask = deliver_bitmask[__i];\ if (__mask) {\ for(__j = 0; __j < 32; __j++) {\ - if (__mask & (1 << __j)) {\ + if (__mask & (1U << __j)) {\ apic = local_apics[__i * 32 + __j];\ if (apic) {\ code;\ From ac43fa508cc1cfe6d6f67c8eb99dc012e52c164e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:32 +0000 Subject: [PATCH 12/23] hw/pci/pci_host.c: Avoid shifting left into sign bit Add U suffix to avoid undefined behaviour. Signed-off-by: Peter Maydell Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael Tokarev --- hw/pci/pci_host.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index 77c7d1f86b..3e26f9256c 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -142,8 +142,9 @@ static uint64_t pci_host_data_read(void *opaque, { PCIHostState *s = opaque; uint32_t val; - if (!(s->config_reg & (1 << 31))) + if (!(s->config_reg & (1U << 31))) { return 0xffffffff; + } val = pci_data_read(s->bus, s->config_reg | (addr & 3), len); PCI_DPRINTF("read addr " TARGET_FMT_plx " len %d val %x\n", addr, len, val); From d9631b90da6ac592ea76b41a654dd5d29b2645d4 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:33 +0000 Subject: [PATCH 13/23] hw/i386/acpi_build.c: Avoid shifting left into sign bit Add U suffix to avoid undefined behaviour. Signed-off-by: Peter Maydell Reviewed-by: Michael S. Tsirkin Signed-off-by: Michael Tokarev --- hw/i386/acpi-build.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 7597517b97..b34d9272d8 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -907,7 +907,7 @@ static void build_pci_bus_end(PCIBus *bus, void *bus_state) build_append_byte(notify, 0x7B); /* AndOp */ build_append_byte(notify, 0x68); /* Arg0Op */ - build_append_int(notify, 0x1 << i); + build_append_int(notify, 0x1U << i); build_append_byte(notify, 0x00); /* NullName */ build_append_byte(notify, 0x86); /* NotifyOp */ build_append_nameseg(notify, "S%.02X_", PCI_DEVFN(i, 0)); From f45cb2f43f5bb0a4122a64e61c746048b59a84ed Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:34 +0000 Subject: [PATCH 14/23] target-mips: Avoid shifting left into sign bit Add U suffix to various places where we shift a 1 left by 31, to avoid undefined behaviour. Signed-off-by: Peter Maydell Signed-off-by: Michael Tokarev --- target-mips/cpu.h | 2 +- target-mips/helper.c | 8 ++++---- target-mips/op_helper.c | 2 +- target-mips/translate_init.c | 22 +++++++++++----------- 4 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 3ba3229e66..6c2014eddd 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -775,7 +775,7 @@ static inline void compute_hflags(CPUMIPSState *env) and disable the MIPS IV extensions to the MIPS III ISA. Some other MIPS IV CPUs ignore the bit, so the check here would be too restrictive for them. */ - if (env->CP0_Status & (1 << CP0St_CU3)) { + if (env->CP0_Status & (1U << CP0St_CU3)) { env->hflags |= MIPS_HFLAG_COP1X; } } diff --git a/target-mips/helper.c b/target-mips/helper.c index b28ae9b033..064622cc31 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -458,7 +458,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->hflags &= ~(MIPS_HFLAG_KSU); /* EJTAG probe trap enable is not implemented... */ if (!(env->CP0_Status & (1 << CP0St_EXL))) - env->CP0_Cause &= ~(1 << CP0Ca_BD); + env->CP0_Cause &= ~(1U << CP0Ca_BD); env->active_tc.PC = (int32_t)0xBFC00480; set_hflags_for_handler(env); break; @@ -478,7 +478,7 @@ void mips_cpu_do_interrupt(CPUState *cs) env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; env->hflags &= ~(MIPS_HFLAG_KSU); if (!(env->CP0_Status & (1 << CP0St_EXL))) - env->CP0_Cause &= ~(1 << CP0Ca_BD); + env->CP0_Cause &= ~(1U << CP0Ca_BD); env->active_tc.PC = (int32_t)0xBFC00000; set_hflags_for_handler(env); break; @@ -616,9 +616,9 @@ void mips_cpu_do_interrupt(CPUState *cs) if (!(env->CP0_Status & (1 << CP0St_EXL))) { env->CP0_EPC = exception_resume_pc(env); if (env->hflags & MIPS_HFLAG_BMASK) { - env->CP0_Cause |= (1 << CP0Ca_BD); + env->CP0_Cause |= (1U << CP0Ca_BD); } else { - env->CP0_Cause &= ~(1 << CP0Ca_BD); + env->CP0_Cause &= ~(1U << CP0Ca_BD); } env->CP0_Status |= (1 << CP0St_EXL); env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0; diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index e56f038d71..4edec6c617 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -648,7 +648,7 @@ static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc, { uint32_t status; uint32_t tcu, tmx, tasid, tksu; - uint32_t mask = ((1 << CP0St_CU3) + uint32_t mask = ((1U << CP0St_CU3) | (1 << CP0St_CU2) | (1 << CP0St_CU1) | (1 << CP0St_CU0) diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index a64fd2b530..29dc2ef738 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c @@ -22,20 +22,20 @@ /* Have config1, uncached coherency */ #define MIPS_CONFIG0 \ - ((1 << CP0C0_M) | (0x2 << CP0C0_K0)) + ((1U << CP0C0_M) | (0x2 << CP0C0_K0)) /* Have config2, no coprocessor2 attached, no MDMX support attached, no performance counters, watch registers present, no code compression, EJTAG present, no FPU */ #define MIPS_CONFIG1 \ -((1 << CP0C1_M) | \ +((1U << CP0C1_M) | \ (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \ (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \ (0 << CP0C1_FP)) /* Have config3, no tertiary/secondary caches implemented */ #define MIPS_CONFIG2 \ -((1 << CP0C2_M)) +((1U << CP0C2_M)) /* No config4, no DSP ASE, no large physaddr (PABITS), no external interrupt controller, no vectored interrupts, @@ -301,16 +301,16 @@ static const mips_def_t mips_defs[] = (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID), .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS), .CP0_SRSConf0_rw_bitmask = 0x3fffffff, - .CP0_SRSConf0 = (1 << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | + .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) | (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1), .CP0_SRSConf1_rw_bitmask = 0x3fffffff, - .CP0_SRSConf1 = (1 << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | + .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) | (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4), .CP0_SRSConf2_rw_bitmask = 0x3fffffff, - .CP0_SRSConf2 = (1 << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | + .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) | (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7), .CP0_SRSConf3_rw_bitmask = 0x3fffffff, - .CP0_SRSConf3 = (1 << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | + .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) | (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10), .CP0_SRSConf4_rw_bitmask = 0x3fffffff, .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) | @@ -355,8 +355,8 @@ static const mips_def_t mips_defs[] = (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_M), - .CP0_Config4 = MIPS_CONFIG4 | (1 << CP0C4_M), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M), + .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M), .CP0_Config4_rw_bitmask = 0, .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR), .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) | @@ -670,7 +670,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def) programmable cache partitioning implemented, number of allocatable and sharable TLB entries, MVP has allocatable TCs, 2 VPEs implemented, 5 TCs implemented. */ - env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | + env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) | (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) | // TODO: actually do 2 VPEs. // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) | @@ -684,7 +684,7 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def) /* Allocatable CP1 have media extensions, allocatable CP1 have FP support, no UDI implemented, no CP2 implemented, 1 CP1 implemented. */ - env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | + env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) | (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) | (0x1 << CP0MVPC1_PCP1); } From 00b0179347bae12c5856c1195b67ef5dc7887b9b Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:35 +0000 Subject: [PATCH 15/23] hw/usb/hcd-ohci.c: Avoid shifting left into sign bit Add U suffix to avoid undefined behaviour. This is only strictly necessary for the 1<<31 cases, but we add it for the other constants in these groups for consistency. Signed-off-by: Peter Maydell Signed-off-by: Michael Tokarev --- hw/usb/hcd-ohci.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index 3d35058b14..93f186f5e7 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -234,15 +234,15 @@ struct ohci_iso_td { #define OHCI_STATUS_OCR (1<<3) #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) -#define OHCI_INTR_SO (1<<0) /* Scheduling overrun */ -#define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */ -#define OHCI_INTR_SF (1<<2) /* Start of frame */ -#define OHCI_INTR_RD (1<<3) /* Resume detect */ -#define OHCI_INTR_UE (1<<4) /* Unrecoverable error */ -#define OHCI_INTR_FNO (1<<5) /* Frame number overflow */ -#define OHCI_INTR_RHSC (1<<6) /* Root hub status change */ -#define OHCI_INTR_OC (1<<30) /* Ownership change */ -#define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */ +#define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */ +#define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */ +#define OHCI_INTR_SF (1U<<2) /* Start of frame */ +#define OHCI_INTR_RD (1U<<3) /* Resume detect */ +#define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */ +#define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */ +#define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */ +#define OHCI_INTR_OC (1U<<30) /* Ownership change */ +#define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */ #define OHCI_HCCA_SIZE 0x100 #define OHCI_HCCA_MASK 0xffffff00 @@ -253,7 +253,7 @@ struct ohci_iso_td { #define OHCI_FMI_FSMPS 0xffff0000 #define OHCI_FMI_FIT 0x80000000 -#define OHCI_FR_RT (1<<31) +#define OHCI_FR_RT (1U<<31) #define OHCI_LS_THRESH 0x628 @@ -265,12 +265,12 @@ struct ohci_iso_td { #define OHCI_RHA_NOCP (1<<12) #define OHCI_RHA_POTPGT_MASK 0xff000000 -#define OHCI_RHS_LPS (1<<0) -#define OHCI_RHS_OCI (1<<1) -#define OHCI_RHS_DRWE (1<<15) -#define OHCI_RHS_LPSC (1<<16) -#define OHCI_RHS_OCIC (1<<17) -#define OHCI_RHS_CRWE (1<<31) +#define OHCI_RHS_LPS (1U<<0) +#define OHCI_RHS_OCI (1U<<1) +#define OHCI_RHS_DRWE (1U<<15) +#define OHCI_RHS_LPSC (1U<<16) +#define OHCI_RHS_OCIC (1U<<17) +#define OHCI_RHS_CRWE (1U<<31) #define OHCI_PORT_CCS (1<<0) #define OHCI_PORT_PES (1<<1) From def60298825ccff006688ab9ee0ebb266c98b7e7 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:36 +0000 Subject: [PATCH 16/23] hw/intc/openpic: Avoid shifting left into sign bit Add U suffix to avoid undefined behaviour. This is only strictly necessary for the 1 << 31 cases; for consistency we extend it to other constants in the same group. Signed-off-by: Peter Maydell Signed-off-by: Michael Tokarev --- hw/intc/openpic.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 7df72f44f0..be76fbd78f 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -123,7 +123,7 @@ static FslMpicInfo fsl_mpic_42 = { #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */ #define IDR_EP_SHIFT 31 -#define IDR_EP_MASK (1 << IDR_EP_SHIFT) +#define IDR_EP_MASK (1U << IDR_EP_SHIFT) #define IDR_CI0_SHIFT 30 #define IDR_CI1_SHIFT 29 #define IDR_P1_SHIFT 1 @@ -220,17 +220,17 @@ typedef struct IRQSource { } IRQSource; #define IVPR_MASK_SHIFT 31 -#define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT) +#define IVPR_MASK_MASK (1U << IVPR_MASK_SHIFT) #define IVPR_ACTIVITY_SHIFT 30 -#define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT) +#define IVPR_ACTIVITY_MASK (1U << IVPR_ACTIVITY_SHIFT) #define IVPR_MODE_SHIFT 29 -#define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT) +#define IVPR_MODE_MASK (1U << IVPR_MODE_SHIFT) #define IVPR_POLARITY_SHIFT 23 -#define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT) +#define IVPR_POLARITY_MASK (1U << IVPR_POLARITY_SHIFT) #define IVPR_SENSE_SHIFT 22 -#define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT) +#define IVPR_SENSE_MASK (1U << IVPR_SENSE_SHIFT) -#define IVPR_PRIORITY_MASK (0xF << 16) +#define IVPR_PRIORITY_MASK (0xFU << 16) #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16)) #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask) From a1f7f97b950a46393b0e55a9a0082e70f540cbbd Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:37 +0000 Subject: [PATCH 17/23] hw/ppc: Avoid shifting left into sign bit Add U suffix to various places where we were doing "1 << 31", which is undefined behaviour, and also to other constant definitions in the same groups, for consistency. Signed-off-by: Peter Maydell Signed-off-by: Michael Tokarev --- hw/ppc/ppc.c | 2 +- hw/ppc/ppc440_bamboo.c | 4 ++-- hw/ppc/ppc4xx_devs.c | 2 +- hw/ppc/ppc_booke.c | 24 ++++++++++++------------ hw/ppc/virtex_ml507.c | 4 ++-- 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 0e82719b69..9c2a13280b 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -1002,7 +1002,7 @@ static void cpu_4xx_wdt_cb (void *opaque) case 0x1: timer_mod(ppc40x_timer->wdt_timer, next); ppc40x_timer->wdt_next = next; - env->spr[SPR_40x_TSR] |= 1 << 31; + env->spr[SPR_40x_TSR] |= 1U << 31; break; case 0x2: timer_mod(ppc40x_timer->wdt_timer, next); diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index ec15bab0b5..2ddc2ed4b9 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -128,7 +128,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, tlb->attr = 0; tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1 << 31; /* up to 0x80000000 */ + tlb->size = 1U << 31; /* up to 0x80000000 */ tlb->EPN = va & TARGET_PAGE_MASK; tlb->RPN = pa & TARGET_PAGE_MASK; tlb->PID = 0; @@ -136,7 +136,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, tlb = &env->tlb.tlbe[1]; tlb->attr = 0; tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1 << 31; /* up to 0xffffffff */ + tlb->size = 1U << 31; /* up to 0xffffffff */ tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; tlb->PID = 0; diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 9160ee7769..8a43111a51 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -161,7 +161,7 @@ static void ppcuic_set_irq (void *opaque, int irq_num, int level) uint32_t mask, sr; uic = opaque; - mask = 1 << (31-irq_num); + mask = 1U << (31-irq_num); LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", __func__, irq_num, level, diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index d8399602d6..8b94da6b08 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -34,15 +34,15 @@ /* Timer Control Register */ #define TCR_WP_SHIFT 30 /* Watchdog Timer Period */ -#define TCR_WP_MASK (0x3 << TCR_WP_SHIFT) +#define TCR_WP_MASK (0x3U << TCR_WP_SHIFT) #define TCR_WRC_SHIFT 28 /* Watchdog Timer Reset Control */ -#define TCR_WRC_MASK (0x3 << TCR_WRC_SHIFT) -#define TCR_WIE (1 << 27) /* Watchdog Timer Interrupt Enable */ -#define TCR_DIE (1 << 26) /* Decrementer Interrupt Enable */ +#define TCR_WRC_MASK (0x3U << TCR_WRC_SHIFT) +#define TCR_WIE (1U << 27) /* Watchdog Timer Interrupt Enable */ +#define TCR_DIE (1U << 26) /* Decrementer Interrupt Enable */ #define TCR_FP_SHIFT 24 /* Fixed-Interval Timer Period */ -#define TCR_FP_MASK (0x3 << TCR_FP_SHIFT) -#define TCR_FIE (1 << 23) /* Fixed-Interval Timer Interrupt Enable */ -#define TCR_ARE (1 << 22) /* Auto-Reload Enable */ +#define TCR_FP_MASK (0x3U << TCR_FP_SHIFT) +#define TCR_FIE (1U << 23) /* Fixed-Interval Timer Interrupt Enable */ +#define TCR_ARE (1U << 22) /* Auto-Reload Enable */ /* Timer Control Register (e500 specific fields) */ @@ -53,12 +53,12 @@ /* Timer Status Register */ -#define TSR_FIS (1 << 26) /* Fixed-Interval Timer Interrupt Status */ -#define TSR_DIS (1 << 27) /* Decrementer Interrupt Status */ +#define TSR_FIS (1U << 26) /* Fixed-Interval Timer Interrupt Status */ +#define TSR_DIS (1U << 27) /* Decrementer Interrupt Status */ #define TSR_WRS_SHIFT 28 /* Watchdog Timer Reset Status */ -#define TSR_WRS_MASK (0x3 << TSR_WRS_SHIFT) -#define TSR_WIS (1 << 30) /* Watchdog Timer Interrupt Status */ -#define TSR_ENW (1 << 31) /* Enable Next Watchdog Timer */ +#define TSR_WRS_MASK (0x3U << TSR_WRS_SHIFT) +#define TSR_WIS (1U << 30) /* Watchdog Timer Interrupt Status */ +#define TSR_ENW (1U << 31) /* Enable Next Watchdog Timer */ typedef struct booke_timer_t booke_timer_t; struct booke_timer_t { diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index ce8ea91e8b..3e3569d4b8 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -71,7 +71,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, tlb->attr = 0; tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1 << 31; /* up to 0x80000000 */ + tlb->size = 1U << 31; /* up to 0x80000000 */ tlb->EPN = va & TARGET_PAGE_MASK; tlb->RPN = pa & TARGET_PAGE_MASK; tlb->PID = 0; @@ -79,7 +79,7 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, tlb = &env->tlb.tlbe[1]; tlb->attr = 0; tlb->prot = PAGE_VALID | ((PAGE_READ | PAGE_WRITE | PAGE_EXEC) << 4); - tlb->size = 1 << 31; /* up to 0xffffffff */ + tlb->size = 1U << 31; /* up to 0xffffffff */ tlb->EPN = 0x80000000 & TARGET_PAGE_MASK; tlb->RPN = 0x80000000 & TARGET_PAGE_MASK; tlb->PID = 0; From a879125b47c3ae554c01824f996a64a45a86556e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:38 +0000 Subject: [PATCH 18/23] tests/libqos/pci-pc: Avoid shifting left into sign bit Add U suffix when doing "1 << 31" to avoid undefined behaviour. Signed-off-by: Peter Maydell Signed-off-by: Michael Tokarev --- tests/libqos/pci-pc.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/tests/libqos/pci-pc.c b/tests/libqos/pci-pc.c index 3bde8ab190..bf741a43ac 100644 --- a/tests/libqos/pci-pc.c +++ b/tests/libqos/pci-pc.c @@ -110,37 +110,37 @@ static void qpci_pc_io_writel(QPCIBus *bus, void *addr, uint32_t value) static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); return inb(0xcfc); } static uint16_t qpci_pc_config_readw(QPCIBus *bus, int devfn, uint8_t offset) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); return inw(0xcfc); } static uint32_t qpci_pc_config_readl(QPCIBus *bus, int devfn, uint8_t offset) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); return inl(0xcfc); } static void qpci_pc_config_writeb(QPCIBus *bus, int devfn, uint8_t offset, uint8_t value) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); outb(0xcfc, value); } static void qpci_pc_config_writew(QPCIBus *bus, int devfn, uint8_t offset, uint16_t value) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); outw(0xcfc, value); } static void qpci_pc_config_writel(QPCIBus *bus, int devfn, uint8_t offset, uint32_t value) { - outl(0xcf8, (1 << 31) | (devfn << 8) | offset); + outl(0xcf8, (1U << 31) | (devfn << 8) | offset); outl(0xcfc, value); } From 7d45e784015971e70239e33256fd606638107a3e Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:39 +0000 Subject: [PATCH 19/23] hw/intc/slavio_intctl: Avoid shifting left into sign bit Add 'U' suffix to avoid undefined behaviour. Signed-off-by: Peter Maydell Signed-off-by: Michael Tokarev --- hw/intc/slavio_intctl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/slavio_intctl.c b/hw/intc/slavio_intctl.c index 41a1672800..b10fb66b8d 100644 --- a/hw/intc/slavio_intctl.c +++ b/hw/intc/slavio_intctl.c @@ -272,7 +272,7 @@ static void slavio_check_interrupts(SLAVIO_INTCTLState *s, int set_irqs) CPU_IRQ_TIMER_IN; if (i == s->target_cpu) { for (j = 0; j < 32; j++) { - if ((s->intregm_pending & (1 << j)) && intbit_to_level[j]) { + if ((s->intregm_pending & (1U << j)) && intbit_to_level[j]) { s->slaves[i].intreg_pending |= 1 << intbit_to_level[j]; } } From 0bc60bd7b34ad6e59b47dbf91179ba9427a85df7 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:40 +0000 Subject: [PATCH 20/23] hw/intc/xilinx_intc: Avoid shifting left into sign bit Avoid undefined behaviour shifting left into the sign bit. Signed-off-by: Peter Maydell Signed-off-by: Michael Tokarev --- hw/intc/xilinx_intc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 4a103988f3..1b228ff4e0 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -71,8 +71,9 @@ static void update_irq(struct xlx_pic *p) /* Update the vector register. */ for (i = 0; i < 32; i++) { - if (p->regs[R_IPR] & (1 << i)) + if (p->regs[R_IPR] & (1U << i)) { break; + } } if (i == 32) i = ~0; From af23906d50c7d7c28e7e5ff49f7cbf0fa5c6228a Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 17 Mar 2014 16:00:41 +0000 Subject: [PATCH 21/23] hw/pci-host/apb.c: Avoid shifting left into sign bit Add U suffix to avoid undefined behaviour. Signed-off-by: Peter Maydell Signed-off-by: Michael Tokarev --- hw/pci-host/apb.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/pci-host/apb.c b/hw/pci-host/apb.c index 1b399ddbc3..252caefda7 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/apb.c @@ -58,11 +58,11 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #define PBM_PCI_IMR_MASK 0x7fffffff #define PBM_PCI_IMR_ENABLED 0x80000000 -#define POR (1 << 31) -#define SOFT_POR (1 << 30) -#define SOFT_XIR (1 << 29) -#define BTN_POR (1 << 28) -#define BTN_XIR (1 << 27) +#define POR (1U << 31) +#define SOFT_POR (1U << 30) +#define SOFT_XIR (1U << 29) +#define BTN_POR (1U << 28) +#define BTN_XIR (1U << 27) #define RESET_MASK 0xf8000000 #define RESET_WCMASK 0x98000000 #define RESET_WMASK 0x60000000 From c9f2d70cc88346d50020d01face2135481e5acde Mon Sep 17 00:00:00 2001 From: Prasad Joshi Date: Sun, 23 Mar 2014 14:58:41 +0530 Subject: [PATCH 22/23] hw/timer/grlib_gptimer: remove unnecessary assignment Signed-off-by: Prasad Joshi Signed-off-by: Michael Tokarev --- hw/timer/grlib_gptimer.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c index 7672d3ad8a..d655bb2a27 100644 --- a/hw/timer/grlib_gptimer.c +++ b/hw/timer/grlib_gptimer.c @@ -328,7 +328,6 @@ static void grlib_gptimer_reset(DeviceState *d) unit->scaler = 0; unit->reload = 0; - unit->config = 0; unit->config = unit->nr_timers; unit->config |= unit->irq_line << 3; From 3768d505adcd6c3fe819432d7dabd312995fa678 Mon Sep 17 00:00:00 2001 From: Prasad Joshi Date: Sun, 23 Mar 2014 14:58:42 +0530 Subject: [PATCH 23/23] linux-user: remove duplicate statement Signed-off-by: Prasad Joshi Acked-by: Riku Voipio Signed-off-by: Michael Tokarev --- linux-user/signal.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/linux-user/signal.c b/linux-user/signal.c index e5fb9332e3..7d6246f448 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -4043,8 +4043,6 @@ static void setup_rt_frame(int sig, struct target_sigaction *ka, struct target_rt_sigframe *frame; abi_ulong info_addr, uc_addr; - frame_addr = get_sigframe(ka, env, sizeof *frame); - frame_addr = get_sigframe(ka, env, sizeof(*frame)); if (!lock_user_struct(VERIFY_WRITE, frame, frame_addr, 0)) { goto give_sigsegv;