diff --git a/hw/xbox/nv2a/Makefile.objs b/hw/xbox/nv2a/Makefile.objs
index f49bddfab5..dd5a230aa1 100644
--- a/hw/xbox/nv2a/Makefile.objs
+++ b/hw/xbox/nv2a/Makefile.objs
@@ -3,27 +3,21 @@ obj-y += swizzle.o
 
 obj-y += nv2a.o
 obj-y += nv2a_debug.o
-obj-y += nv2a_shaders.o
-
-###
-# These are just #included into nv2a.c for build time savings
-#
-# obj-y += nv2a_pbus.o
-# obj-y += nv2a_pcrtc.o
-# obj-y += nv2a_pfb.o
-# obj-y += nv2a_pfifo.o
-# obj-y += nv2a_pgraph.o
-# obj-y += nv2a_pmc.o
-# obj-y += nv2a_pramdac.o
-# obj-y += nv2a_prmcio.o
-# obj-y += nv2a_prmvio.o
-# obj-y += nv2a_ptimer.o
-# obj-y += nv2a_pvideo.o
-# obj-y += nv2a_user.o
-# obj-y += nv2a_stubs.o
-###
-
+obj-y += nv2a_pbus.o
+obj-y += nv2a_pcrtc.o
+obj-y += nv2a_pfb.o
+obj-y += nv2a_pfifo.o
+obj-y += nv2a_pgraph.o
+obj-y += nv2a_pmc.o
+obj-y += nv2a_pramdac.o
+obj-y += nv2a_prmcio.o
+obj-y += nv2a_prmvio.o
 obj-y += nv2a_psh.o
+obj-y += nv2a_ptimer.o
+obj-y += nv2a_pvideo.o
+obj-y += nv2a_shaders.o
+obj-y += nv2a_stubs.o
+obj-y += nv2a_user.o
 obj-y += nv2a_vsh.o
 
 obj-y += gl/
diff --git a/hw/xbox/nv2a/nv2a.c b/hw/xbox/nv2a/nv2a.c
index 785e9c2d04..b69f154ae7 100644
--- a/hw/xbox/nv2a/nv2a.c
+++ b/hw/xbox/nv2a/nv2a.c
@@ -19,58 +19,9 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
-#include <assert.h>
-
-#include "qemu/osdep.h"
-#include "qemu/thread.h"
-#include "qemu/main-loop.h"
-#include "qapi/error.h"
-#include "qemu/error-report.h"
-#include "migration/vmstate.h"
-#include "sysemu/runstate.h"
-
-#include "hw/hw.h"
-#include "hw/display/vga.h"
-#include "hw/display/vga_int.h"
-#include "hw/display/vga_regs.h"
-#include "hw/pci/pci.h"
-#include "cpu.h"
-
-#include "swizzle.h"
-
 #include "hw/xbox/nv2a/nv2a_int.h"
 
-#include "hw/xbox/nv2a/nv2a.h"
-
-
-#define DEFINE_PROTO(n)                                              \
-    uint64_t n##_read(void *opaque, hwaddr addr, unsigned int size); \
-    void n##_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size);
-
-DEFINE_PROTO(pmc)
-DEFINE_PROTO(pbus)
-DEFINE_PROTO(pfifo)
-DEFINE_PROTO(prma)
-DEFINE_PROTO(pvideo)
-DEFINE_PROTO(ptimer)
-DEFINE_PROTO(pcounter)
-DEFINE_PROTO(pvpe)
-DEFINE_PROTO(ptv)
-DEFINE_PROTO(prmfb)
-DEFINE_PROTO(prmvio)
-DEFINE_PROTO(pfb)
-DEFINE_PROTO(pstraps)
-DEFINE_PROTO(pgraph)
-DEFINE_PROTO(pcrtc)
-DEFINE_PROTO(prmcio)
-DEFINE_PROTO(pramdac)
-DEFINE_PROTO(prmdio)
-// DEFINE_PROTO(pramin)
-DEFINE_PROTO(user)
-
-#undef DEFINE_PROTO
-
-static void update_irq(NV2AState *d)
+void nv2a_update_irq(NV2AState *d)
 {
     /* PFIFO */
     if (d->pfifo.pending_interrupts & d->pfifo.enabled_interrupts) {
@@ -101,7 +52,7 @@ static void update_irq(NV2AState *d)
     }
 }
 
-static DMAObject nv_dma_load(NV2AState *d, hwaddr dma_obj_address)
+DMAObject nv_dma_load(NV2AState *d, hwaddr dma_obj_address)
 {
     assert(dma_obj_address < memory_region_size(&d->ramin));
 
@@ -118,7 +69,7 @@ static DMAObject nv_dma_load(NV2AState *d, hwaddr dma_obj_address)
     };
 }
 
-static void *nv_dma_map(NV2AState *d, hwaddr dma_obj_address, hwaddr *len)
+void *nv_dma_map(NV2AState *d, hwaddr dma_obj_address, hwaddr *len)
 {
     DMAObject dma = nv_dma_load(d, dma_obj_address);
 
@@ -135,29 +86,14 @@ static void *nv_dma_map(NV2AState *d, hwaddr dma_obj_address, hwaddr *len)
     return d->vram_ptr + dma.address;
 }
 
-#include "nv2a_pbus.c"
-#include "nv2a_pcrtc.c"
-#include "nv2a_pfb.c"
-#include "nv2a_pgraph.c"
-#include "nv2a_pfifo.c"
-#include "nv2a_pmc.c"
-#include "nv2a_pramdac.c"
-#include "nv2a_prmcio.c"
-#include "nv2a_prmvio.c"
-#include "nv2a_ptimer.c"
-#include "nv2a_pvideo.c"
-#include "nv2a_stubs.c"
-#include "nv2a_user.c"
-
-#define ENTRY(NAME, OFFSET, SIZE, RDFUNC, WRFUNC)      \
+const struct NV2ABlockInfo blocktable[] = {
+    #define ENTRY(NAME, OFFSET, SIZE, RDFUNC, WRFUNC)  \
     [NV_##NAME] = {                                    \
         .name   = #NAME,                               \
         .offset = OFFSET,                              \
         .size   = SIZE,                                \
         .ops    = { .read = RDFUNC, .write = WRFUNC }, \
     }
-
-const struct NV2ABlockInfo blocktable[] = {
     ENTRY(PMC,      0x000000, 0x001000, pmc_read,      pmc_write),
     ENTRY(PBUS,     0x001000, 0x001000, pbus_read,     pbus_write),
     ENTRY(PFIFO,    0x002000, 0x002000, pfifo_read,    pfifo_write),
@@ -179,12 +115,12 @@ const struct NV2ABlockInfo blocktable[] = {
     // ENTRY(PRAMIN,   0x700000, 0x100000, pramin_read,   pramin_write),
     ENTRY(USER,     0x800000, 0x800000, user_read,     user_write),
 };
-
 #undef ENTRY
 
-static const char* nv2a_reg_names[] = {};
+#ifdef NV2A_DEBUG
+static const char *nv2a_reg_names[] = {};
 
-static void reg_log_read(int block, hwaddr addr, uint64_t val)
+void nv2a_reg_log_read(int block, hwaddr addr, uint64_t val)
 {
     if (blocktable[block].name) {
         hwaddr naddr = blocktable[block].offset + addr;
@@ -201,7 +137,7 @@ static void reg_log_read(int block, hwaddr addr, uint64_t val)
     }
 }
 
-static void reg_log_write(int block, hwaddr addr, uint64_t val)
+void nv2a_reg_log_write(int block, hwaddr addr, uint64_t val)
 {
     if (blocktable[block].name) {
         hwaddr naddr = blocktable[block].offset + addr;
@@ -217,6 +153,7 @@ static void reg_log_write(int block, hwaddr addr, uint64_t val)
                      block, addr, val);
     }
 }
+#endif
 
 #if 0
 /* FIXME: Probably totally wrong */
@@ -382,7 +319,7 @@ static void nv2a_vga_gfx_update(void *opaque)
 
     NV2AState *d = container_of(vga, NV2AState, vga);
     d->pcrtc.pending_interrupts |= NV_PCRTC_INTR_0_VBLANK;
-    update_irq(d);
+    nv2a_update_irq(d);
 }
 
 static void nv2a_init_memory(NV2AState *d, MemoryRegion *ram)
diff --git a/hw/xbox/nv2a/nv2a_int.h b/hw/xbox/nv2a/nv2a_int.h
index 9a5bb9555f..f7c0998276 100644
--- a/hw/xbox/nv2a/nv2a_int.h
+++ b/hw/xbox/nv2a/nv2a_int.h
@@ -22,21 +22,32 @@
 #ifndef HW_NV2A_INT_H
 #define HW_NV2A_INT_H
 
+#include <assert.h>
+
 #include "qemu/osdep.h"
+#include "qemu/thread.h"
+#include "qemu/main-loop.h"
+#include "qapi/error.h"
+#include "qemu/error-report.h"
+#include "migration/vmstate.h"
+#include "sysemu/runstate.h"
 
 #include "hw/hw.h"
-// #include "hw/i386/pc.h"
-// #include "qapi/qmp/qstring.h"
-// #include "qemu/thread.h"
-// #include "cpu.h"
+#include "hw/display/vga.h"
+#include "hw/display/vga_int.h"
+#include "hw/display/vga_regs.h"
+#include "hw/pci/pci.h"
+#include "cpu.h"
 
+#include "swizzle.h"
 #include "lru.h"
 #include "gl/gloffscreen.h"
 
-#include "hw/xbox/nv2a/nv2a_debug.h"
-#include "hw/xbox/nv2a/nv2a_shaders.h"
-#include "hw/xbox/nv2a/nv2a_debug.h"
-#include "hw/xbox/nv2a/nv2a_regs.h"
+#include "nv2a.h"
+#include "nv2a_debug.h"
+#include "nv2a_shaders.h"
+#include "nv2a_debug.h"
+#include "nv2a_regs.h"
 
 #define USE_TEXTURE_CACHE 1
 
@@ -354,9 +365,52 @@ typedef struct NV2ABlockInfo {
     MemoryRegionOps ops;
 } NV2ABlockInfo;
 
-static void reg_log_read(int block, hwaddr addr, uint64_t val);
-static void reg_log_write(int block, hwaddr addr, uint64_t val);
+void nv2a_update_irq(NV2AState *d);
 
+#ifdef NV2A_DEBUG
+void nv2a_reg_log_read(int block, hwaddr addr, uint64_t val);
+void nv2a_reg_log_write(int block, hwaddr addr, uint64_t val);
+#else
+#define nv2a_reg_log_read(block, addr, val) do {} while (0)
+#define nv2a_reg_log_write(block, addr, val) do {} while (0)
+#endif
+
+#define DEFINE_PROTO(n) \
+    uint64_t n##_read(void *opaque, hwaddr addr, unsigned int size); \
+    void n##_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size);
+
+DEFINE_PROTO(pmc)
+DEFINE_PROTO(pbus)
+DEFINE_PROTO(pfifo)
+DEFINE_PROTO(prma)
+DEFINE_PROTO(pvideo)
+DEFINE_PROTO(ptimer)
+DEFINE_PROTO(pcounter)
+DEFINE_PROTO(pvpe)
+DEFINE_PROTO(ptv)
+DEFINE_PROTO(prmfb)
+DEFINE_PROTO(prmvio)
+DEFINE_PROTO(pfb)
+DEFINE_PROTO(pstraps)
+DEFINE_PROTO(pgraph)
+DEFINE_PROTO(pcrtc)
+DEFINE_PROTO(prmcio)
+DEFINE_PROTO(pramdac)
+DEFINE_PROTO(prmdio)
+// DEFINE_PROTO(pramin)
+DEFINE_PROTO(user)
+#undef DEFINE_PROTO
+
+DMAObject nv_dma_load(NV2AState *d, hwaddr dma_obj_address);
+void *nv_dma_map(NV2AState *d, hwaddr dma_obj_address, hwaddr *len);
+
+void pgraph_init(NV2AState *d);
+void pgraph_destroy(PGRAPHState *pg);
+void pgraph_context_switch(NV2AState *d, unsigned int channel_id);
+void pgraph_method(NV2AState *d, unsigned int subchannel,
+                   unsigned int method, uint32_t parameter);
+
+void *pfifo_thread(void *arg);
 void pfifo_kick(NV2AState *d);
 
 #endif
diff --git a/hw/xbox/nv2a/nv2a_pbus.c b/hw/xbox/nv2a/nv2a_pbus.c
index 764d0409d8..dee4dcc582 100644
--- a/hw/xbox/nv2a/nv2a_pbus.c
+++ b/hw/xbox/nv2a/nv2a_pbus.c
@@ -19,6 +19,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 /* PBUS - bus control */
 uint64_t pbus_read(void *opaque, hwaddr addr, unsigned int size)
 {
@@ -40,7 +42,7 @@ uint64_t pbus_read(void *opaque, hwaddr addr, unsigned int size)
         break;
     }
 
-    reg_log_read(NV_PBUS, addr, r);
+    nv2a_reg_log_read(NV_PBUS, addr, r);
     return r;
 }
 
@@ -49,7 +51,7 @@ void pbus_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
     NV2AState *s = opaque;
     PCIDevice *d = PCI_DEVICE(s);
 
-    reg_log_write(NV_PBUS, addr, val);
+    nv2a_reg_log_write(NV_PBUS, addr, val);
 
     switch (addr) {
     case NV_PBUS_PCI_NV_1:
diff --git a/hw/xbox/nv2a/nv2a_pcrtc.c b/hw/xbox/nv2a/nv2a_pcrtc.c
index 8707bb1cd1..0d5a34e777 100644
--- a/hw/xbox/nv2a/nv2a_pcrtc.c
+++ b/hw/xbox/nv2a/nv2a_pcrtc.c
@@ -19,6 +19,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 uint64_t pcrtc_read(void *opaque, hwaddr addr, unsigned int size)
 {
     NV2AState *d = (NV2AState *)opaque;
@@ -38,7 +40,7 @@ uint64_t pcrtc_read(void *opaque, hwaddr addr, unsigned int size)
             break;
     }
 
-    reg_log_read(NV_PCRTC, addr, r);
+    nv2a_reg_log_read(NV_PCRTC, addr, r);
     return r;
 }
 
@@ -46,16 +48,16 @@ void pcrtc_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
 {
     NV2AState *d = (NV2AState *)opaque;
 
-    reg_log_write(NV_PCRTC, addr, val);
+    nv2a_reg_log_write(NV_PCRTC, addr, val);
 
     switch (addr) {
     case NV_PCRTC_INTR_0:
         d->pcrtc.pending_interrupts &= ~val;
-        update_irq(d);
+        nv2a_update_irq(d);
         break;
     case NV_PCRTC_INTR_EN_0:
         d->pcrtc.enabled_interrupts = val;
-        update_irq(d);
+        nv2a_update_irq(d);
         break;
     case NV_PCRTC_START:
         val &= 0x07FFFFFF;
diff --git a/hw/xbox/nv2a/nv2a_pfb.c b/hw/xbox/nv2a/nv2a_pfb.c
index 45efcdaaf6..511d24d919 100644
--- a/hw/xbox/nv2a/nv2a_pfb.c
+++ b/hw/xbox/nv2a/nv2a_pfb.c
@@ -19,6 +19,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 uint64_t pfb_read(void *opaque, hwaddr addr, unsigned int size)
 {
     NV2AState *d = (NV2AState *)opaque;
@@ -40,7 +42,7 @@ uint64_t pfb_read(void *opaque, hwaddr addr, unsigned int size)
         break;
     }
 
-    reg_log_read(NV_PFB, addr, r);
+    nv2a_reg_log_read(NV_PFB, addr, r);
     return r;
 }
 
@@ -48,7 +50,7 @@ void pfb_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
 {
     NV2AState *d = (NV2AState *)opaque;
 
-    reg_log_write(NV_PFB, addr, val);
+    nv2a_reg_log_write(NV_PFB, addr, val);
 
     switch (addr) {
     default:
diff --git a/hw/xbox/nv2a/nv2a_pfifo.c b/hw/xbox/nv2a/nv2a_pfifo.c
index 849b5e9649..f148464a1f 100644
--- a/hw/xbox/nv2a/nv2a_pfifo.c
+++ b/hw/xbox/nv2a/nv2a_pfifo.c
@@ -19,6 +19,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 typedef struct RAMHTEntry {
     uint32_t handle;
     hwaddr instance;
@@ -56,7 +58,7 @@ uint64_t pfifo_read(void *opaque, hwaddr addr, unsigned int size)
 
     qemu_mutex_unlock(&d->pfifo.lock);
 
-    reg_log_read(NV_PFIFO, addr, r);
+    nv2a_reg_log_read(NV_PFIFO, addr, r);
     return r;
 }
 
@@ -64,18 +66,18 @@ void pfifo_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
 {
     NV2AState *d = (NV2AState *)opaque;
 
-    reg_log_write(NV_PFIFO, addr, val);
+    nv2a_reg_log_write(NV_PFIFO, addr, val);
 
     qemu_mutex_lock(&d->pfifo.lock);
 
     switch (addr) {
     case NV_PFIFO_INTR_0:
         d->pfifo.pending_interrupts &= ~val;
-        update_irq(d);
+        nv2a_update_irq(d);
         break;
     case NV_PFIFO_INTR_EN_0:
         d->pfifo.enabled_interrupts = val;
-        update_irq(d);
+        nv2a_update_irq(d);
         break;
     default:
         d->pfifo.regs[addr] = val;
@@ -93,6 +95,31 @@ void pfifo_kick(NV2AState *d)
     qemu_cond_broadcast(&d->pfifo.fifo_cond);
 }
 
+static int pgraph_can_fifo_access(NV2AState *d) {
+    return !!(d->pgraph.regs[NV_PGRAPH_FIFO] & NV_PGRAPH_FIFO_ACCESS);
+}
+
+/* If NV097_FLIP_STALL was executed, check if the flip has completed.
+ * This will usually happen in the VSYNC interrupt handler.
+ */
+static int pgraph_is_flip_stall_complete(NV2AState *d)
+{
+    PGRAPHState *pg = &d->pgraph;
+
+    NV2A_DPRINTF("flip stall read: %d, write: %d, modulo: %d\n",
+        GET_MASK(pg->regs[NV_PGRAPH_SURFACE], NV_PGRAPH_SURFACE_READ_3D),
+        GET_MASK(pg->regs[NV_PGRAPH_SURFACE], NV_PGRAPH_SURFACE_WRITE_3D),
+        GET_MASK(pg->regs[NV_PGRAPH_SURFACE], NV_PGRAPH_SURFACE_MODULO_3D));
+
+    uint32_t s = pg->regs[NV_PGRAPH_SURFACE];
+    if (GET_MASK(s, NV_PGRAPH_SURFACE_READ_3D)
+        != GET_MASK(s, NV_PGRAPH_SURFACE_WRITE_3D)) {
+        return 1;
+    }
+
+    return 0;
+}
+
 static bool pfifo_stall_for_flip(NV2AState *d)
 {
     bool should_stall = false;
@@ -470,11 +497,11 @@ static void pfifo_run_pusher(NV2AState *d)
         SET_MASK(*dma_push, NV_PFIFO_CACHE1_DMA_PUSH_STATUS, 1); /* suspended */
 
         // d->pfifo.pending_interrupts |= NV_PFIFO_INTR_0_DMA_PUSHER;
-        // update_irq(d);
+        // nv2a_update_irq(d);
     }
 }
 
-static void *pfifo_thread(void *arg)
+void *pfifo_thread(void *arg)
 {
     NV2AState *d = (NV2AState *)arg;
     glo_set_current(d->pgraph.gl_context);
diff --git a/hw/xbox/nv2a/nv2a_pgraph.c b/hw/xbox/nv2a/nv2a_pgraph.c
index 537c7b28d4..e5c3ef5f2d 100644
--- a/hw/xbox/nv2a/nv2a_pgraph.c
+++ b/hw/xbox/nv2a/nv2a_pgraph.c
@@ -19,6 +19,7 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
 #include "xxhash.h"
 
 static const GLenum pgraph_texture_min_filter_map[] = {
@@ -376,7 +377,7 @@ uint64_t pgraph_read(void *opaque, hwaddr addr, unsigned int size)
 
     qemu_mutex_unlock(&pg->lock);
 
-    reg_log_read(NV_PGRAPH, addr, r);
+    nv2a_reg_log_read(NV_PGRAPH, addr, r);
     return r;
 }
 
@@ -385,7 +386,7 @@ void pgraph_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
     NV2AState *d = (NV2AState *)opaque;
     PGRAPHState *pg = &d->pgraph;
 
-    reg_log_write(NV_PGRAPH, addr, val);
+    nv2a_reg_log_write(NV_PGRAPH, addr, val);
 
     qemu_mutex_lock(&d->pfifo.lock); // FIXME: Factor out fifo lock here
     qemu_mutex_lock(&pg->lock);
@@ -491,28 +492,7 @@ static void pgraph_flush(NV2AState *d)
     // FIXME: Flush more?
 }
 
-/* If NV097_FLIP_STALL was executed, check if the flip has completed.
- * This will usually happen in the VSYNC interrupt handler.
- */
-static int pgraph_is_flip_stall_complete(NV2AState *d)
-{
-    PGRAPHState *pg = &d->pgraph;
- 
-    NV2A_DPRINTF("flip stall read: %d, write: %d, modulo: %d\n",
-        GET_MASK(pg->regs[NV_PGRAPH_SURFACE], NV_PGRAPH_SURFACE_READ_3D),
-        GET_MASK(pg->regs[NV_PGRAPH_SURFACE], NV_PGRAPH_SURFACE_WRITE_3D),
-        GET_MASK(pg->regs[NV_PGRAPH_SURFACE], NV_PGRAPH_SURFACE_MODULO_3D));
-
-    uint32_t s = pg->regs[NV_PGRAPH_SURFACE];
-    if (GET_MASK(s, NV_PGRAPH_SURFACE_READ_3D)
-        != GET_MASK(s, NV_PGRAPH_SURFACE_WRITE_3D)) {
-        return 1;
-    }
-
-    return 0;
-}
-
-static void pgraph_method(NV2AState *d,
+void pgraph_method(NV2AState *d,
                    unsigned int subchannel,
                    unsigned int method,
                    uint32_t parameter)
@@ -724,7 +704,7 @@ static void pgraph_method(NV2AState *d,
 
             qemu_mutex_unlock(&pg->lock);
             qemu_mutex_lock_iothread();
-            update_irq(d);
+            nv2a_update_irq(d);
             qemu_mutex_unlock_iothread();
             qemu_mutex_lock(&pg->lock);
         }
@@ -2624,7 +2604,7 @@ static void pgraph_method(NV2AState *d,
     }
 }
 
-static void pgraph_context_switch(NV2AState *d, unsigned int channel_id)
+void pgraph_context_switch(NV2AState *d, unsigned int channel_id)
 {
     bool channel_valid =
         d->pgraph.regs[NV_PGRAPH_CTX_CONTROL] & NV_PGRAPH_CTX_CONTROL_CHID;
@@ -2645,16 +2625,12 @@ static void pgraph_context_switch(NV2AState *d, unsigned int channel_id)
         qemu_mutex_unlock(&d->pgraph.lock);
         qemu_mutex_lock_iothread();
         d->pgraph.pending_interrupts |= NV_PGRAPH_INTR_CONTEXT_SWITCH;
-        update_irq(d);
+        nv2a_update_irq(d);
         qemu_mutex_unlock_iothread();
         qemu_mutex_lock(&d->pgraph.lock);
     }
 }
 
-static int pgraph_can_fifo_access(NV2AState *d) {
-    return !!(d->pgraph.regs[NV_PGRAPH_FIFO] & NV_PGRAPH_FIFO_ACCESS);
-}
-
 // static const char* nv2a_method_names[] = {};
 
 static void pgraph_method_log(unsigned int subchannel,
@@ -2738,7 +2714,7 @@ static void pgraph_finish_inline_buffer_vertex(PGRAPHState *pg)
     pg->inline_buffer_length++;
 }
 
-static void pgraph_init(NV2AState *d)
+void pgraph_init(NV2AState *d)
 {
     int i;
 
@@ -2818,7 +2794,7 @@ static void pgraph_init(NV2AState *d)
     glo_set_current(NULL);
 }
 
-static void pgraph_destroy(PGRAPHState *pg)
+void pgraph_destroy(PGRAPHState *pg)
 {
     qemu_mutex_destroy(&pg->lock);
 
diff --git a/hw/xbox/nv2a/nv2a_pmc.c b/hw/xbox/nv2a/nv2a_pmc.c
index 5d8ade57ce..b87ef0a9ff 100644
--- a/hw/xbox/nv2a/nv2a_pmc.c
+++ b/hw/xbox/nv2a/nv2a_pmc.c
@@ -19,6 +19,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 /* PMC - card master control */
 uint64_t pmc_read(void *opaque, hwaddr addr, unsigned int size)
 {
@@ -44,7 +46,7 @@ uint64_t pmc_read(void *opaque, hwaddr addr, unsigned int size)
         break;
     }
 
-    reg_log_read(NV_PMC, addr, r);
+    nv2a_reg_log_read(NV_PMC, addr, r);
     return r;
 }
 
@@ -52,17 +54,17 @@ void pmc_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
 {
     NV2AState *d = (NV2AState *)opaque;
 
-    reg_log_write(NV_PMC, addr, val);
+    nv2a_reg_log_write(NV_PMC, addr, val);
 
     switch (addr) {
     case NV_PMC_INTR_0:
         /* the bits of the interrupts to clear are wrtten */
         d->pmc.pending_interrupts &= ~val;
-        update_irq(d);
+        nv2a_update_irq(d);
         break;
     case NV_PMC_INTR_EN_0:
         d->pmc.enabled_interrupts = val;
-        update_irq(d);
+        nv2a_update_irq(d);
         break;
     default:
         break;
diff --git a/hw/xbox/nv2a/nv2a_pramdac.c b/hw/xbox/nv2a/nv2a_pramdac.c
index c8e2cd28a7..69e7c3597d 100644
--- a/hw/xbox/nv2a/nv2a_pramdac.c
+++ b/hw/xbox/nv2a/nv2a_pramdac.c
@@ -19,6 +19,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 uint64_t pramdac_read(void *opaque, hwaddr addr, unsigned int size)
 {
     NV2AState *d = (NV2AState *)opaque;
@@ -81,7 +83,7 @@ void pramdac_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
     NV2AState *d = (NV2AState *)opaque;
     uint32_t m, n, p;
 
-    reg_log_write(NV_PRAMDAC, addr, val);
+    nv2a_reg_log_write(NV_PRAMDAC, addr, val);
 
     switch (addr) {
     case NV_PRAMDAC_NVPLL_COEFF:
diff --git a/hw/xbox/nv2a/nv2a_prmcio.c b/hw/xbox/nv2a/nv2a_prmcio.c
index e8c68d05f5..f672ee67cd 100644
--- a/hw/xbox/nv2a/nv2a_prmcio.c
+++ b/hw/xbox/nv2a/nv2a_prmcio.c
@@ -19,13 +19,15 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 /* PRMCIO - aliases VGA CRTC and attribute controller registers */
 uint64_t prmcio_read(void *opaque, hwaddr addr, unsigned int size)
 {
     NV2AState *d = opaque;
     uint64_t r = vga_ioport_read(&d->vga, addr);
 
-    reg_log_read(NV_PRMCIO, addr, r);
+    nv2a_reg_log_read(NV_PRMCIO, addr, r);
     return r;
 }
 
@@ -33,7 +35,7 @@ void prmcio_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
 {
     NV2AState *d = opaque;
 
-    reg_log_write(NV_PRMCIO, addr, val);
+    nv2a_reg_log_write(NV_PRMCIO, addr, val);
 
     switch (addr) {
     case VGA_ATT_W:
diff --git a/hw/xbox/nv2a/nv2a_prmvio.c b/hw/xbox/nv2a/nv2a_prmvio.c
index f1809fbfc5..a014fb8eab 100644
--- a/hw/xbox/nv2a/nv2a_prmvio.c
+++ b/hw/xbox/nv2a/nv2a_prmvio.c
@@ -19,13 +19,15 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 /* PRMVIO - aliases VGA sequencer and graphics controller registers */
 uint64_t prmvio_read(void *opaque, hwaddr addr, unsigned int size)
 {
     NV2AState *d = opaque;
     uint64_t r = vga_ioport_read(&d->vga, addr);
 
-    reg_log_read(NV_PRMVIO, addr, r);
+    nv2a_reg_log_read(NV_PRMVIO, addr, r);
     return r;
 }
 
@@ -33,6 +35,6 @@ void prmvio_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
 {
     NV2AState *d = opaque;
 
-    reg_log_write(NV_PRMVIO, addr, val);
+    nv2a_reg_log_write(NV_PRMVIO, addr, val);
     vga_ioport_write(&d->vga, addr, val);
 }
diff --git a/hw/xbox/nv2a/nv2a_ptimer.c b/hw/xbox/nv2a/nv2a_ptimer.c
index be6b8cee5c..3d16a2a269 100644
--- a/hw/xbox/nv2a/nv2a_ptimer.c
+++ b/hw/xbox/nv2a/nv2a_ptimer.c
@@ -19,6 +19,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 /* PTIMER - time measurement and time-based alarms */
 static uint64_t ptimer_get_clock(NV2AState *d)
 {
@@ -57,7 +59,7 @@ uint64_t ptimer_read(void *opaque, hwaddr addr, unsigned int size)
         break;
     }
 
-    reg_log_read(NV_PTIMER, addr, r);
+    nv2a_reg_log_read(NV_PTIMER, addr, r);
     return r;
 }
 
@@ -65,16 +67,16 @@ void ptimer_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
 {
     NV2AState *d = opaque;
 
-    reg_log_write(NV_PTIMER, addr, val);
+    nv2a_reg_log_write(NV_PTIMER, addr, val);
 
     switch (addr) {
     case NV_PTIMER_INTR_0:
         d->ptimer.pending_interrupts &= ~val;
-        update_irq(d);
+        nv2a_update_irq(d);
         break;
     case NV_PTIMER_INTR_EN_0:
         d->ptimer.enabled_interrupts = val;
-        update_irq(d);
+        nv2a_update_irq(d);
         break;
     case NV_PTIMER_DENOMINATOR:
         d->ptimer.denominator = val;
diff --git a/hw/xbox/nv2a/nv2a_pvideo.c b/hw/xbox/nv2a/nv2a_pvideo.c
index 6f97bf987f..f4a469b608 100644
--- a/hw/xbox/nv2a/nv2a_pvideo.c
+++ b/hw/xbox/nv2a/nv2a_pvideo.c
@@ -19,6 +19,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 static void pvideo_vga_invalidate(NV2AState *d)
 {
     int y1 = GET_MASK(d->pvideo.regs[NV_PVIDEO_POINT_OUT],
@@ -43,7 +45,7 @@ uint64_t pvideo_read(void *opaque, hwaddr addr, unsigned int size)
         break;
     }
 
-    reg_log_read(NV_PVIDEO, addr, r);
+    nv2a_reg_log_read(NV_PVIDEO, addr, r);
     return r;
 }
 
@@ -51,7 +53,7 @@ void pvideo_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
 {
     NV2AState *d = opaque;
 
-    reg_log_write(NV_PVIDEO, addr, val);
+    nv2a_reg_log_write(NV_PVIDEO, addr, val);
 
     switch (addr) {
     case NV_PVIDEO_BUFFER:
diff --git a/hw/xbox/nv2a/nv2a_stubs.c b/hw/xbox/nv2a/nv2a_stubs.c
index 4abdb9408e..6c7313a69d 100644
--- a/hw/xbox/nv2a/nv2a_stubs.c
+++ b/hw/xbox/nv2a/nv2a_stubs.c
@@ -19,12 +19,14 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 #define DEFINE_STUB(name, region_id) \
     uint64_t name ## _read(void *opaque, \
                            hwaddr addr, \
                            unsigned int size) \
     { \
-        reg_log_read(region_id, addr, 0); \
+        nv2a_reg_log_read(region_id, addr, 0); \
         return 0; \
     } \
     void name ## _write(void *opaque, \
@@ -32,7 +34,7 @@
                         uint64_t val, \
                         unsigned int size) \
     { \
-        reg_log_write(region_id, addr, val); \
+        nv2a_reg_log_write(region_id, addr, val); \
     } \
 
 DEFINE_STUB(prma, NV_PRMA)
diff --git a/hw/xbox/nv2a/nv2a_user.c b/hw/xbox/nv2a/nv2a_user.c
index 501f1f8539..2efd719346 100644
--- a/hw/xbox/nv2a/nv2a_user.c
+++ b/hw/xbox/nv2a/nv2a_user.c
@@ -19,6 +19,8 @@
  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  */
 
+#include "nv2a_int.h"
+
 /* USER - PFIFO MMIO and DMA submission area */
 uint64_t user_read(void *opaque, hwaddr addr, unsigned int size)
 {
@@ -64,7 +66,7 @@ uint64_t user_read(void *opaque, hwaddr addr, unsigned int size)
 
     qemu_mutex_unlock(&d->pfifo.lock);
 
-    reg_log_read(NV_USER, addr, r);
+    nv2a_reg_log_read(NV_USER, addr, r);
     return r;
 }
 
@@ -72,7 +74,7 @@ void user_write(void *opaque, hwaddr addr, uint64_t val, unsigned int size)
 {
     NV2AState *d = (NV2AState *)opaque;
 
-    reg_log_write(NV_USER, addr, val);
+    nv2a_reg_log_write(NV_USER, addr, val);
 
     unsigned int channel_id = addr >> 16;
     assert(channel_id < NV2A_NUM_CHANNELS);