mirror of https://github.com/xemu-project/xemu.git
tcg/s390x: Check for load-on-condition facility at startup
The general-instruction-extension facility was introduced in z196, which itself was end-of-life in 2021. In addition, z196 is the minimum CPU supported by our set of supported operating systems: RHEL 7 (z196), SLES 12 (z196) and Ubuntu 16.04 (zEC12). Check for facility number 45, which will be the consilidated check for several facilities. Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -1252,7 +1252,6 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
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TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
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TCGReg dest, TCGReg c1, TCGArg c2, int c2const)
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{
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{
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int cc;
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int cc;
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bool have_loc;
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/* With LOC2, we can always emit the minimum 3 insns. */
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/* With LOC2, we can always emit the minimum 3 insns. */
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if (HAVE_FACILITY(LOAD_ON_COND2)) {
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if (HAVE_FACILITY(LOAD_ON_COND2)) {
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@ -1263,9 +1262,6 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
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return;
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return;
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}
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}
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have_loc = HAVE_FACILITY(LOAD_ON_COND);
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/* For HAVE_LOC, only the paths through GTU/GT/LEU/LE are smaller. */
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restart:
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restart:
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switch (cond) {
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switch (cond) {
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case TCG_COND_NE:
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case TCG_COND_NE:
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@ -1310,60 +1306,36 @@ static void tgen_setcond(TCGContext *s, TCGType type, TCGCond cond,
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case TCG_COND_LT:
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case TCG_COND_LT:
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case TCG_COND_GE:
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case TCG_COND_GE:
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/* Swap operands so that we can use LEU/GTU/GT/LE. */
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/* Swap operands so that we can use LEU/GTU/GT/LE. */
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if (c2const) {
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if (!c2const) {
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if (have_loc) {
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break;
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}
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tcg_out_movi(s, type, TCG_TMP0, c2);
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c2 = c1;
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c2const = 0;
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c1 = TCG_TMP0;
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} else {
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TCGReg t = c1;
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TCGReg t = c1;
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c1 = c2;
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c1 = c2;
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c2 = t;
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c2 = t;
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}
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cond = tcg_swap_cond(cond);
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cond = tcg_swap_cond(cond);
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goto restart;
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goto restart;
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}
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break;
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default:
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default:
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g_assert_not_reached();
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g_assert_not_reached();
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}
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}
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cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
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cc = tgen_cmp(s, type, cond, c1, c2, c2const, false);
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if (have_loc) {
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/* Emit: d = 0, t = 1, d = (cc ? t : d). */
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/* Emit: d = 0, t = 1, d = (cc ? t : d). */
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tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
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tcg_out_movi(s, TCG_TYPE_I64, dest, 0);
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tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
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tcg_out_movi(s, TCG_TYPE_I64, TCG_TMP0, 1);
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tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
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tcg_out_insn(s, RRF, LOCGR, dest, TCG_TMP0, cc);
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} else {
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/* Emit: d = 1; if (cc) goto over; d = 0; over: */
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tcg_out_movi(s, type, dest, 1);
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tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
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tcg_out_movi(s, type, dest, 0);
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}
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}
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}
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static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
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static void tgen_movcond(TCGContext *s, TCGType type, TCGCond c, TCGReg dest,
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TCGReg c1, TCGArg c2, int c2const,
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TCGReg c1, TCGArg c2, int c2const,
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TCGArg v3, int v3const)
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TCGArg v3, int v3const)
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{
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{
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int cc;
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int cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
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if (HAVE_FACILITY(LOAD_ON_COND)) {
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cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
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if (v3const) {
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if (v3const) {
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tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
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tcg_out_insn(s, RIE, LOCGHI, dest, v3, cc);
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} else {
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} else {
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tcg_out_insn(s, RRF, LOCGR, dest, v3, cc);
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tcg_out_insn(s, RRF, LOCGR, dest, v3, cc);
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}
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}
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} else {
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c = tcg_invert_cond(c);
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cc = tgen_cmp(s, type, c, c1, c2, c2const, false);
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/* Emit: if (cc) goto over; dest = r3; over: */
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tcg_out_insn(s, RI, BRC, cc, (4 + 4) >> 1);
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tcg_out_insn(s, RRE, LGR, dest, v3);
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}
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}
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}
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static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
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static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
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@ -1382,14 +1354,8 @@ static void tgen_clz(TCGContext *s, TCGReg dest, TCGReg a1,
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} else {
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} else {
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tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
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tcg_out_mov(s, TCG_TYPE_I64, dest, a2);
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}
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}
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if (HAVE_FACILITY(LOAD_ON_COND)) {
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/* Emit: if (one bit found) dest = r0. */
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/* Emit: if (one bit found) dest = r0. */
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tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
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tcg_out_insn(s, RRF, LOCGR, dest, TCG_REG_R0, 2);
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} else {
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/* Emit: if (no one bit found) goto over; dest = r0; over: */
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tcg_out_insn(s, RI, BRC, 8, (4 + 4) >> 1);
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tcg_out_insn(s, RRE, LGR, dest, TCG_REG_R0);
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}
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}
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}
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}
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}
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@ -3124,6 +3090,7 @@ static void query_s390_facilities(void)
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}
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}
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/*
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/*
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* Minimum supported cpu revision is z196.
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* Check for all required facilities.
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* Check for all required facilities.
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* ZARCH_ACTIVE is done via preprocessor check for 64-bit.
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* ZARCH_ACTIVE is done via preprocessor check for 64-bit.
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*/
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*/
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@ -3139,6 +3106,15 @@ static void query_s390_facilities(void)
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which = "general-instructions-extension";
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which = "general-instructions-extension";
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goto fail;
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goto fail;
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}
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}
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/*
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* Facility 45 is a big bin that contains: distinct-operands,
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* fast-BCR-serialization, high-word, population-count,
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* interlocked-access-1, and load/store-on-condition-1
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*/
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if (!HAVE_FACILITY(45)) {
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which = "45";
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goto fail;
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}
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return;
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return;
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fail:
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fail:
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@ -58,12 +58,12 @@ typedef enum TCGReg {
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#define FACILITY_LONG_DISP 18
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#define FACILITY_LONG_DISP 18
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#define FACILITY_EXT_IMM 21
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#define FACILITY_EXT_IMM 21
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#define FACILITY_GEN_INST_EXT 34
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#define FACILITY_GEN_INST_EXT 34
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#define FACILITY_45 45
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/* Facilities that are checked at runtime. */
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/* Facilities that are checked at runtime. */
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#define FACILITY_LOAD_ON_COND 45
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#define FACILITY_FAST_BCR_SER 45
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#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND
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#define FACILITY_DISTINCT_OPS 45
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#define FACILITY_DISTINCT_OPS FACILITY_LOAD_ON_COND
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#define FACILITY_LOAD_ON_COND2 53
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#define FACILITY_LOAD_ON_COND2 53
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#define FACILITY_VECTOR 129
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#define FACILITY_VECTOR 129
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#define FACILITY_VECTOR_ENH1 135
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#define FACILITY_VECTOR_ENH1 135
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