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RISC-V PR for 9.1 

* roms/opensbi: update to v1.5.1
 * target/riscv: Add asserts for out-of-bound access
 * Remove redundant insn length check for zama16b
 -----BEGIN PGP SIGNATURE-----
 
 iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmaxwTwACgkQr3yVEwxT
 gBOpoQ/9EoGHvGZtd3Zio/51G+tiNok/H+LJGZxGOPl5xc12efhJk15nN/JwVCFp
 zETriTjQ8UUlx+/xvpoQhQbfNm+MtCSl+xyNcPsjAgE6le8MTn38zjroGhUI0JEB
 AuIp9FfwRx4z7nEpuzO8cYdl2Suw5Nh8gi/+0SSrX1vXLY44Ma7UZdM8BjvkGbZp
 TWSqetj236bMoBqSHIk4OddVFbAPlnCQZRo6fwslsjzV6y12PVQw/FgVKKmN7J9k
 qtBoGSuqwFgMnXgxvJXqFmOQYAipgLONRRBaQEj/sGf09UTR/MppMz8CKilAPAYy
 9+UT0/5t+GUUpmbBN2ijWJEgYC9Ev4USIzfGe03XJSWA8uDEyTpJbnbGKDKotfrC
 /qmx2y4Lb4I/3AkJiKgHW32fNeTMURQvzs+ws8frwebWAmH8zwBVbj0EbbceH5M/
 SavAuDivbU4MLdSNKpp5yvB/pkREzCE7pwbjOr0skSLrCiT/S+t9tryt7p+iHxQl
 1xhMbOYFPcbxq7mJvLurtkzn8fl4o1j93tBcq1BcBvRE5O3Odn5VJpje29BYPDpk
 AG82CEeUJ2N+ZVzcV/rYhJaz8WZ7ck+I/j9cK1UtMsp57zmm2awp+mMwyShpAmP3
 MPMHwROJrue9V3z4qdaimNfpaB0p9NCOl9A95J70A/59Q2vO32k=
 =bjWM
 -----END PGP SIGNATURE-----

Merge tag 'pull-riscv-to-apply-20240806-2' of https://github.com/alistair23/qemu into staging

RISC-V PR for 9.1

* roms/opensbi: update to v1.5.1
* target/riscv: Add asserts for out-of-bound access
* Remove redundant insn length check for zama16b

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmaxwTwACgkQr3yVEwxT
# gBOpoQ/9EoGHvGZtd3Zio/51G+tiNok/H+LJGZxGOPl5xc12efhJk15nN/JwVCFp
# zETriTjQ8UUlx+/xvpoQhQbfNm+MtCSl+xyNcPsjAgE6le8MTn38zjroGhUI0JEB
# AuIp9FfwRx4z7nEpuzO8cYdl2Suw5Nh8gi/+0SSrX1vXLY44Ma7UZdM8BjvkGbZp
# TWSqetj236bMoBqSHIk4OddVFbAPlnCQZRo6fwslsjzV6y12PVQw/FgVKKmN7J9k
# qtBoGSuqwFgMnXgxvJXqFmOQYAipgLONRRBaQEj/sGf09UTR/MppMz8CKilAPAYy
# 9+UT0/5t+GUUpmbBN2ijWJEgYC9Ev4USIzfGe03XJSWA8uDEyTpJbnbGKDKotfrC
# /qmx2y4Lb4I/3AkJiKgHW32fNeTMURQvzs+ws8frwebWAmH8zwBVbj0EbbceH5M/
# SavAuDivbU4MLdSNKpp5yvB/pkREzCE7pwbjOr0skSLrCiT/S+t9tryt7p+iHxQl
# 1xhMbOYFPcbxq7mJvLurtkzn8fl4o1j93tBcq1BcBvRE5O3Odn5VJpje29BYPDpk
# AG82CEeUJ2N+ZVzcV/rYhJaz8WZ7ck+I/j9cK1UtMsp57zmm2awp+mMwyShpAmP3
# MPMHwROJrue9V3z4qdaimNfpaB0p9NCOl9A95J70A/59Q2vO32k=
# =bjWM
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 06 Aug 2024 04:22:52 PM AEST
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20240806-2' of https://github.com/alistair23/qemu:
  roms/opensbi: Update to v1.5.1
  target/riscv: Add asserts for out-of-bound access
  target/riscv: Relax fld alignment requirement
  target/riscv: Add MXLEN check for F/D/Q applies to zama16b
  target/riscv: Remove redundant insn length check for zama16b

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2024-08-06 17:35:51 +10:00
parent e7207a9971 b3a34eb90d
commit c659b7b3b4
7 changed files with 25 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

BIN
pc-bios/opensbi-riscv32-generic-fw_dynamic.bin
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pc-bios/opensbi-riscv64-generic-fw_dynamic.bin
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2
roms/opensbi

@ -1 +1 @@
Subproject commit 455de672dd7c2aa1992df54dfb08dc11abbc1b1a
Subproject commit 43cace6c3671e5172d0df0a8963e552bb04b7b20

18
target/riscv/insn_trans/trans_rvd.c.inc
View File

@ -47,8 +47,18 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
/*
* FLD and FSD are only guaranteed to execute atomically if the effective
* address is naturally aligned and XLEN≥64. Also, zama16b applies to
* loads and stores of no more than MXLEN bits defined in the F, D, and
* Q extensions.
*/
if (get_xl_max(ctx) == MXL_RV32) {
memop |= MO_ATOM_NONE;
} else if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
} else {
memop |= MO_ATOM_IFALIGN;
}
decode_save_opc(ctx);
@ -67,8 +77,12 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
if (get_xl_max(ctx) == MXL_RV32) {
memop |= MO_ATOM_NONE;
} else if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
} else {
memop |= MO_ATOM_IFALIGN;
}
decode_save_opc(ctx);

4
target/riscv/insn_trans/trans_rvf.c.inc
View File

@ -48,7 +48,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
@ -70,7 +70,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVF);
if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}

4
target/riscv/insn_trans/trans_rvi.c.inc
View File

@ -268,7 +268,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
{
bool out;
if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
decode_save_opc(ctx);
@ -369,7 +369,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, MemOp memop)
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
if (ctx->cfg_ptr->ext_zama16b) {
memop |= MO_ATOM_WITHIN16;
}
decode_save_opc(ctx);

4
target/riscv/pmu.c
View File

@ -204,6 +204,7 @@ static void riscv_pmu_icount_update_priv(CPURISCVState *env,
}
if (env->virt_enabled) {
g_assert(env->priv <= PRV_S);
counter_arr = env->pmu_fixed_ctrs[1].counter_virt;
snapshot_prev = env->pmu_fixed_ctrs[1].counter_virt_prev;
} else {
@ -212,6 +213,7 @@ static void riscv_pmu_icount_update_priv(CPURISCVState *env,
}
if (new_virt) {
g_assert(newpriv <= PRV_S);
snapshot_new = env->pmu_fixed_ctrs[1].counter_virt_prev;
} else {
snapshot_new = env->pmu_fixed_ctrs[1].counter_prev;
@ -242,6 +244,7 @@ static void riscv_pmu_cycle_update_priv(CPURISCVState *env,
}
if (env->virt_enabled) {
g_assert(env->priv <= PRV_S);
counter_arr = env->pmu_fixed_ctrs[0].counter_virt;
snapshot_prev = env->pmu_fixed_ctrs[0].counter_virt_prev;
} else {
@ -250,6 +253,7 @@ static void riscv_pmu_cycle_update_priv(CPURISCVState *env,
}
if (new_virt) {
g_assert(newpriv <= PRV_S);
snapshot_new = env->pmu_fixed_ctrs[0].counter_virt_prev;
} else {
snapshot_new = env->pmu_fixed_ctrs[0].counter_prev;