mirror of https://github.com/xemu-project/xemu.git
target/riscv: Support pointer masking for RISC-V for i/c/f/d/a types of instructions
Signed-off-by: Alexey Baturo <space.monkey.delivers@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20211025173609.2724490-7-space.monkey.delivers@gmail.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -25,6 +25,7 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, MemOp mop)
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if (a->rl) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL);
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}
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src1 = gen_pm_adjust_address(ctx, src1);
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tcg_gen_qemu_ld_tl(load_val, src1, ctx->mem_idx, mop);
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if (a->aq) {
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tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ);
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@ -44,6 +45,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop)
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TCGLabel *l2 = gen_new_label();
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src1 = get_gpr(ctx, a->rs1, EXT_ZERO);
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src1 = gen_pm_adjust_address(ctx, src1);
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tcg_gen_brcond_tl(TCG_COND_NE, load_res, src1, l1);
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/*
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@ -84,6 +86,7 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a,
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TCGv src1 = get_gpr(ctx, a->rs1, EXT_NONE);
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TCGv src2 = get_gpr(ctx, a->rs2, EXT_NONE);
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src1 = gen_pm_adjust_address(ctx, src1);
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func(dest, src1, src2, ctx->mem_idx, mop);
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gen_set_gpr(ctx, a->rd, dest);
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@ -31,6 +31,7 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
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tcg_gen_addi_tl(temp, addr, a->imm);
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addr = temp;
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}
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addr = gen_pm_adjust_address(ctx, addr);
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tcg_gen_qemu_ld_i64(cpu_fpr[a->rd], addr, ctx->mem_idx, MO_TEQ);
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@ -51,6 +52,7 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a)
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tcg_gen_addi_tl(temp, addr, a->imm);
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addr = temp;
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}
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addr = gen_pm_adjust_address(ctx, addr);
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tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEQ);
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@ -37,6 +37,7 @@ static bool trans_flw(DisasContext *ctx, arg_flw *a)
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tcg_gen_addi_tl(temp, addr, a->imm);
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addr = temp;
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}
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addr = gen_pm_adjust_address(ctx, addr);
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dest = cpu_fpr[a->rd];
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tcg_gen_qemu_ld_i64(dest, addr, ctx->mem_idx, MO_TEUL);
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@ -59,6 +60,7 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a)
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tcg_gen_addi_tl(temp, addr, a->imm);
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addr = temp;
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}
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addr = gen_pm_adjust_address(ctx, addr);
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tcg_gen_qemu_st_i64(cpu_fpr[a->rs2], addr, ctx->mem_idx, MO_TEUL);
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@ -144,6 +144,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp memop)
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tcg_gen_addi_tl(temp, addr, a->imm);
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addr = temp;
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}
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addr = gen_pm_adjust_address(ctx, addr);
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tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, memop);
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gen_set_gpr(ctx, a->rd, dest);
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@ -185,6 +186,7 @@ static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
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tcg_gen_addi_tl(temp, addr, a->imm);
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addr = temp;
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}
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addr = gen_pm_adjust_address(ctx, addr);
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tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, memop);
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return true;
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@ -271,6 +271,14 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
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ctx->base.is_jmp = DISAS_NORETURN;
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}
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/*
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* Temp stub: generates address adjustment for PointerMasking
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*/
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static TCGv gen_pm_adjust_address(DisasContext *s, TCGv src)
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{
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return src;
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}
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#ifndef CONFIG_USER_ONLY
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/* The states of mstatus_fs are:
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* 0 = disabled, 1 = initial, 2 = clean, 3 = dirty
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