From c625ff95070e3ef96bd007de744e1d97c881efeb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 1 Mar 2018 11:05:56 +0000 Subject: [PATCH] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson Message-id: 20180227143852.11175-28-alex.bennee@linaro.org Signed-off-by: Peter Maydell --- target/arm/translate-a64.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1096ff48ac..86231b33bb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -11388,6 +11388,7 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ need_fpst = false; break; + case 0x7d: /* FRSQRTE */ case 0x7f: /* FSQRT (vector) */ break; default: @@ -11452,6 +11453,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); + break; default: g_assert_not_reached(); } @@ -11504,6 +11508,9 @@ static void disas_simd_two_reg_misc_fp16(DisasContext *s, uint32_t insn) case 0x6f: /* FNEG */ tcg_gen_xori_i32(tcg_res, tcg_op, 0x8000); break; + case 0x7d: /* FRSQRTE */ + gen_helper_rsqrte_f16(tcg_res, tcg_op, tcg_fpstatus); + break; case 0x7f: /* FSQRT */ gen_helper_sqrt_f16(tcg_res, tcg_op, tcg_fpstatus); break;