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vmxnet3: Support reading IMR registers on bar0 

Instead of asserting, return the actual IMR register value.
This is aligned with what's returned on ESXi.

Signed-off-by: Shmulik Ladkani <shmulik.ladkani@ravellosystems.com>
Tested-by: Dana Rubin <dana.rubin@ravellosystems.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Shmulik Ladkani 2015-09-21 17:09:02 +03:00 committed by Jason Wang
parent a7278b36fc
commit c6048f849c
1 changed files with 5 additions and 1 deletions
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6
hw/net/vmxnet3.c
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@ -1163,9 +1163,13 @@ vmxnet3_io_bar0_write(void *opaque, hwaddr addr,
static uint64_t static uint64_t
vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size) vmxnet3_io_bar0_read(void *opaque, hwaddr addr, unsigned size)
{ {
VMXNET3State *s = opaque;
if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR, if (VMW_IS_MULTIREG_ADDR(addr, VMXNET3_REG_IMR,
VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) { VMXNET3_MAX_INTRS, VMXNET3_REG_ALIGN)) {
g_assert_not_reached(); int l = VMW_MULTIREG_IDX_BY_ADDR(addr, VMXNET3_REG_IMR,
VMXNET3_REG_ALIGN);
return s->interrupt_states[l].is_masked;
} }
VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size); VMW_CBPRN("BAR0 unknown read [%" PRIx64 "], size %d", addr, size);